A PCIe bridge chip verification method based on hardware simulation accelerator

Abstract

The present invention belongs to the field of integrated circuit verification technology, and particularly relates to a PCIe bridge chip verification method based on a hardware simulation accelerator. It includes a PCIe bridge chip controller to be verified, a mode configuration module, a speed reduction bridge module suitable for a hardware simulation accelerator, and a commercial PCIe device, wherein one end of the speed reduction bridge module is connected to the commercial PCIe device through a gold finger, and the other end of the speed reduction bridge module is connected to the PCIe bridge chip controller to be verified through a standard PIPE interface. The mode configuration module is used to configure the number of group lanes, lane rate, PCIe controller working mode, and PIPE interface bit width and rate of the top wrapper of the speed reduction bridge module of the PCIe bridge chip controller to be verified. The present invention can realize multi-mode and full bandwidth performance verification of the PCIe bridge chip controller to be verified, shorten the engineering iteration cycle, and improve verification efficiency.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit verification, and in particular relates to a PCIe bridge chip verification method based on a hardware simulation accelerator. Background Art

[0002] With the booming development of artificial intelligence and server markets, computer systems have a growing demand for the speed and bandwidth of big data transmission. PCIe (Peripheral Component Interconnect express), as a high-speed serial computer expansion bus, has become an important interface component for computer-external data interaction. PCIe bridge is a high-speed switching device with multiple PCIe interfaces, which facilitates computers / servers to expand more PCIe interfaces, thereby connecting more PCIe sub-devices to meet the needs of big data interaction.

[0003] As the scale and complexity of chip design grow exponentially, a lot of verification work is required before chip tape-out to avoid chip malfunction due to insufficient verification, wasting tape-out costs, and even missing the chip market. However, there is currently no efficient verification solution for PCIe bridge chips.

[0004] The traditional EDA (Eletronic Design Automation) verification speed is too slow and cannot cover the actual usage scenarios of the chip to be verified; although FPGA prototype verification speeds up verification, due to the limitations of the FPGA chip itself, its running speed cannot meet the full bandwidth application scenarios of PCIe switching equipment, such as PCIe rate of Gen3 and lane number of X16. In addition, for different PCIe bridge chip configurations, separate FPGA bit files need to be generated, the iteration cycle is long, and the degree of automation is not high. Therefore, it is necessary to propose a PCIe bridge chip verification method based on hardware simulation accelerator to solve the above problems. Summary of the invention

[0005] The purpose of the present invention is to overcome the above-mentioned shortcomings of the prior art and provide a PCIe bridge chip verification method based on a hardware simulation accelerator, which can realize multi-mode and full-bandwidth performance verification of the PCIe bridge chip controller to be verified, and automatically generate a hardware simulation accelerator verification project under the current configuration mode according to the input control instructions of the mode configuration module, with high verification automation efficiency, reduced human participation in the verification process, and accelerated chip verification process.

[0006] In order to solve the above technical problems, the present invention provides a PCIe bridge chip verification method based on a hardware simulation accelerator, comprising:

[0007] PCIe bridge controller to be verified;

[0008] Commercial PCIe devices;

[0009] A speed reduction bridge module, one end of which is connected to the commercial PCIe device via a gold finger, and the other end of which is a top-level wrapper, which is connected to the PCIe bridge controller to be verified via a standard PIPE interface;

[0010] The mode configuration module is used to configure the number of group lanes, lane rate, PCIe controller working mode of the PCIe bridge controller to be verified, and the PIPE interface width and rate of the top-level wrapper.

[0011] Preferably, the PCIe bridge controller to be verified can be configured with up to M PCIe controllers internally, with a total of N physical lane interfaces; each physical lane interface is connected to the top-level wrapper of the speed reduction bridge through a standard PIPE interface, and the PIPE interface bit width and rate of each PCIe controller can be flexibly configured through the mode configuration module.

[0012] Preferably, the mode configuration module also includes: decoding the input control instructions in the compilation stage and converting them into corresponding macro parameters, the PCIe bridge controller to be verified and the speed reduction bridge module select the code of the corresponding function for compilation according to the corresponding macro parameters, and respectively configure the number of PCIe controllers on the PCIe bridge controller to be verified, the working mode of each PCIe controller, the PIPE interface bit width and rate of each PCIe controller, and simultaneously configure the PIPE interface bit width and rate of the top-level wrapper.

[0013] Preferably, the working mode of each of the PCIe controllers includes an EP or RC working mode, and the rate of each of the PCIe controllers can be configured to Gen1, Gen2, Gen3 and Gen4.

[0014] Preferably, the speed reduction bridge module serves as a PCIe transparent bridge device connected between the PCIe bridge controller to be verified and the commercial PCIe device, and is connected to one end of the PCIe controller bridge to be verified, communicates at the design rate of the PCIe bridge controller to be verified, and is connected to one end of the commercial PCIe device to communicate at a fixed rate.

[0015] Preferably, after the end of the speed reduction bridge module connected to the PCIe bridge chip controller to be verified receives a message from the PCIe transparent bridge device to be verified, it caches the message in the PCIe transparent bridge device, and forwards the cached message to the end connected to the commercial PCIe device through the PCIe transparent bridge device. The two ends of the speed reduction bridge module have different rates, and there is a rate ratio for communication between the two ends, and the value of the rate ratio depends on the configuration parameters of the mode configuration module.

[0016] Preferably, the commercial PCIe device uses RC devices and EP devices with different physical lane numbers and rates.

[0017] Preferably, the input control instruction is 96-bit data, wherein bit15-bit0 represents the parameters of the 0th PCIe controller of the PCIe bridge controller to be verified; bit31-bit16 represents the parameters of the 1st PCIe controller of the PCIe bridge controller to be verified; and so on, bit95-bit80 represents the parameters of the 5th PCIe controller of the PCIe bridge controller to be verified.

[0018] Preferably, the input control instruction is 96'hB838_A929_AB2B_C848_B939_4BCB.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] The present invention configures the PCIe bridge controller to be verified into a working mode with a variable number of PCIe controllers, selectable working modes, and adjustable speed through a mode configuration module, and configures the interface width and speed of the top-level wrapper of the speed reduction bridge module to match the PCIe bridge controller to be verified. By changing the input control instructions of the mode configuration module, a hardware simulation accelerator verification project of the PCIe bridge controller to be verified in different application scenarios is generated. The present invention can realize multi-mode and full-bandwidth performance verification of the PCIe bridge controller to be verified, shorten the engineering iteration cycle, and improve verification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a principle block diagram of a PCIe bridge chip verification method based on a hardware simulation accelerator of the present invention.

[0022] Figure 2 It is a verification framework diagram of a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0023] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0024] like Figure 1 As shown, an embodiment of the present invention provides a PCIe bridge verification method based on a hardware simulation accelerator, including a PCIe bridge controller to be verified, a mode configuration module, a speed reduction bridge module suitable for a hardware simulation accelerator, and a commercial PCIe device; wherein, the PCIe bridge controller to be verified contains a total of N physical lanes, and can be configured as M PCIe controllers at most, each PCIe controller can be configured to EP or RC working mode, and the rate of each PCIe controller can be configured to Gen1, Gen2, Gen3 and Gen4; according to different application scenarios, the PCIe bridge controller to be verified can be configured to have different numbers of PCIe controllers, and each PCIe controller can be configured with different numbers of lanes, including X1 (1 lane) mode, X2 (2 lanes) mode, X4 (4 lanes) mode, X8 (8 lanes) mode and X16 (16 lanes) mode.

[0025] Moreover, the number of PCIe controllers, the working mode of PCIe controllers and the number of lanes can be arbitrarily combined. In order to fully verify the chip function, it is necessary to construct a verification project covering different numbers of PCIe controllers of the PCIe bridge controller to be verified, and any combination of the speed and working mode of each PCIe controller. From the above analysis, it can be seen that the PCIe bridge controller to be verified can be configured with many application scenarios. How to efficiently construct a project to cover all verification scenarios is also one of the key problems solved by the present invention.

[0026] In order to solve the above problems, the mode configuration module automatically configures the number of PCIe controllers, the speed of each PCIe controller and the working mode of the PCIe bridge controller to be verified according to the input control instructions, and at the same time configures the PIPE interface bit width and rate of the top-level wrapper of the speed reduction bridge module suitable for the hardware simulation accelerator.

[0027] The above input control instruction is 96-bit data, wherein bit15-bit0 represents the parameters of the 0th PCIe controller of the PCIe bridge controller to be verified.

[0028] The parameters of the 0th PCIe controller are specifically described as follows:

[0029] Among them, bit2-bit0 is configured as the rate of the 0th PCIe controller, 000 represents gen1, 001 represents gen2, 010 represents gen3, 011 represents gen4, and 100 represents gen5; bit3 is configured to determine whether the current rate is valid; bit6-bit4 is configured to determine the number of lanes of the 0th PCIe controller, 000 represents x1 mode, 001 represents x2 mode, 010 represents x4 mode, 011 represents x8 mode, and 100 represents x16 mode; bit7 is configured to determine the working mode of the 0th PCIe controller, 0 represents RC mode, and 1 represents EP mode; bit10-bit8 is configured to determine the rate of the top-level wrapper of the speed reduction bridge module 0, 000 represents gen1, 001 represents x2 mode, 010 represents x4 mode, 011 represents x8 mode, and 100 represents x16 mode. 1 represents gen2, 010 represents gen3, 011 represents gen4, and 100 represents gen5; bit11 configures the PIPE interface bit width of the top-level wrapper of the speed reduction bridge module 0, 0 represents the PIPE interface bit width of 16 bits, and 1 represents the PIPE interface bit width of 32 bits; bit14-bit12 are configured as the number of PIPE interface lanes of the top-level wrapper of the speed reduction bridge module 0, 000 represents 1 lane, 001 represents 2 lanes, 010 represents 4 lanes, 011 represents 8 lanes, and 100 represents 16 lanes; bit15 is configured as the working mode of the top-level wrapper of the speed reduction bridge module 0, 0 represents RC mode, and 1 represents EP mode.

[0030] Among them, bit31-bit16 represents the parameters of the first PCIe controller of the PCIe bridge controller to be verified, and the specific definition of each bit is consistent with bit15-bit0. Similarly, bit95-bit80 represents the parameters of the fifth PCIe controller of the PCIe bridge controller to be verified.

[0031] like Figure 2As shown in the verification framework diagram of a preferred embodiment of the present invention, the input control instruction in this embodiment is 96'hB838_A929_AB2B_C848_B939_4BCB, and the PCIe bridge controller to be verified is configured as 6 PCIe controllers, namely PCIe0 controller, PCIe1 controller, PCIe2 controller, PCIe3 controller, PCIe4 controller and PCIe5 controller; the PCIe0 controller is configured as X16 mode, and the rate is Gen 4, the working mode is EP; the PCIe1 controller is configured in X8 mode, the rate is Gen2, and the working mode is RC; the PCIe2 controller is configured in X16 mode, the rate is Gen1, and the working mode is RC; the PCIe3 controller is configured in X4 mode, the rate is Gen4, and the working mode is RC; the PCIe4 controller is configured in X4 mode, the rate is Gen2, and the working mode is RC; the PCIe5 controller is configured in X8 mode, the rate is Gen1, and the working mode is RC.

[0032] The speed reduction bridge modules need to be configured with 6. The PIPE interface bit width of the top-level wrapper of the speed reduction bridge module 0 is 32 bits, the number of lanes is configured in X16 mode, the rate is Gen4, and the working mode is RC; the PIPE interface bit width of the top-level wrapper of the speed reduction bridge module 1 is 32 bits, the number of lanes is configured in X8 mode, the rate is Gen2, and the working mode is EP; the PIPE interface bit width of the top-level wrapper of the speed reduction bridge module 2 is 32 bits, the number of lanes is configured in X16 mode, the rate is Gen1, The working mode is EP; the PIPE interface bit width of the top-level wrapper of the speed reduction bridge module 3 is 32 bits, the number of lanes is configured in X4 mode, the rate is Gen4, and the working mode is EP; the PIPE interface bit width of the top-level wrapper of the speed reduction bridge module 4 is 32 bits, the number of lanes is configured in X4 mode, the rate is Gen2, and the working mode is EP; the PIPE interface bit width of the top-level wrapper of the speed reduction bridge module 5 is 32 bits, the number of lanes is configured in X8 mode, the rate is Gen1, and the working mode is EP.

[0033] In the embodiment of the present invention, a total of 6 types of commercial PCIe devices are used, PCIe device 0 uses an X86 server host, PCIe device 1 uses an NVME hard disk, PCIe device 2 uses a PCIe to SATA hard disk, PCIe device 3 uses an NVME hard disk, PCIe device 4 uses a commercial Gigabit network card, and PCIe device 5 uses a commercial 10 Gigabit network card.

[0034] After the verification project based on the embodiment of the present invention is run on the hardware simulation accelerator, the X86 server host of PCIe device 0 is turned on, and PCIe device 1, PCIe device 2, PCIe device 3, PCIe device 4, and PCIe device 5 are automatically enumerated after startup. After entering the system, on the X86 server host of PCIe device 0, the application is enabled to perform read and write tests on the hard disks of PCIe device 1, PCIe device 2, and PCIe device 3, and to perform speed tests on the network cards of PCIe device 4 and PCIe device 5. The speed test results obtained by the application software are multiplied by the rate ratio of the speed reduction bridge to obtain the actual bandwidth of the PCIe bridge controller to be verified, and the test results are consistent with the bandwidth range of the corresponding PCIe controller.

[0035] In summary, through the mode configuration module, the working mode and working bandwidth configuration of the PCIe bridge controller to be verified are realized, and the corresponding configured hardware simulation accelerator verification project is automatically generated. The speed test results show that the present invention can verify the full bandwidth performance of the PCIe bridge controller to be verified, and at the same time, only the input control instructions of the mode configuration module need to be changed to generate the hardware simulation accelerator project of the PCIe bridge controller to be verified in different application scenarios, thereby improving work efficiency and the reliability of the PCIe bridge controller to be verified.

[0036] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A PCIe bridge chip verification device based on hardware simulation accelerator, characterized in that: include: PCIe bridge controller to be verified; PCIe devices; A speed reduction bridge module, one end of which is connected to the PCIe device via a gold finger, and the other end of which is a top-level wrapper, which is connected to the PCIe bridge controller to be verified via a PIPE interface; A mode configuration module, used to configure the number of group lanes, lane rate, PCIe controller working mode of the PCIe bridge controller to be verified, and the PIPE interface width and rate of the top-level wrapper; The PCIe bridge controller to be verified can be configured with M PCIe controllers internally, with a total of N physical lane interfaces; Each physical lane interface is connected to the top wrapper of the speed reduction bridge via a PIPE interface, and the PIPE interface bit width and rate of each PCIe controller can be flexibly configured via the mode configuration module; The mode configuration module also includes: decoding the input control instructions in the compilation stage and converting them into corresponding macro parameters. The PCIe bridge controller to be verified and the speed reduction bridge module select the code of the corresponding function for compilation according to the corresponding macro parameters, and respectively configure the number of PCIe controllers on the PCIe bridge controller to be verified, the working mode of each PCIe controller, the PIPE interface bit width and rate of each PCIe controller, and simultaneously configure the PIPE interface bit width and rate of the top-level wrapper.

2. A PCIe bridge chip verification device based on a hardware simulation accelerator as claimed in claim 1, characterized in that: The working mode of each of the PCIe controllers includes an EP or RC working mode, and the rate of each of the PCIe controllers can be configured to Gen1, Gen2, Gen3 and Gen4.

3. A PCIe bridge chip verification device based on hardware simulation accelerator as claimed in claim 1, characterized in that: The speed reduction bridge module serves as a PCIe transparent bridge device connected between the PCIe bridge controller to be verified and the PCIe device, and is connected to one end of the PCIe controller bridge to be verified, communicates according to the design rate of the PCIe bridge controller to be verified, and is connected to one end of the PCIe device to communicate at a fixed rate.

4. A PCIe bridge chip verification device based on hardware simulation accelerator as claimed in claim 3, characterized in that: After receiving a message from the PCIe transparent bridge device to be verified, the speed reduction bridge module at one end connected to the PCIe bridge controller to be verified caches the message in the PCIe transparent bridge device, and forwards the cached message to the end connected to the PCIe device through the PCIe transparent bridge device. The two ends of the speed reduction bridge module have different rates, and there is a rate ratio for communication between the two ends, and the value of the rate ratio depends on the configuration parameters of the mode configuration module.

5. A PCIe bridge chip verification device based on hardware simulation accelerator as claimed in claim 1, characterized in that: The PCIe device selects RC devices and EP devices with different physical lane numbers and rates.

6. A PCIe bridge chip verification device based on hardware simulation accelerator as claimed in claim 1, characterized in that: The input control instruction is 96-bit data, in which bit15-bit0 represents the parameters of the 0th PCIe controller of the PCIe bridge controller to be verified; bit31-bit16 represents the parameters of the 1st PCIe controller of the PCIe bridge controller to be verified; and so on, bit95-bit80 represents the parameters of the 5th PCIe controller of the PCIe bridge controller to be verified.

7. A PCIe bridge chip verification device based on hardware simulation accelerator as claimed in claim 6, characterized in that: The input control instruction is 96'hB838_A929_AB2B_C848_B939_4BCB.

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