Cache data writing method, cache data reading method and storage medium thereof

Abstract

The present application provides a cache data writing method, a cache data reading method and a storage medium thereof. In response to a write request for target data, a target page code address of a write cache logical space is obtained, and then, based on the target page code address, it is determined whether the write request hits the cache. Then, when the write request does not hit the cache, the target data is written to a flash memory; when the write request hits the cache, based on the target page code address, the target data is written to a cache space of a cache node corresponding to a write cache linked list or a read cache linked list, wherein the cache nodes in the write cache linked list or the read cache linked list are mapped to the target page code address, and then, in the case of a cache hit, through the write call design between multiple cache linked lists and the mapping relationship between the cache logical space and the cache linked list, there is no need to directly call the flash memory each time a new write operation is executed, thereby reducing the number of writes to the flash memory and improving the durability of the flash memory.

Description

Technical Field

[0001] The present application relates to the field of computer cache, and in particular to a cache data writing method, a cache data reading method and a storage medium thereof. Background Art

[0002] With the development of the Internet of Things, smart homes and mobile Internet, the popularity of embedded systems and mobile devices continues to increase. These devices usually need to use Flash storage to store data and programs. Flash storage has the advantages of high speed, low power consumption and reliability, so it has been widely used in embedded and mobile devices. However, the management of Flash storage has challenges in different hardware platforms and operating system environments, such as complex data erasure, data management, memory life management and performance optimization.

[0003] In the prior art, NAND Flash memory has a limit on the number of writes during the reading and writing process, because each write operation will cause the storage unit to wear out, and eventually the storage unit will not be able to correctly save data. This means that when a large amount of data is continuously written, the NAND Flash memory may have a life problem; and each time a new write operation is performed, the NAND Flash memory needs to erase the original data first. This erasing process is relatively slow and needs to be performed before the data is written, which may also increase the latency of the data response. At the same time, when the NAND Flash memory reads data, it will also increase the latency of the data response based on the hysteresis of the write data operation. Summary of the invention

[0004] The main purpose of the embodiments of the present application is to propose a cache data writing method, a cache data reading method and a storage medium thereof. Through the read and write call design between multiple cache linked lists and the mapping relationship between the cache logical space and the cache linked list, there is no need to directly call the flash memory every time a new read and write operation is performed, thereby reducing the number of read and write operations of the flash memory, improving the durability of the flash memory, and also improving the data reading and writing speed and reducing the latency of data response.

[0005] To achieve the above-mentioned purpose, a first aspect of an embodiment of the present application proposes a cache data writing method, comprising:

[0006] In response to a write request for target data, obtaining a target page address of a write cache logical space;

[0007] Determine whether the write request hits the cache based on the target page address;

[0008] When a write request does not hit the cache, the target data is written to the flash memory;

[0009] When a write request hits the cache, the target data is written to the cache space of the cache node corresponding to the write cache linked list or the read cache linked list according to the target page number address, wherein the cache node in the write cache linked list or the read cache linked list is mapped to the target page number address.

[0010] Further, in some embodiments, writing the target data into the cache space of the cache node corresponding to the write cache linked list or the read cache linked list according to the target page address includes:

[0011] According to the target page number address, extract the first cache node at the page number mapping position corresponding to the write cache linked list, and determine whether there is a node cache corresponding to the target page number address in the cache space of the first cache node;

[0012] When the cache space of the first cache node has a node cache corresponding to the target page address, the first cache node is placed at the end of the write cache linked list, and the target data is written to the cache space of the first cache node;

[0013] When the cache space of the first cache node does not have a node cache corresponding to the target page number address, extract the second cache node at the page number mapping position corresponding to the read cache linked list according to the target page number address, and determine whether the cache space of the second cache node has a node cache corresponding to the target page number address;

[0014] When the cache space of the second cache node contains a node cache corresponding to the target page address, the second cache node is placed at the end of the write cache linked list, and the target data is written into the cache space of the second cache node;

[0015] When the cache space of the second cache node does not have a node cache corresponding to the target page address, a free list is obtained, and the target data is written to the cache space of the corresponding cache node according to the cache node in the free list.

[0016] Further, in some embodiments, before placing the second cache node at the end of the write cache linked list or before obtaining the free linked list, the cache data writing method further includes:

[0017] Counting a first quantity value of cache nodes in the write cache linked list;

[0018] When the first quantity value is equal to the maximum quantity value, the third cache node is extracted from the head of the write cache linked list, the data of the third cache node is written into the flash memory, and the third cache node is placed at the end of the read cache linked list.

[0019] Further, in some embodiments, writing the target data into the cache space of the corresponding cache node according to the cache node of the free list includes:

[0020] Determine whether the cache node of the free list exists;

[0021] When the cache node of the free linked list does not exist, extract the fourth cache node at the head of the read cache linked list, put the fourth cache node at the end of the write cache linked list, and write the target data into the cache space of the fourth cache node;

[0022] Alternatively, when the cache node of the free list exists, the fifth cache node is extracted from the head of the free list, and the fifth cache node is placed at the end of the write cache list, and the target data is written to the cache space of the fifth cache node.

[0023] Further, in some embodiments, determining whether the write request hits the cache according to the target page address includes:

[0024] Obtain the total page address range of the cache logic space, and determine whether the target page address is within the total page address range;

[0025] When the target page address is within the total page address interval, obtaining a target writing scenario of the target data, and determining whether the target writing scenario conforms to a first preset writing scenario;

[0026] When the target writing scenario meets the first preset writing scenario, determining that the writing request does not hit the cache;

[0027] When the target writing scene does not conform to the first preset writing scene, determining whether the target writing scene conforms to the second preset writing scene;

[0028] When the target writing scenario meets the second preset writing scenario, determining that the writing request hits the cache;

[0029] When the target writing scenario does not conform to the second preset writing scenario, it is determined that the writing request does not hit the cache.

[0030] To achieve the above object, a second aspect of an embodiment of the present application proposes a cache data reading method, comprising:

[0031] In response to a read request for target data, obtaining a target page address of a read cache logical space;

[0032] Determine whether the read request hits the cache based on the target page address;

[0033] When the read request does not hit the cache, the target data is read from the flash memory;

[0034] When a read request hits the cache, the target data is read from the flash memory or the read cache linked list according to the target page address, the storage data of the corresponding cache node in the write cache linked list, and the storage data of the corresponding cache node in the read cache linked list.

[0035] Further, in some embodiments, according to the target page address, the storage data of the corresponding cache node in the write cache linked list, and the storage data of the corresponding cache node in the read cache linked list, the target data is read in the flash memory or the read cache linked list, including:

[0036] Determine whether there is a sixth cache node in the write cache linked list, wherein the cache space of the sixth cache node stores the target data;

[0037] When there is a sixth cache node in the write cache linked list, determining whether the storage location of the target data covers the read address interval based on the target page address;

[0038] When the storage location of the target data covers the read address interval, reading the target data from the sixth cache node;

[0039] When the storage location of the target data does not cover the read address interval, reading the target data in the flash memory;

[0040] When the sixth cache node does not exist in the write cache linked list, determining whether a seventh cache node exists in the read cache linked list, wherein the cache space of the seventh cache node stores the target data;

[0041] When the seventh cache node exists in the read cache linked list, the target data is read from the seventh cache node;

[0042] When the seventh cache node does not exist in the read cache linked list, the target data is read from the flash memory, and a cache node corresponding to the target data is added at the end of the read cache linked list.

[0043] Further, in some embodiments, adding a cache node corresponding to the target data stored at the end of the read cache linked list includes:

[0044] Get the free list and determine whether the cache node of the free list exists;

[0045] When the cache node of the free linked list does not exist, extract the eighth cache node at the head of the read cache linked list, read the target data into the cache space of the eighth cache node in the flash memory, and put the eighth cache node at the end of the read cache linked list;

[0046] Alternatively, when the cache node of the free list exists, the ninth cache node is extracted from the head of the free list, the target data is read into the cache space of the ninth cache node in the flash memory, and the ninth cache node is placed at the end of the read cache list.

[0047] Further, in some embodiments, determining whether the read request hits the cache according to the target page address includes:

[0048] Obtain the total page address range of the cache logic space, and determine whether the target page address is within the total page address range;

[0049] When the target page address is within the total page address interval, obtaining a target reading scenario of the target data, and determining whether the target reading scenario meets a first preset reading scenario;

[0050] When the target reading scenario meets the first preset reading scenario, determining that the reading request does not hit the cache;

[0051] When the target reading scenario does not conform to the first preset reading scenario, it is determined that the reading request hits the cache.

[0052] To achieve the above-mentioned purpose, the third aspect of an embodiment of the present application proposes a storage medium, which is a computer-readable storage medium. The storage medium stores a computer program, and when the computer program is executed by a processor, it implements a cache data writing method of the above-mentioned first aspect embodiment, and / or implements a cache data reading method of the above-mentioned second aspect embodiment.

[0053] The embodiments of the present application have the following beneficial effects: on the one hand, the present application obtains the target page code address of the write cache logical space in response to a write request for the target data, and then determines whether the write request hits the cache based on the target page code address. Then, when the write request does not hit the cache, the target data is written to the flash memory; when the write request hits the cache, the target data is written to the cache space of the cache node corresponding to the write cache linked list or the read cache linked list based on the target page code address, wherein the cache nodes in the write cache linked list or the read cache linked list are mapped to the target page code address, and then, when the write request hits the cache, through the write call design between multiple cache linked lists and the mapping relationship between the cache logical space and the cache linked list, there is no need to directly call the flash memory each time a new write operation is executed, thereby reducing the number of writes to the flash memory, reducing the write amplification effect of the flash memory, improving the durability of the flash memory, and also improving the data writing speed and reducing the latency of the data response.

[0054] On the other hand, the present application obtains the target page code address of the read cache logical space in response to a read request for the target data, and then determines whether the read request hits the cache based on the target page code address. When the read request does not hit the cache, the target data is read in the flash memory. When the read request hits the cache, the target data is read in the flash memory or the read cache linked list based on the storage data of the cache nodes corresponding to the write cache linked list and the read cache linked list. Furthermore, when the read request hits the cache, through the read call design between multiple cache linked lists, there is no need to directly call the flash memory each time a new read operation is executed, thereby improving the data reading speed and reducing the latency of data response. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 is a flow chart of a method for writing cache data provided by an embodiment of the present application;

[0056] Figure 2 The embodiment of this application provides Figure 1 Flow chart of step S140;

[0057] Figure 3 It is a schematic diagram of placing the first cache node provided by an embodiment of the present application at the end of the write cache linked list;

[0058] Figure 4 It is a schematic diagram of placing the second cache node provided by an embodiment of the present application at the end of the write cache linked list;

[0059] Figure 5 This is a flow chart of placing the second cache node before the end of the write cache linked list provided by an embodiment of the present application;

[0060] Figure 6 It is a schematic diagram of placing the third cache node at the end of the read cache linked list provided by an embodiment of the present application;

[0061] Figure 7 This is a flow chart before obtaining the free list provided in an embodiment of the present application;

[0062] Figure 8 The embodiment of this application provides Figure 2 Flow chart of step S205;

[0063] Fig. 9 It is a schematic diagram of placing the fourth cache node or the fifth cache node provided by an embodiment of the present application at the end of the write cache linked list;

[0064] Fig.10 The embodiment of this application provides Figure 1 Flow chart of step S102;

[0065] Fig.11 is a flow chart of a cache data reading method provided in an embodiment of the present application;

[0066] Fig.12 The embodiment of this application provides Fig.11 Flowchart of step S1104 in FIG.

[0067] Fig.13 It is a flowchart of adding a cache node at the end of a read cache linked list provided by an embodiment of the present application;

[0068] Fig.14 The embodiment of this application provides Fig.11Flowchart of step S1102 in FIG.

[0069] Fig.15 A schematic diagram of the structure of a cache data writing system provided in an embodiment of the present application;

[0070] Fig.16 A schematic diagram of the structure of a cache data reading system provided in an embodiment of the present application;

[0071] Fig.17 is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application;

[0072] Fig.18 It is a schematic diagram of a scenario in which the storage location of target data in the sixth cache node covers the read address interval provided by an embodiment of the present application;

[0073] Fig.19 This is a schematic diagram of a scenario in which the storage location of target data in the sixth cache node provided by an embodiment of the present application does not cover the read address interval. DETAILED DESCRIPTION

[0074] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0075] In the description of the present application, it should be understood that descriptions involving orientation, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0076] It should also be noted that in the description of this application, "several" means more than one, "more" means more than two, "greater than", "less than", "exceed", etc. are understood to exclude the number itself, and "above", "below", "within", etc. are understood to include the number itself. If there is a description of "first" or "second", it is only used to distinguish the technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0077] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0078] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0079] First, some nouns involved in this application are analyzed:

[0080] NAND Flash memory is a non-volatile memory widely used to store data, which will not be lost even after power failure. With its high density, low cost and high write / erase performance, it has become the core technology of devices such as solid-state drives (SSDs), USB flash drives, and SD cards. Among them, NAND Flash uses block-level operations when writing and erasing data.

[0081] A linked list is a data structure used to store a series of linear data elements. Unlike an array, the elements in a linked list are not stored continuously, but each element is linked together through pointers or references. The basic component of a linked list is a node, and each node consists of two parts: a cache space (used to store specific data) and a pointer space (used to store a pointer to the next node or a pointer to the previous node).

[0082] In the prior art, NAND Flash memory has a limit on the number of writes during the reading and writing process, because each write operation will cause the storage unit to wear out, and eventually the storage unit will not be able to correctly save data. This means that when a large amount of data is continuously written, the NAND Flash memory may have a life problem; and each time a new write operation is performed, the NAND Flash memory needs to erase the original data first. This erasing process is relatively slow and needs to be performed before the data is written, which may also increase the latency of the data response. At the same time, when the NAND Flash memory reads data, it will also increase the latency of the data response based on the hysteresis of the write data operation.

[0083] Based on this, an embodiment of the present application provides a cache data writing method, a cache data reading method and a storage medium thereof. On the one hand, the present application obtains a target page code address of a write cache logical space in response to a write request for target data, and then determines whether the write request hits the cache based on the target page code address. Then, when the write request does not hit the cache, the target data is written to the flash memory; when the write request hits the cache, the target data is written to the cache space of the cache node corresponding to the write cache linked list or the read cache linked list according to the target page code address, wherein the cache nodes in the write cache linked list or the read cache linked list are mapped to the target page code address, and then, when the write request hits the cache, through the write call design between multiple cache linked lists and the mapping relationship between the cache logical space and the cache linked list, there is no need to directly call the flash memory each time a new write operation is executed, thereby reducing the number of writes to the flash memory, reducing the write amplification effect of the flash memory, improving the durability of the flash memory, and also improving the data writing speed and reducing the latency of the data response. On the other hand, the present application obtains the target page code address of the read cache logical space in response to a read request for the target data, and then determines whether the read request hits the cache based on the target page code address. When the read request does not hit the cache, the target data is read from the flash memory. When the read request hits the cache, the target data is read from the flash memory or the read cache linked list based on the storage data of the cache nodes corresponding to the write cache linked list and the read cache linked list. Furthermore, when the read request hits the cache, through the read call design between multiple cache linked lists, there is no need to directly call the flash memory each time a new read operation is executed, thereby improving the data reading speed and reducing the latency of the data response.

[0084] A cache data writing method, a cache data reading method and a storage medium thereof provided in an embodiment of the present application are specifically described through the following embodiments.

[0085] In the first aspect, a cache data writing method in an embodiment of the present application is first described.

[0086] Reference Figure 1 As shown, Figure 1 is a flowchart of a cache data writing method provided in an embodiment of the present application. The cache data writing method may include but is not limited to steps S101 to S104.

[0087] Step S101: in response to a write request for target data, obtaining a target page address of a write cache logical space.

[0088] Specifically, in response to a write request for target data, a target page address of the write cache logical space is acquired.

[0089] Among them, each logical page page of the cache logical space is mapped to a physical page page of the physical storage space. The write request carries the starting sector address sector_addr and sector length sector_len of the target data mapped in the logical space, and multiple sectors of the cache logical space will be converted into each logical page page of the logical space. Finally, these sectors are mapped to the physical page pages corresponding to the physical storage space.

[0090] It should be noted that the target page address page_num is obtained by the following formula:

[0091] Logical mapping coefficient = one logical page capacity / one sector capacity;

[0092] Starting page address = ALIGN_DOWN (starting sector address, logical mapping coefficient) / logical mapping coefficient;

[0093] Among them, there are two situations for the last page address:

[0094] If the sector start address is an integer multiple of the logical mapping coefficient, or the sector end address is an integer multiple of the logical mapping coefficient, then:

[0095] End page address = start page address + [ALIGN_UP (sector length, logical mapping coefficient) / logical mapping coefficient - 1];

[0096] If it is any other case, then:

[0097] End page address = start page address + [ALIGN_UP (sector length, logical mapping coefficient) / logical mapping coefficient];

[0098] Target page address = [starting page address, ending page address];

[0099] Among them, the target page number address is a positive integer, ALIGN_DOWN() is a round-down function (for example: ALIGN_DOWN(7, 4) / 4=1, ALIGN_DOWN(9, 4) / 4=2), and ALIGN_UP() is a round-up function (for example: ALIGN_UP(10, 4) / 4=3, ALIGN_UP(13, 4) / 4=4).

[0100] It should also be noted that when the starting page address is equal to the ending page address, the target page address is 1 (ie, target page address = starting page address = ending page address); when the starting page address is equal to the ending page address, the target page address is multiple.

[0101] In a possible implementation, the capacity of a sector is 512 bytes, and the capacity of a logical page is 2048 bytes, then the logical mapping coefficient is 2048 / 512=4, that is, a logical page is mapped to 4 sectors, and then responds to a write request for the target data and parses the write request to obtain a starting sector address sector_addr of 100 and a sector length sector_len of 10, then the starting page code address = ALIGN_DOWN(100, 4) / 4=25, the ending page code address = 25+[ALIGN_UP(10, 4) / 4-1]=27, then the target page code address of the write cache logical space has a value range of [25,27], that is, the target page code address can be 25, the target page code address can also be 26, and the target page code address can also be 27, which is not specifically limited in this application.

[0102] In one possible implementation, the capacity of a sector is 512 bytes, and the capacity of a logical page is 2048 bytes, then the logical mapping coefficient is 2048 / 512=4, that is, a logical page is mapped to 4 sectors, and then responds to a write request for the target data and parses the write request to obtain a starting sector address sector_addr of 7 and a sector length sector_len of 12, then the starting page code address = ALIGN_DOWN (7, 4) / 4 = 1, the ending page code address = 1 + [ALIGN_UP (12, 4) / 4] = 4, then the target page code address of the write cache logical space has a value range of [1, 4], that is, the target page code address can be 1, the target page code address can also be 2, the target page code address can also be 3, and the target page code address can also be 4, which is not specifically limited in this application.

[0103] Step S102: Determine whether the write request hits the cache according to the target page address.

[0104] In one possible implementation, the target page code address 27 is compared with the maximum value and the minimum value of the total page code address interval [0,100] of the cache logical space, respectively, to determine that the target page code address 27 is greater than the minimum value 0 of the total page code address interval, and the target page code address 27 is less than the maximum value 100 of the total page code address interval, that is, the target page code address 27 is within the total page code address interval [0,100], indicating that the write operation of this write request does not exceed the writable range of the cache logical space, and then the target write scenario of the target data is obtained, and it is determined whether the target write scenario meets the first preset write scenario. When the target write scenario meets the first preset write scenario, it is determined that the write request does not hit the cache; when the target write scenario does not meet the first preset write scenario, it is determined that the write request hits the cache, wherein the first preset write scenario can be represented as a scenario in which the target data needs to be burned to an embedded microprocessor. In the scenario of burning data to an embedded microprocessor, not calling the cache can greatly improve the data burning speed.

[0105] In one possible implementation, the target page code address 25 is compared with the maximum value and the minimum value of the total page code address interval [0,100] of the cache logical space, respectively, to determine that the target page code address 25 is greater than the minimum value 0 of the total page code address interval, and the target page code address 25 is less than the maximum value 100 of the total page code address interval, that is, the target page code address 25 is within the total page code address interval [0,100], indicating that the write operation of this write request does not exceed the writable range of the cache logical space, and then the target write scenario of the target data is obtained, and it is determined whether the target write scenario meets the second preset write scenario. When the target write scenario meets the second preset write scenario, it is determined that the write request does not hit the cache; when the target write scenario does not meet the second preset write scenario, it is determined that the write request hits the cache, wherein the second preset write scenario can be represented as a scenario in which a large number of target data are performing write operations. In the scenario in which a large number of target data are performing write operations, not calling the cache can avoid occupying a large amount of cache resources for a long time, thereby freeing up the cache to process other data in time and avoiding task congestion.

[0106] In one possible implementation, the target page code address 62 is compared with the maximum and minimum values ​​of the total page code address interval [0, 60] of the cache logical space, respectively, to determine that the target page code address 62 is greater than the minimum value 0 of the total page code address interval, and the target page code address 62 is greater than the maximum value 60 of the total page code address interval, that is, the target page code address 62 is not within the total page code address interval [0, 60], indicating that the write operation of this write request exceeds the writable range of the cache logical space, and the write operation is directly terminated.

[0107] Step S103: When the write request does not hit the cache, the target data is written into the flash memory.

[0108] Specifically, when the write request does not hit the cache, the target data is written into the flash memory NAND Flash.

[0109] Step S104: when the write request hits the cache, the target data is written into the cache space of the cache node corresponding to the write cache linked list or the read cache linked list according to the target page number address.

[0110] Among them, the cache nodes in the write cache linked list or the read cache linked list are mapped to the target page number address, that is, the pointer part of each cache node in the write cache linked list or the read cache linked list stores a mapping address field, and the numerical value of the mapping address field corresponds to the target page number address.

[0111] Specifically, when a write request hits the cache, the target data is written to the cache space of the cache node corresponding to the write cache linked list cache_write_list or the read cache linked list cache_read_list according to the target page number address.

[0112] Reference Figure 2 As shown, Figure 2 The embodiment of this application provides Figure 1 In the flowchart of step S140, the cache data writing method may include but is not limited to steps S201 to S205.

[0113] Step S201: extracting a first cache node from a page mapping position corresponding to a write cache linked list according to a target page address, and determining whether a node cache corresponding to the target page address exists in the cache space of the first cache node.

[0114] The value of the mapping address field stored in the pointer portion of the first cache node is the same as the target page address.

[0115] In one possible implementation, based on the target page code address being 27, the first cache node whose mapping address field value is 27 is traversed in the write cache linked list and its corresponding page code mapping position X is determined, and then the first cache node is extracted, that is, the predecessor pointer and the successor pointer of the first cache node are both set to null, and then, the successor pointer of the cache node at the X-1 page code mapping position is pointed to the cache node at the X+1 page code mapping position, and the predecessor pointer of the cache node at the X+1 page code mapping position is pointed to the cache node at the X-1 page code mapping position, and finally, it is determined whether there is a node cache corresponding to the target page code address in the cache space of the first cache node.

[0116] Step S202: when the cache space of the first cache node has a node cache corresponding to the target page address, the first cache node is placed at the end of the write cache linked list, and the target data is written into the cache space of the first cache node.

[0117] In one possible implementation, refer to Figure 3 As shown, Figure 3 This is a schematic diagram of placing the first cache node at the end of the write cache linked list provided by an embodiment of the present application. When there is a node cache corresponding to the target page number address in the cache space of the first cache node, the first cache node is placed at the end of the write cache linked list, that is, the rear drive pointer of the cache node at the end of the write cache linked list points to the first cache node. Finally, the target data is written to the cache space of the first cache node.

[0118] Step S203: When the cache space of the first cache node does not have a node cache corresponding to the target page number address, extract the second cache node at the page number mapping position corresponding to the read cache linked list according to the target page number address, and determine whether the cache space of the second cache node has a node cache corresponding to the target page number address.

[0119] The value of the mapping address field stored in the pointer portion of the second cache node is the same as the target page address.

[0120] In a possible implementation, when there is no node cache corresponding to the target page number address in the cache space of the first cache node, based on the target page number address of 27, the first cache node whose mapping address field value is 27 is traversed in the read cache linked list and its corresponding page number mapping position X is determined, and then the first cache node is extracted, that is, the predecessor pointer and the successor pointer of the first cache node are set to null, and then, the successor pointer of the cache node at the X-1 page number mapping position is pointed to the cache node at the X+1 page number mapping position, and the predecessor pointer of the cache node at the X+1 page number mapping position is pointed to the cache node at the X-1 page number mapping position, and finally, it is determined whether there is a node cache corresponding to the target page number address in the cache space of the second cache node.

[0121] Step S204: when the cache space of the second cache node has a node cache corresponding to the target page address, the second cache node is placed at the end of the write cache linked list, and the target data is written into the cache space of the second cache node.

[0122] In one possible implementation, refer to Figure 4 As shown, Figure 4This is a schematic diagram of placing the second cache node at the end of the write cache linked list provided by an embodiment of the present application. When there is a node cache corresponding to the target page number address in the cache space of the second cache node, the second cache node is placed at the end of the read cache linked list, that is, the rear drive pointer of the cache node at the end of the read cache linked list points to the second cache node. Finally, the target data is written to the cache space of the second cache node.

[0123] Step S205: when the cache space of the second cache node does not have a node cache corresponding to the target page address, a free list is obtained, and the target data is written into the cache space of the corresponding cache node according to the cache node in the free list.

[0124] In a possible implementation, when the cache space of the second cache node does not have a node cache corresponding to the target page address, a free list empty_cache_list is obtained, and the target data is written to the cache space of the corresponding cache node according to the cache node in the free list.

[0125] Reference Figure 5 As shown, Figure 5 This is a flowchart provided by an embodiment of the present application for placing the second cache node at the end of the write cache linked list. Before placing the second cache node at the end of the write cache linked list, the cache data writing method may also include but is not limited to steps S501 to S502.

[0126] Step S501: Counting a first quantity value of cache nodes in a write cache linked list.

[0127] In one possible implementation, the first quantity is initialized to start from the head cache node of the write cache linked list and traverse downward through each cache node in sequence. Each time a cache node is traversed, the first quantity value is accumulated by 1 until the tail cache node of the write cache linked list is traversed to obtain the first quantity value.

[0128] Step S502: when the first quantity value is equal to the maximum quantity value, extract the third cache node at the head of the write cache linked list, write the data of the third cache node into the flash memory, and put the third cache node at the end of the read cache linked list.

[0129] It should be noted that the third cache node is the cache node pointed to by the successor pointer of the head node of the written cache linked list.

[0130] In one possible implementation, refer to Figure 6 As shown, Figure 6This is a schematic diagram of placing the third cache node at the end of the read cache linked list provided by an embodiment of the present application. When the first quantity value 10 is equal to the maximum quantity value 10, the third cache node is extracted at the head of the write cache linked list, that is, the rear-drive pointer of the third cache node is set to null, and then the data of the third cache node is written to the flash memory NAND Flash. Finally, the third cache node is placed at the end of the read cache linked list, that is, the rear-drive pointer of the cache node at the end of the read cache linked list points to the third cache node.

[0131] Reference Figure 7 As shown, Figure 7 This is a flowchart before obtaining the free list provided in an embodiment of the present application. Before obtaining the free list, the cache data writing method may also include but is not limited to steps S701 to S702.

[0132] Step S701: Count a first quantity value of cache nodes in a write cache linked list.

[0133] In one possible implementation, the first quantity is initialized to start from the head cache node of the write cache linked list and traverse downward through each cache node in sequence. Each time a cache node is traversed, the first quantity value is accumulated by 1 until the tail cache node of the write cache linked list is traversed to obtain the first quantity value.

[0134] Step S702: when the first quantity value is equal to the maximum quantity value, extract the third cache node at the head of the write cache linked list, write the data of the third cache node into the flash memory, and put the third cache node at the end of the read cache linked list.

[0135] It should be noted that the third cache node is the cache node pointed to by the successor pointer of the head node of the written cache linked list.

[0136] In a possible implementation, when the first quantity value 10 is equal to the maximum quantity value 10, the third cache node is extracted at the head of the write cache linked list, that is, the follower pointer of the third cache node is set to null, and then the data of the third cache node is written to the flash memory NAND Flash, and finally, the third cache node is placed at the end of the read cache linked list, that is, the follower pointer of the cache node at the end of the read cache linked list points to the third cache node.

[0137] Reference Figure 8 As shown, Figure 8 The embodiment of this application provides Figure 2 In the flowchart of step S205, the cache data writing method may include but is not limited to steps S801 to S803.

[0138] Step S801: Determine whether a cache node in the free list exists.

[0139] Specifically, it is determined whether a cache node of the free list exists, that is, whether the free list is an empty list.

[0140] Step S802: when the cache node of the free linked list does not exist, extract the fourth cache node at the head of the read cache linked list, put the fourth cache node at the end of the write cache linked list, and write the target data into the cache space of the fourth cache node.

[0141] It should be noted that the fourth cache node is the cache node pointed to by the successor pointer of the head node of the read cache linked list.

[0142] In one possible implementation, refer to Fig. 9 As shown, Fig. 9 This is a schematic diagram of placing the fourth cache node or the fifth cache node at the end of the write cache linked list provided in an embodiment of the present application. When the cache node of the free linked list does not exist, the fourth cache node is extracted at the head of the read cache linked list, that is, the follower pointer of the fourth cache node is set to null, and then the fourth cache node is placed at the end of the write cache linked list, that is, the follower pointer of the cache node at the end of the read cache linked list points to the fourth cache node. Finally, the data in the cache space of the fourth cache node is cleared, and the target data is written to the cache space of the fourth cache node.

[0143] It should also be noted that the data of each cache node in the read cache linked list are data that have been written to the flash memory NAND Flash, and the data of each cache node in the write cache linked list are data that have not been written to the flash memory NAND Flash. When the cache node in the free linked list does not exist, it means that the cache resources are in short supply. At this time, it is necessary to borrow the cache nodes in the read cache linked list to complete the write operation of the target data, thereby improving the efficiency of cache resource scheduling. At the same time, the reason for not borrowing the cache nodes in the read cache linked list is that the data of the cache nodes in the write cache linked list are data that have not been written to the flash memory NAND Flash. Once the cache nodes in the write cache linked list are borrowed, data loss will occur.

[0144] Step S803: Alternatively, when a cache node of the free list exists, extract the fifth cache node at the head of the free list, put the fifth cache node at the end of the write cache list, and write the target data into the cache space of the fifth cache node.

[0145] It should be noted that the fifth cache node is the cache node pointed to by the successor pointer of the head node of the free linked list.

[0146] In one possible implementation, referring again to Fig. 9As shown, when the cache node of the free linked list exists, the fifth cache node is extracted from the head of the free linked list, that is, the rear-drive pointer of the fifth cache node is set to null, and then the fifth cache node is placed at the end of the write cache linked list, that is, the rear-drive pointer of the cache node at the end of the read cache linked list points to the fifth cache node, and finally the target data is written to the cache space of the fifth cache node.

[0147] It should also be noted that when the cache node in the free list does not exist, it means that there are still cache resources left. At this time, it is necessary to directly use the cache node in the free list to complete the write operation of the target data without borrowing the cache node in the read cache list. Therefore, when responding to a read request, data can be read from the cache node in the read cache list first, without reading data from the flash memory, thereby improving read and write performance.

[0148] Furthermore, before writing the target data to the target cache node (eg, the first cache node, the second cache node, the third cache node, the fourth cache node, the fifth cache node, etc.), steps A to B may also be included but are not limited to.

[0149] Step A: According to the starting sector address, determine whether other data spaces of the target cache node are continuous with its cache space.

[0150] Among them, the other data space may be a pointer space.

[0151] In one possible implementation, the current starting sector address is 0x12345, and the end address of the pointer space is 0x10000, and the end address of the pointer space is subtracted from the starting sector address to obtain a difference address of 0x02345. Based on the difference address 0x02345, it is determined whether other data spaces of the target cache node are continuous with its cache space.

[0152] Step B: When the other data spaces of the target cache node are not continuous with the cache space, pre-read the data to be filled from the flash memory NAND Flash, and fill the data to be filled between the other data spaces of the target cache node and its cache space.

[0153] In a possible implementation, according to the difference address 0x02345>1, it means that the other data space and the cache space of the target cache node are discontinuous, and the data to be filled is pre-read from the flash memory NAND Flash, and the data to be filled is filled between the other data space of the target cache node and its cache space, that is, filled to [0x10000, 0x12345], thereby avoiding data holes in the process of writing target data.

[0154] Reference Fig.10 As shown, Fig.10The embodiment of this application provides Figure 1 In the flowchart of step S102, the cache data writing method may include but is not limited to steps S1001 to S1006.

[0155] Step S1001: Obtain the total page address interval of the cache logic space, and determine whether the target page address is in the total page address interval.

[0156] In one possible implementation, the target page code address 27 is compared with the maximum and minimum values ​​of the total page code address range [0,100] of the cache logical space, respectively, to determine that the target page code address 27 is greater than the minimum value 0 of the total page code address range, and the target page code address 27 is less than the maximum value 100 of the total page code address range, that is, the target page code address 27 is within the total page code address range [0,100], indicating that the write operation of this write request does not exceed the writable range of the cache logical space.

[0157] Step S1002: when the target page address is within the total page address interval, obtaining a target writing scenario of the target data, and determining whether the target writing scenario complies with a first preset writing scenario.

[0158] In a possible implementation, when the target page address 27 is within the total page address interval [0, 100], a target write scenario {dont_use_cache: 0; cache_sort=0} of the target data is obtained, and it is determined whether the target write scenario meets the first preset write scenario.

[0159] The first preset writing scenario may be a scenario where target data needs to be burned into an embedded microprocessor. In the scenario where data is burned into the embedded microprocessor, not calling the cache can greatly improve the speed of data burning.

[0160] It should be noted that the dont_use_cache field in the above-mentioned target write scenario is used as a judgment field for whether it complies with the first preset write scenario. For example: when the value of dont_use_cache is equal to 1, it means that the target write scenario complies with the first preset write scenario. When the value of dont_use_cache is equal to 0, it means that the target write scenario does not comply with the first preset write scenario.

[0161] Step S1003: When the target writing scenario matches the first preset writing scenario, it is determined that the writing request does not hit the cache.

[0162] In a possible implementation, when the target write scenario is {dont_use_cache:1; cache_sort=0}, that is, the value of dont_use_cache is equal to 1, it means that the target write scenario meets the first preset write scenario, and it is determined that the write request does not hit the cache.

[0163] Step S1004: when the target writing scene does not conform to the first preset writing scene, determining whether the target writing scene conforms to the second preset writing scene.

[0164] In a possible implementation, when the target writing scenario is {dont_use_cache:0; cache_sort=0}, that is, the value of dont_use_cache is equal to 0, it indicates that the target writing scenario does not conform to the first preset writing scenario, and further, it is determined whether the target writing scenario conforms to the second preset writing scenario.

[0165] Among them, the second preset write scenario can be represented as a scenario in which a large amount of target data is used to perform write operations. In this scenario in which a large amount of target data is used to perform write operations, calling the cache can process the target data in large quantities in a timely manner, avoid task congestion, significantly reduce write delays, and subsequently reduce response delays for read requests.

[0166] It should be noted that the cache_sort field in the above-mentioned target write scenario is used as a judgment field for whether it complies with the second preset write scenario. For example: when the value of cache_sort is equal to 1, it means that the target write scenario complies with the second preset write scenario. When the value of cache_sort is equal to 0, it means that the target write scenario does not comply with the second preset write scenario.

[0167] Step S1005: When the target writing scenario meets the second preset writing scenario, it is determined that the writing request hits the cache.

[0168] In a possible implementation, when the target write scenario is {dont_use_cache:0; cache_sort=1}, that is, the value of dont_use_cache is equal to 0 and cache_sort=1, it means that the target write scenario does not conform to the first preset write scenario, but the target write scenario conforms to the second preset write scenario, and it is determined that the write request hits the cache.

[0169] Step S1006: When the target writing scenario does not conform to the second preset writing scenario, it is determined that the writing request does not hit the cache.

[0170] In a possible implementation, when the target write scenario is {dont_use_cache:0; cache_sort=0}, that is, the value of dont_use_cache is equal to 0 and cache_sort=0, it means that the target write scenario does not conform to the first preset write scenario, and the target write scenario does not conform to the second preset write scenario, and it is determined that the write request does not hit the cache.

[0171] In the second aspect, a cache data reading method in an embodiment of the present application is described.

[0172] Reference Fig.11 As shown, Fig.11 1 is a flowchart of a cache data reading method provided in an embodiment of the present application. The cache data reading method may include but is not limited to steps S1101 to S1104.

[0173] Step S1101: in response to a read request for target data, obtaining a target page address of a read cache logical space.

[0174] The specific description of the target page address has been described in the above embodiments and will not be repeated here.

[0175] In a possible implementation, the capacity of a sector is 512 bytes, and the capacity of a logical page is 2048 bytes, then the logical mapping coefficient is 2048 / 512=4, that is, a logical page is mapped to 4 sectors, and then responds to a write request for the target data and parses the write request to obtain a starting sector address sector_addr of 100 and a sector length sector_len of 10, then the starting page code address = ALIGN_DOWN(100, 4) / 4=25, the ending page code address = 25+[ALIGN_UP(10 / 4)-1]=27, then the target page code address of the write cache logical space has a value range of [25,27], that is, the target page code address can be 25, the target page code address can also be 26, and the target page code address can also be 27, which is not specifically limited in this application.

[0176] Step S1102: Determine whether the read request hits the cache according to the target page address.

[0177] Step S1103: When the read request does not hit the cache, the target data is read from the flash memory.

[0178] In one possible implementation, the target page code address 56 is compared with the maximum value and the minimum value of the total page code address interval [0,100] of the cache logical space, respectively, to determine that the target page code address 56 is greater than the minimum value 0 of the total page code address interval, and the target page code address 56 is less than the maximum value 100 of the total page code address interval, that is, the target page code address 56 is within the total page code address interval [0,100], indicating that the read operation of this read request does not exceed the readable range of the cache logical space, and then the target read scenario of the target data is obtained, and it is determined whether the target read scenario meets the first preset read scenario. When the target read scenario meets the first preset read scenario, it is determined that the read request does not hit the cache; when the target read scenario does not meet the first preset read scenario, it is determined that the read request hits the cache, wherein the first preset read scenario can be represented as a scenario of reading the target data from an embedded microprocessor. In the scenario of reading the target data from the embedded microprocessor, not calling the cache can greatly improve the data reading speed.

[0179] In one possible implementation, the target page code address 90 is compared with the maximum value and the minimum value of the total page code address interval [0, 100] of the cache logical space, respectively, to determine that the target page code address 90 is greater than the minimum value 0 of the total page code address interval, and the target page code address 90 is less than the maximum value 100 of the total page code address interval, that is, the target page code address 90 is within the total page code address interval [0, 100], indicating that the read operation of this read request does not exceed the readable range of the cache logical space, and then the target read scenario of the target data is obtained, and it is determined whether the target read scenario meets the second preset read scenario. When the target read scenario meets the second preset read scenario, it is determined that the read request does not hit the cache; when the target read scenario does not meet the second preset read scenario, it is determined that the read request hits the cache, wherein the second preset read scenario can be represented as a scenario of reading target data in large batches. In this scenario of reading target data in large batches, not calling the cache can avoid occupying a large amount of cache resources for a long time, thereby freeing up the cache to process other data in time and avoiding task congestion.

[0180] In one possible implementation, the target page code address 51 is compared with the maximum and minimum values ​​of the total page code address interval [0, 50] of the cache logical space, respectively, to determine that the target page code address 51 is greater than the minimum value 0 of the total page code address interval, and the target page code address 51 is greater than the maximum value 50 of the total page code address interval, that is, the target page code address 51 is not within the total page code address interval [0, 50], indicating that the read operation of this read request exceeds the readable range of the cache logical space, and the read operation is directly terminated.

[0181] Step S1104: When the read request hits the cache, the target data is read from the flash memory or the read cache linked list according to the target page address, the storage data of the corresponding cache node in the write cache linked list, and the storage data of the corresponding cache node in the read cache linked list.

[0182] Specifically, when a read request hits the cache, the target data is read from the flash memory NAND Flash or the read cache linked list cache_read_list according to the target page code address, the storage data of the corresponding cache node in the write cache linked list cache_write_list, and the storage data of the corresponding cache node in the read cache linked list cache_read_list.

[0183] Reference Fig.12 As shown, Fig.12 The embodiment of this application provides Fig.11 In the flowchart of step S1104, the cache data reading method may include but is not limited to steps S1201 to S1207.

[0184] Step S1201: Determine whether there is a sixth cache node in the write cache linked list.

[0185] The cache space of the sixth cache node stores the target data.

[0186] In one possible implementation, each cache node in the write cache linked list is traversed and the corresponding cache data is read, and the cache data of each cache node is compared with the target data. If the cache data of the currently traversed cache node is the same as the target data, it means that the sixth cache node is found, and the traversal is stopped; or, when the last cache node of the write cache linked list is traversed and its corresponding cache data is still different from the target data, it means that the sixth cache node is not found, and the traversal is stopped.

[0187] Step S1202: When there is a sixth cache node in the write cache linked list, determine whether the storage location of the target data covers the read address interval based on the target page address.

[0188] In one possible implementation, when there is a sixth cache node in the write cache linked list, it is determined based on the target page code address whether the storage location of the target data covers the read address interval. For example, when the target page code address can be 1, the target page code address can also be 2, that is, the read address interval of the cache logical space is [1,2], and then it is determined whether the storage address of the target data covers the read address interval.

[0189] Step S1203: when the storage location of the target data covers the read address interval, the target data is read from the sixth cache node.

[0190] In a possible implementation, the read address interval of the cache logic space is [1,2]. Fig.18 As shown, Fig.18 This is a schematic diagram of a scenario in which the storage location of the target data in the sixth cache node covers the read address interval provided by an embodiment of the present application. It can be seen that the storage location of the target data in the sixth cache node is the first 3 sectors in the sixth cache node, that is, the storage page code address interval of the target data in the sixth cache node is [0,2], and [0,2] just covers the read address interval of [1,2]. The target data is read directly from the sixth cache node, thereby improving the reading speed.

[0191] Step S1204: when the storage address of the target data does not cover the read address interval, the target data is read from the flash memory.

[0192] In a possible implementation, the read address interval of the cache logic space is [2, 3]. Fig.19 As shown, Fig.19 This is a schematic diagram of a scenario in which the storage location of the target data in the sixth cache node does not cover the read address interval provided in an embodiment of the present application. It can be seen that the target data in the sixth cache node is stored in the first three sectors in the sixth cache node, that is, the storage page code address interval of the target data in the sixth cache node is [0,2], and [0,2] does not cover the read address interval [2,3], so the target data is read in the flash memory.

[0193] Step S1205: When the sixth cache node does not exist in the write cache linked list, determine whether the seventh cache node exists in the read cache linked list.

[0194] The cache space of the seventh cache node stores the target data.

[0195] In one possible implementation, when the sixth cache node does not exist in the write cache linked list, each cache node in the read cache linked list is traversed and the corresponding cache data is read, and the cache data of each cache node is compared with the target data. When the cache data of the currently traversed cache node is the same as the target data, it means that the seventh cache node is found, and then the traversal is stopped; or, when the traversal reaches the last cache node in the write cache linked list, its corresponding cache data is still different from the target data, it means that the seventh cache node is not found, and then the traversal is stopped.

[0196] Step S1206: when there is a seventh cache node in the read cache linked list, the target data is read from the seventh cache node.

[0197] In a possible implementation, when there is a seventh cache node in the read cache linked list, the target data is directly read from the seventh cache node, thereby improving the reading efficiency and reducing the reading delay.

[0198] Step S1207: when the seventh cache node does not exist in the read cache linked list, the target data is read from the flash memory, and a cache node corresponding to the target data is added at the end of the read cache linked list.

[0199] In one possible implementation, when the seventh cache node does not exist in the read cache linked list, the target data is read from the flash memory, and a cache node corresponding to the target data is added to the end of the read cache linked list, so that the target data can be read directly from the read cache linked list the next time the target data is requested, thereby improving the reading efficiency and reducing the reading delay.

[0200] Reference Fig.13 As shown, Fig.13 This is a flowchart of adding a cache node at the end of a read cache linked list provided by an embodiment of the present application. The method of adding a cache node at the end of a read cache linked list may include but is not limited to steps S1301 to S1303.

[0201] Step S1301: Obtain a free list and determine whether a cache node in the free list exists.

[0202] Specifically, a free list is obtained, and it is determined whether a cache node of the free list exists, that is, whether the free list is an empty list is determined.

[0203] Step S1302: When the cache node of the free linked list does not exist, the eighth cache node is extracted from the head of the read cache linked list, the target data is read into the cache space of the eighth cache node in the flash memory, and the eighth cache node is placed at the end of the read cache linked list.

[0204] It should be noted that the eighth cache node is the cache node pointed to by the successor pointer of the head node of the read cache linked list.

[0205] In one possible implementation, when the cache node of the free linked list does not exist, the eighth cache node is extracted at the head of the read cache linked list, that is, the follower pointer of the eighth cache node is set to null, and then the data in the cache space of the eighth cache node is cleared, and the target data is read into the cache space of the eighth cache node in the flash memory. Finally, the eighth cache node is placed at the end of the write cache linked list, that is, the follower pointer of the cache node at the end of the read cache linked list points to the eighth cache node.

[0206] It should also be noted that the data of each cache node in the read cache linked list are data that have been written to the flash memory NAND Flash, and the data of each cache node in the write cache linked list are data that have not been written to the flash memory NAND Flash. When the cache node in the free linked list does not exist, it means that the cache resources are in short supply. At this time, it is necessary to borrow the cache nodes in the read cache linked list to complete the write operation of the target data, thereby improving the efficiency of cache resource scheduling. At the same time, the reason for not borrowing the cache nodes in the read cache linked list is that the data of the cache nodes in the write cache linked list are data that have not been written to the flash memory NAND Flash. Once the cache nodes in the write cache linked list are borrowed, data loss will occur.

[0207] Step S1303: Alternatively, when a cache node of the free list exists, the ninth cache node is extracted from the head of the free list, and the target data is read into the cache space of the ninth cache node in the flash memory, and the ninth cache node is placed at the end of the read cache list.

[0208] It should be noted that the ninth cache node is the cache node pointed to by the successor pointer of the head node of the free linked list.

[0209] In one possible implementation, when a cache node of the free linked list exists, the ninth cache node is extracted from the head of the free linked list, i.e., the follower pointer of the ninth cache node is set to null, and then the target data is read into the cache space of the ninth cache node in the flash memory, and finally the ninth cache node is placed at the end of the write cache linked list, i.e., the follower pointer of the cache node at the end of the read cache linked list points to the ninth cache node.

[0210] Reference Fig.14 As shown, Fig.14 The embodiment of this application provides Fig.11 In the flowchart of step S1102, the cache data reading method may include but is not limited to steps S1401 to S1404.

[0211] Step S1401: Obtain the total page address interval of the cache logic space, and determine whether the target page address is in the total page address interval.

[0212] In one possible implementation, the target page code address 27 is compared with the maximum and minimum values ​​of the total page code address range [0,100] of the cache logical space, respectively, to determine that the target page code address 27 is greater than the minimum value 0 of the total page code address range, and the target page code address 27 is less than the maximum value 100 of the total page code address range, that is, the target page code address 27 is within the total page code address range [0,100], indicating that the write operation of this write request does not exceed the writable range of the cache logical space.

[0213] Step S1402: when the target page address is within the total page address interval, obtaining a target reading scenario of the target data, and determining whether the target reading scenario conforms to a first preset reading scenario.

[0214] In a possible implementation, when the target page address 27 is within the total page address interval [0, 100], a target read scenario {dont_use_cache: 0; cache_sort=0} of the target data is obtained, and it is determined whether the target read scenario meets the first preset read scenario.

[0215] The first preset reading scenario may be represented as a scenario of reading target data from an embedded microprocessor. In the scenario of reading target data from an embedded microprocessor, not calling the cache can greatly improve the speed of data reading.

[0216] It should be noted that the dont_use_cache field in the above-mentioned target reading scenario is used as a judgment field for whether it complies with the first preset reading scenario. For example, when the value of dont_use_cache is equal to 1, it means that the target reading scenario complies with the first preset reading scenario. When the value of dont_use_cache is equal to 0, it means that the target reading scenario does not comply with the first preset reading scenario.

[0217] Step S1403: When the target reading scenario matches the first preset reading scenario, it is determined that the reading request does not hit the cache.

[0218] In a possible implementation, when the target read scenario is {dont_use_cache:1}, that is, the value of dont_use_cache is equal to 1, it means that the target read scenario meets the first preset read scenario, and it is determined that the read request does not hit the cache.

[0219] Step S1404: when the target reading scenario does not conform to the first preset reading scenario, determining that the reading request hits the cache.

[0220] In a possible implementation, when the target read scenario is {dont_use_cache:0}, that is, the value of dont_use_cache is equal to 0, it means that the target read scenario does not meet the first preset read scenario, and it is determined that the read request does not hit the cache.

[0221] In a third aspect, the present application also provides a cache data writing system, referring to Fig.15 , Fig.15 This is a schematic diagram of the structure of a cache data writing system provided in an embodiment of the present application. The cache data writing system 1500 includes:

[0222] The data acquisition module 1501 is used to respond to a write request of target data and acquire a target page address of a write cache logical space;

[0223] A cache hit determination module 1502, the cache hit determination module 1502 is used to determine whether the write request hits the cache according to the target page address;

[0224] The data writing module 1503 is used to write the target data into the flash memory when the write request does not hit the cache;

[0225] In addition, the data write module 1503 is also used to write the target data to the cache space of the cache node corresponding to the write cache linked list or the read cache linked list according to the target page number address when the write request hits the cache, wherein the cache node in the write cache linked list or the read cache linked list is mapped to the target page number address.

[0226] The cache data writing system 1500 and the cache data writing method are based on the same inventive concept. The above process describes the cache data writing system 1500 of the embodiment of the present application. The data acquisition module 1501 responds to the write request of the target data and obtains the target page address of the write cache logical space. Then, the cache hit determination module 1502 determines whether the write request hits the cache according to the target page address. Then, when the write request does not hit the cache, the data writing module 1503 writes the target data into the flash memory. When the write request hits the cache, the data writing module 1503 determines whether the write request hits the cache according to the target page address. The target data is written to the cache space of the cache node corresponding to the write cache linked list or the read cache linked list, wherein the cache node in the write cache linked list or the read cache linked list is mapped to the target page number address, so that when the write request hits the cache, through the write call design between multiple cache linked lists and the mapping relationship between the cache logic space and the cache linked list, there is no need to directly call the flash memory each time a new write operation is executed, thereby reducing the number of writes to the flash memory, reducing the write amplification effect of the flash memory, improving the durability of the flash memory, and also improving the data writing speed and reducing the latency of the data response.

[0227] In a third aspect, the present application also provides a cache data reading system, referring to Fig.16 , Fig.16 This is a schematic diagram of the structure of a cache data reading system provided in an embodiment of the present application. The cache data reading system 1600 includes:

[0228] The data acquisition module 1601 is used to obtain the target page address of the read cache logical space in response to a read request of the target data;

[0229] A cache hit determination module 1602, the cache hit determination module 1602 is used to determine whether the read request hits the cache according to the target page address;

[0230] The data reading module 1603 is used to read the target data in the flash memory when the read request does not hit the cache;

[0231] Furthermore, the data reading module 1603 is further configured to store data of the cache nodes corresponding to the write cache linked list and the read cache linked list when a read request hits the cache.

[0232] The above-mentioned cache data reading system 1600 and the above-mentioned cache data reading method are based on the same inventive concept. The above-mentioned process describes the cache data reading system 1600 of an embodiment of the present application. The data acquisition module 1601 responds to the read request of the target data to obtain the target page code address of the read cache logical space. Then, the cache hit determination module 1602 determines whether the read request hits the cache according to the target page code address. When the read request does not hit the cache, the data reading module 1603 reads the target data in the flash memory. When the read request hits the cache, the data reading module 1603 reads the target data in the flash memory or the read cache linked list according to the storage data of the cache nodes corresponding to the write cache linked list and the read cache linked list. Then, when the read request hits the cache, through the read call design between multiple cache linked lists, there is no need to directly call the flash memory each time a new read operation is executed, thereby improving the data reading speed and reducing the latency of data response.

[0233] The embodiment of the present application also provides an electronic device, the electronic device includes a memory and a processor, the memory stores a computer program, and the processor implements the above cache data writing method and / or cache data reading method when executing the computer program. The electronic device can be any smart terminal including a mobile phone, a tablet computer, a car computer, etc.

[0234] See also Fig.17 , Fig.17 : is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application, and the electronic device includes:

[0235] The processor 1701 may be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the cache data writing method and / or cache data reading method provided in the embodiments of the present application;

[0236] The memory 1702 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 1702 can store an operating system and other applications. When the technical solution provided in the embodiments of this specification is implemented by software or firmware, the relevant program code is stored in the memory 1702, and the processor 1701 calls and executes the cache data writing method and / or cache data reading method provided in the embodiments of this application;

[0237] Input / output interface 1703, used to implement information input and output;

[0238] Communication interface 1704, used to realize communication interaction between the device and other devices, which can be realized through wired mode (such as USB, network cable, etc.) or wireless mode (such as mobile network, WIFI, Bluetooth, etc.);

[0239] A bus 1705 that transmits information between various components of the device (e.g., the processor 1701, the memory 1702, the input / output interface 1703, and the communication interface 1704);

[0240] The processor 1701 , the memory 1702 , the input / output interface 1703 and the communication interface 1704 are connected to each other in communication within the device via the bus 1705 .

[0241] An embodiment of the present application further provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the cache data writing method and / or cache data reading method provided in the embodiment of the present application are provided.

[0242] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0243] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0244] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0245] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0246] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0247] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0248] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0249] In the several embodiments provided in the present application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0250] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0251] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0252] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-accessible storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0253] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A method for writing cache data, characterized in that: include: In response to a write request for target data, obtaining a target page address of a write cache logical space; Determining whether the write request hits the cache according to the target page address; When the write request does not hit the cache, writing the target data into the flash memory; When the write request hits the cache, the target data is written to the cache space of the cache node corresponding to the write cache linked list or the read cache linked list according to the target page number address, wherein the cache node in the write cache linked list or the read cache linked list is mapped to the target page number address; The process of determining whether the write request hits the cache according to the target page address includes the following steps: Obtaining a total page address interval of the cache logic space, and determining whether the target page address is within the total page address interval; When the target page address is within the total page address interval, obtaining a target writing scenario of the target data, and determining whether the target writing scenario conforms to a first preset writing scenario; When the target writing scenario matches the first preset writing scenario, determining that the writing request does not hit the cache; When the target writing scene does not conform to the first preset writing scene, determining whether the target writing scene conforms to a second preset writing scene; When the target writing scenario matches the second preset writing scenario, determining that the writing request hits the cache; When the target writing scenario does not conform to the second preset writing scenario, it is determined that the writing request does not hit the cache.

2. The cache data writing method according to claim 1, characterized in that: The step of writing the target data into a cache space of a cache node corresponding to a write cache linked list or a read cache linked list according to the target page address includes: According to the target page number address, extract the first cache node at the page number mapping position corresponding to the write cache linked list, and determine whether there is a node cache corresponding to the target page number address in the cache space of the first cache node; When the cache space of the first cache node contains a node cache corresponding to the target page address, the first cache node is placed at the end of the write cache linked list, and the target data is written into the cache space of the first cache node; When the cache space of the first cache node does not have a node cache corresponding to the target page number address, extract the second cache node at the page number mapping position corresponding to the read cache linked list according to the target page number address, and determine whether the cache space of the second cache node has a node cache corresponding to the target page number address; When the cache space of the second cache node contains a node cache corresponding to the target page address, the second cache node is placed at the end of the write cache linked list, and the target data is written into the cache space of the second cache node; When the cache space of the second cache node does not have a node cache corresponding to the target page number address, a free list is obtained, and the target data is written to the cache space of the corresponding cache node according to the cache node in the free list.

3. The cache data writing method according to claim 2, characterized in that: Before placing the second cache node at the end of the write cache linked list or before obtaining the free linked list, the cache data writing method further includes: Counting a first quantity value of cache nodes in the write cache linked list; When the first quantity value is equal to the maximum quantity value, the third cache node is extracted from the head of the write cache linked list, the data of the third cache node is written into the flash memory, and the third cache node is placed at the end of the read cache linked list.

4. The cache data writing method according to claim 2, characterized in that: The step of writing the target data into the cache space of the corresponding cache node according to the cache node of the free linked list includes: Determine whether a cache node of the free list exists; When the cache node of the free linked list does not exist, extracting the fourth cache node at the head of the read cache linked list, placing the fourth cache node at the end of the write cache linked list, and writing the target data into the cache space of the fourth cache node; Alternatively, when a cache node of the free linked list exists, the fifth cache node is extracted from the head of the free linked list, and the fifth cache node is placed at the end of the write cache linked list, and the target data is written to the cache space of the fifth cache node.

5. A cache data reading method, characterized in that: include: In response to a read request for target data, obtaining a target page address of a read cache logical space; Determining whether the read request hits the cache according to the target page address; When the read request does not hit the cache, reading the target data in the flash memory; When the read request hits the cache, the target data is read in the flash memory or the read cache linked list according to the target page address, the storage data of the corresponding cache node in the write cache linked list, and the storage data of the corresponding cache node in the read cache linked list; The process of determining whether the read request hits the cache according to the target page address includes the following steps: Obtaining a total page address interval of the cache logic space, and determining whether the target page address is within the total page address interval; When the target page address is within the total page address interval, obtaining a target reading scenario of the target data, and determining whether the target reading scenario conforms to a first preset reading scenario; When the target reading scenario meets the first preset reading scenario, determining that the reading request does not hit the cache; When the target reading scenario does not conform to the first preset reading scenario, it is determined that the reading request hits the cache.

6. The cache data reading method according to claim 5, characterized in that: The corresponding reading of the target data in the flash memory or the read cache linked list according to the target page address, the storage data of the corresponding cache node in the write cache linked list, and the storage data of the corresponding cache node in the read cache linked list includes: Determine whether there is a sixth cache node in the write cache linked list, wherein the cache space of the sixth cache node stores the target data; When the sixth cache node exists in the write cache linked list, determining whether the storage location of the target data covers a read address interval based on the target page address; When the storage location of the target data covers the read address interval, reading the target data from the sixth cache node; When the storage location of the target data does not cover the read address interval, reading the target data in the flash memory; When the sixth cache node does not exist in the write cache linked list, determining whether there is a seventh cache node in the read cache linked list, wherein the cache space of the seventh cache node stores the target data; When the seventh cache node exists in the read cache linked list, reading the target data from the seventh cache node; When the seventh cache node does not exist in the read cache linked list, the target data is read from the flash memory, and a cache node corresponding to the target data is added at the end of the read cache linked list.

7. The cache data reading method according to claim 6, characterized in that: The step of adding a cache node corresponding to the target data stored at the end of the read cache linked list includes: Obtain a free list and determine whether a cache node of the free list exists; When the cache node of the free linked list does not exist, extract the eighth cache node at the head of the read cache linked list, read the target data into the cache space of the eighth cache node in the flash memory, and put the eighth cache node at the end of the read cache linked list; Alternatively, when the cache node of the free list exists, the ninth cache node is extracted from the head of the free list, the target data is read into the cache space of the ninth cache node in the flash memory, and the ninth cache node is placed at the end of the read cache list.

8. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the cache data writing method described in any one of claims 1 to 4 and / or the cache data reading method described in any one of claims 5 to 7 are implemented.

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