Address translation method and apparatus, electronic device, and storage medium

Abstract

An address conversion method and device, electronic equipment and storage medium. The method is applied to an address conversion device, which includes multiple groups of conversion buffers, each group being configured to store page table information for converting a virtual address into a physical address. The method comprises: in response to obtaining a first virtual address conversion request, determining a target conversion buffer from the multiple groups of conversion buffers according to a first mapping algorithm, the first virtual address conversion request including an object virtual address; accessing the page table information in the target conversion buffer to convert the object virtual address into an object physical address. The method further comprises: obtaining access frequency information for each group of the multiple groups of conversion buffers; determining whether the first mapping algorithm needs to be updated according to the access frequency information; and in response to the first mapping algorithm needing to be updated, updating the mapping algorithm to a second mapping algorithm. The method can alleviate uneven allocation of conversion buffer resources for virtual address conversion requests and improve the utilization rate of conversion buffer resources.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to an address translation method and apparatus, an electronic device, and a storage medium. BACKGROUND

[0002] Currently, devices requiring virtual addressing, such as Central Processing Unit (CPU) chips, Graphics Processing Unit (GPU), etc., usually have specific address translation apparatuses responsible for virtual address to physical address translation. For example, a CPU has a Memory Management Unit (MMU) responsible for virtual address to physical address translation. SUMMARY

[0003] At least one embodiment of the present disclosure provides an address translation method applied to an address translation apparatus, the address translation apparatus including a plurality of sets of translation buffers, each set of translation buffers including first page table information for translating a virtual address to a physical address, the method including: in response to obtaining a first virtual address translation request, determining a target translation buffer from the plurality of sets of translation buffers according to a first mapping algorithm, the first virtual address translation request including an object virtual address; and accessing the first page table information in the target translation buffer to translate the object virtual address to an object physical address, the method further including: obtaining access frequency information for each set of the plurality of sets of translation buffers; determining whether the first mapping algorithm needs to be updated according to the access frequency information; and in response to the first mapping algorithm needing to be updated, updating the first mapping algorithm to a second mapping algorithm.

[0004] For example, in the address translation method provided by some embodiments of the present disclosure, the address translation apparatus further includes a multi-level page table query module including second page table information, and the accessing the first page table information in the target translation buffer to translate the object virtual address to the object physical address includes: accessing the first page table information in the target translation buffer to determine whether there is first target page table information matching the first virtual address translation request in the first page table information; in response to there being no first target page table information in the target translation buffer, providing the first virtual address translation request to the multi-level page table query module; determining whether there is second target page table information matching the first virtual address translation request in the second page table information; and in response to there being no second target page table information matching the first virtual address translation request in the second page table information, translating the object virtual address to the object physical address based on translation information provided by an external memory.

[0005] For example, in the address conversion method provided by some embodiments of the present disclosure, the first page table information includes a plurality of page table entries, each page table entry corresponding to a physical page, the second page table information includes a plurality of page tables, each page table includes a plurality of page directory entries, each page directory entry is used to point to the physical address of a next level page table, and each page directory entry in the last level page table in the plurality of page tables is used to point to a page table entry in the first page table information.

[0006] For example, in the address conversion method provided by some embodiments of the present disclosure, determining whether the second page table information has second target page table information matching the first virtual address conversion request includes: based on the object virtual address and the base address, obtaining a first page table read address of at least one page table in the plurality of page tables; and based on the first page table read address, determining whether the second page table information has second target page table information matching the first virtual address conversion request.

[0007] For example, in the address conversion method provided by some embodiments of the present disclosure, in response to the second page table information not having the second target page table information matching the first virtual address conversion request, converting the object virtual address into the object physical address based on the conversion information provided by the external memory includes: in response to the second page table information not having the second target page table information matching the first virtual address conversion request, determining whether a merge signal is valid; in response to the merge signal being valid, comparing whether the first page table read address is the same as a second page table read address of a second virtual address conversion request before the first virtual address conversion request; in response to the first page table read address being the same as the second page table read address, merging the first virtual address conversion request with the second virtual address conversion request, waiting for the conversion information provided by the external memory in response to the second virtual address conversion request; and converting the object virtual address into the object physical address based on the conversion information.

[0008] For example, in the address conversion method provided by some embodiments of the present disclosure, in response to the second page table information not having the second target page table information matching the first virtual address conversion request, converting the object virtual address into the object physical address based on the conversion information provided by the external memory further includes: in response to the first page table read address being different from the second page table read address, providing a page table read request based on the first virtual address conversion request to the external memory to obtain the conversion information from the external memory; and updating the merge signal to be invalid.

[0009] For example, in the address conversion method provided by some embodiments of the present disclosure, in response to the second page table information not existing the second target page table information matching the first virtual address conversion request, the object virtual address is converted into the object physical address based on the conversion information provided by the external memory, and the method further includes: in response to the merge signal being invalid, providing a page table read request based on the first virtual address conversion request to the external memory to obtain the conversion information from the external memory; and updating the merge signal to valid.

[0010] For example, in the address conversion method provided by some embodiments of the present disclosure, in response to the second page table information not existing the second target page table information matching the first virtual address conversion request, the object virtual address is converted into the object physical address based on the conversion information provided by the external memory, and the method further includes: in response to receiving the conversion information provided by the external memory in response to the second virtual address conversion request, updating the merge signal to invalid.

[0011] For example, in the address conversion method provided by some embodiments of the present disclosure, the page table read request includes: a page table read address of the virtual address conversion request, an object virtual address, and a hardware access unit identifier providing the virtual address conversion request, and the page table read address is obtained based on a base address and page directory entry data of at least one level of page table in the multi-level page table.

[0012] For example, in the address conversion method provided by some embodiments of the present disclosure, accessing the first page table information in the target conversion buffer to convert the object virtual address into the object physical address includes: accessing the first page table information in the target conversion buffer to determine whether there is a target page table entry in the first page table information matching the object virtual address conversion request; in response to there being a target page table entry in the first page table information matching the object virtual address conversion request, determining the object physical address corresponding to the object virtual address based on the target page table entry and an intra-page offset indicated by the object virtual address.

[0013] For example, in the address conversion method provided by some embodiments of the present disclosure, the conversion information includes the target page table entry.

[0014] For example, in the address conversion method provided by some embodiments of the present disclosure, obtaining the access frequency information of each group of the plurality of groups of conversion buffers includes: counting the number of accesses to each group of the plurality of groups of conversion buffers to obtain a count value of each group of the plurality of groups of conversion buffers within a preset time period.

[0015] For example, in the address conversion method provided by some embodiments of the present disclosure, determining whether the first mapping algorithm needs to be updated according to the access frequency information comprises: calculating an average access value of the count values of the plurality of groups of translation buffers based on the count values of each group of the plurality of groups of translation buffers; obtaining an allowed access deviation; calculating an effective access rate of the plurality of groups of translation buffers based on the allowed access deviation and the average access value; and determining whether the first mapping algorithm needs to be updated based on the effective access rate.

[0016] For example, in the address conversion method provided by some embodiments of the present disclosure, calculating an effective access rate of the plurality of groups of translation buffers based on the allowed access deviation and the average access value comprises: calculating an access deviation value of each group of the plurality of groups of translation buffers based on the allowed access deviation; calculating an effective utilization indication value of each group of the plurality of groups of translation buffers based on the access deviation value, wherein for each group of the plurality of groups of translation buffers, the effective utilization indication value of the translation buffer is set to a first preset value in response to a sum of the access deviation value and the count value being greater than or equal to the average access value, and the effective utilization indication value of the translation buffer is set to a second preset value in response to the sum of the access deviation value and the count value being less than the average access value; and taking an average value of the effective utilization indication values of the plurality of groups of translation buffers as the effective access rate.

[0017] For example, in the address conversion method provided by some embodiments of the present disclosure, determining whether the first mapping algorithm needs to be updated based on the effective access rate comprises: determining that the first mapping algorithm does not need to be updated in response to the effective access rate being greater than or equal to a preset access rate; and determining that the first mapping algorithm needs to be updated in response to the effective access rate being less than the preset access rate.

[0018] For example, in the address conversion method provided by some embodiments of the present disclosure, the first mapping algorithm comprises determining the target translation buffer according to a first target bit of the object virtual address in the virtual address conversion request, and the second mapping algorithm comprises determining the target translation buffer according to a second target bit of the object virtual address in the virtual address conversion request, wherein the first target bit and the second target bit are different.

[0019] For example, in the address conversion method provided by some embodiments of the present disclosure, the first target bit comprises a plurality of first bit positions in the object virtual address in succession, and the second target bit comprises a plurality of second bit positions in the object virtual address in succession.

[0020] The address conversion device provided by some embodiments of the present disclosure comprises: an address conversion module comprising a plurality of sets of conversion buffers; an arbitration module configured to determine a target conversion buffer from the plurality of sets of conversion buffers according to a first mapping algorithm in response to obtaining a first virtual address conversion request, the first virtual address conversion request comprising an object virtual address; each set of the plurality of sets of conversion buffers is configured to store first page table information for converting the object virtual address into an object physical address; the address conversion module is configured to access the first page table information in the target conversion buffer to convert the object virtual address into the object physical address; the address conversion device further comprises an address conversion performance monitoring module configured to: obtain access frequency information of each set of the plurality of sets of conversion buffers; determine whether the first mapping algorithm needs to be updated according to the access frequency information; and in response to the first mapping algorithm needing to be updated, update the mapping algorithm to a second mapping algorithm.

[0021] For example, in the address conversion device provided by some embodiments of the present disclosure, further comprising: a multi-level page table query module comprising second page table information; the address conversion module is configured to access the first page table information in the target conversion buffer to determine whether there is first target page table information matching the first virtual address conversion request in the first page table information; in response to the first target page table information not existing in the target conversion buffer, provide the first virtual address conversion request to the multi-level page table query module; the multi-level page table query module is configured to: receive the first virtual address conversion request provided by the address conversion module; determine whether there is second target page table information matching the first virtual address conversion request in the second page table information; and in response to the second target page table information not existing in the second page table information, obtain conversion information provided by an external memory, the conversion information being used to convert the object virtual address into the object physical address.

[0022] For example, in the address conversion device provided by some embodiments of the present disclosure, the first page table information comprises a plurality of page table entries, each page table entry corresponding to a physical page; the second page table information comprises a plurality of multi-level page tables, each multi-level page table comprising a plurality of page directory entries, each page directory entry being used to point to a physical address of a next-level page table; and each page directory entry in a last-level page table in the plurality of multi-level page tables is used to point to a page table entry in the first page table information.

[0023] For example, in the address conversion device provided by some embodiments of the present disclosure, the multi-level page table query module is configured to: based on the object virtual address and the base address, obtain a first page table read address of at least one level of page table in the multi-level page table; based on the first page table read address, determine whether the second page table information exists second target page table information matching the first virtual address conversion request.

[0024] For example, in the address conversion device provided by some embodiments of the present disclosure, the multi-level page table query module includes a same read address merging unit and a conversion information cache unit, the same read address merging unit is configured to: in response to the second page table information not existing second target page table information matching the first virtual address conversion request, determine whether a merging signal is valid; in response to the merging signal being valid, compare whether the first page table read address and a second page table read address of a second virtual address conversion request located before the first virtual address conversion request are same; in response to the first page table read address and the second page table read address being same, merge the first virtual address conversion request and the second virtual address conversion request, and wait for the conversion information provided by the external memory in response to the second virtual address conversion request, the conversion information cache unit is configured to: cache the conversion information, and in the case that the address conversion module is in an idle state, provide the conversion information to the address conversion module.

[0025] Some embodiments of the present disclosure also provide an electronic device, including: a processor; a memory including one or more computer program instructions; the one or more computer program instructions are stored in the memory and implemented by the processor to implement the address conversion method provided by any of the embodiments of the present disclosure.

[0026] For example, some embodiments of the present disclosure also provide a computer readable storage medium, which non-transitively stores computer readable instructions, when the computer readable instructions are executed by a processor, the address conversion method provided by any of the embodiments of the present disclosure is implemented. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present disclosure, but not limit the present disclosure.

[0028] Figure 1A A system schematic diagram of an address conversion device, a hardware access unit and an external memory connection is shown;

[0029] Figure 1B A schematic diagram of a 4-level page table structure is shown;

[0030] Figure 2A AndFigure 2B A flow chart of a method of address translation is shown according to at least one embodiment of the present disclosure;

[0031] Figure 3 A schematic block diagram of an address translation apparatus is shown according to at least one embodiment of the present disclosure;

[0032] Figure 4A A schematic block diagram of an address translation apparatus is shown according to at least one embodiment of the present disclosure; Figure 2A A flow chart of a method of address translation is shown according to at least one embodiment of the present disclosure;

[0033] Figure 4B A schematic block diagram of an address translation apparatus is shown according to at least one embodiment of the present disclosure; Figure 3 A schematic block diagram of an arbitration module is shown according to at least one embodiment of the present disclosure;

[0034] Figure 5 A schematic block diagram of an address translation apparatus is shown according to at least one embodiment of the present disclosure; Figure 3 A schematic block diagram of an L2 TLB is shown according to at least one embodiment of the present disclosure;

[0035] Figure 6 A schematic diagram showing a principle of querying a page table by a virtual address and a page table base address under a four-level page table structure is shown according to some embodiments of the present disclosure;

[0036] Figure 7 A schematic block diagram of an address translation apparatus is shown according to at least one embodiment of the present disclosure; Figure 3 A schematic block diagram of a multi-level page table querying module is shown according to at least one embodiment of the present disclosure;

[0037] Figure 8A A flow chart of a method of address translation is shown according to at least one embodiment of the present disclosure; Figure 2B A flow chart of a method of address translation is shown according to at least one embodiment of the present disclosure;

[0038] Figure 8B A schematic block diagram of an address translation apparatus is shown according to at least one embodiment of the present disclosure; Figure 3 A schematic block diagram of an address translation performance monitoring module is shown according to at least one embodiment of the present disclosure;

[0039] Figure 8C A flow chart of a method of address translation is shown according to at least one embodiment of the present disclosure;

[0040] Figure 9 A schematic diagram of an address translation apparatus is shown according to at least one embodiment of the present disclosure;

[0041] Figure 10A A schematic block diagram of an electronic device is shown according to some embodiments of the present disclosure;

[0042] Figure 10B A schematic block diagram of another electronic device is shown according to some embodiments of the present disclosure; and

[0043] Figure 11 A schematic diagram of a storage medium provided in some embodiments of the present disclosure is shown. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0045] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0046] Figure 1A A schematic diagram of an address translation device, a hardware access unit, and an external memory connection is shown. Figure 1B A schematic diagram of a 4-level page table structure is shown.

[0047] like Figure 1A As shown, the system includes an address translation device 101, n hardware access units, and external memory 102. The address translation device 101 is, for example, the MMU in the CPU. The n hardware access units include, for example, hardware access unit 1, hardware access unit 2, ..., hardware access unit n. The external memory 102 may include, for example, physical memory.

[0048] An executable program can only use virtual memory addresses, which must be translated into physical memory addresses to access the corresponding data in physical memory; this translation is essential. Most mainstream address translation devices use multi-level page table structures to perform the translation from virtual to physical addresses.

[0049] likeFigure 1B As shown, each of the first three levels of page tables stores a Page Directory Entry (PDE). This entry is used to retrieve the physical address of the next-level page table. For example, the first three levels of page tables include page table PDE2 (level 1), page table PDE1 (level 2), and page table PDE0 (level 3). The last level of page table (i.e., page table PTE0 (level 4)) stores page table entries (PTEs). These entries are used to retrieve the actual physical address in memory. In this example, the complete address translation process requires reading the page tables four times. Since page tables are typically stored in physical memory, the entire address translation process is very delayed. Therefore, address translation devices usually use translation lookaside buffers (TLBs) to reduce the performance impact of read latency. Each PDE and PTE in a multi-level page table structure has a corresponding TLB to store the relevant page table information. If a PDE or PTE matching the virtual address translation request exists in the TLB, it is called a "hit"; otherwise, it is called a "miss". If a TLB miss occurs, the PDE or PTE information matching the virtual address translation request needs to be read from the multi-level page table structure in physical memory, and the TLB is then updated. A TLB hit avoids the process of rereading the PDE or PTE from physical memory, resulting in a much faster translation speed. Therefore, TLB performance is particularly important.

[0050] like Figure 1A As shown, the address translation device 101 includes n first-level (L1) TLBs, namely L1 TLB1, L1 TLB2, ..., L1 TLBn, and a second-level TLB (L2 TLB). Each of the n first-level TLBs corresponds one-to-one with one of the n hardware access units. Compared to the L1 TLB, the L2 TLB has a larger capacity and can store more PTEs and PDEs. The address translation device 101 also includes a multi-level page table lookup module and a bus.

[0051] When any one of the hardware access units 1-n needs to do address translation, a virtual address translation request is sent to the corresponding L1 TLB. When the L1 TLB receives the virtual address translation request from the hardware access unit, it determines whether the L1 TLB is hit according to the virtual address in the virtual address translation request. If the L1 TLB is hit, the physical memory address is determined based on the physical address field in the hit L1 TLB and the offset of the corresponding virtual address, and then sent to the hardware access unit. If the L1 TLB is not hit, a page table read request is sent to the L2 TLB through the bus 121. If the L2 TLB is hit, it is transmitted to the L1 TLB through the bus 121, and then the physical memory address is determined by the L1 TLB according to the physical address field in the PTE and the offset of the corresponding virtual address, and then sent to the hardware access unit, while the L1 TLB is updated. If the L2 TLB is not hit, the virtual address and other information are sent to the multi-level page table query module 111. The multi-level page table query module 111 has M TLB modules for storing PDE and PTE information of an M-level page table structure, where M is an integer greater than or equal to 1. For example, for a 4-level page table structure, M = 4. When the multi-level page table query module 111 receives a virtual address translation request from the L2 TLB, it queries the PDE and PTE matching the virtual address translation request from the M TLB modules level by level. If there is no PDE or PTE information matching the virtual address translation request in the M TLB modules, a read request is sent to the external memory 102 to read the PDE or PTE information in the multi-level page table stored in the external memory 102, and the corresponding TLB is updated. When the PTE matching the virtual address translation request is found, the PTE is returned to the L2 TLB and the L1 TLB in turn, while the data of the L2 TLB and the L1 TLB is updated. The L1 TLB determines the physical memory address based on the physical address field in the matching PTE and the offset of the corresponding virtual address, and then sends it to the hardware access unit, thus ending the entire address translation process.

[0052] Currently, the data cached in the address translation device includes PTE and PDE. After the previous level TLB is not hit, it goes to the next level TLB to query level by level until the PTE matching the virtual address translation request is obtained. The physical memory page base address in the PTE is extracted, the corresponding offset in the virtual address is added, the actual physical address is obtained, and the physical address and other information are returned to the hardware access unit, while the data of the TLB not hit in the address translation device is updated.

[0053] The TLB capacity of the address conversion apparatus 101 is limited. When a large number of threads are concurrently executed instantaneously, especially when having irregular memory access patterns, the data stored in the TLB will be frequently replaced, and the hit rate of the TLB will be greatly reduced. In this case, the address conversion apparatus 101 needs to frequently send a page table reading request to the physical memory to read the PDE or PTE in the multi-level page table stored in the physical memory. A large number of reading requests can cause serious blocking of the module between the address conversion apparatus and the physical memory, and increase the delay of reading back the PDE or PTE. At this time, a faster processor core or higher physical memory can not help much, and increasing the TLB capacity of the address conversion apparatus 101 can also cause problems such as increased chip area and increased power consumption.

[0054] Therefore, the current allocation of TLB cache resources is unreasonable, and when facing a large number of virtual address conversion requests with irregular memory access patterns, the TLB resources cannot be fully utilized, the address conversion efficiency is greatly reduced, the delay of the entire address conversion process is increased, and the system performance is reduced.

[0055] The present disclosure provides an address conversion method applied to an address conversion apparatus. The address conversion apparatus includes a plurality of sets of conversion buffers, each set of conversion buffers being configured to store first page table information used to convert a virtual address into a physical address. The method includes: in response to obtaining a first virtual address conversion request, determining a target conversion buffer from the plurality of sets of conversion buffers according to a first mapping algorithm, the first virtual address conversion request including an object virtual address; and accessing the first page table information in the target conversion buffer to convert the object virtual address into an object physical address. The method further includes: obtaining access frequency information of each set of the plurality of sets of conversion buffers; determining whether the first mapping algorithm needs to be updated according to the access frequency information; and in response to the first mapping algorithm needing to be updated, updating the mapping algorithm to a second mapping algorithm. The method can alleviate the uneven allocation of conversion buffer resources for virtual address conversion requests and improve the utilization rate of conversion buffer resources.

[0056] Figure 2A And Figure 2B A flowchart of an address conversion method provided by at least one embodiment of the present disclosure is shown.

[0057] As Figure 2A shown, the address conversion method includes steps S201 and S202; as Figure 2B shown, the address conversion method includes steps S201 and S202, and further includes steps S203-S205. Figure 2A And Figure 2B The address conversion method shown in

[0058] Figure 3 A schematic block diagram of an address translation apparatus is shown.

[0059] As shown in Figure 3 , the address translation apparatus 300 comprises an L2 TLB 310, for example, the L2 TLB 310 comprises a plurality of sets of translation buffers. Figure 2A and Figure 2B The address translation method shown in Figure 2A and Figure 2B may be applied to the address translation apparatus 300, that is, the address translation apparatus 300 can perform the address translation method shown in

[0060] In some embodiments of the present disclosure, each set of the plurality of sets of translation buffers comprises first page table information, for example, the first page table information comprises a plurality of page table entries, each page table entry corresponding to a physical page. For example, the first page table information is a level 4 page table PTE0 as shown in Figure 1B . The level 4 page table PTE0 comprises a plurality of page table entries, each page table entry corresponding to an actual physical page. By querying the level 4 page table PTE0, a virtual address can be converted to an actual physical page.

[0061] Step S201: in response to obtaining a first virtual address translation request, determining a target translation buffer from the plurality of sets of translation buffers according to a first mapping algorithm, the first virtual address translation request comprising an object virtual address.

[0062] Step S202: accessing the first page table information in the target translation buffer to convert the object virtual address to an object physical address.

[0063] Step S203: obtaining access frequency information of each set of the plurality of sets of translation buffers.

[0064] Step S204: determining whether the first mapping algorithm needs to be updated according to the access frequency information.

[0065] Step S205: in response to the need to update the first mapping algorithm, updating the mapping algorithm to a second mapping algorithm.

[0066] The method enables the address translation apparatus to adaptively adjust the mapping algorithm when facing a large number of irregular virtual address translation requests, avoiding the situation that the virtual address translation request is only mapped to a single TLB, and ensuring the utilization rate of TLB resources.

[0067] For step S201, for example, the address translation apparatus 300 receives the first virtual address translation request provided by the hardware access unit 1 to the hardware access unit n.

[0068] Hardware access units 1 to 2 are devices in the CPU or GPU that require address translation, such as Smart Direct Memory Access (SDMA), Semaphore (SEM), and Command Processor Fetcher (CPF).

[0069] The first virtual address translation request includes the object's virtual address, which needs to be translated into the object's physical address.

[0070] In some embodiments of this disclosure, the first mapping algorithm determines the target translation buffer based on the object's virtual address. The mapping algorithm for selecting the target translation buffer based on the object's virtual address is calculated by taking a specified address range from the virtual address. For example, when the L2 TLB 310 contains 8 sets of translation buffers, bits 26 to 24 of the 48-bit virtual address can be used as the result of selecting 8 sets of translation buffers. It should be noted that which 3 bits of the virtual address are selected as the target translation buffer can be changed according to the register configuration.

[0071] In some embodiments of this disclosure, for example, multiple consecutive bits are selected as the selection bits of the target conversion buffer, which can uniformly query multiple conversion buffers.

[0072] like Figure 3 As shown, the address translation device 300 also includes an arbitration module 301. Step S201 is performed, for example, by the arbitration module 301.

[0073] For step S202, for example, accessing the PTE in the target translation buffer to obtain the physical page corresponding to the object's virtual address.

[0074] For example, step S202 includes accessing the first page table information in the target translation buffer, determining whether there is a target page table entry in the first page table information that matches the object virtual address translation request; in response to the existence of a target page table entry matching the object virtual address translation request in the first page table information, determining the object physical address corresponding to the object virtual address based on the target page table entry and the page offset indicated by the object virtual address. For example, if there is a target page table entry (PTE) matching the object virtual address in PTE0 of the target translation buffer, the object physical address corresponding to the object virtual address is determined according to the target page table entry and the page offset indicated by the object virtual address. For example, certain consecutive bits of the object virtual address indicate the page offset. Please refer to this embodiment for more details. Figure 6 The description.

[0075] For step S203, the access frequency information is represented, for example, by the number of times the conversion buffer is accessed within a preset time period. For example, the number of accesses to each of the multiple conversion buffers is counted to obtain the count value of each of the multiple conversion buffers within the preset time period.

[0076] For step S204, if the access frequency information indicates that the access frequencies of multiple sets of conversion buffers differ significantly, then the first mapping algorithm needs to be updated. Conversely, if the access frequency information indicates that the access frequencies of multiple sets of conversion buffers are not significantly different, or if the multiple sets of conversion buffers are accessed evenly, then the first mapping algorithm does not need to be updated.

[0077] For step S205, if the first mapping algorithm needs to be updated, it is updated to the second mapping algorithm. The second mapping algorithm is different from the first mapping algorithm. For example, the specified address ranges of the first and second mapping algorithms are different. For example, the first mapping algorithm uses bits 26 to 24 of the 48-bit virtual address as the result of selecting 8 sets of translation buffers, while the second mapping algorithm uses bits 24 to 22 of the virtual address as the result of selecting 8 sets of translation buffers.

[0078] like Figure 3 As shown, the address translation device 300 also includes an address translation performance monitoring module 302. Steps S203 to S205 are executed, for example, by the address translation performance monitoring module 302.

[0079] In some embodiments of this disclosure, the address translation device 300 further includes a multi-level page table lookup module 303. The multi-level page table lookup module 303 includes second page table information. The second page table information includes multi-level page tables, each level of which includes multiple page directory entries, each page directory entry pointing to the physical address of the next-level page table. For example, the multi-level page table includes... Figure 1B The diagram shows level 1 page table PDE2, level 2 page table PDE1, and level 3 page table PDE0. Each level of page table includes multiple PDEs, which point to the physical addresses of the next level page table. Each page directory entry in the last level page table of the multi-level page table points to a page table entry in the first page table information. For example, each page directory entry in the last level page table PDE0 of the multi-level page table points to a page table entry in the first page table information PTE0.

[0080] In some embodiments of the present disclosure, the address translation apparatus 300 further comprises a register configuration module 304. The register configuration module 304 is configured to perform register configuration on registers of the L2 TLB 310, the arbitration module 301, the multi-level page table query module, and the address translation performance monitoring module 302, for example, to provide register configuration values. For example, the register configuration of the mapping algorithm of the arbitration module 301 is set to a value, so that the mapping algorithm is set to the second mapping algorithm. The register configuration module performs register configuration on the monitoring period in the address translation performance monitoring module 302, and the like.

[0081] Figure 4A An address translation method provided by at least one embodiment of the present disclosure is shown. Figure 2A A method flowchart of step S202 is shown.

[0082] As shown in Figure 4A Step S202 can include steps S212-S242.

[0083] Step S212: Access the first page table information in the target translation buffer, and determine whether the first target page table information matching the first virtual address translation request exists in the first page table information.

[0084] Step S222: In response to the first target page table information not existing in the target translation buffer, provide the first virtual address translation request to the multi-level page table query module.

[0085] Step S232: Determine whether the second target page table information matching the first virtual address translation request exists in the second page table information.

[0086] Step S242: In response to the second target page table information not existing in the second page table information matching the first virtual address translation request, convert the object virtual address into the object physical address based on the conversion information provided by the external memory.

[0087] For step S212, for example, access the PTE in the target translation buffer, and determine whether the object virtual address hits the PTE in the target translation buffer. If the object virtual address hits the PTE in the target translation buffer, the hit PTE is the first target page table information, i.e., the first target page table information indicates the physical page where the object virtual address is located. If the object virtual address does not hit the PTE in the target translation buffer, step S222 is performed.

[0088] For step S222, for example, the object virtual address does not hit the PTE in the target translation buffer, and then the L2 TLB 310 provides the first virtual address translation request to the multi-level page table query module 303.

[0089] For step S232, for example, it is judged whether the object virtual address hits the first level page table PDE2, the second level page table PDE1 and the third level page table PDE0 in the multi-level page table query module 303.

[0090] In some embodiments of the present disclosure, step S232, for example, comprises: based on the object virtual address and the base address, obtaining a first page table read address of at least one page table in the multi-level page table; based on the first page table read address, judging whether the second page table information exists second target page table information matching the first virtual address conversion request.

[0091] The base address is configured, for example, by configuring the value of the base address register in the register configuration module 304. The base address in the register configuration module 304 specifies the starting address of the first level page table in the physical memory. The data field stored in the first level page table PDE2 (as the second level page table PDE1 page table physical base address) specifies the starting address of the second level page table PDE1 in the physical memory, the data field stored in the second level page table PDE1 (as the third level page table PDE0 page table physical base address) specifies the starting address of the third level page table PDE0 in the physical memory, the data field stored in the third level page table PDE0 (as the fourth level page table PTE0 page table physical base address) specifies the starting address of the fourth level page table PTE0 in the physical memory, and the data field stored in the fourth level page table specifies the starting address of the page pointed to by the PTE in the physical memory.

[0092] In some embodiments of the present disclosure, the starting level of the page table for query can also be configured by the register configuration module 304, that is, the starting page table for query is configured. For example, the starting query is set to the first level page table PDE2 by the register configuration module 304. For example, the multi-level page table query module 303 queries the PDE2 cache resource according to the base address configured by the register and the 47th-39th bits of the virtual address as the first level page table PDE2 read address; if the match is successful, the second level page table PDE1 page table read address is obtained according to the matched first level page table PDE2 field (indicating the second level page table PDE1 physical address field) and the 38th-30th bits of the virtual address, and the second level page table PDE1 cache resource is queried. If the match is not successful in the first level page table PDE2 cache resource, the PDE2 data corresponding to the read address in the physical memory is read according to the first level page table PDE2 page table read address.

[0093] In the above example, the sum of the 47th to 39th bits in the object virtual address and the base address in the register configuration module 304 is used as the read address of the first-level page table PDE2 (an example of a first page table read address). If the read address of the first-level page table PDE2 does not hit the first-level page table PDE2, it is determined that the second page table information does not exist for the second target page table information matching the first virtual address conversion request. If the read address of the first-level page table PDE2 hits the first-level page table PDE2, it is determined whether the hit exists in the second-level page table PDE1 cache resource according to the sum of the 38th to 30th bits in the upper virtual address and the field of the first-level page table PDE2 matching successfully used as the second-level page table PDE1 page table read address. If the hit does not exist, it is determined that the second page table information does not exist for the second target page table information matching the first virtual address conversion request. In the same way, until the third-level page table PDE0 matches successfully, it is determined that the second page table information exists for the second target page table information matching the first virtual address conversion request. The page table information matching the object virtual address in the third-level page table PDE0 is the second target page table information.

[0094] For step S242, for example, if the object virtual address does not hit the multi-level page table query module 303, the first virtual address conversion request is provided to the external memory to obtain conversion information for converting the object virtual address into the object physical address from the external memory. The external memory is, for example, the physical memory as shown in Figure 3 For example, the physical memory stores a complete four-level page table, which is, for example, the structure as shown in Figure 1B In response to the first virtual address conversion request, the conversion information obtained by querying the four-level page table is, for example, the PTE that hits the object virtual address, i.e., the target page table item matching the object virtual address.

[0095] In some embodiments of the present disclosure, step S242 can obtain the conversion information according to whether the merge request signal is valid. For this embodiment, please refer to the description of the multi-level page table query module 303 in the following Figure 7 .

[0096] The specific implementation of the address conversion method provided by the present disclosure will be described below in combination with the embodiment of Figure 3 .

[0097] As shown in Figure 3 , the address conversion device 300 can process virtual address conversion requests of n hardware access units (for example, hardware access unit 1 to hardware access unit n), and the virtual address conversion request includes virtual address, hardware access unit identifier, and other key information. n is an integer greater than or equal to 1. In some embodiments of the present disclosure, n first-level TLBs can be arranged in each hardware conversion unit, as shown in Figure 3The hardware access unit 1 to the hardware access unit n each includes a first level (L1) TLB. In other embodiments of the present disclosure, n first level TLBs can be provided in the address translation device 300, as shown in the structure. Figure 1A Embodiments of the present disclosure do not limit the first level TLB.

[0098] The arbitration module 301 is configured to receive the virtual address translation request from the n hardware access units into the cache inside the arbitration module 301, process the virtual address translation request in turn through the arbitration algorithm, and the processing process includes determining which group (i.e., the target TLB) in the k groups of TLBs inside the L2 TLB 310 the virtual address translation request maps to through the mapping algorithm, and determining the target TLB address index and the comparison tag information according to the virtual address, and sending these information to the L2 TLB 310 together with the virtual address translation request; after receiving the virtual address translation result returned from the L2 TLB 310, sending the virtual address translation result to the corresponding hardware access unit according to the hardware access unit identifier in the virtual address translation result. n and k are integers greater than or equal to 1.

[0099] The mapping algorithm for the arbitration module 301 to select the target TLB according to the specified address range in the virtual address is calculated by taking the specified address range in the virtual address. For example, when the L2 TLB 310 contains 8 groups of TLBs, the 26th to 24th bits of the 48-bit virtual address can be used as the result of selecting the 8 groups of TLBs. Which 3 bits of the virtual address can be changed according to the register configuration; selecting 3 consecutive bits of the address as the target TLB selection bit can make consecutive virtual addresses be able to query the 8 groups of TLBs evenly.

[0100] The arbitration module 301 obtains the index bit of the target TLB according to the specified address range in the virtual address. For example, when the depth of the target TLB is 64, the 20th to 15th bits of the 48-bit virtual address can be used as the index bit of the target TLB. Which 6 bits of the virtual address can be changed according to the register configuration; the PTE data of the target TLB with the index depth is queried through the value of the index bit to perform matching. Whether it matches is determined by comparing the tag; the arbitration module 301 obtains the tag information according to the specified address range in the virtual address, for example, the 47th to 12th bits of the 48-bit virtual address can be used as the tag value sent to the L2 TLB 310 to compare with the tag value of the target TLB with the index depth; if they are the same, the matching is successful, otherwise, the matching fails.

[0101] Figure 4B Fig. 1 shows a schematic block diagram of an arbitration module according to an embodiment of the present disclosure. Figure 3 Fig. 1 shows a schematic block diagram of an arbitration module according to an embodiment of the present disclosure.

[0102] As shown in Figure 4B Arbitration module 301 includes conversion request input arbitration module 311, conversion result output arbitration module 321, n hardware input FIFO buffers and n hardware output FIFO buffers. The n hardware input FIFO buffers correspond to the n hardware access units one by one, and the n hardware output FIFO buffers correspond to the n hardware access units one by one. The n hardware input FIFO buffers include, for example, hardware 1 input FIFO buffer ~ hardware n input FIFO buffer. The n hardware output FIFO buffers include, for example, hardware 1 output FIFO buffer ~ hardware n output FIFO buffer.

[0103] Hardware x input FIFO buffer is used to buffer the virtual address conversion request from hardware access unit x, where x is an integer greater than or equal to 1 and less than or equal to n.

[0104] Conversion request input arbitration module 311 is used to process virtual address conversion requests, for example, by using a round-robin scheduling algorithm to determine whether the n hardware input FIFO buffers are empty one by one. If not, read the virtual address conversion request (an example of the first virtual address conversion request) in the hardware input FIFO buffer for processing, calculate the target TLB, tag, and index information corresponding to the virtual address by a virtual address and TLB mapping algorithm, and send the above information to L2 TLB 310 module together with the virtual address conversion request; the TLB mapping algorithm can be adjusted by register configuration module 304. For the round-robin scheduling algorithm, please refer to the relevant materials in the art, which will not be described in detail here. It should be noted that other scheduling algorithms in the art can also be used to determine whether the n hardware input FIFO buffers are empty one by one, and the present disclosure does not limit the scheduling algorithm, and the person skilled in the art can select a suitable scheduling algorithm according to the needs.

[0105] Conversion result output arbitration module 321 is used to receive the virtual address conversion result from L2 TLB 310, and send the virtual address conversion result to the corresponding hardware x output FIFO buffer through the hardware access unit identifier in the virtual address conversion result.

[0106] Hardware x output FIFO buffer is used to buffer the virtual address conversion result of hardware access unit x, and when hardware access unit x is in an "idle" state, the virtual address conversion result is sent to hardware access unit x, where x is an integer greater than or equal to 1 and less than or equal to n.

[0107] Figure 5 A schematic block diagram of an L2 TLB in an embodiment of the present disclosure is shown. Figure 3

[0108] As​Figure 5 As shown, the L2 TLB 310 includes k sets of TLB input buffers, k sets of TLBs, a PTE checking unit 312, an address translation unit 322, and a virtual address translation result output buffer 332. The k sets of TLB input buffers correspond to the k sets of TLBs one-to-one, and k is an integer greater than or equal to 1. The k sets of TLB input buffers are respectively a TLB1 input buffer, a TLB2 input buffer,..., and a TLBk input buffer, and the k sets of TLBs respectively include a TLB1, a TLB2,..., and a TLBk.

[0109] The L2 TLB 310 includes, for example, k sets of TLBs, which are all used to store data in a last-level page table in an M-level page table structure, i.e., PTE data; where M and k are both integers greater than or equal to 1; for example, the M-level page table structure is a 3-level page table structure, and the k sets of TLBs all store PTE data in a 3rd-level page table; or the M-level page table structure is a 4-level page table structure, and the k sets of TLBs all store PTE data in a 4th-level page table. Placing all the PTE cache resources in the L2 TLB module can improve the L2 TLB query hit rate, and such a design can more reasonably utilize the PTE cache resources and improve the address translation efficiency.

[0110] For example, the k sets of TLB input buffers adopt a set-associative cache structure, or a full-associative cache structure. The set-associative cache structure and the full-associative cache structure can be referred to related materials in the art, and will not be described herein.

[0111] The TLBy input buffer is used to buffer a virtual address translation request from the arbitration module 301 and targeted at a TLB y, where y is an integer greater than or equal to 1 and less than or equal to k. The virtual address translation request includes a virtual address, a hardware access unit identifier, target TLB information, index, and tag information, etc.

[0112] The TLBy is used to take the virtual address translation request from the TLBy input buffer and perform matching in the TLBy, where y is an integer greater than or equal to 1 and less than or equal to k. For example, the TLBy finds the tag saved in an index row in the TLBy according to the index in the virtual address translation request, and compares the tag with the tag in the virtual address translation request; if they are the same, the matching is successful, and the PTE data saved in the index row in the TLBy is sent to the PTE checking unit; if they are not the same, the TLBy misses, and the virtual address translation request is sent to the multi-level page table query module 303.

[0113] The PTE checking unit 312 is configured to check the PTEs of the k TLB hits and the PTEs returned from the multi-level page table query module 303. The PTE checking unit 312 determines whether the PTEs can be used as normal PTEs by checking the information of specific fields in the matched PTEs. For example, the PTE checking unit 312 checks whether the valid bit (V-bit) of the PTE is valid. If the V-bit is invalid, it means that the PTE is invalid and cannot be used as a normal PTE. In this case, the default address configured by the register is sent to the address translation unit as the physical address field of the PTE, and the error indication signal is pulled high to indicate that the virtual address translation result is problematic. If the V-bit of the PTE is valid, the physical address field information of the PTE is sent to the address translation unit 322.

[0114] The address translation unit 322 reads the physical address information in the PTE field from the PTE checking unit 312, adds the corresponding offset in the virtual address to the physical address information to obtain the physical memory address corresponding to the virtual address translation request, and sends the physical memory address, the virtual address, and the hardware access unit identifier as the virtual address translation result to the virtual address translation result output buffer 332.

[0115] The virtual address translation result output buffer 332 is configured to store the virtual address translation result. When the arbitration module 301 is in the "idle" state, the virtual address translation result output buffer 332 sends the virtual address translation result to the arbitration module 301.

[0116] For example, the L2 TLB 310 is configured to receive a virtual address translation request from the arbitration module 301, compare the tag in the virtual address translation request with the tag information stored in the index row in the target TLB according to the target TLB, index, and tag information in the virtual address translation request, and if the tag in the virtual address translation request is the same as the tag information stored in the index row, a match is successful, the PTE data stored in the index row is read, and after the PTE data is checked, the PTE data is sent to the address translation unit 322 in the L2 TLB 310. The address translation unit 322 reads the physical address field in the PTE, adds the corresponding offset in the virtual address, and obtains the physical memory address corresponding to the virtual address translation request. The physical memory address, the virtual address, and the hardware access unit identifier are sent to the arbitration module 301 as the virtual address translation result. If the tag in the virtual address translation request is not the same as the tag information stored in the index row, a match is not successful, and the virtual address translation request is sent to the multi-level page table query module 303. The multi-level page table query module 303 returns the PTE matched by the virtual address request, the virtual address, the hardware access unit identifier, the target TLB information, the index, and the tag information to the L2 TLB 310. The L2 TLB 310 updates the PTE data and the tag data of the index row in the target TLB according to the target TLB information and the index. Meanwhile, the L2 TLB 310 sends the returned PTE data, the virtual address, and the hardware access unit identifier to the address translation unit 322 after the PTE data is checked by the PTE checking unit 312. The address translation unit 322 calculates the physical memory address and sends the physical memory address, the virtual address, and the hardware access unit identifier to the arbitration module 301 as the virtual address translation result.

[0117] The multi-level page table query module 303 is configured to cache the PDE data of the other levels of the M-level page table structure except the last level of the M-level page table structure, so that the multi-level page table query module 303 can query the PDE data of the corresponding level according to the virtual address translation request from the L2 TLB 310. Figure 1B For example, the four-level page table structure, the multi-level page table query module 303 caches the PDE2, PDE1, and PDE0 data. When the multi-level page table query module 303 receives a virtual address translation request from the L2 TLB 310, the multi-level page table query module 303 queries the PDE data from the cached PDE data level by level. If there is no matching PDE data of the corresponding level, the multi-level page table query module 303 needs to determine the address of the target PDE in the physical memory according to the virtual address offset and the target level page table base address, read the target PDE from the physical memory, and update the TLB data based on the read PDE data. After the PDE0 data is matched, the multi-level page table query module 303 reads the PTE data from the physical memory according to the PTE table base address information in the PDE0 and the corresponding offset in the virtual address, and writes the PTE data back to the L2 TLB 310.

[0118] If M is an integer greater than or equal to 2, the multi-level page table query module 303 is further configured to determine whether the matched PDE item can be directly used as a PTE when querying the PDE data. For example, a bit of the PDE is selected as a flag bit. When the flag bit is valid, the PDE can be used as a PTE, and when the flag bit is invalid, the PDE needs to be queried in the next level page table. When the PDE can be directly used as a PTE, the PDE is directly returned to the L2 TLB 310 as PTE data, and the physical address in the PDE field is directly used as a physical memory page base address. The physical address obtained by adding the corresponding offset in the virtual address is the actual physical address converted from the virtual address.

[0119] It is considered that not all virtual address conversion requests are based on M-level page table address conversion even under the structure of M-level page table. For example, under the four-level page table structure shown in Figure 1B , some requests are only based on the one-level page table structure, i.e., only based on the PTE page table in Figure 1B . At this time, when the L2 TLB 310 is not hit, it is not necessary to query the PDE page table in the multi-level page table query module, and the physical memory read request is directly sent to the physical memory by the multi-level page table query module 303 to read the matched PTE data. Figure 1B Some requests are based on the two-level page table structure, i.e., only the PDE0 page table and the PTE page table in . At this time, when the L2 TLB 310 is not hit, the PDE0 page table is directly queried in the multi-level page table query module 303 whether the TLB resource is cached, and it is not necessary to query the PDE2 page table and the PDE1 page table. The multi-level page table query module 303 can determine the level of the PDE page table (target PDE page table) from which the query starts through a register configuration.

[0120] Figure 6 A schematic diagram of querying a page table through a virtual address and a page table base address under a four-level page table structure is shown.

[0121] Taking the four-level page table in Figure 6 as an example, the first-level page table stores PDE2 data, the second-level page table stores PDE1 data, the third-level page table stores PDE0 data, and the fourth-level page table stores PTE data.

[0122] Figure 6This demonstrates the meaning of the offsets represented by each field in the virtual address within a 4-level page table structure. Bits 47-39 represent the offset within the first level of the 4-level page table; bits 38-30 represent the offset within the second level; bits 29-21 represent the offset within the third level; bits 20-12 represent the offset within the fourth level; and bits 11-0 represent the offset within the page pointed to by the PTE's internal page physical address. The virtual address field added to the address translation unit in the L2 TLB310, namely bits 11-0 of the virtual address, yields the actual physical memory address.

[0123] If the register configuration requires a lookup starting from the PDE2 cache, the multi-level page table lookup module 303 uses the base address configured in the register plus bits 47-39 of the virtual address as the PDE2 page table read address to query the PDE2 cache resource. If a match is found in the PDE2 cache resource, the PDE1 page table physical address field in the matched PDE2 field plus bits 38-30 of the virtual address is used as the PDE1 page table read address to query the PDE1 cache resource. If no match is found in the PDE2 cache resource, the PDE2 data corresponding to the read address is read from physical memory using the PDE2 page table read address. The offsets in the virtual address corresponding to other page tables are used in a similar manner and will not be elaborated here. The base address configured in the register specifies the starting address of the Level 1 page table in physical memory. The physical base address of the PDE1 page table in the PDE2 data field stored in the Level 1 page table specifies the starting address of the Level 2 page table in physical memory. The physical base address of the PDE0 page table in the PDE1 data field stored in the Level 2 page table specifies the starting address of the Level 3 page table in physical memory. The physical base address of the PTB page table in the PDE0 data field stored in the Level 3 page table specifies the starting address of the Level 4 page table in physical memory. The physical address field in the PTE data field stored in the Level 4 page table specifies the starting address of the page pointed to by the PTE in physical memory.

[0124] Figure 7 At least one embodiment of the present disclosure is shown. Figure 3 A schematic block diagram of a multi-level page table query module.

[0125] like Figure 7 As shown, the multi-level page table lookup module 303 includes a virtual address translation request cache module 313, a translation information cache module 323, a virtual address translation request query selection module 333, a PDE2 cache TLB, a PDE1 cache TLB, a PDE0 cache TLB, and a same read address merging module 343. The PDE2 cache TLB, PDE1 cache TLB, and PDE0 cache TLB may employ a set-associative cache structure or a fully associative cache structure, for example.

[0126] In some embodiments of the present disclosure, the multi-level page table query module 303 can merge the page table read requests with the same read address sent to the physical memory through the same read address merging module 343, which includes the page table read address of the virtual address translation request, the virtual address, and the hardware access unit identifier providing the virtual address translation request, etc. The hardware access unit identifier is, for example, the number of the hardware access unit. The page table read address is obtained based on the base address and the page directory entry data of at least one level of the multi-level page table. The page table read address is, for example, the sum of the register-configured base address and the page directory entry data in the first-level page table PDE2. For another example, the page table read address is, for example, the sum of the register-configured base address and the page directory entry data in the first-level page table PDE2, and the page directory entry data in the second-level page table PDE1 obtained.

[0127] Step S242 can obtain the translation information according to whether the merging request signal is valid. For example, in response to the second page table information not existing the second target page table information matching the first virtual address translation request, it is judged whether the merging signal is valid; in response to the merging signal being valid, it is compared whether the first page table read address and the second page table read address of the second virtual address translation request located before the first virtual address translation request are the same; in response to the first page table read address and the second page table read address being the same, the first virtual address translation request is merged with the second virtual address translation request, and the translation information provided by the external memory in response to the second virtual address translation request is waited for; and the object virtual address is converted into the object physical address based on the translation information. This embodiment can effectively merge the same read address requests in the requests initiated by the address translation device to the physical memory, and optimize the congestion problem without reducing the hit rate of the virtual address translation request of the address translation device.

[0128] For example, if the second target page table information matching the object virtual address does not exist in the multi-level page table query module 303, it is judged whether the merging signal in the same read address merging module 343 is valid.

[0129] For example, when the multi-level page table query module 303 sends a page table read request to the physical memory once, the same read address merging module 343 records the page table read address data, the virtual address, and the hardware access unit identifier corresponding to the read request, and at the same time, the merging signal is made valid. When the next page table read request (an example of the first page table read address of the first virtual address translation request) is sent to the physical memory, if the merging signal is valid, it is compared whether the page table read address in the page table read request and the page table read address in the previous page table read request (an example of the second page table read address of the second virtual address translation request) are the same.

[0130] If the page table read request is consistent with the previous page table read address, a merge signal, the virtual address and the hardware access unit identifier are sent to the virtual address translation request query selection module 333, and the page table read request is no longer sent to the physical memory, and the conversion information provided by the physical memory in response to the second virtual address translation request is waited for.

[0131] In some embodiments of the present disclosure, in response to the first page table read address and the second page table read address being different, a page table read request based on the first virtual address translation request is provided to the external memory to obtain conversion information from the external memory; and the merge signal is updated to be invalid. For example, if the page table read request in the above embodiment is inconsistent with the previous page table read address, the page table read request is sent to the physical memory, and the merge signal is invalidated.

[0132] In some embodiments of the present disclosure, in response to the second page table information not existing the second target page table information matched with the first virtual address translation request, the object virtual address is converted to the object physical address based on the conversion information provided by the external memory, and the method further comprises: in response to receiving the conversion information provided by the external memory in response to the second virtual address translation request, updating the merge signal to be invalid.

[0133] In this embodiment, for example, the merge signal is pulled low (i.e., updated to be invalid) when data is fed back from the physical memory. Because when the data comes back, it is necessary to determine which requests are merged, and the read data is given to these merged requests, so that subsequent virtual address translation requests can be issued.

[0134] For example, the PDE2 cache TLB in the multi-level page table query module 303 needs to send 3 same page table read addresses and 1 different page table read address to the physical memory through the same read address merging module 343. When the PDE2 cache TLB sends the first page table read request to the same read address merging module 343, the merging signal is invalid, at this time the same read address merging module 343 records the page table read address of the first page table read request and sends the page table read request to the physical memory, and makes the merging signal valid. When the PDE2 cache TLB sends the second page table read request to the same read address merging module 343, the same read address merging module 343 judges whether the merging signal is valid, at this time the merging signal is valid, then the same read address merging module 343 compares the page table read address of the request with the page table read address of the first page table read request, and finds that they are the same, then sends the merging signal, the virtual address and the hardware access unit identifier to the virtual address conversion request query selection module 333. If the PDE2 cache TLB sends the third page table read request to the same read address merging module before the first page table read request reads back the PDE or PTE data from the physical memory, the same read address merging module 343 judges whether the merging signal is valid at this time, and if valid, the merging signal is invalid. At this time, when the PDE2 cache TLB sends the third same page table read request to the same read address, since the merging signal is invalid, the page table read request is sent to the physical memory, and the address merging signal is valid. When the PDE2 cache TLB sends the fourth page table read request to the same read address merging module 343, since the merging signal is valid, at this time it is needed to judge whether the page table read request address is the same as the recorded page table read request address, and if not the same, the merging signal is invalid, and the page table read request is sent to the physical memory. If the PTE or PDE data has not been returned before the third page table read request is sent, the same read address merging module 343 merges the first page table read request, the second page table read request and the third page table read request.

[0135] The virtual address conversion request cache module 313 is used for caching the virtual address conversion request from the L2 TLB 310.

[0136] The virtual address translation request query selection module 333 is configured to process the virtual address translation request. After obtaining the virtual address translation request data from the virtual address translation request, the virtual address translation request query selection module 333 determines, according to the register configuration, from which level of the PDE cache TLB the virtual address translation request starts to match. Taking the PDE2 cache TLB as an example, the virtual address translation request query selection module 333 first obtains the PDE2 page table read address by adding the base address of the register configuration to the 47th to 39th bits of the virtual address; then obtains the index and tag of the PDE2 cache TLB according to the specified address range in the PDE2 page table read address. For example, when the depth of the target TLB is 128, the 12th to 6th bits of the 48-bit PDE2 read address can be used as the index of the PDE2 cache TLB, and the 47th to 6th bits can be used as the tag. The specific selection of which bits of the PDE2 read address are used as the index and tag can be changed according to the register configuration. After calculating the PDE2 read address, the index and the tag, the virtual address translation request query selection module 333 sends the PDE2 read address, the index and the tag, together with the virtual address and the hardware access unit identifier, to the PDE2 cache TLB. The virtual address translation request query selection module 333 receives the PDE2 data returned from the physical memory or the PDE2 data from the PDE2 cache TLB. If the virtual address translation request query selection module 333 receives the PDE2 data returned from the physical memory, the virtual address translation request query selection module 333 sends the PDE2 data, together with the corresponding PDE2 cache TLB index and tag information, to the PDE2 cache TLB, and updates the data in the PDE2 cache TLB.

[0137] The virtual address translation request query selection module 333 determines, in response to receiving the PDE2 data returned from the PDE2 cache TLB or the physical memory, whether the PDE2 data can be used as a PTE. If the PDE2 data can be used as a PTE, the virtual address translation request query selection module 333 sends the PDE2 data, together with the corresponding virtual address and hardware access unit identifier, to the translation information cache module 323. If the PDE2 data cannot be directly used, the virtual address translation request query selection module 333 obtains the PDE1 read address by adding the PDE1 page table physical base address field information in the PDE2 data to the 38th to 30th bits of the virtual address, and calculates the index and tag of the PDE1 cache TLB corresponding to the virtual address translation request according to the PDE1 read address. The subsequent process is similar to the above process; until the PTE is read back from the physical memory, the PTE data and the virtual address and hardware access unit identifier matched with the PTE data (including the combined valid virtual address and hardware access unit identifier) are sent to the translation information cache module 323.

[0138] The PDE2 cache TLB, the PDE1 cache TLB and the PDE0 cache TLB are configured to receive PDE read requests and PDE write requests from the virtual address translation request query selection module 333. The PDE read requests include a PDE read address, an index, a tag, a virtual address, a hardware access unit identifier and the like. The index and the tag are matched in the cache TLB. If the matching is successful, the PDE data, the virtual address and the hardware access unit identifier are sent to the virtual address translation request query selection module 333. If the matching is unsuccessful, i.e. a miss, the page table read address, the virtual address and the hardware access unit identifier are sent to the same read address merging module 343. The PDE write requests are used to update the data in the PDE cache TLB with the PDE data read from the physical memory and the index and the tag information when the PDE cache TLB is a miss.

[0139] The same read address merging request module 343 is configured to determine whether the page table read requests from the PDE cache TLB can be merged. If the page table read requests can be merged, the merged virtual address and the hardware access unit identifier are sent to the virtual address translation request query selection module 333. If the page table read requests cannot be merged, the page table read requests are sent to the physical memory. In some embodiments of the present disclosure, the merging function can be enabled or disabled by a register, for example.

[0140] The translation information cache module 323 is configured to receive the PTE data and the corresponding virtual address, the hardware access unit identifier and the like queried by the virtual address translation request query selection module 333. When the L2 TLB 310 is in an "idle" state, the data are sent to the L2 TLB 310.

[0141] In some embodiments of this disclosure, the multi-level page table lookup module includes a same read address request merging module and a virtual address translation request query selection module. When the multi-level page table lookup module sends a page table read request to physical memory, the same read address merging module records the page table read address data, virtual address, and hardware access unit identifier corresponding to the read request, and simultaneously activates the merge valid signal. When sending the next page table read request to physical memory, if the merge valid signal is valid, the module compares whether the page table read request is consistent with the previous page table read address. If the page table read request is consistent with the previous page table read address, the module sends the merge valid signal, virtual address, and hardware access unit identifier to the virtual address translation request query selection module within the multi-level page table lookup module, and no longer sends the page table read request to physical memory. If the current page table read address is inconsistent with the previous page table read address, the module sends the page table read request to physical memory, and simultaneously deactivates the merge valid signal. After reading the matching PTE back from physical memory, the virtual address translation request arbitration module will send all virtual address translation request information (including merged virtual address translation requests) that match the PTE to the L2 TLB module. This can effectively merge the same read address requests in the requests initiated by the address translation module to physical memory, and optimize the congestion problem without reducing the virtual address translation request hit rate of the address translation module.

[0142] It should be noted that in the above embodiments, the multi-level page table query module does not include a cache for storing PTE page tables, but it can be configured as follows: Figure 1A The structure adds a PTE page table caching structure to the multi-level page table query module.

[0143] Figure 8A At least one embodiment of the present disclosure is shown. Figure 2B The flowchart of step S204.

[0144] like Figure 8A As shown, step S204 includes steps S214 to S244.

[0145] Step S214: Calculate the average access value of the multiple sets of conversion buffer counts based on the count value of each set of multiple conversion buffers.

[0146] Step S224: Obtain the allowed access deviation.

[0147] Step S234: Calculate the effective access rate of multiple sets of conversion buffers based on the allowed access deviation and average access value.

[0148] Step S244: Based on the effective access rate, determine whether the first mapping algorithm needs to be updated.

[0149] The following is combined with Figure 8B illustrateFigure 8A The method described.

[0150] Figure 8B At least one embodiment of the present disclosure is shown. Figure 3 A schematic block diagram of the address translation performance monitoring module.

[0151] The address translation performance monitoring module 302 records the number of queries for each of the k groups of TLBs in the L2 TLB module within a fixed clock cycle, determines whether the TLB mapping algorithm in the arbitration module 301 needs to be adjusted based on the adjustment algorithm, and adaptively adjusts the TLB mapping algorithm. The TLB mapping algorithm may include, for example, a first mapping algorithm and a second mapping algorithm.

[0152] like Figure 8B As shown, the address translation performance monitoring module 302 includes k TLB access counters and a TLB mapping algorithm adjustment module 312. Each of the k TLB access counters is, for example, a 48-bit counter, or a counter of other bit lengths. The k TLB access counters include, for example, TLB1 access counter, TLB2 access counter, ..., TLBk access counter.

[0153] The TLBx access counter is used to record the access status of TLBx in the L2 TLB module, where x is less than or equal to k and greater than or equal to 1. For example, on each rising edge of the clock, if the TLBx query enable from the arbitration module 301 is valid, the TLBx access counter is incremented by 1.

[0154] In some embodiments of this disclosure, the address translation performance monitoring module may also include other types of counters, such as address translation delay counters, specific PTE error type counters, TLB miss counters, etc.

[0155] For step S214, for example, the k groups of TLBs are counted by the k TLB access counters respectively to obtain the count value of each of the k groups of conversion buffers.

[0156] The TLB mapping algorithm adjustment module 312 is used to determine whether to adjust the mapping algorithm based on the count value of the TLB access counter, and adaptively adjust the TLB mapping algorithm when adjustment is required.

[0157] For example, the TLB mapping algorithm adjustment module 312 reads the count values ​​of k TLB access counters every F clock cycles, calculates the average access value Ave_tlb for accessing the k TLB modules over F clock cycles, and simultaneously resets the values ​​of the k TLB access counters to zero. For example, the average access value Ave_tlb can be calculated using the following formula.

[0158] Ave_tlb=(N TLB0 +NTLB1 +…+N TLBk ) / k,N TLBx represents a count value of the TLBx access counter.

[0159] For step S224, for example, the access allowance deviation is Δ, and the access allowance deviation can be set by those skilled in the art as needed, and the disclosure does not limit the value of the access allowance deviation.

[0160] For step S234, for example, it includes: based on the access allowance deviation, calculating the access deviation value of each group of the plurality of groups of translation buffers; based on the access deviation value, calculating the effective utilization indication value of each group of the plurality of groups of translation buffers; and taking the average value of the effective utilization indication values of the plurality of groups of translation buffers as the effective access rate.

[0161] For example, the access deviation value n of each group of TLB allowed to access is calculated by the following formula: Δ。

[0162] n Δ = Ave_tlb x Δ

[0163] For example, for each group of the plurality of groups of translation buffers, in response to the sum of the access deviation value and the count value being greater than or equal to the average access value, the effective utilization indication value of the translation buffer is set to a first preset value, and in response to the sum of the access deviation value and the count value being less than the average access value, the effective utilization indication value of the translation buffer is set to a second preset value. For example, the first preset value is 1, and the second preset value is 0.

[0164] If N TLBx +n Δ ≥ Ave_tlb, the TLBx effective utilization indication value E TLBx is 1, otherwise 0. Next, for example, the average value of the TLB effective utilization indication value can be calculated as the effective access rate TLB_usaget by the following formula:

[0165] TLB_usaget = (E TLB0 +E TLB1 +…+E TLBk ) / k

[0166] For step S244, for example, in response to the effective access rate TLB_usaget being greater than or equal to a preset access rate, it is determined that the first mapping algorithm does not need to be updated; in response to the effective access rate TLB_usaget being less than the preset access rate, it is determined that the first mapping algorithm needs to be updated.

[0167] When TLB_usaget≥α, the first mapping algorithm does not need to be updated, the arbitration module 301 still selects the target translation buffer according to the first mapping algorithm, α is a preset access rate, 0<α≤1, different values can be set according to the value of k. When TLB_usaget<α, the first mapping algorithm needs to be updated to the second mapping algorithm, the arbitration module 301 selects the target translation buffer according to the second mapping algorithm.

[0168] For example, the TLB mapping algorithm adjustment module 312 sends the mapping algorithm of the selected target register in the arbitration module 301 and the related register configuration adjustment information to the register configuration module 304.

[0169] In some embodiments of the present disclosure, the first mapping algorithm includes: determining the target translation buffer according to the first target bit of the object virtual address in the virtual address translation request, and the second mapping algorithm includes: determining the target translation buffer according to the second target bit of the object virtual address in the virtual address translation request, the first target bit and the second target bit are different.

[0170] For example, the first target bit includes a plurality of first bit positions in the object virtual address in series, and the second target bit includes a plurality of second bit positions in the object virtual address in series. For example, the 26th-24th bit of the 48-bit virtual address is used as a plurality of first bit positions, and the 25th-23rd bit of the 48-bit virtual address is used as a plurality of second bit positions. The first target bit and the second target bit are a plurality of bit positions in series, which can make uniform access to a plurality of groups of translation buffers.

[0171] For example, k=8 and the arbitration module 301 selects the 26th-24th bit of the 48-bit virtual address as the mapping result of 8 groups of TLBs at this time. If after 109 clocks, the TLB_usaget result is less than 0.8 (the value of α at this time is 0.8), the TLB mapping algorithm adjustment module 312 sends the 25th-23rd bit of the 48-bit virtual address to the register configuration module 304 as the register configuration adjustment information of TLB mapping, and then sends it to the arbitration module to adjust the TLB mapping algorithm 314.

[0172] In some embodiments of the present disclosure, the first target bit or the second target bit can also be a plurality of bit positions in series.

[0173] It should be noted that although in the above embodiments, the TLB mapping algorithm is adjusted for the target translation buffer of mapping, embodiments of the present disclosure are not limited thereto, and can also include adaptive adjustment algorithms for index and tag.

[0174] Before the TLB mapping algorithm is adjusted, the virtual address translation request that acquires the target TLB information, the tag information and the index information through the arbitration module 301 still queries the L2 TLB module according to the information acquired before the adjustment. After the TLB mapping algorithm is adjusted, the virtual address translation request that is not input to the arbitration module 301 for conversion request processing will acquire new target TLB information, tag information and index information according to the new TLB mapping algorithm, and then query the L2 TLB module. It should be noted that after the arbitration module 301 receives the register configuration adjustment information from the register configuration module 314, the data in the k groups of TLBs in the L2 TLB will not change. After the TLB mapping algorithm is adjusted, the L2 TLB will update the data in the TLB through a virtual address translation request miss.

[0175] Figure 8C A flowchart of another address translation method provided by at least one embodiment of the present disclosure is shown.

[0176] As shown in Figure 8C , the address translation method includes steps S801-S804.

[0177] Step S801: The arbitration module determines the target translation buffer, the index and the tag information mapped by the virtual address translation request according to the mapping algorithm.

[0178] For example, after the arbitration module receives the virtual address translation request from the hardware access unit, it selects the virtual address translation request to be processed through the polling algorithm, and determines the target TLB, the index and the tag information corresponding to the virtual address translation request according to the mapping algorithm and the virtual address, and then sends these information to the L2 TLB module together with the virtual address translation request. This step S801 is similar to step S201 in the execution Figure 2A .

[0179] Step S802: Determine whether there is a PTE matching the virtual address translation request in the L2 TLB module. If there is no PTE matching the virtual address translation request in the L2 TLB, execute S803. If there is a PTE matching the virtual address translation request in the L2 TLB, execute S804. The specific implementation process of S802 can be to compare the target TLB information, the index and the tag information in the request with the tag information of the index row stored in the target TLB, so as to determine whether there is a PTE matching the virtual address translation request.

[0180] Step S803: The multi-level page table query module is queried level by level to read back the PTE matching the virtual address translation request from the physical memory. After receiving the virtual address translation request from step S802, it is determined whether there is a PDE matching the virtual address translation request in the multi-level page table query module level by level until the PDE0 matching the virtual address translation request is obtained; after reading back the PTE from the physical memory according to the PTB physical base address in the PDE0 field and the corresponding offset in the virtual address field, step S804 is executed.

[0181] Step S804: The physical memory address is determined based on the offset of the physical address and the virtual address in the matched PTE field, and the virtual address to physical address translation is completed.

[0182] Steps S802-S804 are similar to, for example, performing steps S202 in Figure 2A .

[0183] Figure 9 A schematic diagram of an address translation device 900 provided by at least one embodiment of the present disclosure is shown. The address translation device 900 includes an address translation module 901, an arbitration module 902, and an address translation performance monitoring module 903.

[0184] The arbitration module 902 is configured to determine a target translation buffer from the plurality of translation buffers according to a first mapping algorithm in response to obtaining a first virtual address translation request, the first virtual address translation request including an object virtual address. The arbitration module 902 is similar to the arbitration module 301 in the above Figure 3 , and reference is made to the description above. The arbitration module 902 performs, for example, step S201 in the above Figure 2A .

[0185] The address translation module 901 includes a plurality of sets of translation buffers. Each set of the plurality of sets of translation buffers is configured to store first page table information for translating an object virtual address into an object physical address. The address translation module 901 is configured to access the first page table information in the target translation buffer to translate the object virtual address into the object physical address. The address translation module 901 is similar to the L2 TLB in the above Figure 3 , and reference is made to the description above. The address translation module 901 performs, for example, step S202 in the above Figure 2A .

[0186] The address translation performance monitoring module 903 is configured to obtain access frequency information of each set of the plurality of sets of translation buffers; determine whether the first mapping algorithm needs to be updated according to the access frequency information; and update the mapping algorithm to a second mapping algorithm in response to the first mapping algorithm needing to be updated. The address translation performance monitoring module 903 is similar to the address translation performance monitoring module 303 in the above Figure 3The address translation performance monitoring module 302 is similar to the address translation performance monitoring module 302 described above. The address translation performance monitoring module 903, for example, performs Figure 2B The steps S203-S205 are similar to the steps S203-S205 described above.

[0187] The address translation device 900 adaptively adjusts the TLB mapping algorithm when facing a large number of virtual address translation requests with irregular memory access patterns, avoids the situation that the virtual address translation request is only mapped to a single TLB, and ensures the utilization rate of the TLB resource.

[0188] In some embodiments of the present disclosure, as shown in Figure 9 The address translation device 900 further includes a multi-level page table query module 904, which includes second page table information.

[0189] The address translation module 901 is configured to access the first page table information in the target translation buffer, determine whether the first target page table information matching the first virtual address translation request exists in the first page table information, and in response to the first target page table information not existing in the target translation buffer, provide the first virtual address translation request to the multi-level page table query module 904. The multi-level page table query module 904 is configured to receive the first virtual address translation request provided by the address translation module, determine whether the second target page table information matching the first virtual address translation request exists in the second page table information, and in response to the second target page table information not existing in the second page table information, obtain the conversion information provided by the external memory, the conversion information being used to convert the object virtual address into the object physical address.

[0190] For example, the first page table information includes a plurality of page table entries, each page table entry corresponding to a physical page, the second page table information includes a plurality of multi-level page tables, each level of the page table includes a plurality of page directory entries, each page directory entry being used to point to the physical address of the next level of the page table, and each page directory entry in the last level of the multi-level page table being used to point to the page table entry in the first page table information.

[0191] In some embodiments of the present disclosure, the multi-level page table query module is configured to obtain a first page table read address of at least one level of the multi-level page table based on the object virtual address and the base address, and determine whether the second target page table information matching the first virtual address translation request exists in the second page table information based on the first page table read address.

[0192] In some embodiments of the present disclosure, the multi-level page table query module 904 comprises a same read address merging unit and a translation information cache unit. The same read address merging unit is configured to: in response to the second page table information not existing the second target page table information matching the first virtual address translation request, determine whether a merging signal is valid; in response to the merging signal being valid, compare whether the first page table read address and a second page table read address of a second virtual address translation request located before the first virtual address translation request are same; in response to the first page table read address and the second page table read address being same, merge the first virtual address translation request with the second virtual address translation request, and wait for the translation information provided by the external memory in response to the second virtual address translation request. The translation information cache unit is configured to cache the translation information, and provide the translation information to the address translation module in the case that the address translation module is in an idle state.

[0193] Some embodiments of the present disclosure add a same read address merging module to the multi-level page table query module, merge the same read page table requests sent to the physical memory without affecting the L2 TLB module TLB data update and virtual address translation, and effectively reduce the congestion situation.

[0194] The multi-level page table query module 904 is similar to the multi-level page table query module 303 in the foregoing description. The function and structure of the address translation device 900 are similar to the function and structure of the address translation device 300 in the foregoing description. Figure 3 The function and structure of the address translation device 900 are similar to the function and structure of the address translation device 300 in the foregoing description. Figure 3 The function and structure of the address translation device 900 are similar to the function and structure of the address translation device 300 in the foregoing description.

[0195] For example, the address translation module 901, the arbitration module 902, the address translation performance monitoring module 903 and the multi-level page table query module 904 can be hardware, software, firmware and any feasible combination thereof. For example, the address translation module 901, the arbitration module 902, the address translation performance monitoring module 903 and the multi-level page table query module 904 can be special-purpose or general-purpose circuits, chips or devices, or a combination of a processor and a memory. The specific implementation form of each unit is not limited in the embodiments of the present disclosure.

[0196] It should be noted that in the embodiments of the present disclosure, each unit of the address translation device 900 and the address translation device 300 corresponds to each step of the address translation method, and the specific functions of the address translation device 900 and the address translation device 300 can be referred to the related description of the address translation method, which will not be repeated here. Figure 9 The components and structures of the address translation device 900 shown are only exemplary and are not limited, and the address translation device 900 can also comprise other components and structures as needed.

[0197] At least one embodiment of the present disclosure also provides an electronic device including a processor and a memory including one or more computer program modules. The one or more computer program modules are stored in the memory and configured to be executed by the processor, and the one or more computer program modules include instructions for implementing the address translation method described above. The electronic device can alleviate uneven allocation of virtual address translation request conversion buffer resources and improve utilization of conversion buffer resources.

[0198] Figure 10A A schematic block diagram of an electronic device provided by some embodiments of the present disclosure is shown. As shown, the electronic device 1000 includes a processor 1010 and a memory 1020. The memory 1020 is configured to store non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 1010 is configured to execute the non-transitory computer-readable instructions, which, when executed by the processor 1010, can perform one or more steps of the address translation method described above. The memory 1020 and the processor 1010 can be interconnected by a bus system and / or other forms of connection mechanism (not shown). Figure 10A

[0199] For example, the processor 1010 can be a central processing unit (CPU), a graphics processing unit (GPU), or other forms of processing units having data processing and / or program execution capabilities. For example, the central processing unit (CPU) can be of X86 or ARM architecture, etc. The processor 1010 can be a general-purpose processor or a special-purpose processor, and can control other components in the electronic device 1000 to perform desired functions.

[0200] For example, the memory 1020 can include any combination of one or more computer program products, which can include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory, for example, can include random access memory (RAM), cache memory, and / or the like. Non-volatile memory, for example, can include read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), compact disc read-only memory (CD-ROM), USB memory, flash memory, and / or the like. One or more computer program modules can be stored on the computer-readable storage media, and the processor 1010 can execute the one or more computer program modules to implement various functions of the electronic device 1000. Various application programs and various data used and / or generated by the application programs, etc. can also be stored in the computer-readable storage media.

[0201] ​It should be noted that, in the embodiments of the present disclosure, the specific functions and technical effects of the electronic device 1000 can refer to the description of the address conversion method in the foregoing description, and will not be repeated here.

[0202] Figure 10B Another schematic block diagram of an electronic device is provided for some embodiments of the present disclosure. The electronic device 1100 is suitable for implementing the address conversion method provided by the embodiments of the present disclosure, for example. The electronic device 1100 can be a terminal device or the like. It should be noted that, Figure 10B The electronic device 1100 shown is merely an example, which does not bring any limitation to the functions and use range of the embodiments of the present disclosure.

[0203] As Figure 10B shown, the electronic device 1100 can include a processing device (such as a central processing unit, a graphics processing unit, etc.) 1110, which can perform various appropriate actions and processes according to programs stored in a read-only memory (ROM) 1120 or loaded from a storage device 1180 to a random access memory (RAM) 1130. Various programs and data required for the operation of the electronic device 1100 are also stored in the RAM 1130. The processing device 1110, the ROM 1120, and the RAM 1130 are connected to each other through a bus 1140. An input / output (I / O) interface 1150 is also connected to the bus 1140.

[0204] Generally, the following devices can be connected to the I / O interface 1150: an input device 1160 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 1170 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1180 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1190. The communication device 1190 can allow the electronic device 1100 to communicate with other electronic devices wirelessly or by wire to exchange data. Although Figure 10B The electronic device 1100 with various devices is shown, but it should be understood that it is not required to implement or have all the shown devices, and the electronic device 1100 can instead implement or have more or fewer devices.

[0205] For example, according to an embodiment of the present disclosure, the address translation method described above can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program comprising program code for performing the address translation method described above. In such an embodiment, the computer program can be downloaded and installed from a network through the communication apparatus 1190, or installed from the storage apparatus 1180, or installed from the ROM 1120. When the computer program is executed by the processing apparatus 1110, the functions defined in the address translation method provided by an embodiment of the present disclosure can be implemented.

[0206] At least one embodiment of the present disclosure also provides a computer-readable storage medium for storing non-transitory computer-readable instructions, which can implement the address translation method described above when executed by a computer. With the computer-readable storage medium, the uneven allocation of virtual address translation request translation buffer resources can be alleviated, and the utilization rate of translation buffer resources can be improved.

[0207] Figure 11 A schematic diagram of a storage medium provided by some embodiments of the present disclosure is shown. As shown in Figure 11 , the storage medium 1200 is used to store non-transitory computer-readable instructions 1210. For example, when the non-transitory computer-readable instructions 1210 are executed by a computer, one or more steps of the address translation method described above can be performed.

[0208] For example, the storage medium 1200 can be applied in the electronic device 1000 described above. For example, the storage medium 1200 can be the memory 1020 in the electronic device 1000 as shown in Figure 10A For example, the relevant description of the storage medium 1200 can refer to the corresponding description of the memory 1020 in the electronic device 1000 as shown in Figure 10A , and details are not repeated here.

[0209] For the present disclosure, the following points need to be explained:

[0210] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can be referred to the general design.

[0211] (2) In the case of no conflict, the features in the same and different embodiments of the present disclosure can be combined with each other.

[0212] The above merely describes specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. An address translation method applied to an address translation apparatus, the address translation apparatus comprising multiple sets of translation buffers, each set of translation buffers including first page table information for translating virtual addresses into physical addresses, the method comprising: In response to receiving a first virtual address translation request, a target translation buffer is determined from the plurality of translation buffers according to a first mapping algorithm, wherein the first virtual address translation request includes an object virtual address; and Access the first page table information in the target translation buffer to translate the object virtual address into the object physical address. The method further includes: Obtain the access frequency information for each of the multiple sets of conversion buffers; Based on the access frequency information, determine whether the first mapping algorithm needs to be updated; and In response to the need to update the first mapping algorithm, the first mapping algorithm is updated to the second mapping algorithm.

2. The method according to claim 1, wherein, The address translation device further includes a multi-level page table lookup module, which includes second page table information. Accessing the first page table information in the target translation buffer to translate the object virtual address to the object physical address includes: Access the first page table information in the target translation buffer to determine whether there is first target page table information in the first page table information that matches the first virtual address translation request; In response to the absence of the first target page table information in the target translation buffer, the first virtual address translation request is provided to the multi-level page table query module; Determine whether the second page table information contains second target page table information that matches the first virtual address translation request; and In response to the absence of a second target page table information matching the first virtual address translation request in the second page table information, the object virtual address is translated into the object physical address based on the translation information provided by the external memory.

3. The method according to claim 2, wherein, The first page table information includes multiple page table entries, each corresponding to a physical page. The second page table information includes multi-level page tables, each level of which includes multiple page directory entries. Each page directory entry points to the physical address of the next-level page table. In this context, each page directory entry in the last-level page table of the multi-level page table is used to point to a page table entry in the first page table information.

4. The method according to claim 3, wherein, Determining whether the second page table information exists and whether it matches the first virtual address translation request includes: Based on the object's virtual address and base address, obtain the first page table read address of at least one level of the multi-level page table; Based on the first page table read address, determine whether the second page table information contains second target page table information that matches the first virtual address translation request.

5. The method according to claim 4, wherein, In response to the absence of a second target page table information matching the first virtual address translation request in the second page table information, the object virtual address is translated into the object physical address based on the translation information provided by the external memory, including: In response to the fact that the second page table information does not contain second target page table information that matches the first virtual address translation request, it is determined whether the merging signal is valid; In response to the merging signal being valid, compare whether the first page table read address and the second page table read address of the second virtual address translation request preceding the first virtual address translation request are the same; In response to the first page table read address and the second page table read address being the same, the first virtual address translation request and the second virtual address translation request are merged, and the system waits for the external memory to respond with the translation information provided by the second virtual address translation request; and Based on the conversion information, the virtual address of the object is converted into the physical address of the object.

6. The method according to claim 5, wherein, In response to the absence of second target page table information matching the first virtual address translation request in the second page table information, the method of translating the object virtual address into the object physical address based on the translation information provided by the external memory further includes: In response to the fact that the first page table read address and the second page table read address are different, a page table read request based on the first virtual address translation request is provided to the external memory to obtain the translation information from the external memory; and The merged signal is updated to invalid.

7. The method according to claim 5, wherein, In response to the absence of second target page table information matching the first virtual address translation request in the second page table information, the method of translating the object virtual address into the object physical address based on the translation information provided by the external memory further includes: In response to the invalidation of the merge signal, a page table read request based on the first virtual address translation request is provided to the external memory to obtain the translation information from the external memory; and Update the merged signal to be valid.

8. The method according to claim 5, wherein, In response to the absence of second target page table information matching the first virtual address translation request in the second page table information, the method of translating the object virtual address into the object physical address based on the translation information provided by the external memory further includes: In response to receiving the translation information provided by the external memory in response to the second virtual address translation request, the merge signal is updated to invalid.

9. The method according to claim 6 or 7, wherein, The page table read request includes: the page table read address of the virtual address translation request, the object virtual address, and the hardware access unit identifier providing the virtual address translation request. The page table read address is obtained based on the base address and the page directory entry data of at least one level of the multi-level page table.

10. The method according to claim 3, wherein, Accessing the first page table information in the target translation buffer to translate the object virtual address to the object physical address includes: Access the first page table information in the target translation buffer to determine whether there is a target page table entry in the first page table information that matches the object virtual address translation request; In response to the existence of a target page table entry in the first page table information that matches the object virtual address translation request, the object physical address corresponding to the object virtual address is determined based on the target page table entry and the page offset indicated by the object virtual address.

11. The method according to claim 10, wherein, The conversion information includes the target page table entry.

12. The method according to claim 1, wherein, Obtaining access frequency information for each of the multiple sets of conversion buffers includes: The number of accesses to each of the multiple sets of conversion buffers is counted to obtain the count value of each of the multiple sets of conversion buffers within a preset time period.

13. The method according to claim 12, wherein, Based on the access frequency information, determining whether the first mapping algorithm needs to be updated includes: Based on the count value of each of the multiple sets of conversion buffers, calculate the average access value of the count values ​​of the multiple sets of conversion buffers; Obtain the allowed access deviation; Based on the allowed access deviation and the average access value, the effective access rate of the multiple sets of conversion buffers is calculated; Based on the effective access rate, determine whether the first mapping algorithm needs to be updated.

14. The method according to claim 13, wherein, Based on the allowed access deviation and the average access value, the effective access rate of the multiple sets of conversion buffers is calculated, including: Based on the allowed access deviation, calculate the access deviation value for each of the multiple sets of conversion buffers; Based on the access deviation value, an effective utilization indicator value is calculated for each of the multiple sets of switching buffers. Specifically, for each set of switching buffers, in response to the sum of the access deviation value and the count value being greater than or equal to the average access value, the effective utilization indicator value of the switching buffer is set to a first preset value; and in response to the sum of the access deviation value and the count value being less than the average access value, the effective utilization indicator value of the switching buffer is set to a second preset value. The average of the effective utilization indicators of the multiple sets of conversion buffers is taken as the effective access rate.

15. The method according to claim 14, wherein, Based on the effective access rate, determining whether the first mapping algorithm needs to be updated includes: In response to the effective access rate being greater than or equal to a preset access rate, it is determined that the first mapping algorithm does not need to be updated; In response to the effective access rate being less than the preset access rate, it is determined that the first mapping algorithm needs to be updated.

16. The method according to claim 1, wherein, The first mapping algorithm includes: determining the target translation buffer based on the first target bit of the object virtual address in the virtual address translation request. The second mapping algorithm includes: determining the target translation buffer based on the second target bit of the object virtual address in the virtual address translation request. The first target bit and the second target bit are different.

17. The method according to claim 16, wherein, The first target bit includes a plurality of consecutive first bits in the object virtual address, and the second target bit includes a plurality of consecutive second bits in the object virtual address.

18. An address translation device, comprising: The address translation module includes multiple sets of translation buffers; An arbitration module is configured to, in response to receiving a first virtual address translation request, determine a target translation buffer from the plurality of translation buffers according to a first mapping algorithm, wherein the first virtual address translation request includes an object virtual address; Each of the multiple sets of translation buffers is configured to store first page table information for converting the object's virtual address to the object's physical address. The address translation module is configured to access the first page table information in the target translation buffer to translate the object virtual address into the object physical address. The address translation device further includes: The address translation performance monitoring module is configured as follows: Obtain the access frequency information for each of the multiple sets of conversion buffers; Based on the access frequency information, determine whether the first mapping algorithm needs to be updated; and In response to the need to update the first mapping algorithm, the first mapping algorithm is updated to the second mapping algorithm.

19. The address translation apparatus according to claim 18, further comprising: A multi-level page table query module, which includes second-level page table information. The address translation module is configured as follows: Access the first page table information in the target translation buffer to determine whether there is first target page table information in the first page table information that matches the first virtual address translation request; In response to the absence of the first target page table information in the target translation buffer, the first virtual address translation request is provided to the multi-level page table query module; The multi-level page table query module is configured as follows: Receive the first virtual address translation request provided by the address translation module; Determine whether the second page table information contains second target page table information that matches the first virtual address translation request; and In response to the absence of a second target page table information matching the first virtual address translation request in the second page table information, translation information provided by the external memory is obtained, the translation information being used to translate the object virtual address into the object physical address.

20. The address translation device according to claim 19, wherein, The first page table information includes multiple page table entries, each corresponding to a physical page. The second page table information includes multi-level page tables, each level of which includes multiple page directory entries. Each page directory entry points to the physical address of the next-level page table. In this context, each page directory entry in the last-level page table of the multi-level page table is used to point to a page table entry in the first page table information.

21. The address translation device according to claim 20, wherein, The multi-level page table query module is configured as follows: Based on the object's virtual address and base address, obtain the first page table read address of at least one level of the multi-level page table; Based on the first page table read address, determine whether the second page table information contains second target page table information that matches the first virtual address translation request.

22. The address translation device according to claim 21, wherein, The multi-level page table query module includes a unit for merging identical read addresses and a conversion information caching unit. The same read address merging unit is configured as follows: In response to the fact that the second page table information does not contain second target page table information that matches the first virtual address translation request, it is determined whether the merging signal is valid; In response to the merging signal being valid, compare whether the first page table read address and the second page table read address of the second virtual address translation request preceding the first virtual address translation request are the same; In response to the first page table read address and the second page table read address being the same, the first virtual address translation request and the second virtual address translation request are merged, and the system waits for the external memory to respond with the translation information provided by the second virtual address translation request. The conversion information caching unit is configured to cache the conversion information and provide the conversion information to the address conversion module when the address conversion module is in an idle state.

23. An electronic device, comprising: processor; Memory, which includes one or more computer program instructions; The one or more computer program instructions are stored in the memory and, when executed by the processor, implement the address translation method according to any one of claims 1 to 17.

24. A computer-readable storage medium that non-temporarily stores computer-readable instructions, wherein, The address translation method according to any one of claims 1 to 17 is implemented when the computer-readable instructions are executed by a processor.

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