A three-dimensional package-on-package structure

Abstract

The application discloses a three-dimensional stacked packaging structure which realizes the effect of doubling the number of chip layers by combining two packaging structures, and solves the process bottleneck encountered by the current single packaging of multi-layer chips. The three-dimensional stacked packaging structure comprises an upper substrate, a lower substrate, a three-dimensional pad and a chip group, wherein the chip group comprises a group of master control chips and a plurality of storage chips; the upper substrate is placed on the upper portion of the lower substrate and is connected by bonding copper columns around to form an integral structure; a space region between the upper substrate and the lower substrate forms a chip stacking space; the three-dimensional pad is arranged vertically in the chip stacking space; the upper portion of the three-dimensional pad supports the lower surface of the upper substrate; the lower portion of the three-dimensional pad supports the upper surface of the lower substrate; the three-dimensional pad divides the chip stacking space into two side spaces, namely a first space and a second space; and the lower surface of the upper substrate corresponding to the first space and the second space sequentially stacks a plurality of corresponding storage chips.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a three-dimensional stacking packaging structure. Background Art

[0002] Existing packaging technologies all use a combination of wire bonding and flip-chip processes to achieve electrical connections between multi-layer stacked chip products. The wire bonding process is limited by the number of stacked chips. The more chip layers there are, the greater the risk of wire sweeps between gold wires. As a result, the higher the number of stacked chips, the lower the production yield.

[0003] How to stack more chips within a limited height space is a technical problem that chip packaging technology urgently needs to solve. Summary of the Invention

[0004] In response to the above problems, the present invention provides a three-dimensional stacked packaging structure, which doubles the number of chip layers by combining two packaging structures, solving the current process bottleneck encountered in individually packaging multi-layer chips.

[0005] A three-dimensional stacked packaging structure, characterized in that it comprises:

[0006] upper base plate;

[0007] lower base plate;

[0008] Three-dimensional pad;

[0009] and a chipset, which includes a set of main control chips and several memory chips;

[0010] The upper substrate is placed on the upper part of the lower substrate and is connected on all sides by bonding copper pillars to form an integral structure. The space area between the upper substrate and the lower substrate forms a chip stacking space. A vertically arranged three-dimensional pad is provided in the chip stacking space. The upper part of the three-dimensional pad supports the lower surface of the upper substrate, and the lower part of the three-dimensional pad is supported on the upper surface of the lower substrate. The three-dimensional pad divides the chip stacking space into two side spaces, namely the first space and the second space. The lower surface of the upper substrate corresponding to the first space and the second space is sequentially stacked with corresponding memory chips, and the upper surface of the lower substrate corresponding to the first space and the second space is sequentially stacked with corresponding memory chips. The main control chip is independently provided in one area of ​​the upper substrate or the lower substrate;

[0011] The positions of the three-dimensional pad corresponding to the first space and the second space are provided with corresponding number of convex solder joints according to the stacking state of the chip;

[0012] The memory chips stacked and mounted on the upper substrate and the lower substrate and the independently arranged main control chip are all connected to the corresponding convex solder joints of the three-dimensional solder pads through bonding gold wires.

[0013] It is further characterized by:

[0014] The upper substrate and the lower substrate are both independently stacked with chips at one time through the core loading machine, thereby improving assembly efficiency;

[0015] The three-dimensional pad is divided into an upper pad portion and a lower pad portion, wherein the areas of the upper pad portion corresponding to the first space and the second space are respectively provided with convex solder joints with side protrusions, and the areas of the lower pad portion corresponding to the first space and the second space are respectively provided with convex solder joints with side protrusions, and the convex solder joints of the lower pad portion corresponding to the first space and the second space are respectively connected to the chips on the lower substrate of the corresponding spaces through bonding gold wires, and the convex solder joints of the upper pad portion corresponding to the first space and the second space are respectively connected to the chips on the upper substrate of the corresponding spaces through bonding gold wires;

[0016] The lower surface of the upper substrate is provided with other components in addition to the chip;

[0017] The upper surface of the lower substrate is provided with other components in addition to the chip;

[0018] Preferably, the main control chip is only provided in the second space of the lower substrate, and the area of ​​the lower pad portion corresponding to the second space is only provided with one row of external convex solder joints;

[0019] A stacked chip group is arranged at a position corresponding to the first space of the lower substrate, and a corresponding number of convex solder joints are arranged in the same row as the stacked chips in the lower pad portion corresponding to the first space. The stacked chips at corresponding height positions are connected to the convex solder joints arranged at corresponding heights to ensure the correct connection;

[0020] A stacked chip group is arranged at positions corresponding to the first space and the second space of the upper substrate, and the areas corresponding to the first space and the second space of the upper pad portion are respectively provided with the same number of convex solder joints as the stacked chips, and the stacked chips at corresponding height positions are connected to the convex solder joints arranged at corresponding heights to ensure the correct connection;

[0021] The contacts of the stacked chips for connecting to the three-dimensional pads are arranged close to the three-dimensional pads, and the contacts of the stacked chips in the same group close to the three-dimensional pads are arranged in staggered layers, ensuring fast and reliable connection through bonding wires.

[0022] After adopting the above technical solution, the surfaces of the upper substrate and the lower substrate used for connecting chips are respectively completed with stacked chips, and then the three-dimensional pads are placed in a preset position, so that the three-dimensional pads separate the chip stacking space into two side spaces, namely the first space and the second space. The stacked chips corresponding to the first space and the second space of the upper substrate and the lower substrate are respectively connected to the corresponding external protruding contacts of the three-dimensional pads through bonding gold wires to complete the electrical interconnection of each chip. In terms of overall structural strength, the upper substrate and the lower substrate are connected around by bonding copper pillars to form an overall structure. The bonding copper pillars not only realize electrical interconnection, but also improve the overall strength. It achieves the effect of doubling the number of chip layers by combining the two packaging structures, solving the current process bottleneck encountered in separately packaging multi-layer chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of the main structure of a specific embodiment of the present invention;

[0024] Figure 2 It is a bottom view structural schematic diagram of the upper substrate in a stacked state according to a specific embodiment of the present invention;

[0025] Figure 3 It is a schematic top view of the structure of the lower substrate in a stacked state according to a specific embodiment of the present invention;

[0026] Figure 4 It is a schematic diagram of the left side view structure of a three-dimensional pad according to a specific embodiment of the present invention;

[0027] Figure 5 It is a schematic structural diagram of a right side view of a three-dimensional pad according to a specific embodiment of the present invention;

[0028] The names corresponding to the serial numbers in the figure are as follows:

[0029] Upper substrate 1, lower substrate 2, main control chip 3, bonding copper pillar 4, memory chip 5, solder ball 6, three-dimensional pad 7, resistor 8, capacitor 9, bonding gold wire 10, external convex solder joint 11, upper pad part 12, lower pad part 13, stacked layer wire 14;

[0030] The first space 20 and the second space 30. DETAILED DESCRIPTION

[0031] A three-dimensional stacked packaging structure, see Figure 1-Figure 5 : It includes an upper substrate 1, a lower substrate 2, a three-dimensional bonding pad 7, and a chipset;

[0032] In the specific embodiment, the chipset includes a group of main control chips 3 and a plurality of memory chips 5 , and the upper substrate 1 and the lower substrate 2 have the same surface coverage.

[0033] The upper substrate 1 is placed on the upper part of the lower substrate 2 and connected to the lower substrate 2 by bonding copper pillars 4 to form an integral structure. The solder balls 6 of the upper substrate 1 are arranged on the upper surface of the upper substrate 1, and the solder balls 6 of the lower substrate 2 are arranged on the lower surface of the lower substrate 2.

[0034] The space between the upper substrate 1 and the lower substrate 2 forms a chip stacking space. A vertically arranged three-dimensional pad 7 is provided in the chip stacking space. The upper portion of the three-dimensional pad 7 supports the lower surface of the upper substrate 1, and the lower portion of the three-dimensional pad 7 supports the upper surface of the lower substrate 2. The three-dimensional pad 7 divides the chip stacking space into two side spaces, namely a first space 20 and a second space 30. The lower surface of the upper substrate 1 corresponding to the first space 20 and the second space 30 is sequentially stacked with corresponding five memory chips 5. The surface of the lower substrate 2 corresponding to the first space 20 is sequentially stacked with corresponding five memory chips 5. The second space 30 of the lower substrate 2 is independently provided with a main control chip 3.

[0035] At the positions of the three-dimensional pad 7 corresponding to the first space 20 and the second space 30, corresponding layers of convex solder joints 11 are provided according to the stacking state of the chip;

[0036] The memory chip 5 stacked on the upper substrate 1 and the lower substrate 2 and the independently arranged main control chip 3 are all connected to the corresponding convex solder joints 11 of the three-dimensional solder pads 7 through bonding gold wires 10 .

[0037] During specific implementation, the upper substrate 1 and the lower substrate 2 are independently stacked with chips at one time through the chip loading machine, thereby improving assembly efficiency.

[0038] In a specific implementation, the three-dimensional pad 7 is divided into an upper pad portion 12 and a lower pad portion 13. The upper pad portion 12 is stacked on the lower pad portion 13 and a stacked layer line 14 is formed to ensure reliable bonding connection.

[0039] The areas of the upper pad portion 12 corresponding to the first space 20 and the second space 30 are respectively provided with side-convex convex solder joints 11, and the areas of the lower pad portion 13 corresponding to the first space 20 and the second space 30 are respectively provided with side-convex convex solder joints 11. The convex solder joints 11 corresponding to the first space 20 and the second space 30 of the lower pad portion 13 are respectively connected to the chips on the lower substrate 2 of the corresponding spaces through bonding wires 10, and the convex solder joints corresponding to the first space 20 and the second space 30 of the upper pad portion 12 are respectively connected to the chips on the upper substrate 1 of the corresponding spaces through bonding wires 10.

[0040] In a specific implementation, in addition to the chip, a resistor 8 and a capacitor 9 are also provided on the lower surface of the upper substrate;

[0041] In addition to the chip, a resistor 8 and a capacitor 9 are also provided on the upper surface of the lower substrate.

[0042] In a specific implementation, only the main control chip 3 is separately arranged in the second space 30 of the lower substrate 2, and only one row of external convex solder joints 11 is arranged in the area of ​​the lower pad portion 13 corresponding to the second space 30;

[0043] A group of five stacked memory chips 5 are arranged at positions corresponding to the first spaces 20 of the lower substrate 2. Five rows of external bumps 11 are arranged in the region corresponding to the first spaces 20 of the lower pad portion 13. The memory chips 5 at corresponding height positions and the external bumps 11 arranged at corresponding heights are connected to each other via bonding wires 10 to ensure correct connection.

[0044] A stacked chip group is provided at positions corresponding to the first space 20 and the second space 30 of the upper substrate 1. Each group of memory chips 5 has five memory chips 5. Five rows of external bumps 11 are provided in the areas corresponding to the first space 20 and the second space 30 of the upper pad portion 12. The memory chips 5 at corresponding height positions and the external bumps 11 arranged at corresponding heights are connected to each other via bonding wires 10 to ensure correct connection.

[0045] The contacts of the stacked memory chips 5 for connecting to the three-dimensional pad 7 are arranged close to the three-dimensional pad 7, and the contacts of the stacked chips 5 in the same group close to the three-dimensional pad 7 are staggered to ensure fast and reliable connection through bonding gold wires; in specific implementation, the memory chip located on the upper substrate is provided with a welding contact corresponding to the side close to the three-dimensional pad 7, and is arranged in a shrinking manner from top to bottom toward a position away from the three-dimensional pad 7, and the memory chip located on the lower substrate is provided with a welding contact corresponding to the side close to the three-dimensional pad 7, and is arranged in a shrinking manner from bottom to top toward a position away from the three-dimensional pad 7.

[0046] In a specific embodiment, the three-dimensional pad 7 is arranged perpendicular to the upper substrate 1 and the lower substrate 2 to ensure stable and reliable connection.

[0047] Its working principle is as follows: the surfaces of the upper substrate and the lower substrate used for connecting chips are each used to complete the stacked chips, and then the three-dimensional pads are placed in a preset position so that the three-dimensional pads separate the chip stacking space into two side spaces, namely the first space and the second space. The stacked chips corresponding to the first space and the second space of the upper substrate and the lower substrate are respectively connected to the corresponding external protruding contacts of the three-dimensional pads through bonding gold wires to complete the electrical interconnection of each chip. In terms of overall structural strength, the upper substrate and the lower substrate are connected around by bonding copper pillars to form an overall structure.

[0048] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0049] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A three-dimensional stacked packaging structure, characterized in that: It includes: upper base plate; lower base plate; Three-dimensional pad; and a chipset, which includes a set of main control chips and several memory chips; The upper substrate is placed on the upper part of the lower substrate and is connected on all sides by bonding copper pillars to form an integral structure. The space area between the upper substrate and the lower substrate forms a chip stacking space. A vertically arranged three-dimensional pad is provided in the chip stacking space. The upper part of the three-dimensional pad supports the lower surface of the upper substrate, and the lower part of the three-dimensional pad is supported on the upper surface of the lower substrate. The three-dimensional pad divides the chip stacking space into two side spaces, namely the first space and the second space. The lower surface of the upper substrate corresponding to the first space and the second space is sequentially stacked with corresponding memory chips, and the upper surface of the lower substrate corresponding to the first space and the second space is sequentially stacked with corresponding memory chips. The main control chip is independently provided in one area of ​​the upper substrate or the lower substrate; The positions of the three-dimensional pad corresponding to the first space and the second space are provided with corresponding number of convex solder joints according to the stacking state of the chip; The memory chips stacked and mounted on the upper substrate and the lower substrate and the independently arranged main control chip are all connected to the corresponding convex solder joints of the three-dimensional solder pads through bonding gold wires.

2. The three-dimensional stacked package structure according to claim 1, wherein: The upper substrate and the lower substrate are independently stacked with chips at one time through a core loading machine.

3. The three-dimensional stacked package structure according to claim 1, wherein: The three-dimensional pad is divided into an upper pad part and a lower pad part. The areas of the upper pad part corresponding to the first space and the second space are respectively provided with convex solder joints with side protrusions, and the areas of the lower pad part corresponding to the first space and the second space are respectively provided with convex solder joints with side protrusions. The convex solder joints of the lower pad part corresponding to the first space and the second space are respectively connected to the chips on the lower substrate of the corresponding spaces through bonding gold wires, and the convex solder joints of the upper pad part corresponding to the first space and the second space are respectively connected to the chips on the upper substrate of the corresponding spaces through bonding gold wires.

4. The three-dimensional stacked package structure according to claim 1, wherein: The lower surface of the upper substrate is provided with other components besides the chip; the upper surface of the lower substrate is provided with other components besides the chip.

5. The three-dimensional stacked package structure according to claim 3, wherein: The main control chip is only arranged in the second space of the lower substrate, and the area of ​​the lower pad portion corresponding to the second space is only provided with a row of external convex solder joints.

6. The three-dimensional stacked package structure according to claim 3, wherein: A group of stacked chips are set at the position corresponding to the first space of the lower substrate, and the lower pad part corresponding to the first space area is provided with the same number of corresponding rows of convex solder joints as the stacked chips, and the stacked chips at corresponding height positions are correspondingly connected to the convex solder joints arranged at corresponding heights.

7. The three-dimensional stacked package structure according to claim 6, wherein: A group of stacked chips are set at the positions corresponding to the first space and the second space of the upper substrate, and the areas corresponding to the first space and the second space of the upper pad part are respectively provided with the same number of corresponding rows of convex solder joints as the stacked chips, and the stacked chips at corresponding height positions are correspondingly connected to the convex solder joints arranged at corresponding heights.

8. The three-dimensional stacked package structure according to claim 7, wherein: The contacts of the stacked chips for connecting to the three-dimensional pads are arranged close to the three-dimensional pads, and the contacts of the stacked chips in the same group close to the three-dimensional pads are arranged in staggered layers.

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