A SiC MOSFET structure and a manufacturing method thereof

Abstract

The application relates to a SiC MOSFET structure and a manufacturing method thereof, a cell of the SiC MOSFET structure comprising: an N+ substrate, an N- epitaxial layer, a P hydrazine region and an N+ region arranged in sequence from bottom to top; at least one groove extending into the N- epitaxial layer, each groove having opposite side walls and a bottom; the side walls and the bottom of the groove in the N- epitaxial layer are provided with P+ injection regions; the inner surface of the groove is provided with a gate oxide layer and a gate, the gate comprises two parts, the width of the gate part facing away from the N- epitaxial layer is greater than the width of the gate part close to the N- epitaxial layer; an interlayer dielectric is arranged above the gate oxide layer and the gate; a source region is arranged above the N+ region at both ends of the groove; a source electrode is arranged above the interlayer dielectric and the source region; the application reduces the gate-drain parasitic capacitance C GD , improves the switching characteristic, reduces the power consumption and improves the chip reliability.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power semiconductors, and particularly relates to a SiC MOSFET structure and a manufacturing method thereof. BACKGROUND

[0002] SiC material has advantages of wide band gap, high thermal conductivity, high breakdown field strength, high saturation velocity, etc., and is very suitable for manufacturing high-temperature and high-power semiconductor devices. SiC-based power devices can greatly exert their characteristics of high temperature, high frequency and low loss, so that they have great application prospects in high voltage, high temperature, high frequency, high power, strong radiation, etc. Especially, SiC power MOSFET devices have been commercialized by many manufacturers.

[0003] With the improvement of use requirements, N-channel SiC MOSFET gradually develops from a planar structure to a trench structure; however, both the planar structure and the trench structure have a parasitic PIN body diode, which is turned on when the chip is reverse current flowing, causing a "bipolar degradation effect". The most effective solution at present is to integrate an SBD diode in the chip cell. "A novel SiC asymmetric cell trench mosfet with split gate and integrated JBS diode, J Zhang et al, JEDS. 2021. 3097390" proposes to integrate an SBD in the trench source region and obtains good results. However, such a design must reserve the critical dimension of the SBD in the source region, and cannot achieve further refinement of the cell. In addition, in order to achieve higher electric energy conversion efficiency, reducing the parasitic capacitance (especially the gate-drain capacitance CGD) in the SiC MOSFET structure has always been a research hotspot in the industry. SUMMARY

[0004] The technical problem to be solved by the application is to provide a SiC MOSFET structure and a manufacturing method thereof, which reduce the gate-drain parasitic capacitance C GD , improve the switching characteristics, reduce the power consumption, improve the reverse conduction capability and reverse recovery characteristics, improve the chip reliability, and improve the effective use area of the chip cell.

[0005] The SiC MOSFET structure provided by the embodiment of the application comprises:

[0006] An N+ substrate, an N- epitaxial layer, a P-hydrazine region and an N+ region are sequentially arranged from bottom to top;

[0007] At least one trench extending into the N- epitaxial layer, each trench having opposite side walls and a bottom;

[0008] The side wall and bottom of the trench in the N-epitaxial layer have P+ implantation regions;

[0009] The inner surface of the trench is provided with a gate oxide layer, and the gate oxide layer is provided with a gate electrode, the gate electrode comprises two parts, the width of the gate electrode part facing away from the N-epitaxial layer is greater than the width of the gate electrode part close to the N-epitaxial layer;

[0010] The gate oxide layer and the gate electrode are provided with an interlayer dielectric above them;

[0011] The source electrode region is provided above the N+ region at both ends of the trench;

[0012] The source electrode is provided above the interlayer dielectric and the source electrode region.

[0013] In one embodiment, the gate electrode comprises a tapered part and a columnar part, the width of the gate electrode of the tapered part gradually decreases in the direction of the N-epitaxial layer until it is equal to the width of the gate electrode of the columnar part, and at least a part of the tapered part is located in the N-epitaxial layer.

[0014] In one embodiment, the tapered part is in contact with the P+ implantation region, and the inclination of the tapered part in contact with the P+ implantation region is 42-28°, more preferably 45°.

[0015] In one embodiment, the shape of the gate electrode is tapered, and the width of the gate electrode gradually decreases in the direction of the N-epitaxial layer; further comprising a Schottky junction inside the gate electrode, the Schottky junction penetrates the P+ implantation region and enters the N-epitaxial layer, and the Schottky junction and the gate electrode are separated by an interlayer dielectric.

[0016] In one embodiment, the distance between the highest position of the P+ implantation region of the side wall of the trench and the uppermost end of the N-epitaxial layer is not less than 0.1 μm;

[0017] The concentration of the N+ substrate is greater than 5E18 cm -3 The concentration of the N-epitaxial layer is 1E14-5E16 cm -3 ;

[0018] The concentration of the P-well region is 1E16-1E18 cm -3 , and the thickness is 0.2-0.4 μm; the concentration of the N+ region is greater than 1E18 cm -3 , and the thickness is 0.2-0.4 μm; the doping concentration of the P+ implantation region is greater than 1E18 cm -3 , the depth of the P+ implantation region at the bottom of the trench is not less than 1.5 μm, and the thickness of the P+ implantation region of the side wall of the trench is not less than 0.2 μm;

[0019] The end face width of the trench away from the N-epitaxial layer is not more than 2 μm, and the end face width of the trench close to the N-epitaxial layer is not less than 0.2 μm.

[0020] In one embodiment, the number of trenches is greater than 2, and the trenches include deep trenches and shallow trenches, the depth of the deep trenches is greater than that of the shallow trenches;

[0021] The gate in the deep trench includes a tapered portion and a columnar portion, the gate width of the tapered portion gradually decreases in the direction of the N-epitaxial layer until it is equal to the gate width of the columnar portion, and at least a part of the tapered portion is located in the N-epitaxial layer;

[0022] The gate in the shallow trench is tapered in shape, and the gate width gradually decreases in the direction of the N-epitaxial layer; further including a Schottky junction located inside the gate, the Schottky junction penetrates the P+ implantation region and enters the N-epitaxial layer, and the Schottky junction is separated from the gate and the gate oxide layer by an interlayer dielectric.

[0023] In one embodiment, the number of gates is greater than 2, and the trenches include deep trenches and shallow trenches, the depth of the deep trenches is greater than that of the shallow trenches;

[0024] The gate in the deep trench includes two columnar portions with different widths, the columnar portion with a larger width at least partially extends into the N-epitaxial layer, and the columnar portion with a smaller width is completely located in the N-epitaxial layer, and the P+ implantation region is located in the region of the columnar portion with a smaller width;

[0025] The gate in the shallow trench is columnar in shape, and further includes a Schottky junction located inside the gate in the shallow trench, the Schottky junction penetrates the P+ implantation region and enters the N-epitaxial layer, and the Schottky junction is separated from the gate and the gate oxide layer by an interlayer dielectric.

[0026] In one embodiment, at least one side of the trench and the adjacent trench are provided with a P+ implantation region directly contacting the source region, and the P+ implantation region between the adjacent trenches is further connected with a P+ implantation region located on the sidewall of the trench, so that the P+ implantation region at the bottom of the trench does not float;

[0027] The depth of the shallow trench is 0.8-2 μm, and the depth of the deep trench is 1.5-4 μm.

[0028] Specifically, the P+ implantation region is arranged between at least one side of the trench and the adjacent trench, and is located below the source region and directly contacts and connects the source region, and the P+ implantation region between the adjacent trenches is further connected with the P+ implantation region located on the sidewall of the trench, so that the P+ implantation region at the bottom of the trench is not floating.

[0029] The P+ implantation region between the adjacent trenches can be arranged at some or multiple positions between the adjacent trenches (it can also be arranged at all positions between the adjacent trenches), and the thickness of the P+ implantation region between the adjacent trenches is not less than 1.2 μm.

[0030] The distance between the P+ implantation regions arranged at multiple positions between the adjacent trenches is not less than 1 μm, so as to prevent occupying too much current channel.

[0031] The P+ implantation region arranged between the adjacent two trenches has N, and the P+ implantation region arranged between the other two adjacent two trenches adjacent to the above-mentioned adjacent two trenches has M, and the N P+ implantation regions and the M P+ implantation regions are staggered with each other. N and M are greater than or equal to 1.

[0032] In one embodiment, the number of the trenches is at least 4, and the deep trenches and the shallow trenches are arranged at intervals.

[0033] In one embodiment, the back of the N+ substrate is sequentially provided with a silicon-nickel layer and a drain, and the source includes tungsten metal and source metal.

[0034] The embodiment of the present application provides a preparation method of the SiC MOSFET structure, and the preparation method comprises the following steps:

[0035] 1) sequentially preparing an N+ substrate, an N- epitaxial layer, a P+ implantation region and an N+ region on a SiC substrate;

[0036] 2) etching to form a trench, and implanting ions at the bottom and the sidewall of the trench to form a P+ implantation region;

[0037] 3) performing trench gate oxide, gate filling, interlayer dielectric deposition and source region preparation;

[0038] 4) opening the source region, preparing a source, and obtaining a SiC MOSFET structure.

[0039] The beneficial effects of this invention are as follows: The invention employs a split trench gate, which reduces the coupling area between the gate and drain, directly reducing the gate-drain parasitic capacitance (CGD), improving switching characteristics, and reducing power consumption. Simultaneously, integrating a Schottky junction in the split gate region can suppress the turn-on of the SiC MOSFET body diode in reverse conduction mode, improving reverse conduction capability and reverse recovery characteristics, and enhancing chip reliability. Furthermore, integrating a Schottky junction in the split gate region enables cell refinement, increasing the effective usable area of ​​the chip cells.

[0040] All trenches in this invention have current-carrying paths on both sides, and the use of the {0-33-8} high-mobility crystal plane as the channel current-carrying method can significantly reduce the on-resistance of the device.

[0041] This invention intermittently sets deep trenches and performs P+ deep junction injection, combined with intermittently sets shallow trenches and performs P+ shallow junction injection, which reduces the gate oxide electric field and also has a better Rdson-BV tradeoff.

[0042] The intermittent shallow trench split integrated Schottky diode forms a depletion extension layer to protect the trench gate oxide when forward biased; at the same time, it also has excellent freewheeling effect when reverse biased, preventing the device body diode from turning on and improving device reliability.

[0043] All trenches are designed with P+ protection or integrated Schottky diodes at the bottom, which reduces the coupling area between the gate bottom and the drain, directly reduces the gate-drain parasitic capacitance CGD, improves switching characteristics, and reduces device power consumption.

[0044] Regularly injecting P+ into the source region and grounding it can prevent P+ from floating, significantly improving the device's switching frequency and reducing losses. Attached Figure Description

[0045] Figure 1a This is a top view schematic diagram of the structure of Embodiment 1 of the present invention.

[0046] Figure 1b for Figure 1a AA ， Cross-sectional view.

[0047] Figure 2 This is a schematic diagram of the structure after step (1) of the preparation method in Embodiment 1 of the present invention.

[0048] Figure 3 This is a schematic diagram of the structure after step (2) of the preparation method in Example 1 of the present invention.

[0049] Figure 4 This is a schematic diagram of the structure after step (3) of the preparation method in Example 1 of the present invention.

[0050] Figure 5A schematic diagram of the structure after step (4) of the preparation method of Example 1 of the present application.

[0051] Figure 6 A schematic diagram of the structure after step (5) of the preparation method of Example 1 of the present application.

[0052] Figure 7 A schematic diagram of the structure of Example 2 of the present application. Figure 7 (a) is a schematic top view of the structure of Example 2, Figure 7 (b) is a schematic cross-sectional view of A-A of (a). Figure 7 (a). ，

[0053] Figure 8 A schematic diagram of the structure of Example 3 of the present application. Figure 8 (a) is a schematic top view of the structure of Example 3, Figure 8 (b) is a schematic cross-sectional view of A-A of (a). Figure 8 (a). ，

[0054] Figure 9 A schematic diagram of the structure of Example 4 of the present application. Figure 9 (a) is a schematic top view of the structure of Example 4, Figure 9 (b) is a schematic cross-sectional view of A-A of (a). Figure 9 (a). ，

[0055] Figure 10 A schematic diagram of the structure of Example 5 of the present application. Figure 10 (a) is a schematic top view of the structure of Example 5, Figure 10 (b) is a schematic cross-sectional view of A-A of (a). Figure 10 (a). ，

[0056] Figure 11 A schematic diagram of the structure of Example 6 of the present application. Figure 11 (a) is a schematic top view of the structure of Example 6, Figure 11 (b) is a schematic cross-sectional view of A-A of (a). Figure 11 (a). ，

[0057] Figure 12 A schematic diagram of the structure of Example 7 of the present application. Figure 12 (a) is a schematic top view of the structure of Example 7, Figure 12 (b) is a schematic cross-sectional view of A-A of (a). Figure 12 (a). ，

[0058] ​​​​​​In the figure, 1 is the drain, 2 is the nickel silicon layer, 3 is the N+ substrate, 4 is the N- epitaxial layer, 5 is the P+ implantation region, 6 is the gate oxide layer, 7 is the gate, 8 is the Schottky junction, 9 is the P-hydrazine region, 10 is the N+ region, 11 is the source region, 12 is the interlayer dielectric, 13 is the tungsten metal, 14 is the source metal, and 15 is the SiC layer. Detailed Implementation

[0059] Example 1

[0060] As shown in Figure 1, a SiC MOSFET structure is described, wherein the cell of the SiC MOSFET structure comprises:

[0061] The drain electrode 1, the nickel-silicon layer 2, the N+ substrate 3, the N- epitaxial layer 4, the P-hydrazine region 9, and the N+ region 10 are arranged sequentially from bottom to top.

[0062] At least one trench (four trenches in Example 1) extends into the N-epitaxial layer 4, each trench having opposing sidewalls and a bottom, the trenches extending from the N+ region 10 into the N-epitaxial layer 4. Figure 1b It is filled with gate oxide layer 6 and gate 7, which in Figure 3 The middle section is located above the P+ injection region;

[0063] The trench located within the N-epitaxial layer 4 has P+ implantation regions 5 on its sidewalls and bottom. The depth of the P+ implantation region 5 at the bottom of the trench depends on the ion implantation depth and is generally not less than 1.5 μm. The highest position of the P+ implantation region 5 on the sidewall of the trench is at a certain distance (≥0.1 μm) from the P-hydrazine region, that is, the highest position of the P+ implantation region 5 on the sidewall of the trench is at a certain distance (≥0.1 μm) from the top of the N-epitaxial layer 4. This allows for adjustment of the depletion layer size of the PN junction between the P+ implantation region 5 and the P-hydrazine region, increasing the current path and reducing the accumulation resistance of the device.

[0064] A gate oxide layer 6 is disposed on the inner surface of the trench, and a gate 7 is disposed within the gate oxide layer 6. The gate 7 comprises two parts, with the width of the gate 7 part facing away from the N-epitaxial layer 4 being greater than the width of the gate 7 part approaching the N-epitaxial layer 4.

[0065] The gate oxide layer 6 is made of silicon dioxide and exists only on the inner surface of the trench. Inside the gate oxide layer 6, at the center of the trench, a gate 7 is also disposed. The gate 7 is made of polysilicon. Both the gate oxide layer 6 and the gate 7 extend from the uppermost N+ region 10 into the N- epitaxial layer 4. The gate oxide layer 6 is located between the inner wall of the trench and the gate 7.

[0066] The trench is divided into two parts: the upper part is conical, and its width decreases from top to bottom; the lower part is columnar, and its width is equal to the width of the bottom of the cone. Therefore, the shape of the gate oxide layer 6 and the gate 7 filled in the trench is the same as the shape of the trench. In this embodiment, at least a portion of the cone extends into the N-epitaxial layer 4. Therefore, the trenches located in the P-hydrazine region 9 and the N+ region 10 are filled with the conical portion of the gate oxide layer 6 and the gate 7. All trenches of the present invention have current-passing paths on both sides. The conical portion contacts the P-hydrazine region 9, and the inclination of the conical portion in contact with the P-hydrazine region 9 is 45°. It can utilize the {0-33-8} high mobility crystal plane as the channel current-passing, which can significantly reduce the on-resistance of the device.

[0067] By adopting the above structure, the present invention utilizes the high mobility crystal plane {0-33-8} to conduct current, which significantly reduces the channel resistance of the device, thereby reducing the on-resistance of the device.

[0068] An interlayer dielectric 12 is disposed above the gate oxide layer 6 and the gate 7. The interlayer dielectric 12 not only completely covers the top of the gate oxide layer 6 and the gate 7, but also extends outward for a certain distance.

[0069] Source regions 11 are located at both ends of the trench and above the N+ region 10. The material of the source region 11 is a source alloy. The source alloy generally refers to NiSi compound generated by the reaction of Ni and its alloys with SiC at 1000℃. The source region 11 is located between the interlayer dielectric 12 and is used to draw out current.

[0070] A source electrode is disposed above the interlayer medium 12 and the source electrode region 11, and the source electrode includes tungsten metal 13 and source electrode metal 14.

[0071] In this embodiment, there are four trenches, including deep trenches and shallow trenches, and the depth of the deep trenches is greater than that of the shallow trenches.

[0072] The gate 7 in the deep trench includes a conical portion and a columnar portion. In the direction of the N-epitaxial layer 4, the width of the gate 7 in the conical portion gradually decreases until it is equal to the width of the gate 7 in the columnar portion. At least a portion of the conical portion is located in the N-epitaxial layer 4.

[0073] The gate 7 in the shallow trench is conical in shape, and its width gradually decreases towards the N-epitaxial layer 4. It also includes a Schottky junction 8 located inside the gate 7. The Schottky junction 8 penetrates the P+ implantation region 5 and enters the N-epitaxial layer 4. The Schottky junction 8 is separated from the gate 7 and the gate oxide layer 6 by an interlayer dielectric.

[0074] The deep trenches and shallow trenches in Embodiment 1 of the present invention are arranged alternately.

[0075] As shown in FIG. 1, the cell of the SiC MOSFET structure includes 2 deep trenches and 2 shallow trenches, from left to right, they are deep trench A, shallow trench B, deep trench C and shallow trench D, a P+ implantation region is arranged between deep trench A and shallow trench B, a P+ implantation region is arranged between deep trench C and shallow trench D, a P+ implantation region can be arranged or not arranged between shallow trench B and deep trench C, and FIG. 1 is a schematic diagram of not arranging a P+ implantation region. The P+ implantation region arranged between deep trench A and shallow trench B and the P+ implantation region arranged between deep trench C and shallow trench D are staggered with each other.

[0076] The P+ implantation region between adjacent trenches can be arranged at one or more positions between all positions of the trenches (it is also possible to arrange the P+ implantation region at all positions of the trenches), as shown in FIG. 1, the P+ implantation region between adjacent trenches is arranged at two positions, and the distance between the two P+ implantation regions is not less than 1 μm.

[0077] The preparation method of the SiC MOSFET structure of embodiment 1 is as follows,

[0078] 1) A SiC epitaxial wafer is provided, the substrate is a high-concentration N+ substrate 3, the concentration is greater than 5E18 cm -3 , and the epitaxial is a thinner N-type drift region, i.e. N-epitaxial layer 4, the drift region has a concentration of about 1E14~5E16 cm -3 , and the drift region concentration and thickness need to be optimized according to the chip voltage resistance.

[0079] P well, N+ and P+ ion implantation are sequentially performed on the SiC epitaxial wafer to form P well region 9, N+ region 10 and P+ implantation region, wherein the concentration of P well region 9 ranges from 1E16 to 1E18 cm -3 , and the thickness is 0.2-0.4 μm (i.e. y in Figure 2 ); the concentration of N+ region 10 is greater than 1E18 cm -3 , and the thickness is 0.2-0.4 μm (i.e. x in Figure 2 ); the doping concentration of P+ implantation region is greater than 1E18 cm -3 , and the depth of P+ implantation region is not less than 1.2 μm (i.e. z in Figure 2 ), as shown in Figure 2 .

[0080] 2) Trench etching forms deep trench and shallow trench structures (the deep trench is deeper than the shallow trench), the depth of the shallow trench ranges from 0.8 to 2 μm, the depth of the deep trench ranges from 1.5 to 4 μm, the end face width of the trench away from N-epitaxial layer 4 is not greater than 2 μm, and the end face width of the trench close to N-epitaxial layer 4 is not less than 0.2 μm, i.e. Figure 3The upper and lower surfaces of the blank areas are used. Combined with ion implantation technology, Pshield structures, i.e., P+ implantation regions 5, are formed at the bottom and sidewalls of both deep and shallow trenches. The Pshield ion implantation concentration is greater than 1E18cm⁻¹. -3 This ensures that the depth of the P+ injection region 5 at the bottom of the trench is ≥1.5 μm and the thickness of the P+ injection region 5 on the sidewall of the trench is ≥0.2 μm. Subsequently, a C-film is used to protect the trench, and ion implantation activation is performed at a high temperature of 1600℃-1800℃. Figure 3 As shown. The depth of the P+ injection region 5 at the bottom of the trench is not less than 1.5 μm, and the thickness of the P+ injection region 5 on the sidewall of the trench is not less than 0.2 μm.

[0081] 3) Perform processes such as trench gate oxide deposition, gate POLY filling, trench surface POLY etching back, interlayer dielectric deposition, source alloy opening, source Ni metal sputtering, and source ohmic alloying, etc. Figure 4 As shown.

[0082] 4) CMP process is used to remove Figure 5 The interlayer dielectric at the top of the middle trench is followed by a second etching of the shallow trench, with an etching depth greater than the Pshield junction depth. The etching mask on the sidewalls of the shallow trench is retained and filled with Schottky metal, followed by Schottky annealing to complete the split-gate SBD integration, thus obtaining Schottky junction 8, as shown below. Figure 5 As shown.

[0083] 5) Based on this, an interlayer dielectric layer is deposited on the surface, selectively opening holes to expose the source alloy, i.e., source region 11, and tungsten is used to fill the holes to guide the source alloy. A layer of source metal 14 is sputtered to complete all the front-side structures, such as... Figure 6 As shown.

[0084] 6) Finally, the back side is subjected to substrate thinning, Ni metal sputtering, laser annealing to form an ohmic alloy, and drain metal thickening. The final structure is as follows. Figure 1b As shown.

[0085] Example 2

[0086] like Figure 7 As shown, a SiC MOSFET structure is illustrated. The cell of the SiC MOSFET structure includes at least three deep trenches and one shallow trench. From left to right, the trenches are deep trench A, shallow trench B, and N deep trenches B. A P+ injection region is provided between deep trench A and the shallow trench, and a P+ injection region is provided between the N deep trenches B. A P+ injection region may or may not be provided between the shallow trench and the deep trench B to its right. Figure 7 This is a schematic diagram showing the absence of a P+ injection region.

[0087] The P+ injection region between adjacent trenches can not be provided between all positions of the trenches (it can also be provided between all positions of the trenches), but only provided at one or more positions between adjacent trenches. As shown in Figure 7 The P+ injection region between adjacent trenches is provided at two positions.

[0088] The N deep trenches B only need to satisfy that the P+ injection region is provided between at least one side of the trench and the adjacent trench, that is, when the number of deep trenches B is 3, the P+ injection region is provided between the 3 deep trenches, when the number of deep trenches B is 4, the P+ injection region can only need to be provided between the 1st and 2nd deep trenches B, the P+ injection region is provided between the 3rd and 4th deep trenches B, and the P+ injection region can not be provided between the 2nd and 3rd deep trenches B (it can also be provided, and it is preferred not to be provided). The other structures are the same as those in Embodiment 1.

[0089] Embodiment 3

[0090] As shown in Figure 8 A SiC MOSFET structure, the cell of the SiC MOSFET structure includes 2 deep trenches and at least 2 shallow trenches, from left to right, they are deep trench A, N shallow trenches B, deep trench C in sequence, the P+ injection region is provided between the deep trench A and the shallow trench B, the P+ injection region is provided between the N shallow trenches B, and the P+ injection region is provided between the shallow trench B and the deep trench C on the right side of the shallow trench B.

[0091] The P+ injection region between adjacent trenches can not be provided between all positions of the trenches (it can also be provided between all positions of the trenches), but only provided at one or more positions between adjacent trenches. As shown in Figure 8 The P+ injection region between adjacent trenches is provided at two positions.

[0092] The N deep trenches B only need to satisfy that the P+ injection region is provided between at least one side of the trench and the adjacent trench, that is, when the number of deep trenches B is 3, the P+ injection region is provided between the 3 deep trenches, when the number of deep trenches B is 4, the P+ injection region can only need to be provided between the 1st and 2nd deep trenches B, the P+ injection region is provided between the 3rd and 4th deep trenches B, and the P+ injection region can not be provided between the 2nd and 3rd deep trenches B (it can also be provided, and it is preferred not to be provided). The other structures are the same as those in Embodiment 1.

[0093] Embodiment 4

[0094] As shown in Figure 9 A SiC MOSFET structure, the cell of the SiC MOSFET structure includes 2 deep trenches A and 2 shallow trenches B, from left to right, they are deep trench A, 2 shallow trenches B, deep trench C in sequence.

[0095] The difference compared with Example 3 is that P+ injection region is provided at all positions between the 2nd and 3rd shallow trenches B. The rest is the same as Example 3.

[0096] Example 5

[0097] As shown in Figure 10 , a SiC MOSFET structure, the cell of the SiC MOSFET structure includes 4 deep trenches, from left to right in turn are deep trench A, deep trench B, deep trench C, deep trench D, P+ injection region is provided between deep trench A and deep trench B, P+ injection region is provided between deep trench C and deep trench D, no P+ injection region is provided between deep trench B and deep trench C, the rest is the same as Example 1.

[0098] Example 6

[0099] As shown in Figure 11 , a SiC MOSFET structure, the cell of the SiC MOSFET structure includes 4 shallow trenches, from left to right in turn are shallow trench A, shallow trench B, shallow trench C, shallow trench D, P+ injection region is provided between shallow trench A and shallow trench B, P+ injection region is provided between shallow trench C and shallow trench D, no P+ injection region is provided between shallow trench B and shallow trench C, the rest is the same as Example 1.

[0100] Example 7

[0101] As shown in Figure 12 , a SiC MOSFET structure, the cell of the SiC MOSFET structure includes 2 deep trenches and 2 shallow trenches. The deep trenches and shallow trenches are provided at intervals.

[0102] As shown in Figure 12 , from left to right in turn are deep trench A, shallow trench B, deep trench C and shallow trench D, P+ injection region is provided between deep trench A and shallow trench B, P+ injection region is provided between deep trench C and shallow trench D, no P+ injection region can be provided between shallow trench B and deep trench C, or P+ injection region can be provided, Figure 12 , which is a schematic diagram of not providing P+ injection region.

[0103] The P+ injection region between adjacent trenches can not be provided at all positions between the trenches (it is also possible to be provided at all positions between the trenches), but only at one or more positions between adjacent trenches. As shown in Figure 12 , the setting position of P+ injection region between adjacent trenches is 2.

[0104] The gate 7 in the deep trench comprises two columnar parts with different widths, the columnar part with a larger width extends at least partially into the N-epitaxial layer 4, and the columnar part with a smaller width is entirely located in the N-epitaxial layer 4, and the P+ implantation region 5 is located in the region of the columnar part with a smaller width;

[0105] The gate 7 in the shallow trench is columnar in shape, and further comprises a Schottky junction 8 located inside the gate 7 in the shallow trench, the Schottky junction 8 penetrates the P+ implantation region 5 and enters the N-epitaxial layer 4, and the Schottky junction 8 is separated from the gate 7 and the gate oxide layer 6 by an interlayer dielectric. The rest is the same as in Embodiment 1.

[0106] It should be understood by those of ordinary skill in the art that the above discussion of any of the embodiments is merely exemplary and is not intended to suggest any limitation as to the scope of protection; the above embodiments or technical features among different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes of different aspects of one or more embodiments of the present application as described above, which are not provided in detail for the sake of brevity.

[0107] One or more embodiments of the present application are intended to cover all such alternatives, modifications and variations as fall within the broad scope of the present application. Therefore, any omission, modification, equivalent replacement, improvement, etc. made in the spirit and principles of one or more embodiments of the present application should be included in the scope of protection of the present application.

Claims

1. A SiC MOSFET structure characterized by, The cell of the SiC MOSFET structure comprises: N+ substrate (3), N- epitaxial layer (4), P well region (9) and N+ region (10) arranged from bottom to top; At least one trench extending into the N- epitaxial layer (4), each trench having opposite sidewalls and a bottom; The sidewalls and the bottom of the trench in the N- epitaxial layer (4) have P+ implantation region (5); The inner surface of the trench is provided with a gate oxide layer (6), and the gate oxide layer (6) is provided with a gate electrode (7), the width of the gate electrode (7) part away from the N- epitaxial layer (4) is greater than the width of the gate electrode (7) part close to the N- epitaxial layer (4); The gate oxide layer (6) and the gate electrode (7) are provided with an interlayer dielectric (12) above; The source region (11) is arranged above the N+ region (10) at both ends of the trench; The interlayer dielectric (12) and the source region (11) are provided with a source electrode above; The number of trenches is greater than 2, the trenches include deep trenches and shallow trenches, and the depth of the deep trench is greater than that of the shallow trench; The shape of the gate electrode (7) in the shallow trench is conical, and the width of the gate electrode (7) gradually decreases in the direction of the N- epitaxial layer (4); further comprising a Schottky junction (8) inside the gate electrode (7), the Schottky junction (8) penetrates the P+ implantation region (5) and enters the N- epitaxial layer (4), and the Schottky junction (8) is separated from the gate electrode (7) and the gate oxide layer (6) by the interlayer dielectric; or, The shape of the gate electrode (7) in the shallow trench is columnar, and further comprising a Schottky junction (8) inside the gate electrode (7) in the shallow trench, the Schottky junction (8) penetrates the P+ implantation region (5) and enters the N- epitaxial layer (4), and the Schottky junction (8) is separated from the gate electrode (7) and the gate oxide layer (6) by the interlayer dielectric.

2. The SiC MOSFET structure of claim 1, wherein, The gate electrode (7) in the deep trench includes a conical part and a columnar part, and the width of the gate electrode (7) of the conical part gradually decreases in the direction of the N- epitaxial layer (4) until it is equal to the width of the gate electrode (7) of the columnar part, and at least a part of the conical part is located in the N- epitaxial layer (4).

3. The SiC MOSFET structure of claim 2, wherein, The conical part is in contact with the P well region (9), and the inclination of the conical part in contact with the P well region (9) is 42-28°.

4. The SiC MOSFET structure of claim 1, wherein, The distance between the highest position of the P+ implantation region (5) of the sidewall of the trench and the uppermost end of the N- epitaxial layer (4) is not less than 0.1 μm; The concentration of the N+ substrate (3) is greater than 5E18 cm -3 The concentration of the N- epitaxial layer (4) is 1E14 to 5E16 cm -3 ; The concentration of the P well region (9) ranges from 1E16 to 1E18 cm -3 The thickness of the N+ region (10) is 0.2-0.4 μm; the concentration of the N+ region (10) is greater than 1E18 cm -3 The thickness of the P+ injection region (5) is 0.2-0.4 μm; the doping concentration of the P+ injection region (5) is greater than 1E18 cm -3 The depth of the P+ injection region (5) at the bottom of the trench is not less than 1.5 μm, and the thickness of the P+ injection region (5) at the sidewall of the trench is not less than 0.2 μm; The end face width of the trench away from the N- epitaxial layer (4) is not greater than 2 μm, and the end face width of the trench close to the N- epitaxial layer (4) is not less than 0.2 μm.

5. The SiC MOSFET structure of claim 1, wherein, The number of gate electrodes (7) is greater than 2; The gate electrode (7) in the deep trench includes two columnar parts with different widths, the wide columnar part at least partially extends into the N- epitaxial layer (4), the narrow columnar part is completely located in the N- epitaxial layer (4), and the P+ implantation region (5) is located in the region of the narrow columnar part.

6. The SiC MOSFET structure of claim 5, wherein, At least one side of the trench and between the adjacent trench is provided with P+ implantation region in direct contact with the source region (11), and the P+ implantation region between the adjacent trenches is also connected with the P+ implantation region (5) on the sidewall of the trench, so that the P+ implantation region (5) at the bottom of the trench is not floating; The P+ implantation region between the adjacent trenches is provided at one or more positions between the adjacent trenches, and the thickness of the P+ implantation region between the adjacent trenches is not less than 1.2 μm; The distance between the P+ implantation regions provided at multiple positions between the adjacent trenches is not less than 1 μm; There are N P+ implantation regions between the adjacent two trenches, and there are M P+ implantation regions between the other two adjacent two trenches adjacent to the above-mentioned adjacent two trenches, and the N P+ implantation regions and the M P+ implantation regions are staggered with each other; The depth of the shallow trench is 0.8-2 μm, and the depth of the deep trench is 1.5-4 μm.

7. The SiC MOSFET structure of claim 6, wherein, The number of the trenches is at least 4, and the deep trenches and the shallow trenches are arranged at intervals.

8. The SiC MOSFET structure of claims 1-5, wherein, The back of the N+ substrate (3) is provided with a silicon-nickel layer (2) and a drain (1) in sequence, and the source includes tungsten metal (13) and source metal (14).

9. A method of producing a SiC MOSFET structure as claimed in any one of claims 1 to 8, characterized by, The method comprises the following steps, 1) sequentially preparing N+ substrate (3), N-epitaxial layer (4), P well region (9) and N+ region (10) on SiC substrate; 2) etching to form a trench, and implanting ions at the bottom and sidewall of the trench to form a P+ implantation region (5); 3) performing trench gate oxide, gate filling, interlayer dielectric deposition, and preparing a source region; 4) source region opening, preparing a source, and obtaining a SiC MOSFET structure.

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