Method for preparing solar cell and solar cell

Abstract

The present application provides a method for preparing a solar cell and a solar cell, the method comprising providing a silicon substrate, the silicon substrate having a relative front and back surface; depositing a first dielectric layer on the front side; forming alternatingly distributed P regions and N regions on the back side, the formation of the alternatingly distributed P regions and N regions comprising etching doped silicon with an alkaline solution, etching the first dielectric layer with an alkaline solution, and forming depressions and / or micropores on the surface of the first dielectric layer away from the silicon substrate; depositing a second dielectric layer on the surface of the first dielectric layer away from the silicon substrate, the temperature for depositing the second dielectric layer being lower than the temperature for depositing the first dielectric layer. The present application deposits the first dielectric layer at a higher temperature, which can improve the passivation effect and anti-reflection effect of the first dielectric layer, and deposits the second dielectric layer at a lower temperature to repair defects on the first dielectric layer, thereby avoiding deterioration of the utilization rate of light by the solar cell.

Description

Technical Field

[0001] The present application mainly relates to the field of photovoltaic technology, and in particular to a method for preparing a solar cell and a solar cell. Background Art

[0002] Interdigitated Back Contact Silicon Heterojunction Solar Cell (HBC) combines the advantages of interdigitated back contact solar cells and heterojunction solar cells with thin intrinsic layers. Interdigitated back contact heterojunction single crystal silicon solar cells have a silicon nitride film layer. During the cell production process, alkaline solutions will etch the silicon nitride layer, which will lead to defects in the silicon nitride layer, which will deteriorate the cell's utilization of light. Summary of the invention

[0003] The technical problem to be solved by the present application is to provide a method for preparing a solar cell and a solar cell, wherein the method for preparing a solar cell and the solar cell can repair depressions and holes on a nitride layer, thereby avoiding deterioration of the utilization rate of light by the solar cell.

[0004] To solve the above technical problems, the present application provides a method for preparing a solar cell, comprising: providing a silicon substrate, the silicon substrate having a relative front side and a back side; depositing a first dielectric layer on the front side; forming alternatingly distributed P regions and N regions on the back side, the formation of the alternatingly distributed P regions and N regions comprising the step of etching with an alkaline solution, the alkaline solution etches the first dielectric layer and forms depressions and / or micropores on the surface of the first dielectric layer away from the silicon substrate; and depositing a second dielectric layer on the surface of the first dielectric layer away from the silicon substrate, the temperature for depositing the second dielectric layer being lower than the temperature for depositing the first dielectric layer.

[0005] In an embodiment of the present application, the time duration for removing the second dielectric layer using the chemical solution containing hydrofluoric acid is shorter than the time duration for removing the first dielectric layer using the chemical solution containing hydrofluoric acid.

[0006] In one embodiment of the present application, the preparation method also includes: forming a third dielectric layer between the silicon substrate and the second dielectric layer, wherein the first dielectric layer and the third dielectric layer include silicon nitride, the second dielectric layer includes silicon oxynitride, the temperature for depositing the first dielectric layer and the third dielectric layer is 400°C~550°C, and the temperature for depositing the second dielectric layer is 160°C~220°C.

[0007] In one embodiment of the present application, the thickness of the third dielectric layer is 5nm~15nm, and the refractive index is 2.2~2.3; the thickness of the first dielectric layer is 10nm~30nm, and the refractive index is 1.9~2.1; the thickness of the second dielectric layer is 30nm~60nm, and the refractive index is 1.6~1.8.

[0008] In one embodiment of the present application, the P region includes stacked intrinsic amorphous silicon and doped amorphous silicon, the N region includes stacked tunneling oxide layers and doped polysilicon, or the P region includes stacked tunneling oxide layers and doped polysilicon, and the N region includes stacked intrinsic amorphous silicon and doped amorphous silicon.

[0009] In one embodiment of the present application, before depositing the first dielectric layer, the silicon substrate is subjected to texturing and polishing to form a front surface with a pyramid structure and a back surface with a polished surface.

[0010] In one embodiment of the present application, the silicon substrate is double-sided polished to first form the N region and then the P region. After forming the N region and before forming the P region, the front side is textured to form a front side with a pyramid structure, wherein the N region includes stacked tunneling oxide layers and doped polysilicon.

[0011] On the other hand, the present application also proposes a solar cell, including a silicon substrate having a relative front side and a back side; a first dielectric layer located on the front side; P regions and N regions alternately distributed on the back side, and the surface of the first dielectric layer facing away from the silicon substrate has depressions and / or micropores; and a second dielectric layer located on the surface of the first dielectric layer facing away from the silicon substrate.

[0012] In an embodiment of the present application, the second dielectric layer fills the recess and / or the microhole.

[0013] In an embodiment of the present application, the time duration for removing the second dielectric layer using the chemical solution containing hydrofluoric acid is shorter than the time duration for removing the first dielectric layer using the chemical solution containing hydrofluoric acid.

[0014] In one embodiment of the present application, the solar cell also includes a third dielectric layer, which is located between the silicon substrate and the first dielectric layer, the first dielectric layer and the third dielectric layer include silicon nitride, the second dielectric layer includes silicon oxynitride, the temperature for depositing the first dielectric layer and the third dielectric layer is 400°C~550°C, and the temperature for depositing the second dielectric layer is 160°C~220°C.

[0015] In one embodiment of the present application, the thickness of the third dielectric layer is 5nm~15nm, and the refractive index is 2.2~2.3; the thickness of the first dielectric layer is 10nm~30nm, and the refractive index is 1.9~2.1; the thickness of the second dielectric layer is 30nm~60nm, and the refractive index is 1.6~1.8.

[0016] In one embodiment of the present application, the P region includes stacked intrinsic amorphous silicon and doped amorphous silicon, the N region includes stacked tunneling oxide layers and doped polysilicon, or the P region includes stacked tunneling oxide layers and doped polysilicon, and the N region includes stacked intrinsic amorphous silicon and doped amorphous silicon.

[0017] Compared with the prior art, the present application has the following advantages: the present application deposits the first dielectric layer at a higher temperature, which can improve the passivation effect and anti-reflection effect of the first dielectric layer, and deposits the second dielectric layer at a lower temperature to repair defects on the first dielectric layer, thereby avoiding deterioration of the utilization rate of light by the solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are included to provide a further understanding of the present application. They are included and constitute a part of the present application. The accompanying drawings illustrate embodiments of the present application and together with the present specification serve to explain the principles of the present application. In the accompanying drawings:

[0019] Figure 1 is a schematic flow chart of a method for preparing a solar cell in one embodiment of the present application;

[0020] Figures 2 to 6 is a schematic cross-sectional view of a solar cell in different steps in an embodiment of the present application;

[0021] Figure 7 is a schematic cross-sectional view of a solar cell in one embodiment of the present application.

[0022] Reference numerals

[0023] Silicon substrate 210 , front surface 211 , back surface 212 , first dielectric layer 220 , P region 230 , N region 240 , second dielectric layer 250 , third dielectric layer 260 , transparent conductive layer 270 , electrode 280 , and insulating groove 290 . DETAILED DESCRIPTION

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for the description of the embodiments. Obviously, the drawings described below are only some examples or embodiments of the present application. For ordinary technicians in this field, the present application can also be applied to other similar scenarios based on these drawings without creative work. Unless it is obvious from the language environment or otherwise explained, the same reference numerals in the figures represent the same structure or operation.

[0025] As shown in this application and claims, unless the context clearly indicates an exception, the words "a", "an", "an" and / or "the" do not refer to the singular and may also include the plural. Generally speaking, the terms "include" and "comprise" only indicate the inclusion of the steps and elements that have been clearly identified, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements.

[0026] Unless otherwise specifically stated, the relative arrangement, numerical expressions and numerical values ​​of the parts and steps set forth in these embodiments do not limit the scope of the present application. At the same time, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to the actual proportional relationship. The technology, method and equipment known to those of ordinary skill in the relevant field may not be discussed in detail, but in appropriate cases, the technology, method and equipment should be considered as a part of the authorization specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so that once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings.

[0027] In the description of the present application, it should be understood that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific direction or be constructed and operated in a specific direction, and therefore cannot be understood as limiting the scope of protection of the present application; the directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0028] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used here to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.

[0029] In addition, it should be noted that the use of words such as "first" and "second" to define components is only for the convenience of distinguishing the corresponding components. If not otherwise stated, the above words have no special meaning and cannot be understood as limiting the scope of protection of this application. In addition, although the terms used in this application are selected from well-known and commonly used terms, some terms mentioned in the specification of this application may be selected by the applicant at his or her discretion, and their detailed meanings are explained in the relevant parts of the description of this article. In addition, it is required to understand this application not only by the actual terms used, but also by the meaning implied by each term.

[0030] Flowcharts are used in the present application to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed accurately in order. On the contrary, various steps may be processed in reverse order or simultaneously. At the same time, other operations may be added to these processes, or one or more operations may be removed from these processes.

[0031] Next, the preparation method of the solar cell and the solar cell of the present application are described through examples.

[0032] refer to Figure 1 The schematic diagram of the process of a method for preparing a solar cell in an embodiment is shown. The method of this embodiment includes the following steps S110 to S140.

[0033] Step S110: providing a silicon substrate, wherein the silicon substrate has a front side and a back side opposite to each other;

[0034] Step S120: depositing a first dielectric layer on the front side;

[0035] Step S130: forming alternately distributed P regions and N regions on the back side, wherein the forming of the alternately distributed P regions and N regions comprises the step of etching with an alkaline solution, wherein the alkaline solution etches the first dielectric layer and forms depressions and / or micropores on the surface of the first dielectric layer away from the silicon substrate;

[0036] Step S140: depositing a second dielectric layer on a surface of the first dielectric layer facing away from the silicon substrate, wherein the temperature for depositing the second dielectric layer is lower than the temperature for depositing the first dielectric layer.

[0037] Next, steps S110 to S140 are described in detail.

[0038] refer to Figure 2 As shown, in step S110, a silicon substrate 210 is provided, wherein the silicon substrate 210 has a front side 211 and a back side 212 opposite to each other. When the solar cell is working, the front side 211 faces the sun. The silicon substrate 210 may be N-type doped single crystal silicon or P-type doped single crystal silicon.

[0039] refer to Figure 3 As shown, in step S120, a first dielectric layer 220 is deposited on one side of the front surface 211. The first dielectric layer 220 may be in contact with the front surface 211, or may not be in contact with the front surface 211, that is, other film layers are formed between the first dielectric layer 220 and the front surface 211, for example, an aluminum oxide layer (not shown) may be formed between the front surface 211 and the first dielectric layer 220, and the aluminum oxide layer may be deposited on the front surface 211 by means of an atomic layer deposition process (ALD).

[0040] refer to Figure 4 As shown, in step S130, alternately distributed P regions 230 and N regions 240 are formed on one side of the back side 212. The process of forming the alternately distributed P regions 230 and N regions 240 includes the step of etching with an alkaline solution, for example, etching the silicon substrate with an alkaline solution to remove damage caused by the laser. During the etching process with the alkaline solution, the alkaline solution will also etch the first dielectric layer 220. After the first dielectric layer 220 is etched, depressions and / or micropores will be formed on the surface 221 away from the silicon substrate 210.

[0041] In one embodiment, the P region includes stacked intrinsic amorphous silicon and P-type doped amorphous silicon, and the N region includes stacked tunneling oxide layers and N-type doped polysilicon, or the P region includes stacked tunneling oxide layers and P-type doped polysilicon, and the N region includes stacked intrinsic amorphous silicon and N-type doped amorphous silicon.

[0042] refer to Figure 5As shown, in step S140, a second dielectric layer 250 is deposited on a surface of the first dielectric layer 220 away from the silicon substrate 210. The temperature at which the second dielectric layer 250 is deposited is lower than the temperature at which the first dielectric layer 220 is deposited. The second dielectric layer 250 is in contact with the surface of the first dielectric layer 220 away from the silicon substrate 210. The first dielectric layer 220 may include silicon nitride (SiN x ), the second dielectric layer 250 may include silicon oxynitride (Si x N y The first dielectric layer 220 and the second dielectric layer 250 may be deposited by plasma enhanced chemical deposition (PECVD). The temperature for depositing the first dielectric layer 220 may be any temperature in the range of 400°C to 550°C, preferably 500°C. The temperature for depositing the second dielectric layer 250 may be any temperature in the range of 160°C to 220°C.

[0043] Here, the technical effect of "the temperature for depositing the second dielectric layer 250 is lower than the temperature for depositing the first dielectric layer 220" is explained. Depositing the first dielectric layer 220 at a higher temperature can improve the passivation effect and anti-reflection effect of the first dielectric layer 220, but the alkaline solution in step S130 will etch the first dielectric layer 220, so that numerous depressions and / or micropores are formed on the surface 221 of the first dielectric layer 220. These depressions and micropores will increase the absorption and reflection of incident light by silicon nitride, thereby deteriorating the utilization rate of light by solar cells. In order to solve this problem, the present application simultaneously deposits the second dielectric layer 250 at a lower temperature to repair the defects on the surface 221, thereby avoiding deteriorating the utilization rate of light by solar cells.

[0044] In one embodiment, the time taken to remove the second dielectric layer 250 using a chemical solution containing hydrofluoric acid is shorter than the time taken to remove the first dielectric layer 220 using a chemical solution containing hydrofluoric acid. For example, the test results of the present application show that the time taken to remove the second dielectric layer 250 using a hydrofluoric acid solution having a mass concentration of 2% is 2 minutes, and the time taken to remove the first dielectric layer 220 using a hydrofluoric acid solution having a mass concentration of 5% is greater than 2 minutes, and even reaches 6 minutes. The fact that the first dielectric layer 220 has a greater corrosion resistance to hydrofluoric acid than the second dielectric layer 250 helps to improve the ability of the second dielectric layer 250 to repair defects and holes on the surface 221 of the first dielectric layer 220.

[0045] refer to Figure 6As shown, in one embodiment, the preparation method of the present application also includes forming a third dielectric layer 260 between the silicon substrate 210 and the first dielectric layer 220, the first dielectric layer 220 and the third dielectric layer 260 include silicon nitride, and the second dielectric layer 250 includes silicon oxynitride. The temperature for depositing the first dielectric layer 220 and the third dielectric layer 260 is 400°C~550°C, for example, the deposition temperature is 400°C, 420°C, 440°C, 460°C, 480°C, 500°C, 520°C, 540°C or 550°C, preferably, the deposition temperature is 500°C; the temperature for depositing the second dielectric layer 250 is 160°C~220°C, for example, the deposition temperature is 160°C, 180°C, 200°C or 220°C.

[0046] refer to Figure 6 As shown, in one embodiment, the thickness of the third dielectric layer 260 is 5nm~15nm, for example, the thickness is 5nm, 10nm or 15nm, and the refractive index is 2.2~2.3, for example, the refractive index is 2.2, 2.25 or 2.3; the thickness of the first dielectric layer 220 is 10nm~30nm, for example, the thickness is 10nm, 20nm or 30nm, and the refractive index is 1.9~2.1, for example, the refractive index is 1.9, 2.0 or 2.1; the thickness of the second dielectric layer is 30nm~60nm, for example, the thickness is 30nm, 40nm, 50nm or 60nm, and the refractive index is 1.6~1.8, for example, the refractive index is 1.6, 1.7 or 1.8. The total thickness of the first dielectric layer 220 and the third dielectric layer 260 can be controlled to be no greater than 40 nm, and the total thickness of the first dielectric layer 220, the third dielectric layer 260 and the second dielectric layer 250 is 65 nm to 90 nm, for example, the total thickness is 65 nm, 75 nm, 85 nm or 90 nm.

[0047] refer to Figure 7 As shown, in one embodiment, the preparation method of the present application further includes forming a transparent conductive layer 270, an electrode 280 and an insulating groove 290. Specifically, a transparent conductive layer 270 covering the P region 230 and the N region 240 is first formed, then an insulating groove 290 penetrating the transparent conductive layer 270 is formed, and finally, an electrode 280 is formed on the transparent conductive layer 270. Figure 7 In the embodiment, the insulating groove 290 is located at the junction of the P region 230 and the N region 240. The position of the insulating groove 290 can be set according to the requirements, and is not limited to Figure 7 shown.

[0048] In one embodiment, before depositing the first dielectric layer, the silicon substrate is subjected to a texturing treatment and a polishing treatment to form a front side with a pyramid structure and a back side with a polished surface. The front side with a pyramid structure can reduce the reflection of incident light by the solar cell. In another embodiment, the silicon substrate is subjected to a double-sided polishing treatment, and an N region is first formed on the back side of the silicon substrate, and then a P region is formed on the back side of the silicon substrate. After forming the N region and before forming the P region, the front side is subjected to a texturing treatment to form a front side with a pyramid structure, wherein the N region includes a stacked tunneling oxide layer and doped polysilicon. The above-mentioned step of forming the back side with a polished surface is conducive to avoiding the occurrence of TCO residue when the transparent conductive layer (TCO) is subjected to an insulating groove opening treatment.

[0049] In order to more clearly understand the preparation method and technical effects of the present application, a non-limiting example and comparative example are given here. Example

[0050] Step 1: Prepare a back-polished silicon substrate. Specifically, a dielectric layer is deposited on the front side of a double-sided velvet silicon substrate, the back side is polished and cleaned, and then the dielectric layer is removed. The dielectric layer is used to protect the front side from the impact of polishing.

[0051] Step 2: Deposit a tunneling oxide layer and an N-type doped polysilicon layer (n-poly) on the back side. Specifically, a layer of silicon dioxide is deposited on the back side as the tunneling oxide layer and the N-type doped polysilicon layer using a low pressure chemical deposition process (LPCVD), and the thickness of the N-type doped polysilicon layer is 150nm.

[0052] Step 3: depositing a silicon nitride mask on the N-type doped polysilicon layer. Specifically, a PECVD process is used to deposit a silicon nitride mask with a thickness of 60 nm, a deposition temperature of 450° C., and a refractive index of 1.92.

[0053] Step 4: Remove the silicon nitride mask plated on the front side of the silicon substrate. Specifically, DHF cleaning is performed on a chain cleaning machine to remove the silicon nitride plated on the front side of the silicon wafer, the mass concentration of HF is 10%, and the process time is 500s.

[0054] Step 5: Deposit aluminum dioxide and three layers of silicon nitride on the front of the silicon substrate. Specifically, use the atomic layer deposition process (ALD) to deposit aluminum dioxide with a thickness of 5nm on the front of the silicon substrate, and then use the PECVD process to deposit three layers of silicon nitride on the aluminum dioxide. The deposition temperature is 400°C. The thickness of the first layer of silicon nitride is 7nm, and the optical refractive index is 2.2. The thickness of the second layer of silicon nitride is 12nm, and the optical refractive index is 2; the third layer of silicon nitride is 20nm, and the optical refractive index is 1.92.

[0055] Step 6: Form a P region and an N region on the back side of the silicon substrate. Specifically, use a laser to remove the silicon nitride mask, N-type doped polysilicon layer and silicon dioxide located in the P region, and use a 5% volume concentration KOH solution (or other alkaline solutions) to etch the exposed silicon substrate to remove the damage caused by the laser to the silicon substrate. The KOH solution will also etch the third layer of silicon nitride away from the surface of the silicon substrate, forming depressions and holes on the surface. The removal temperature is 50°C and the process time is 60s; then, an intrinsic amorphous silicon layer and a P-type doped microcrystalline silicon layer are deposited on the back of the exposed silicon substrate; finally, use a laser to remove the intrinsic amorphous silicon layer and the P-type doped microcrystalline silicon layer located on the N region, and use a 10% volume concentration HF solution to remove the oxide layer caused by laser etching.

[0056] Step 7: Deposit silicon oxynitride on the third silicon nitride layer. Specifically, a PECVD process is used to deposit silicon oxynitride with a thickness of 40 nm on the third silicon nitride layer, the deposition temperature is 200°C (lower than the temperature for depositing the first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer), the refractive index is 1.65, and the total thickness of the first silicon nitride layer, the second silicon nitride layer, the third silicon nitride layer, and the silicon oxynitride is 79 nm.

[0057] Step 8: Forming TCO and electrodes.

[0058] Comparative Example

[0059] Step 1: Prepare a back-polished silicon substrate.

[0060] Step 2: Back tunneling oxide layer and n-poly deposition.

[0061] Step 2: Deposit a tunneling oxide layer and an N-type doped polysilicon layer with a thickness of 150 nm on the back side using LPCVD as the deposition process.

[0062] Step 3: depositing a silicon nitride mask on the N-type doped polysilicon layer. Specifically, the silicon nitride mask is deposited using a PECVD process, with a deposition temperature of 450° C., a film thickness of 60 nm, and a refractive index of 1.92.

[0063] Step 4: Remove the silicon nitride mask plated on the front side of the silicon substrate. Specifically, DHF cleaning is performed on a chain cleaning machine to remove the silicon nitride plated on the front side of the silicon wafer, the mass concentration of HF is 10%, and the process time is 500s.

[0064] Step 5: Deposit aluminum dioxide, three layers of silicon nitride, and silicon oxynitride on the front of the silicon substrate. Specifically, use the atomic layer deposition process (ALD) to deposit a 5nm thick aluminum dioxide film on the silicon substrate. Then, use the PECVD process to deposit three layers of silicon nitride on the aluminum dioxide. The deposition temperature is 400°C. The thickness of the first layer of silicon nitride is 7nm, and the optical refractive index is 2.2. The thickness of the second layer of silicon nitride is 12nm, and the optical refractive index is 2; the third layer of silicon nitride is 20nm, and the optical refractive index is 1.92; on the third layer of silicon nitride, a 45nm thick silicon oxynitride is deposited, and the refractive index is 1.65.

[0065] Step 6: Form a P region and an N region on the back side of the silicon substrate.

[0066] Step 7: Forming TCO and electrodes.

[0067] The parameters of the solar energy in the above embodiment and comparative example were tested, and the following test results were obtained. The battery conversion efficiency in the embodiment was 26.27%, the open circuit voltage was 742 mv, and the short circuit current was 41.8 mA / cm 2 , fill factor is 84.7%, the battery conversion efficiency in the comparative example is 26.5%9, the open circuit voltage is 744 mv, and the short circuit current is 42.1 mA / cm 2 , the filling factor is 84.9%. Compared with the example, the comparative example did not repair the depressions and holes caused by the alkaline solution, while the example repaired the depressions and holes, so all the test results in the example were better than those in the comparative example.

[0068] On the other hand, the present application also proposes a solar cell, Figure 7 As shown, a solar cell in one embodiment includes a silicon substrate 210 , a first dielectric layer 220 , a second dielectric layer 250 , a third dielectric layer 260 , a P region 230 and an N region 240 .

[0069] Specifically, the substrate 210 has a front side 211 and a back side 212 opposite to each other. The third dielectric layer 260, the first dielectric layer 220, and the second dielectric layer 250 are sequentially stacked on the front side 211, the second dielectric layer 250 is in contact with the surface of the first dielectric layer 220 facing away from the silicon substrate 210, and the surface of the first dielectric layer 220 facing away from the silicon substrate 210 has depressions and / or micropores. A layer of aluminum oxide may be formed between the silicon substrate 210 and the third dielectric layer 260, and the aluminum oxide has a passivation effect, and the solar cell may not have the third dielectric layer 260.

[0070] In one embodiment, the first dielectric layer 220 and the third dielectric layer 260 include silicon nitride, and the second dielectric layer 250 includes silicon oxynitride. The first dielectric layer 220, the second dielectric layer 250, and the third dielectric layer 260 may be formed using a PECVD process, and the temperature for forming the second dielectric layer 250 is lower than the temperature for forming the first dielectric layer 220 and the third dielectric layer 260. In a more specific embodiment, the temperature for depositing the first dielectric layer 220 and the second dielectric layer 250 is 400° C. to 550° C.; the temperature for depositing the third dielectric layer 260 is 160° C. to 220° C. The time for removing the second dielectric layer 250 using a chemical solution containing hydrofluoric acid is shorter than the time for removing the first dielectric layer 220 using a chemical solution containing hydrofluoric acid.

[0071] In one embodiment, the second dielectric layer 250 fills the depressions and micropores on the first dielectric layer 220. In this way, the utilization rate of light by the solar cell can be improved.

[0072] In one embodiment, the third dielectric layer 260 has a thickness of 5 nm to 15 nm and a refractive index of 2.2 to 2.3, the first dielectric layer 220 has a thickness of 10 nm to 30 nm and a refractive index of 1.9 to 2.1, and the second dielectric layer 250 has a thickness of 30 nm to 60 nm and a refractive index of 1.6 to 1.8.

[0073] The P region 230 and the N region 240 are alternately distributed on one side of the back surface 212. In one embodiment, the P region 230 includes stacked intrinsic amorphous silicon and doped amorphous silicon, and the N region 240 includes stacked tunnel oxide layers and doped polysilicon, or the P region 230 includes stacked tunnel oxide layers and doped polysilicon, and the N region 240 includes stacked intrinsic amorphous silicon and doped amorphous silicon.

[0074] The solar cell may further include a transparent conductive layer 270 , an electrode 280 , and an insulating trench 290 .

[0075] For other descriptions about the solar cell of the present application, please refer to the description of the preparation method above, which will not be elaborated here.

[0076] The basic concepts have been described above. Obviously, for those skilled in the art, the above application disclosure is only an example and does not constitute a limitation of the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and amendments to the present application. Such modifications, improvements and amendments are suggested in the present application, so such modifications, improvements and amendments still belong to the spirit and scope of the exemplary embodiments of the present application.

[0077] At the same time, the present application uses specific words to describe the embodiments of the present application. For example, "one embodiment", "an embodiment", and / or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more in different positions in this specification does not necessarily refer to the same embodiment. In addition, some features, structures or characteristics in one or more embodiments of the present application can be appropriately combined.

[0078] Similarly, it should be noted that in order to simplify the description of the disclosure of this application and thus help understand one or more application embodiments, in the above description of the embodiments of this application, multiple features are sometimes merged into one embodiment, figure or description thereof. However, this disclosure method does not mean that the features required by the object of this application are more than the features mentioned in the claims. In fact, the features of the embodiments are less than all the features of the single embodiment disclosed above.

[0079] In some embodiments, numbers describing the number of components and attributes are used. It should be understood that such numbers used for the description of the embodiments are modified by the modifiers "about", "approximately" or "substantially" in some examples. Unless otherwise specified, "about", "approximately" or "substantially" indicate that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which can be changed according to the required features of individual embodiments. In some embodiments, the numerical parameters should take into account the specified significant digits and adopt the method of general digit retention. Although the numerical domains and parameters used to confirm the breadth of the range in some embodiments of the present application are approximate values, in specific embodiments, the setting of such numerical values ​​is as accurate as possible within the feasible range.

[0080] Although the present application has been described with reference to the current specific embodiments, ordinary technicians in this technical field should recognize that the above embodiments are only used to illustrate the present application, and various equivalent changes or substitutions may be made without departing from the spirit of the present application. Therefore, as long as the changes and modifications to the above embodiments are within the essential spirit of the present application, they will fall within the scope of the claims of the present application.

Claims

1. A method for preparing a solar cell, characterized in that: include: Providing a silicon substrate having opposite front and back surfaces; Depositing a first dielectric layer on the front side; Forming alternately distributed P regions and N regions on one side of the back surface, wherein the forming of the alternately distributed P regions and N regions comprises the step of etching with an alkaline solution, wherein the alkaline solution etches the first dielectric layer and forms depressions and / or micropores on a surface of the first dielectric layer away from the silicon substrate; as well as A second dielectric layer is deposited on a surface of the first dielectric layer facing away from the silicon substrate, and a temperature for depositing the second dielectric layer is lower than a temperature for depositing the first dielectric layer.

2. The preparation method according to claim 1, characterized in that The time length for removing the second dielectric layer by using the chemical solution containing hydrofluoric acid is shorter than the time length for removing the first dielectric layer by using the chemical solution containing hydrofluoric acid.

3. The preparation method according to claim 1, characterized in that: Also includes: A third dielectric layer is formed between the silicon substrate and the second dielectric layer, wherein the first dielectric layer and the third dielectric layer include silicon nitride, the second dielectric layer includes silicon oxynitride, the temperature for depositing the first dielectric layer and the third dielectric layer is 400° C. to 550° C., and the temperature for depositing the second dielectric layer is 160° C. to 220° C.

4. The preparation method according to claim 3, characterized in that: The thickness of the third dielectric layer is 5nm~15nm, and the refractive index is 2.2~2.

3. The thickness of the first dielectric layer is 10nm~30nm, and the refractive index is 1.9~2.

1. The thickness of the second dielectric layer is 30nm~60nm, and the refractive index is 1.6~1.

8.

5. The preparation method according to claim 1, characterized in that: The P region includes stacked intrinsic amorphous silicon and doped amorphous silicon, and the N region includes stacked tunnel oxide layers and doped polysilicon. Or the P region includes stacked tunnel oxide layers and doped polysilicon, and the N region includes stacked intrinsic amorphous silicon and doped amorphous silicon.

6. The preparation method according to claim 1, characterized in that: Before depositing the first dielectric layer, the silicon substrate is subjected to texturing and polishing to form a front surface with a pyramid structure and a back surface with a polished surface.

7. The preparation method according to claim 1, characterized in that: The silicon substrate is double-sided polished to first form the N region and then the P region. After forming the N region and before forming the P region, the front side is texturized to form a front side with a pyramid structure, wherein the N region includes stacked tunneling oxide layers and doped polysilicon.

8. A solar cell, characterized in that: include, a silicon substrate having opposing front and back sides; A first dielectric layer, located on the front side; P regions and N regions are alternately distributed on the back side, and the surface of the first dielectric layer facing away from the silicon substrate has depressions and / or micropores; as well as The second dielectric layer is located on a surface of the first dielectric layer facing away from the silicon substrate.

9. The solar cell according to claim 8, characterized in that The second dielectric layer fills the recess and / or the microhole.

10. The solar cell according to claim 8, characterized in that The time length for removing the second dielectric layer by using the chemical solution containing hydrofluoric acid is shorter than the time length for removing the first dielectric layer by using the chemical solution containing hydrofluoric acid.

11. The solar cell according to claim 8, wherein: It also includes a third dielectric layer, which is located between the silicon substrate and the first dielectric layer. The first dielectric layer and the third dielectric layer include silicon nitride, and the second dielectric layer includes silicon oxynitride. The temperature for depositing the first dielectric layer and the third dielectric layer is 400°C to 550°C, and the temperature for depositing the second dielectric layer is 160°C to 220°C.

12. The solar cell according to claim 11, wherein: The thickness of the third dielectric layer is 5nm~15nm, and the refractive index is 2.2~2.

3. The thickness of the first dielectric layer is 10nm~30nm, and the refractive index is 1.9~2.

1. The thickness of the second dielectric layer is 30nm~60nm, and the refractive index is 1.6~1.

8.

13. The solar cell according to claim 8, wherein: The P region includes stacked intrinsic amorphous silicon and doped amorphous silicon, and the N region includes stacked tunnel oxide layers and doped polysilicon. Or the P region includes stacked tunnel oxide layers and doped polysilicon, and the N region includes stacked intrinsic amorphous silicon and doped amorphous silicon.

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