Transmitter drive circuit

Abstract

The present application relates to the technical field of electronic circuits, and discloses a transmitter driving circuit, including: a main driving array circuit, including: a first front tap driving unit circuit group, a first main tap driving unit circuit group, and a first rear tap driving unit circuit group; an output impedance calibration array circuit, including: a second front tap, a second main tap, and a second rear tap driving unit circuit group respectively connected to the first front tap, the main tap, and the rear tap driving unit circuit group; an output impedance calibration control circuit, for sending digital control signals to the second front tap, the second main tap, and the second rear tap driving unit circuit group respectively; the first and second front tap, main tap, and rear tap driving unit circuit groups respectively include a plurality of driving unit circuits, and the number ratio of the driving unit circuits included in the first and second front tap, main tap, and rear tap driving unit circuit groups is k. The present application can effectively improve the linearity and signal-to-noise ratio of the signal.

Description

Technical Field

[0001] The present application relates to the field of electronic circuit technology, and in particular to transmitter drive circuit design. Background Art

[0002] Due to the low-pass filtering characteristics of the transmission line, different frequency components will suffer different degrees of attenuation during the transmission of high-speed data signals. This attenuation occurs during the transmission process from the serial transmitter (TX) to the receiver (RX), resulting in severe inter-symbol interference (ISI) in the signal received by the receiver, which directly affects the receiver's ability to judge the current bit data. In order to reduce the impact of this low-pass transmission characteristic, the receiver usually adopts a variety of equalization methods, including continuous time linear equalization (CTLE), decision feedback equalization (DFE) and digital signal processing (DSP). At the same time, in order to reduce the pressure of the receiver's equalization processing, the serial transmitter usually performs feedforward equalization (FFE) on the transmitted signal, such as Figure 1 shown.

[0003] However, although the above measures can alleviate inter-symbol interference and transmission loss to a certain extent, these solutions still face the problem of insufficient signal linearity and signal-to-noise ratio (SNDR) in high-speed data transmission. Insufficient linearity will cause distortion of the signal waveform and increase the bit error rate, while low signal-to-noise ratio will reduce the receiver's ability to detect the signal, further affecting the accuracy and reliability of data transmission. Therefore, although the prior art has taken a variety of measures to improve the quality of signal transmission, improving the linearity and signal-to-noise ratio of the signal in high-speed serial communication is still a technical problem that needs to be solved urgently. Summary of the invention

[0004] The purpose of the present application is to provide a transmitter driving circuit to solve the problems raised in the above background technology.

[0005] The present application discloses a transmitter driving circuit, comprising:

[0006] A main driving array circuit, the main driving array circuit comprising a first front tap driving unit circuit group, a first main tap driving unit circuit group and a first rear tap driving unit circuit group, wherein each group comprises a plurality of driving unit circuits;

[0007] An output impedance calibration array circuit, the output impedance calibration array circuit comprising a second front tap driving unit circuit group, a second main tap driving unit circuit group and a second rear tap driving unit circuit group, wherein each group is connected to a corresponding group in the main driving array circuit;

[0008] An output impedance calibration control circuit, used for sending digital control signals to the second front tap, the second main tap and the second rear tap driving unit circuit groups respectively;

[0009] Among them, the number of driving unit circuits contained in the second front tap, the second main tap, and the second rear tap driving unit circuit groups is k times the number of corresponding driving unit circuits in the first front tap, the first main tap, and the first rear tap driving unit circuit groups, respectively, and k is a constant less than 1. The digital control signal is used to adjust the value of k to accurately adjust the output impedance of the transmitter.

[0010] In a preferred example, the output impedance calibration control circuit includes:

[0011] A voltage detection unit, used to detect the voltage in the series or parallel circuit formed by the main drive array circuit and the reference resistor, the unit captures the voltage value from the voltage division of the main drive array and the reference resistor;

[0012] A voltage comparison unit, used for comparing the output voltage Vout detected by the voltage detection unit with the reference voltage Vref, and generating a comparison result;

[0013] The control signal generating unit is used to generate a digital control signal according to the comparison result of the voltage comparing unit, so as to adjust the output characteristics of the circuit according to the comparison between the output voltage Vout and the reference voltage Vref to achieve the expected output impedance calibration.

[0014] In a preferred example, each driving unit circuit of the first front-tap driving unit circuit group in the main driving array circuit is connected to the corresponding second front-tap driving unit circuit in the output impedance calibration array circuit in a one-to-one correspondence;

[0015] Each driving unit circuit of the first main tap driving unit circuit group in the main driving array circuit is connected to the corresponding second main tap driving unit circuit in the output impedance calibration array circuit in a one-to-one correspondence;

[0016] Each driving unit circuit of the first rear-tap driving unit circuit group in the main driving array circuit is connected to the corresponding second rear-tap driving unit circuit in the output impedance calibration array circuit in a one-to-one correspondence.

[0017] In a preferred example, the first front tap, main tap and rear tap driving unit circuit group in the main driving array circuit are respectively connected in parallel with the second front tap, main tap and rear tap driving unit circuit group in the output impedance calibration array circuit;

[0018] The first front tap driving unit circuit group is connected in parallel with the corresponding second front tap driving unit circuit group to drive the front tap data signal;

[0019] The first main tap driving unit circuit group is connected in parallel with the corresponding second main tap driving unit circuit group to drive the main tap data signal;

[0020] The first rear-tap driving unit circuit group is connected in parallel with the corresponding second rear-tap driving unit circuit group to drive the rear-tap data signal.

[0021] In a preferred example, the digital control signal is in the form of multi-bit binary code, and the high and low level combinations of each binary bit represent different control states, which are used to control the conduction status of the second front tap, second main tap and second rear tap drive unit circuit group in the output impedance calibration array circuit.

[0022] In a preferred example, the main driving array circuit and the output impedance calibration array circuit are connected in parallel, the output impedance calibration array circuit is used to calibrate the output impedance of the transmitter, and the main driving array circuit and the output impedance calibration array circuit are used together to drive the output signal of the transmitter.

[0023] In a preferred example, the digital control signal output by the output impedance calibration control circuit comprises a multi-bit binary code, the number of bits of the binary code is the same as the number of driving unit circuits in the output impedance calibration array circuit, and is used to perform independent switching control on each driving unit circuit.

[0024] In a preferred example, the output impedance calibration control circuit is connected to the output impedance calibration array circuit via a digital interface, and the digital interface is used to transmit a digital control signal.

[0025] Compared with the prior art, the embodiments of the present application have the following technical differences:

[0026] First, an independent output impedance calibration array is used: compared with the traditional solution, the output impedance calibration array circuit in the invention is separated from the main driving array circuit, ensuring that the calibration circuit will not affect the working state of the driving unit circuit.

[0027] Furthermore, a main drive array circuit is used: including multiple pre-tap, main tap and post-tap drive unit circuits. These circuits are configured in parallel to provide flexible equalization processing.

[0028] Furthermore, an innovative design of an output impedance calibration control circuit is adopted: the circuit generates a digital control signal according to a specific voltage detection result, which is used to control the output impedance calibration array circuit to achieve accurate impedance calibration.

[0029] The transmitter driving circuit according to the present application has the following technical effects:

[0030] First, the linearity of signal transmission is improved: through independent impedance calibration, the output linearity of the transmitter is maintained, solving the linearity problem caused by the change in the resistance ratio of MOS tubes and poly resistors in traditional methods.

[0031] Furthermore, the signal-to-noise ratio (SNDR) and spurious-free dynamic range (SFDR) of the signal are improved: simulation results show that the signal-to-noise ratio of the output signal is improved from 31.99dB to 34.76dB, an improvement of 2.7dB; the spurious-free dynamic range of the output signal is improved from 31.74dB to 41.53dB, an improvement of 6.79dB, showing better performance than traditional methods.

[0032] Furthermore, interference of analog control signals is prevented: the switches of the output impedance calibration array are controlled by digital control words, thereby avoiding interference that may be introduced by analog control signals.

[0033] The present application realizes output impedance calibration while ensuring transmitter linearity through precise control of digital control signals, and has obvious technical advantages and effects.

[0034] A large number of technical features are recorded in the specification of this application, which are distributed in various technical solutions. If all possible combinations of technical features of this application (i.e., technical solutions) are to be listed, the specification will be too long. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of this application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions are all deemed to have been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed, and features C and D are equivalent technical means that play the same role. Technically, only one can be used, and it is impossible to use them at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be deemed to have been recorded because it is technically infeasible, and the solution of A+B+C+E should be deemed to have been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a schematic diagram of a transmitter driving circuit in the prior art;

[0036] Figure 2 is a schematic structural diagram of a transmitter driving circuit according to a first embodiment of the present application;

[0037] Figure 3-Figure 5 is a schematic circuit diagram of a transmitter driving unit of a transmitter driving circuit according to a first embodiment of the present application;

[0038] Figure 6 is a schematic diagram of transmitter output resistance calibration of a transmitter driving circuit according to the first embodiment of the present application;

[0039] Figure 7 This is the DFT diagram of the output signal of the traditional calibration method;

[0040] Figure 8 FIG. 1 is a schematic diagram of a DFT of an output signal of a transmitter driving circuit according to the first embodiment of the present application. DETAILED DESCRIPTION

[0041] In the following description, many technical details are provided to help readers better understand the present application. However, those skilled in the art can understand that the technical solution claimed in the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0042] Description of some concepts:

[0043] Pre-tap data: refers to the original serial data signal that has not passed through the delay unit.

[0044] Main data: refers to the serial data signal that passes through a first-stage delay unit.

[0045] Post-tap data: refers to the serial data signal that passes through two stages of delay units.

[0046] Feedforward equalization (FFE): By introducing different degrees of advance into the signal, the signal is compensated to improve the integrity of the signal during transmission.

[0047] Output Impedance: The equivalent impedance of the transmitter to the output terminal. Matching the impedance of the transmitter and the transmission line can maximize the signal transmission efficiency.

[0048] Inter-symbol interference (ISI): Interference between adjacent symbols caused by transmission. It will cause serious attenuation of high-frequency signals and reduce transmission quality.

[0049] Signal-to-noise ratio (SNR): The ratio of signal power to noise power, an indicator of signal quality. The larger the value, the better the signal quality.

[0050] Spurious Free Dynamic Range (SFDR): The dynamic range between the maximum signal and the maximum spurious. Indicates the linearity and purity of the signal.

[0051] The following is a brief description of some of the innovative features of this application:

[0052] After long-term research and analysis, the inventor of the present application found that the traditional output impedance calibration will change the proportional relationship between the on-resistance and the calibration resistance of the MOS tube, thereby causing the linearity of the transmitter to deteriorate. Specifically, the goal of the traditional output impedance calibration is to control the sum of the resistance values ​​of the MOS tube on-resistance (Ron_mosp / Ron_mosn) and the polysilicon resistor (R_poly) to remain constant to meet the requirements of the transmitter output impedance. However, after such calibration, the ratio of the MOS tube on-resistance to the polysilicon resistor (Ron_mosp / R_poly) or (Ron_mosn / R_poly) will change. Due to the process deviation of the CMOS chip, this change in ratio will cause the linearity of the transmitter to deteriorate, which will have an adverse effect on the signal quality. The technical solution of the present application is to solve the technical problem of the deterioration of the transmitter linearity caused by the traditional output impedance calibration method. Through a new circuit structure and control method, the transmitter linearity is guaranteed to remain unchanged or improved while achieving output impedance calibration. Specifically, first, the present application adopts an independent output impedance calibration array: this design feature separates the output impedance calibration array from the main drive array, ensuring that the calibration process does not interfere with the normal operation of the main drive circuit. Furthermore, the present application optimizes the main drive array circuit: the circuit includes multiple front taps, main taps, and rear taps of the drive unit, which work in parallel to provide flexible balancing processing capabilities for the transmission process. Furthermore, the present application proposes an output impedance calibration control circuit: this part of the circuit uses a digital control signal to adjust the output impedance calibration array based on the voltage detection result to achieve precise control.

[0053] The technical problems solved by the present application include: first, improving the linearity of signal transmission: the traditional serial transmitter driving circuit often causes the linearity to decrease due to the change of the resistance ratio of the MOS tube and the poly resistor. The independent output impedance calibration of the present invention effectively solves this problem and maintains the linearity of the output signal. Further, improve the signal-to-noise ratio (SNDR) and spurious-free dynamic range (SFDR) of the signal: through optimized equalization processing and precise impedance calibration, this scheme significantly improves the signal-to-noise ratio and spurious-free dynamic range of the output signal, thereby improving the transmission quality. Further, reduce the interference of analog control signals: the output impedance calibration is controlled by a digital control method, which reduces the interference problem that may be caused by the analog control signal. While completing the output impedance calibration, since the taps of the first and second driving units maintain the same proportional relationship, each step of the FFE remains unchanged and can still meet the minimum equalization step required by the protocol. In general, the present application provides an optimized serial transmitter driving circuit design, which significantly improves the performance of high-speed data transmission, especially in terms of linearity and signal-to-noise ratio, through innovative impedance calibration and equalization processing technology.

[0054] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0055] The first embodiment of the present application relates to a transmitter driving circuit, the structure of which is as follows: Figures 2 to 6 As shown, the transmitter driving circuit of this embodiment includes: a main driving array circuit, an output impedance calibration array circuit and an output impedance calibration control circuit. In this solution, the output impedance calibration array and the main driving array circuit are separated, and the calibration circuit will not affect the working state of the driving unit circuit.

[0056] In general, the main driving array circuit includes a first front tap driving unit circuit group, a first main tap driving unit circuit group and a first rear tap driving unit circuit group, wherein each group includes a plurality of driving unit circuits.

[0057] Furthermore, the output impedance calibration array circuit includes a second front tap driving unit circuit group, a second main tap driving unit circuit group and a second rear tap driving unit circuit group, wherein each group is connected to a corresponding group in the main driving array circuit.

[0058] Furthermore, the output impedance calibration control circuit is used to send digital control signals to the second front tap, the second main tap and the second rear tap drive unit circuit groups respectively, and the output impedance calibration control circuit includes: a voltage detection unit, used to detect the voltage in the series or parallel circuit formed by the main drive array circuit and the reference resistor, and the unit captures the voltage value from the main drive array and the reference resistor voltage division; a voltage comparison unit, used to compare the output voltage Vout detected by the voltage detection unit with the reference voltage Vref and generate a comparison result; a control signal generation unit, used to generate a digital control signal according to the comparison result of the voltage comparison unit, so as to adjust the output characteristics of the circuit according to the comparison between the output voltage Vout and the reference voltage Vref, so as to achieve the expected output impedance calibration.

[0059] Further, the ratio of the number of driving unit circuits included in the first and second front tap, main tap, and rear tap driving unit circuit groups is k, k is a constant less than 1, and the digital control signal is used to adjust the value of k to adjust the output impedance of the transmitter. In other words, the number of driving unit circuits included in the second front tap, second main tap, and second rear tap driving unit circuit groups is k times the number of corresponding driving unit circuits in the first front tap, first main tap, and first rear tap driving unit circuit groups.

[0060] More specifically, in the transmitter driving circuit of the present application, there are two groups of key circuit components: the first group and the second group. The two groups include front tap, main tap, and rear tap driving unit circuit groups, respectively. Each group contains multiple driving unit circuits, but the number of driving unit circuits in the two groups is different. Here, "k" is a constant used to describe the ratio of the number between the two groups. Specifically, "k" is a value less than 1, which represents the ratio of the number of driving unit circuits in the second group (second front tap, second main tap, second rear tap driving unit circuit group) to the number in the first group (first front tap, first main tap, first rear tap driving unit circuit group). For example, if k is 0.5, this means that the number of circuits in each driving unit circuit group in the second group is half of the corresponding circuit group in the first group. The role of the digital control signal is to adjust the value of this ratio k. By changing the value of k, the output impedance of the transmitter can be adjusted. k defines the proportional relationship between the number of circuits in the first group and the second group of driving unit circuit groups. By adjusting the value of k, the output impedance of the transmitter can be finely controlled to optimize its performance.

[0061] Optionally, each driving unit circuit of the first front tap driving unit circuit group in the main driving array circuit is connected one-to-one with the corresponding second front tap driving unit circuit in the output impedance calibration array circuit; each driving unit circuit of the first main tap driving unit circuit group in the main driving array circuit is connected one-to-one with the corresponding second main tap driving unit circuit in the output impedance calibration array circuit; each driving unit circuit of the first rear tap driving unit circuit group in the main driving array circuit is connected one-to-one with the corresponding second rear tap driving unit circuit in the output impedance calibration array circuit.

[0062] Optionally, the first front tap, main tap and rear tap driving unit circuit groups in the main driving array circuit are respectively connected in parallel with the second front tap, main tap and rear tap driving unit circuit groups in the output impedance calibration array circuit; the first front tap driving unit circuit group is connected in parallel with the corresponding second front tap driving unit circuit group to drive the front tap data signal; the first main tap driving unit circuit group is connected in parallel with the corresponding second main tap driving unit circuit group to drive the main tap data signal; the first rear tap driving unit circuit group is connected in parallel with the corresponding second rear tap driving unit circuit group to drive the rear tap data signal.

[0063] Optionally, the digital control signal is in the form of multi-bit binary code, and the high and low level combinations of each binary bit represent different control states, which are used to control the conduction status of the second front tap, second main tap and second rear tap drive unit circuit group in the output impedance calibration array circuit.

[0064] Optionally, the digital control signal output by the output impedance calibration control circuit comprises a multi-bit binary code, the number of bits of the binary code is the same as the number of driving unit circuits in the output impedance calibration array circuit, and is used to perform independent switching control on each driving unit circuit.

[0065] Optionally, the output impedance calibration control circuit is connected to the output impedance calibration array circuit via a digital interface, and the digital interface is used to transmit a digital control signal.

[0066] The structure of the transmitter driving circuit of this embodiment is described in more detail below.

[0067] Main drive array circuit

[0068] The main driving array circuit includes m pre-data, n main data and p post-data driving unit circuits.

[0069] Among them, pre data refers to the pre-tap data, which refers to the serial data signal that has not passed through the delay unit. main data refers to the main tap data, which refers to the serial data signal that has passed through the first-stage delay unit. post data refers to the post-tap data, which refers to the serial data signal that has passed through the two-stage delay unit.

[0070] The Pre / main / post data drive circuit constitutes a feed-forward equalization (FFE) circuit, which achieves signal equalization by attenuating low-frequency signals and amplifying high-frequency signals.

[0071] Specifically, the main driving array circuit includes m parallel pre-tap driving unit circuits (pre data), n parallel main tap driving unit circuits (main data) and p parallel post-tap driving unit circuits (post data).

[0072] The above-mentioned m parallel front tap driving unit circuits, n parallel main tap driving unit circuits and p parallel rear tap driving unit circuits constitute the first front tap driving unit circuit group, the first main tap driving unit circuit group and the first rear tap driving unit circuit group respectively.

[0073] Output Impedance Calibration Array Circuit

[0074] In this embodiment, an output impedance calibration array circuit is creatively added. Specifically, the output impedance calibration array circuit includes m*k parts of pre data, n*k parts of main data and p*k parts of post data driving unit circuits.

[0075] In other words, the output impedance calibration array circuit includes m*k parallel pre-tap driving unit circuits (predata), n*k parallel main tap driving unit circuits (main data) and p*k parallel post-tap driving unit circuits (post data).

[0076] The above-mentioned m*k parallel front tap driving unit circuits, n*k parallel main tap driving unit circuits and p*k parallel rear equalizing driving unit circuits constitute the second front tap driving unit circuit group, the second main tap driving unit circuit group and the second rear tap driving unit circuit group respectively.

[0077] Furthermore, the first front tap driving unit circuit group is connected in parallel with the second front tap driving unit circuit group, the first main tap driving unit circuit group is connected in parallel with the second main tap driving unit circuit group, and the first rear tap driving unit circuit group is connected in parallel with the second rear tap driving unit circuit group.

[0078] Among them, the output impedance calibration parameter k is a constant less than 1. Assume that after the output impedance calibration, the output impedance calibration array circuit turns on m*r parts of pre data, n*r parts of main data and p*r parts of post data unit circuits (r<=k); when implementing equalization processing, the number of pre data, main data and post data driving units are m*(1+r), n*(1+r) and p*(1+r), respectively, and the ratio between them is still m:n:p. In this way, after the impedance calibration, the output signal amplitude can be kept constant; at the same time, each TAP (post / main / pre) of FFE simultaneously introduces the resistance calibration unit array, so that each step of FFE remains unchanged, thereby meeting the minimum equalization step required by the protocol.

[0079] That is, k is used to adjust the number of driver circuits turned on in the output impedance calibration array circuit. Specifically:

[0080] Impedance calibration: When the output impedance calibration array circuit performs impedance calibration, it selectively turns on a specific number of drive unit circuits based on a proportional factor r (r is less than or equal to k). The "m*r parts pre data", "n*r parts main data" and "p*r parts post data" unit circuits here refer to the number of additional drive units turned on according to the impedance calibration needs.

[0081] Equalization: When implementing equalization, the number of pre data, main data, and post data driver units will increase to m*(1+r), n*(1+r), and p*(1+r), respectively. The purpose of this is to keep the original m:n:p ratio unchanged.

[0082] Stability of output signal and equalization step size: This method can maintain constant output signal amplitude while completing impedance calibration and ensure that each TAP (post / main / pre) of the feedforward equalization (FFE) introduces a resistor calibration unit array so that each step size of the FFE remains unchanged. This is important because it meets the protocol requirement for the minimum equalization step size.

[0083] In general, this design allows the ratio and efficiency of the equalization process to be maintained by adjusting the number of units in the impedance calibration circuit while ensuring the stability of the output signal and compliance with the protocol requirements.

[0084] Output impedance calibration control circuit

[0085] This embodiment innovatively adds an output impedance calibration control circuit, which is used to detect the voltage division signal Vout after the transmitter driving unit and the off-chip reference resistor are connected in series, and compare it with the reference voltage Vref to generate a digital control signal. The digital control signal is respectively sent to the second front tap, main tap and rear tap driving unit groups in the output impedance calibration array circuit to control the switches of the driving units in these groups to achieve accurate output impedance adjustment.

[0086] Optionally, the output impedance calibration control circuit can be used as follows Figure 6 The circuit structure shown: The circuit includes a voltage detection circuit and a voltage comparison circuit. Among them, the voltage detection circuit obtains a voltage detection value Vout by connecting the transmitter drive unit and the off-chip reference resistor in series. The voltage comparison circuit compares Vout with the reference voltage Vref. If Vout is higher than Vref, a high-level control signal is output; if Vout is lower than Vref, a low-level control signal is output. The high and low-level control signals in the digital form enter the front tap, main tap and rear tap drive unit groups corresponding to the output impedance calibration array circuit to control whether the transistor switches in these drive unit groups are turned on to adjust the number of drive units, thereby achieving accurate output impedance calibration. In summary, the circuit dynamically adjusts the number of drive units turned on in the output impedance calibration array circuit by means of voltage detection and digital control to achieve the purpose of output impedance calibration and make the transmitter work in the best state. This design allows the detection, comparison, control and other modules to work together to ensure that the output impedance can be accurately adjusted and the transmitter drive circuit works efficiently and stably.

[0087] Transmitter unit drive circuit

[0088] The transmitter unit driver circuit is a key component designed to process and condition serial data signals for efficient transmission. It generally includes multiple tap driver units, such as front tap, main tap, and rear tap driver units, which can be configured in parallel or series. These driver units work together to improve the transmission efficiency and quality of the signal while reducing the attenuation and distortion of the signal during transmission.

[0089] Optionally, the transmitter unit driver circuit can be Figure 3 , Figure 4 , Figure 5 Or other ways to achieve, please point out, Figure 3 and Figure 4 Rswp represents the PMOS switch resistance, Ronp represents the PMOS on-resistance, Rmosp represents the PMOS tube resistance, Ronn represents the NMOS on-resistance, Rswn represents the NMOS switch resistance, Rmosn represents the NMOS tube resistance, Rpoly represents the polysilicon calibration resistance, Enb_drv represents the drive unit enable signal, and En_drv represents the drive unit conduction control signal. Figure 5 Vb_swp represents the PMOS bias voltage, and Vb_swn represents the NMOS bias voltage.

[0090] Off-chip reference resistor

[0091] The off-chip reference resistor is an independent component external to the transmitter drive circuit and is used to provide an accurate resistance reference value for the circuit.

[0092] Specifically, it is connected to the outside of the transmitter driving circuit, connected to the output impedance calibration control circuit, and provides a detection voltage for the latter's voltage detection circuit.

[0093] During voltage detection, one end of the reference resistor is grounded, and the other end outputs a stable detection voltage signal Vout to the voltage detection circuit.

[0094] The voltage detection circuit connects the transmitter drive unit and the reference resistor in series, and feeds the detected series voltage divider voltage value Vout into the voltage comparison circuit. The voltage comparison circuit compares and judges Vout and the reference voltage Vref to generate a digital control signal. The digital control signal then enters the output impedance calibration array circuit to adjust the output impedance of the transmitter.

[0095] In summary, the off-chip reference resistor provides a precise reference resistor for the transmitter drive circuit, and its reference function is to ensure the accuracy and stability of the output impedance calibration. It is a key component to achieve accurate output impedance calibration.

[0096] Working principle:

[0097] The transmitter drive circuit of the above embodiment performs signal conditioning and equalization processing through a series of drive unit circuits to meet the requirements of high-speed data transmission. The front tap, main tap and rear tap drive units are configured in parallel to work together to compensate for the loss and distortion of the signal during transmission. The output impedance calibration array circuit uses digital control signals to dynamically adjust the working state of each drive unit according to the real-time performance of the circuit and the external reference standard to accurately match the impedance of the transmission line. This adjustment ensures the integrity and stability of the signal during transmission, reduces inter-symbol crosstalk, and improves the accuracy and reliability of data transmission. In addition, the off-chip reference resistor provides a stable reference point for the system to calibrate the internal resistance value and ensure the consistency of the circuit output. The design of the entire circuit optimizes the linearity and signal-to-noise ratio of the signal, ensuring stable performance under different working conditions and loads.

[0098] The specific working process of the transmitter driving circuit of the above embodiment is as follows:

[0099] The pre-driving circuit performs different delay processing on the input data signal, obtains the front tap, main tap and rear tap data, and realizes the feedforward equalization of the signal.

[0100] The driving units in the output impedance calibration array circuit correspond to the driving units of the main driving array circuit in a certain ratio, wherein the switches of the driving units are controlled by the output impedance calibration control circuit.

[0101] The output impedance calibration control circuit detects the voltage of the series voltage division of the main driving circuit and the reference resistor voltage, and compares the detection result Vout with the reference voltage Vref to obtain the switch control signal of the driving unit.

[0102] The control signal turns the corresponding drive unit switch on or off to adjust the ratio of the number of drive units in the main drive array circuit and the output impedance calibration array circuit to achieve output impedance calibration.

[0103] After calibration, the stability of the output signal amplitude, the equalization step length, and the constant resistance ratio between the MOS resistor and the poly resistor can be guaranteed, thereby achieving the purpose of improving the linearity of the transmitter.

[0104] Technical effect:

[0105] The goal of the traditional output impedance calibration circuit is to control the sum of the resistance values ​​of Rmosp+Rpoly and Rmosn+Rpoly to remain constant to meet the transmitter output impedance index requirements. However, after calibration, the resistance ratio of the MOS tube on-resistance and the poly resistance (Rmosp / Rpoly or Rmosn / Rpoly) will change, which will cause the linearity of the transmitter to deteriorate under certain process conditions.

[0106] The transmitter driving circuit of the above embodiment of the present application obtains a digital control word through the calibration circuit to control whether the switch of the additional output impedance calibration array circuit is turned on. This can not only avoid the interference that may be caused by the analog control signal, but also ensure that the on-resistance of the MOS tube and the resistance ratio of the poly resistor remain constant, so that the output of the transmitter maintains a constant linearity.

[0107] More specifically, the output impedance calibration control circuit accurately controls the switch of the driving unit in the output impedance calibration array circuit according to the voltage detection result. This keeps the proportional relationship between the number of driving units in the main driving array circuit and the output impedance calibration array circuit constant. In this way, the proportional relationship between the various links of the feedforward equalization can be ensured to remain unchanged, and the final output signal amplitude can be stabilized by increasing the number of driving units provided by the calibration array circuit. While satisfying the output impedance calibration, the linearity of the transmitter is also improved.

[0108] Compared with the traditional analog control method, this embodiment realizes output impedance calibration while ensuring transmitter linearity through precise control of digital control signals, which has obvious technical advantages and effects.

[0109] Simulation results:

[0110] In order to verify the performance of the circuit of this application, a simulation comparison experiment was carried out. Figure 7 is the transmitter output signal spectrum when using the traditional calibration method. Figure 8 The spectrum of the transmitter output signal when using the new method of the present application. Figure 7 and Figure 8 It can be clearly seen that under the same test conditions:

[0111] The output signal signal-to-noise ratio (SNDR) of the technical solution of the present application is 34.76 dB, while that of the conventional method is 31.99 dB, which indicates that the new method significantly improves the signal-to-noise ratio by 2.77 dB.

[0112] The output signal spurious free dynamic range (SFDR) of the technical solution of the present application is 41.53dB, while that of the conventional method is 34.74dB, which indicates that the new method significantly improves the spurious free dynamic range by 6.79dB.

[0113] The relative amplitudes of the subharmonics of the output signal of the technical solution of the present application are significantly lower than the fundamental wave, indicating that the linearity is improved.

[0114] In summary, the simulation results verify that the transmitter driving circuit of the present application has significantly improved linearity and signal-to-noise ratio compared with the conventional technology, which further proves the effectiveness of the circuit structure and control strategy of the present invention.

[0115] In general, the embodiments of the present application have the following technical improvements:

[0116] First, an independent output impedance calibration array is used: compared with the traditional solution, the output impedance calibration array circuit in the invention is separated from the main driving array circuit, ensuring that the calibration circuit will not affect the working state of the driving unit circuit.

[0117] Furthermore, a main drive array circuit is used: including multiple pre-tap, main tap and post-tap drive unit circuits. These circuits are configured in parallel to provide flexible equalization processing.

[0118] Furthermore, an innovative design of an output impedance calibration control circuit is adopted: the circuit generates a digital control signal according to a specific voltage detection result, which is used to control the output impedance calibration array circuit to achieve accurate impedance calibration.

[0119] The transmitter driving circuit according to the present application has the following technical effects:

[0120] First, the linearity of signal transmission is improved: through independent impedance calibration, the output linearity of the transmitter is maintained, solving the linearity problem caused by the change in the resistance ratio of MOS tubes and poly resistors in traditional methods.

[0121] Furthermore, the signal-to-noise ratio (SNDR) and spurious-free dynamic range (SFDR) of the signal are improved: simulation results show that the signal-to-noise ratio of the output signal is improved from 31.99dB to 34.76dB, an improvement of 2.7dB; the spurious-free dynamic range of the output signal is improved from 31.74dB to 41.53dB, an improvement of 6.79dB, showing better performance than traditional methods.

[0122] Furthermore, interference of analog control signals is prevented: the switches of the output impedance calibration array are controlled by digital control words, thereby avoiding interference that may be introduced by analog control signals.

[0123] While completing the impedance calibration, since the taps of the first and second driving units maintain the same proportional relationship, each step length of the FFE remains unchanged and can still meet the minimum equalization step length required by the protocol.

[0124] It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements. In the application documents of this patent, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, which includes two situations: performing the action only according to the element, and performing the action according to the element and other elements. Expressions such as multiple, multiple, and multiple include 2, 2 times, 2 kinds, and more than 2, more than 2 times, and more than 2 kinds.

[0125] All documents mentioned in this application are considered to be included in the disclosure of this application as a whole, so that they can be used as the basis for modification when necessary. In addition, it should be understood that after reading the above disclosure of this application, those skilled in the art can make various changes or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A transmitter driving circuit, characterized in that: include: A main driving array circuit, the main driving array circuit comprising a first front tap driving unit circuit group, a first main tap driving unit circuit group and a first rear tap driving unit circuit group, wherein each group comprises a plurality of driving unit circuits; An output impedance calibration array circuit, the output impedance calibration array circuit comprising a second front tap driving unit circuit group, a second main tap driving unit circuit group and a second rear tap driving unit circuit group, wherein each group is connected to a corresponding group in the main driving array circuit; An output impedance calibration control circuit, used for sending digital control signals to the second front tap driving unit circuit group, the second main tap driving unit circuit group and the second rear tap driving unit circuit group respectively; The number of driving unit circuits included in the second front tap driving unit circuit group, the second main tap driving unit circuit group, and the second rear tap driving unit circuit group is k times the number of corresponding driving unit circuits in the first front tap driving unit circuit group, the first main tap driving unit circuit group, and the first rear tap driving unit circuit group, respectively, k is a constant less than 1, and the digital control signal is used to adjust the value of k to adjust the output impedance of the transmitter; Wherein, the output impedance calibration control circuit comprises: A voltage detection unit, used to detect the divided voltage after the main drive array circuit is connected in series with an off-chip reference resistor; A voltage comparison unit, used for comparing the output voltage Vout detected by the voltage detection unit with the reference voltage Vref, and generating a comparison result; a control signal generating unit, configured to generate a digital control signal according to a comparison result of the voltage comparing unit, so as to adjust the output characteristic of the circuit according to a comparison between the output voltage Vout and the reference voltage Vref, so as to achieve a desired output impedance calibration; and The digital control signal is in the form of multi-bit binary code, and the high and low level combinations of each binary bit represent different control states, which are used to control the conduction status of the second front tap drive unit circuit group, the second main tap drive unit circuit group and the second rear tap drive unit circuit group in the output impedance calibration array circuit.

2. The circuit according to claim 1, characterized in that Each driving unit circuit of the first front-tap driving unit circuit group in the main driving array circuit is connected to the corresponding second front-tap driving unit circuit in the output impedance calibration array circuit in a one-to-one correspondence; Each driving unit circuit of the first main tap driving unit circuit group in the main driving array circuit is connected to the corresponding second main tap driving unit circuit in the output impedance calibration array circuit in a one-to-one correspondence; Each driving unit circuit of the first rear-tap driving unit circuit group in the main driving array circuit is connected to the corresponding second rear-tap driving unit circuit in the output impedance calibration array circuit in a one-to-one correspondence.

3. The circuit according to claim 1, characterized in that The first front tap, main tap and rear tap driving unit circuit group in the main driving array circuit are respectively connected in parallel with the second front tap, main tap and rear tap driving unit circuit group in the output impedance calibration array circuit; The first front tap driving unit circuit group is connected in parallel with the corresponding second front tap driving unit circuit group to drive the front tap data signal; The first main tap driving unit circuit group is connected in parallel with the corresponding second main tap driving unit circuit group to drive the main tap data signal; The first rear-tap driving unit circuit group is connected in parallel with the corresponding second rear-tap driving unit circuit group to drive the rear-tap data signal.

4. The circuit according to claim 1, characterized in that The main driving array circuit and the output impedance calibration array circuit are connected in parallel. The main driving array circuit and the output impedance calibration array circuit are used together to drive the output signal of the transmitter. The output impedance calibration array circuit is also used to calibrate the output impedance of the transmitter.

5. The circuit according to claim 1, characterized in that The digital control signal output by the output impedance calibration control circuit includes a multi-bit binary code, the number of bits of the binary code is the same as the number of driving unit circuits in the output impedance calibration array circuit, and is used to perform independent switch control on each driving unit circuit.

6. The circuit according to claim 1, characterized in that The output impedance calibration control circuit is connected to the output impedance calibration array circuit via a digital interface, and the digital interface is used to transmit a digital control signal.

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