Method, apparatus, device, system and readable storage medium for data transmission

Abstract

Embodiments of the present application disclose a method, apparatus, device, system, and readable storage medium for data transmission. The data transmission method includes: a first module obtains first data, where the first data is data encoded using a first FEC code type and subjected to a first process, and the first process includes interleaving; the first module encodes the first data according to a second FEC code type to obtain a plurality of second codewords; the first module performs a second process on the plurality of second codewords to obtain second data; the first module transmits the second data. This method can enable the transmitted data to have a higher coding gain through concatenated coding, and can effectively correct the data with errors when transmitting in a channel prone to bit errors. Moreover, since the first data is data obtained through interleaving, it can eliminate the correlation of error bits within the codewords corrected by the second FEC code, improve the error correction performance, and further improve the quality of data transmission.

Description

[0001] This application is a divisional application. The application number of the original application is 202111022657.4, the original application date is September 1, 2021, and the entire content of the original application is incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technologies, and in particular, to a method, apparatus, device, system, and readable storage medium for data transmission. Background Art

[0003] With the improvement of data transmission rates, channel losses and noise limit the rate and distance of data transmission. Forward error correction (FEC), as a data coding method that can provide check bits for the transmitted data and improve the data transmission rate and distance in the channel, has been increasingly widely used. During data transmission, the sending end encodes the original data using a specific FEC code type, sends the encoded data to the receiving end, and the receiving end decodes the received data using the same FEC code type to obtain the original data. Summary of the Invention

[0004] This application provides a method, apparatus, device, system, and readable storage medium for data transmission, which is used to improve the quality of data transmission.

[0005] In a first aspect, a method for data transmission is provided. The method includes: a first module obtains first data, where the first data is data encoded using a first forward error correction (FEC) code type and subjected to a first process, and the first process includes interleaving; the first module encodes the first data according to a second FEC code type to obtain a plurality of second codewords; the first module performs a second process on the plurality of second codewords to obtain second data; the first module transmits the second data.

[0006] This method can enable the transmitted data to have a higher coding gain through concatenated coding, and can effectively correct the data with errors when transmitting in a channel prone to error codes. Moreover, since the first data is data obtained through interleaving, the correlation of error bits in the codewords corrected by the second FEC can be eliminated, improving the error correction performance and further improving the quality of data transmission.

[0007] In a possible implementation, the second process includes inserting at least one of a training sequence and a pilot symbol required for a coherent link. By inserting at least one of a training sequence and a pilot symbol required for a coherent link, the method can be applied to a coherent link.

[0008] In a possible implementation manner, at least one of the first processing and the second processing further includes inserting data for adjusting a frequency point. By inserting the data for adjusting the frequency point, the frequency point of the processed data can meet the requirements.

[0009] In a possible implementation manner, the first module obtains first data, including: the first module receives a plurality of first sub-data sent by a second module, where the plurality of first sub-data are data encoded by a first FEC code type and distributed through a physical medium attachment sublayer PMA; the first module aligns the plurality of first sub-data to obtain a plurality of first codewords; the first module performs an interleaving process on the plurality of first codewords to obtain the first data. By performing an interleaving process on the plurality of first codewords, the correlation of error bits within the codewords after subsequent encoding by a second FEC code type can be eliminated, thereby improving the error correction performance.

[0010] In a possible implementation manner, the first module obtains first data, including: the first module receives a plurality of first sub-data sent by a second module, where the plurality of first sub-data are data encoded by a first FEC code type and subjected to an interleaving process and distributed through a physical medium attachment sublayer PMA; the first module aligns the plurality of first sub-data to obtain a plurality of first codewords; the first module performs an interleaving process on the plurality of first codewords to obtain the first data. In the case where the first sub-data have been subjected to an interleaving process, subsequent interleaving of the plurality of first codewords can further eliminate the correlation of error bits within the codewords after subsequent encoding by a second FEC code type, thereby improving the error correction performance.

[0011] In a possible implementation manner, the first module aligns the plurality of first sub-data to obtain a plurality of first codewords, including: the first module aligns the plurality of first sub-data, deinterleaves the aligned data, and obtains a plurality of first codewords according to the result of the deinterleaving; or, the first module aligns the plurality of first sub-data and uses the aligned data as the plurality of first codewords. Using the aligned data as the plurality of first codewords directly without deinterleaving can improve the data transmission speed.

[0012] In a possible implementation manner, the first module obtains first data, including: the first module receives a plurality of first sub-data sent by a second module, where the plurality of first sub-data are data encoded by a first FEC code type and subjected to an interleaving process and distributed through a physical medium attachment sublayer PMA; the first module aligns the plurality of first sub-data to obtain the first data. Since the plurality of first sub-data are data encoded by a first FEC code type and subjected to an interleaving process and PMA distribution, aligning the plurality of first sub-data to obtain the first data can further save time delay and power consumption.

[0013] In a possible implementation, the first module is located on a first chip, and the second module is located on a second chip. Receiving a plurality of first sub-data sent by the second module includes: the first module receiving the plurality of first sub-data sent by the second module through a plurality of channels of an Attachment Unit Interface (AUI).

[0014] In a possible implementation, the first module is located on a first chip, and the first module obtains first data, including: the first module receiving a plurality of first sub-data sent by a second module through a channel of an Attachment Unit Interface (AUI), the second module being located on a second chip, the plurality of first sub-data being data encoded with a first Forward Error Correction (FEC) code type and distributed through a Physical Medium Attachment (PMA) sublayer, or the plurality of first sub-data being data encoded with a first FEC code type and subjected to interleaving processing and distributed through a PMA sublayer; the first module performing Alignment Mark (AM) locking on the plurality of first sub-data to obtain a plurality of first codewords; the first module performing interleaving processing on the plurality of first codewords to obtain the first data.

[0015] In a possible implementation, the plurality of first sub-data are data encoded with a first FEC code type and subjected to interleaving processing and distributed through a PMA sublayer. The first module performing AM locking on the plurality of first sub-data to obtain a plurality of first codewords includes: the first module performing AM locking on the plurality of first sub-data, deinterleaving the data after AM locking, and obtaining a plurality of first codewords according to the result of deinterleaving; or the first module performing AM locking on the plurality of first sub-data and using the data after AM locking as the plurality of first codewords.

[0016] In a possible implementation, the first module is located on a first chip, and the first module obtains first data, including: the first module receiving a plurality of first sub-data sent by a second module through a channel of an Attachment Unit Interface (AUI), the second module being located on a second chip, the plurality of first sub-data being data encoded with a first FEC code type and subjected to interleaving processing and distributed through a PMA sublayer; the first module performing AM locking on the plurality of first sub-data and using the data after AM locking as the first data.

[0017] In a possible implementation, the first module performs a second process on the plurality of second codewords to obtain second data, including: the first module performing interleaving processing on the plurality of second codewords, grouping the interleaving result according to symbols or at least one bit required for data modulation, and distributing the grouped data to corresponding data channels; obtaining second data based on the data in each data channel.

[0018] In a possible implementation, the first module performs a second process on the multiple second codewords to obtain second data, including: the first module groups the multiple second codewords according to symbols or at least one bit required for data modulation, and distributes the grouped data to corresponding data channels; and obtains second data based on the data in each data channel.

[0019] In a possible implementation, the obtaining second data based on the data in each data channel includes: inserting a training sequence and pilot symbols required for a coherent link into the data in each data channel to obtain processed data, and inserting data for adjusting the frequency point into the processed data to obtain second data.

[0020] In a possible implementation, the obtaining second data based on the data in each data channel includes: inserting data for adjusting the frequency point into the data in each data channel to obtain processed data, and inserting a training sequence and pilot symbols required for a coherent link into the processed data to obtain second data.

[0021] In a possible implementation, the interleaving process on the multiple first codewords includes: directly interleaving the multiple first codewords, and the number of interleaved codewords is the number of codewords participating in the interleaving; or, performing staggered interleaving on the multiple first codewords at a reference interval, and the number of interleaved codewords is the number of codewords participating in the interleaving, where the reference interval is the number of code blocks staggered between two codewords; or, performing convolutional interleaving on the multiple first codewords, and the number of interleaved codewords is the number of codewords participating in the interleaving.

[0022] In a possible implementation, the interleaving process on the multiple second codewords includes: interleaving the second codewords from the same encoder among the multiple second codewords; or, interleaving the multiple second codewords from multiple encoders; or, interleaving the second codewords from the same encoder among the multiple second codewords, and then interleaving the multiple data streams from multiple encoders obtained after interleaving.

[0023] In a possible implementation, the first module encodes the first data according to a second FEC code type to obtain multiple second codewords, including: the first module distributes the first data to obtain multiple second sub-data, and the first module encodes the multiple second sub-data according to the second FEC code type respectively to obtain multiple second codewords.

[0024] In a possible implementation, the first module distributes the first data to obtain multiple second sub-data, including: the first module distributes the first data through a physical coding sublayer PCS channel to obtain multiple second sub-data; or, the first module distributes the first data through a physical medium access sublayer PMA to obtain multiple second sub-data.

[0025] In a possible implementation manner, the first module transmits the second data, including: the first module distributes the second data to obtain a plurality of third sub-data, and sends the plurality of third sub-data through a plurality of logical channels.

[0026] In a second aspect, a method for data transmission is provided, the method comprising: a third module acquires second data, the second data is data obtained by encoding first data using a second forward error correction code FEC code type and performing a second processing, the first data is data encoded using a first FEC code type and subjected to a first processing, the first processing comprising an interleaving process; the third module decodes the second data according to the second FEC code type to obtain decoded data.

[0027] In a possible implementation manner, the third module acquires the second data, including: the third module receives a plurality of third sub-data, and restores the second data based on the plurality of third sub-data.

[0028] In a third aspect, a data transmission device is provided, the device is applied to a first module, and the device includes:

[0029] An acquiring unit, configured to acquire first data, wherein the first data is data encoded using a first forward error correction code (FEC) pattern and subjected to a first process, wherein the first process includes an interleaving process;

[0030] an encoding unit, configured to encode the first data according to a second FEC code type to obtain a plurality of second code words;

[0031] A processing unit, configured to perform a second process on the plurality of code words to obtain second data;

[0032] A transmission unit, configured to transmit the second data.

[0033] In a possible implementation manner, the second processing includes inserting at least one of a training sequence and a pilot symbol required by a coherent link.

[0034] In a possible implementation manner, at least one of the first processing and the second processing further includes inserting data for adjusting the frequency point.

[0035] In a possible implementation, the obtaining unit is configured to receive a plurality of first sub-data sent by a second module, where the plurality of first sub-data are data encoded using a first FEC code type and distributed through a physical medium attachment sublayer (PMA); align the plurality of first sub-data to obtain a plurality of first codewords; and perform interleaving processing on the plurality of first codewords to obtain the first data.

[0036] In a possible implementation, the obtaining unit is configured to receive a plurality of first sub-data sent by a second module, where the plurality of first sub-data are data encoded using a first FEC code type and distributed through interleaving processing and a physical medium attachment sublayer (PMA); align the plurality of first sub-data to obtain a plurality of first codewords; and perform interleaving processing on the plurality of first codewords to obtain the first data.

[0037] In a possible implementation, the obtaining unit is configured to align the plurality of first sub-data, de-interleave the aligned data, and obtain a plurality of first codewords according to the result of de-interleaving; or align the plurality of first sub-data and use the aligned data as the plurality of first codewords.

[0038] In a possible implementation, the obtaining unit is configured to receive a plurality of first sub-data sent by a second module, where the plurality of first sub-data are data encoded using a first FEC code type and distributed through interleaving processing and a physical medium attachment sublayer (PMA); align the plurality of first sub-data to obtain the first data.

[0039] In a possible implementation, the first module is located on a first chip, the second module is located on a second chip, and the obtaining unit is configured to receive the plurality of first sub-data sent by the second module through a plurality of channels of an attachment unit interface (AUI).

[0040] In a possible implementation, the first module is located on a first chip, the obtaining unit is configured to receive the plurality of first sub-data sent by the second module through a channel of an attachment unit interface (AUI), the second module is located on a second chip, the plurality of first sub-data are data encoded using a first FEC code type and distributed through a physical medium attachment sublayer (PMA), or the plurality of first sub-data are data encoded using a first FEC code type and distributed through interleaving processing and a physical medium attachment sublayer (PMA); perform alignment mark (AM) locking on the plurality of first sub-data to obtain a plurality of first codewords; and perform interleaving processing on the plurality of first codewords to obtain the first data.

[0041] In a possible implementation, the multiple first sub-data are data encoded using a first FEC code type, subjected to interleaving processing, and distributed by a physical medium attachment sublayer PMA. The obtaining unit is configured to perform AM locking on the multiple first sub-data, de-interleave the data after AM locking, and obtain multiple first codewords according to the result of de-interleaving; or perform AM locking on the multiple first sub-data, and use the data after AM locking as the multiple first codewords.

[0042] In a possible implementation, the first module is located on a first chip. The obtaining unit is configured to receive multiple first sub-data sent by the second module through a channel of an attachment unit interface AUI. The second module is located on a second chip. The multiple first sub-data are data encoded using a first FEC code type, subjected to interleaving processing, and distributed by a physical medium attachment sublayer PMA; perform alignment mark AM locking on the multiple first sub-data, and use the data after AM locking as the first data.

[0043] In a possible implementation, the processing unit is configured to perform interleaving processing on the multiple second codewords, group the interleaving result according to symbols or at least one bit required for data modulation, and distribute the grouped data to corresponding data channels; obtain second data based on the data in each data channel.

[0044] In a possible implementation, the processing unit is configured to group the multiple second codewords according to symbols or at least one bit required for data modulation, and distribute the grouped data to corresponding data channels; obtain second data based on the data in each data channel.

[0045] In a possible implementation, the processing unit is configured to insert a training sequence and pilot symbols required for a coherent link into the data in each data channel to obtain processed data, and insert data for adjusting the frequency point into the processed data to obtain second data.

[0046] In a possible implementation, the processing unit is configured to insert data for adjusting the frequency point into the data in each data channel to obtain processed data, and insert a training sequence and pilot symbols required for a coherent link into the processed data to obtain second data.

[0047] In a possible implementation manner, the obtaining unit is configured to directly interleave the plurality of first codewords, and the number of interleaved codewords is the number of codewords participating in interleaving; alternatively, staggeredly interleave the plurality of first codewords at a reference interval, and the number of interleaved codewords is the number of codewords participating in interleaving, where the reference interval is the number of code blocks staggered between two codewords; or perform convolutional interleaving on the plurality of first codewords, and the number of interleaved codewords is the number of codewords participating in interleaving.

[0048] In a possible implementation manner, the processing unit is configured to interleave the second codewords from the same encoder among the plurality of second codewords; or interleave the plurality of second codewords from multiple encoders; or interleave the second codewords from the same encoder among the plurality of second codewords, and re-interleave the plurality of data streams from multiple encoders obtained after interleaving.

[0049] In a possible implementation manner, the encoding unit is configured to distribute the first data to obtain a plurality of second sub-data, and respectively encode the plurality of second sub-data according to the second FEC code type to obtain a plurality of second codewords.

[0050] In a possible implementation manner, the encoding unit is configured to distribute the first data through a Physical Coding Sublayer (PCS) channel to obtain a plurality of second sub-data; or distribute the first data through a Physical Medium Attachment (PMA) sublayer to obtain a plurality of second sub-data.

[0051] In a possible implementation manner, the transmission unit is configured to distribute the second data to obtain a plurality of third sub-data, and send the plurality of third sub-data through multiple logical channels.

[0052] Fourthly, a data transmission device is provided. The device is applied to a third module, and the device includes:

[0053] An obtaining unit, configured to obtain second data, where the second data is data obtained by encoding the first data using a second Forward Error Correction (FEC) code type and performing a second process, the first data is data encoded using a first FEC code type and subjected to a first process, and the first process includes an interleaving process;

[0054] A decoding unit, configured to decode the second data according to the second FEC code type to obtain decoded data.

[0055] In a possible implementation manner, the obtaining unit is configured to receive a plurality of third sub-data and recover the second data based on the plurality of third sub-data.

[0056] In a fifth aspect, a data transmission device is provided. The device includes a processor coupled to a memory. At least one program instruction or code is stored in the memory and is loaded and executed by the processor to enable the device to implement the data transmission method according to any one of the first aspect or the second aspect.

[0057] In a sixth aspect, a data transmission system is provided. The system includes: a first data transmission device for performing the method according to any one of the first aspect or the first aspect; and a second data transmission device for performing the method according to any one of the second aspect or the second aspect.

[0058] In a seventh aspect, a computer-readable storage medium is provided. At least one program instruction or code is stored in the computer-readable storage medium, and when the program instruction or code is loaded and executed by a processor, it enables the computer to implement the data transmission method according to any one of the first aspect or the second aspect.

[0059] Another communication device is provided. The device includes a communication interface, a memory, and a processor. The memory and the processor communicate with each other through an internal connection path. The memory is used to store instructions, and the processor is used to execute the instructions stored in the memory to control the communication interface to receive data and control the communication interface to send data. When the processor executes the instructions stored in the memory, the processor executes the method according to any one of the first aspect or any possible implementation manner of the first aspect, or executes the method according to any one of the second aspect or any possible implementation manner of the second aspect.

[0060] As an exemplary embodiment, the processor is one or more, and the memory is one or more.

[0061] As an exemplary embodiment, the memory may be integrated with the processor, or the memory and the processor are separately arranged.

[0062] In a specific implementation process, the memory may be a non-transitory memory, such as a read-only memory (ROM). It may be integrated with the processor on the same chip or separately arranged on different chips. The embodiments of the present application do not limit the type of the memory and the setting manner of the memory and the processor.

[0063] A computer program (product) is provided. The computer program (product) includes computer program code, and when the computer program code is run by a computer, it enables the computer to execute the methods in the above aspects.

[0064] A chip is provided, which includes a processor for calling and running instructions stored in a memory, such that a device installed with the chip executes the methods in the above aspects.

[0065] Another chip is provided, which includes: an input interface, an output interface, a processor, and a memory. The input interface, the output interface, the processor, and the memory are connected through an internal connection path. The processor is configured to execute code in the memory, and when the code is executed, the processor is configured to execute the methods in the above aspects.

[0066] A device is provided, which includes the chip in any of the above solutions.

[0067] A device is provided, which includes the first chip in any of the above solutions, and / or, the third chip in any of the above solutions. Description of the Drawings

[0068] Figure 1 It is a schematic diagram of an implementation scenario of a data transmission method provided by an embodiment of the present application;

[0069] Figure 2 It is a flowchart of a data transmission method provided by an embodiment of the present application;

[0070] Figure 3 It is a schematic diagram of an interleaving process provided by an embodiment of the present application;

[0071] Figure 4 It is another schematic diagram of an interleaving process provided by an embodiment of the present application;

[0072] Figure 5 It is a schematic diagram of data transmission provided by an embodiment of the present application;

[0073] Figure 6 It is another schematic diagram of an interleaving process provided by an embodiment of the present application;

[0074] Figure 7 It is another schematic diagram of an interleaving process provided by an embodiment of the present application;

[0075] Figure 8 It is another schematic diagram of an interleaving process provided by an embodiment of the present application;

[0076] Figure 9 It is a schematic diagram of the structure of a data processing system provided by an embodiment of the present application;

[0077] Figure 10 It is another schematic diagram of an interleaving process provided by an embodiment of the present application;

[0078] Figure 11It is another schematic diagram of the interleaving process provided by the embodiments of the present application;

[0079] Figure 12 It is a schematic diagram of a data processing process provided by the embodiments of the present application;

[0080] Figure 13 It is a schematic diagram of the implementation environment of an application scenario provided by the embodiments of the present application;

[0081] Figure 14 It is a schematic diagram of the implementation environment of another application scenario provided by the embodiments of the present application;

[0082] Figure 15 It is a schematic diagram of the implementation environment of another application scenario provided by the embodiments of the present application;

[0083] Figure 16 It is a schematic diagram of the implementation environment of another application scenario provided by the embodiments of the present application;

[0084] Figure 17 It is a schematic diagram of the implementation environment of another application scenario provided by the embodiments of the present application;

[0085] Figure 18 It is a schematic diagram of the implementation environment of another application scenario provided by the embodiments of the present application;

[0086] Figure 19 It is a schematic diagram of the implementation environment of another application scenario provided by the embodiments of the present application;

[0087] Figure 20 It is a flowchart of another method for data transmission provided by the embodiments of the present application;

[0088] Figure 21 It is a schematic diagram of the structure of a data transmission device provided by the embodiments of the present application;

[0089] Figure 22 It is a schematic diagram of the structure of another data transmission device provided by the embodiments of the present application;

[0090] Figure 23 It is a schematic diagram of the structure of another data transmission device provided by the embodiments of the present application. Detailed implementation manners

[0091] The terms used in the implementation part of the present application are only used to explain the embodiments of the present application and are not intended to limit the present application. The embodiments of the present invention will be described below with reference to the accompanying drawings.

[0092] In the field of communication technology, with the increase in data transmission rate, the loss and noise of the channel limit the data transmission rate and distance. The emergence of FEC provides error correction protection for the data in transmission, reduces the bit error rate in the data transmission process, and thus can improve the data transmission rate and transmission distance in the channel. However, with the continuous increase in data transmission rate and the continuous increase in transmission distance, the requirements for FEC are also getting higher and higher. At the same time, stronger FEC often requires more parity bits, resulting in a higher bandwidth required for the data. Therefore, for scenarios with increased link rate and more challenging channels, FEC with higher coding gain may be required. For example, for the ethernet interface of 800 gigabit ethernet (GE) / 1.6 terabit ethernet (TE), or the 200G four-level pulse amplitude modulation (PAM4) optical link, etc. Higher rate transmissions often face more stringent channel and bit error rate requirements, and stronger FEC can keep the bit error rate after error correction at a good level after the bit error rate before error correction increases.

[0093] When the transmission distance is shorter, the proportion of the overall transmission delay occupied by the path delay is lower, and the proportion of the delay brought by FEC is correspondingly higher, becoming a constraint factor for the system delay. For example, if the fiber delay is about 50 μs at a distance of 10 km, the 1 μs FEC delay is only 2% of the path delay. However, if the distance is 1 km and the fiber delay is 5 μs, the 1 μs FEC delay will be 20% of the path delay. As the distance is further shortened, this proportion will continue to increase, which is obviously unacceptable.

[0094] In response to this, the embodiment of the present application provides a data transmission method. Based on the first module for transmitting data, the first data encoded with the first FEC code type is re-encoded through the second FEC code type to obtain the second data with concatenated coding, so that the second data has a higher coding gain. When transmitted in a channel prone to bit errors, it can effectively correct the bit error data, thereby improving the quality of data transmission. Secondly, since the second data is directly encoded based on the first data, the implementation process of this method is relatively simple, improving the efficiency of data transmission. Furthermore, since the first data is data obtained through interleaving processing, it can eliminate the correlation of error bits in the codeword after the second FEC code corrects errors, improve the error correction performance, and further improve the quality of data transmission.

[0095] The method of the embodiments of the present application is applicable to the current Ethernet interface or other scenarios that require data transmission. For example, coherent optics often has long burst errors and a high bit error rate (BER). The method provided by the embodiments of the present application can be used for low-latency concatenated FEC in coherent links. Take Figure 1 the following implementation scenario as an example. This implementation scenario includes multiple modules, and information can be exchanged between the modules to achieve data transmission. As Figure 1 shown, data can be transmitted between the first module 101 and the second module 102, and between the first module 101 and the third module 103. It should be noted that as Figure 1 shown, the implementation scenario can include N modules, where N is a positive integer greater than or equal to 2. Figure 1 Here, only the case where the number of modules is 3 is taken as an example for illustration. In addition, each module can be located within the same chip or in different chips.

[0096] Combined with Figure 1 the implementation scenario shown, the data transmission method provided by the embodiments of the present application is as Figure 2 shown, including but not limited to steps 201 to 204.

[0097] 201. The first module obtains first data, where the first data is data encoded using a first FEC code type and processed through a first process, and the first process includes interleaving processing.

[0098] The method provided by the embodiments of the present application adopts a concatenated coding method. The first data obtained by the first module and encoded using the first FEC code type is re-encoded through a second FEC code type to obtain second concatenated-coded data. Since interleaving processing can eliminate the correlation of error bits in the codewords after subsequent encoding using the second FEC code type, thereby improving the error correction performance, the first data is data encoded using the first FEC code type and processed through the first process, and the first process includes interleaving processing.

[0099] The embodiments of the present application do not limit the manner in which the first module obtains the first data. In a possible implementation, the first module and the second module can transmit data. The first module receives multiple first sub-data sent by the second module and obtains the first data based on the first sub-data. Among them, the first sub-data is data encoded using the first FEC code type. The embodiments of the present application do not limit the first FEC code type. Exemplarily, the first FEC code type is any one of Reed-Solomon (RS) code, Bose-Chaudhuri-Hocquenghem (BCH) code, Fire code, Turbo code, Turbo product code (TPC), Staircase code, and Low-density parity-check (LDPC) code.

[0100] In addition to being encoded using the first FEC code type, the first sub-data also undergoes other processing. The embodiments of the present application do not limit the processing manner of the other processing of the first sub-data other than the first FEC code type encoding. For example, the first sub-data is data encoded using the first FEC code type and distributed through the physical medium attachment sublayer (PMA), or the first sub-data is data encoded using the first FEC code type and undergoes interleaving processing and PMA distribution. According to different situations of the first sub-data, the manner in which the first module obtains the first data includes, but is not limited to, the following four types.

[0101] Manner 1 of obtaining the first data: The first module obtains the first data, including: The first module receives multiple first sub-data sent by the second module, and the multiple first sub-data are data encoded using the first FEC code type and distributed through PMA; the first module aligns the multiple first sub-data to obtain multiple first codewords; the first module performs interleaving processing on the multiple first codewords to obtain the first data.

[0102] In Manner 1 of obtaining the first data, the first module is located on the first chip, and the second module is located on the second chip. The first module receiving the multiple first sub-data sent by the second module includes, but is not limited to, the first module receiving the multiple first sub-data sent by the second module through multiple channels of an attachment unit interface (AUI). Exemplarily, one first sub-data is sent through one AUI channel.

[0103] Among them, multiple first sub-data are data encoded by the first FEC code type and distributed by PMA, but the first sub-data has not been interleaved. Therefore, in order to obtain the first data after interleaving, after the first module receives multiple first sub-data, it aligns the multiple first sub-data to obtain multiple first codewords, and then interleaves the multiple first codewords to obtain the first data. In the first method of obtaining the first data, since the first sub-data has not been interleaved, but the first module interleaves the multiple first codewords. In the embodiments of the present application, the encoding of the first sub-data using the first FEC code type can be referred to as outer code encoding, and the first codeword is referred to as an outer codeword, and this outer code encoding occurs in the second module.

[0104] Regarding the method of aligning multiple first sub-data, the embodiments of the present application do not limit it. Since it is bounded by alignment marker (AM) characters, and precisely because of this, AM characters can provide existing markers for data recognition, which facilitates subsequent recognition of the inserted data. Therefore, for the case where the first sub-data includes AM characters, aligning the multiple first sub-data includes but is not limited to AM locking and Deskew. Among them, AM locking is used to find the boundary of the codeword. After finding the codeword boundary, Deskew can be performed in the manner defined by 400GbE, and then the first codeword can be obtained.

[0105] In the embodiments of the present application, the interleaving process performed by the first module on multiple first codewords is referred to as outer code interleaving. Therefore, in the first method of obtaining the first data, no interleaving process is performed in the second module, and outer code interleaving is performed in the first module. Regarding the method of interleaving multiple first codewords, that is, outer code interleaving, it includes but is not limited to the following three types.

[0106] Outer code interleaving method 1: directly interleave multiple first codewords, and the number of interleaved codewords is the number of codewords participating in the interleaving.

[0107] Direct interleaving means interleaving the codewords participating in the interleaving in sequence according to the interleaving granularity without intervals, and the number of interleaved codewords obtained is the number of codewords participating in the interleaving. As Figure 3 shown, taking multiple first codewords as 4 codewords, namely codeword A, codeword B, codeword C, and codeword D, as an example, the number of interleaved codewords obtained by directly interleaving these 4 codewords is the number of codewords participating in the interleaving. For example, Figure 3 if the number of codewords participating in the interleaving is 4, then the number of interleaved codewords is represented by M, and M = 4.

[0108] As Figure 4As shown, the content of codeword A includes A0, A1, A2, A3, A4, A5, A6, and A7, the content of codeword B includes B0, B1, B2, B3, B4, B5, B6, and B7, the content of codeword C includes C0, C1, C2, C3, C4, C5, C6, and C7, and the content of codeword D includes D0, D1, D2, D3, D4, D5, D6, and D7. After directly interleaving codeword A, codeword B, codeword C, and codeword D, A0, B0, C0, D0, A1, B1, C1, D1... are sent in sequence according to the direction shown by the arrow in Figure 4 , and so on. The sending order is as shown in Figure 5 . Figure 4 and Figure 5 , one cell such as A0, B0 represents the interleaving granularity. The embodiments of the present application do not limit the interleaving granularity, including but not limited to 1 bit, 1 16-QAM symbol, or multiple bits, multiple symbols.

[0109] Outer code interleaving method 2: Staggered interleaving is performed on multiple first codewords at a reference interval. The number of interleaved codewords is the number of codewords participating in the interleaving, and the reference interval is the number of code blocks staggered between two codewords.

[0110] Staggered interleaving means that the codewords participating in the interleaving are interleaved in sequence at the reference interval according to the interleaving granularity, and the number of interleaved codewords obtained is the number of codewords participating in the interleaving. As shown in Figure 6 , taking 4 codewords, namely codeword A, codeword B, codeword C, and codeword D, as the first codewords as an example, after performing staggered interleaving on these 4 codewords at the reference interval, the number of interleaved codewords obtained is the number of codewords participating in the interleaving. For example, Figure 6 if the number of codewords participating in the interleaving is 4, the number of interleaved codewords is represented by M, and M = 4.

[0111] Among them, the content of codeword A includes A0, A1, A2, A3, A4, A5, A6, and A7, the content of codeword B includes B0, B1, B2, B3, B4, B5, B6, and B7, the content of codeword C includes C0, C1, C2, C3, C4, C5, C6, and C7, and the content of codeword D includes D0, D1, D2, D3, D4, D5, D6, and D7. Taking the reference interval as K code blocks and K = 1 as an example, that is, after performing staggered interleaving on codeword A, codeword B, codeword C, and codeword D in sequence at an interleaving granularity with a 1-code-block delay, A0, A1, B0, A2, B1, C0, A3, B2, C1, D0, A4, B3, C2, D1... are sent in the direction shown by the arrow in Figure 7 , and so on. Figure 7Among them, a single cell such as A0, B0 represents the interleaving granularity. The embodiments of the present application do not limit the interleaving granularity, including but not limited to 1 bit, 1 QAM16 symbol, or multiple bits, multiple symbols.

[0112] Optionally, Figure 7 Only taking K = 1, that is, the reference interval is 1 code block as an example for illustration, but it is not used to limit the present application. K can also be other values, that is, the reference interval can be other values, and the embodiments of the present application do not limit the reference interval.

[0113] For the outer code interleaving method three, convolutional interleaving is performed on multiple first codewords, and the number of interleaved codewords is the number of codewords participating in the interleaving.

[0114] In this interleaving method three, the codewords do not enter channels with different time delays in parallel, but serially. Convolutional interleaving means that the input bit stream, that is, multiple first codewords participating in the interleaving, is polled and distributed into multiple registers with different lengths of delay in units of p bits as a data block unit. The delays corresponding to these registers usually increase or decrease equally in the order of arrival of the data block distribution. Then, the data blocks from each register with unequal delays are converged into the same data stream to form an interleaved bit stream. Among them, the embodiments of the present application do not limit the size of p, and it can be set based on the application scenario or experience.

[0115] As Figure 8 shown, multiple first codewords from the first module are sequentially distributed to N channels according to the arrangement order of the original data sent in the first module initially, and each channel has a different time delay. Figure 8 Among them, taking the delay corresponding to the register usually increasing equally in the order of arrival of the data block distribution as an example, the time delay of channel 1 is 1 unit, the time delay of channel 2 is 2 units, and so on. Optionally, the starting point of the time delay accumulation can be 0 units. Taking the delay corresponding to the register usually decreasing equally in the order of arrival of the data block distribution as an example, the time delay of channel 1 can be the maximum value, such as N units, the time delay of channel 2 is N - 1 units, and so on. Optionally, the starting point of the time delay decrease can also be N - 1, until the minimum value is 0.

[0116] Whether it is increasing or decreasing, the above time delay unit can be the time delay corresponding to n bits, where n is a positive integer. Exemplarily, the selected value of n can be the code length of the inner code, that is, the code length of the second FEC code type.

[0117] The second method for obtaining the first data. The first module obtains the first data, including: the first module receives a plurality of first sub-data sent by the second module, and the plurality of first sub-data are data encoded by the first FEC code type, subjected to interleaving processing, and distributed by the physical medium attachment (PMA) sublayer; the first module aligns the plurality of first sub-data to obtain a plurality of first codewords; the first module performs interleaving processing on the plurality of first codewords to obtain the first data.

[0118] In the second method for obtaining the first data, the first module is located on the first chip, and the second module is located on the second chip. The first module receives the plurality of first sub-data sent by the second module, including but not limited to the first module receiving the plurality of first sub-data sent by the second module through multiple channels of an attachment unit interface (AUI). Exemplarily, one first sub-data is sent through one AUI channel.

[0119] Since the plurality of first sub-data are data encoded by the first FEC code type, subjected to interleaving processing, and distributed by the PMA, after the first module receives the plurality of first sub-data, it can align the plurality of first sub-data to obtain a plurality of first codewords. Then, interleaving processing is performed on the plurality of first codewords to obtain the first data. In the second method for obtaining the first data, since the first sub-data are subjected to interleaving processing and the first module further performs interleaving processing on the plurality of first codewords, the error correction performance can be further improved. In addition, in the embodiments of the present application, the interleaving processing performed by the first module on the plurality of first codewords is referred to as outer code interleaving. Therefore, in the second method for obtaining the first data, interleaving processing is performed inside the second module, and outer code interleaving is performed inside the first module.

[0120] Regarding the method for aligning the plurality of first sub-data, it still includes but is not limited to AM locking and de-skewing. In addition, for the method of performing interleaving processing on the plurality of first codewords, reference can be made to the description of the first to third outer code interleaving methods in the first method for obtaining the first data above, and details are not described here again.

[0121] It should be noted that in the second method for obtaining the first data, since the plurality of first sub-data are data encoded by the first FEC code type, subjected to interleaving processing, and distributed by the PMA, and interleaving processing is still required after obtaining the plurality of first codewords, when the first module aligns the plurality of first sub-data to obtain the plurality of first codewords, it may include a de-interleaving operation, or may not perform de-interleaving and directly perform interleaving processing on the plurality of first codewords.

[0122] Exemplarily, the first module aligns multiple first sub-data to obtain multiple first codewords, including: the first module aligns multiple first sub-data, de-interleaves the aligned data, and obtains multiple first codewords according to the de-interleaving result. For example, if the interleaving performed in the second module is 2-codeword interleaving, then the first module obtains multiple first sub-data, aligns the multiple first sub-data, and obtains data with a length of 2*n codewords. In the case of de-interleaving, the data with a length of 2*n codewords is de-interleaved, and multiple first codewords are obtained according to the de-interleaving result, and the descriptions of outer code interleaving methods 1 to 3 in Method 1 for obtaining the first data are performed.

[0123] Alternatively, the first module aligns multiple first sub-data to obtain multiple first codewords, including: the first module aligns multiple first sub-data and uses the aligned data as multiple first codewords. For example, if the interleaving performed in the second module is 2-codeword interleaving, then the first module obtains multiple first sub-data, aligns the multiple first sub-data, and obtains data with a length of 2*n codewords. In the case of not de-interleaving, the data with a length of 2*n codewords is used as 2*n codewords, that is, multiple first codewords, and the descriptions of outer code interleaving methods 1 to 3 in Method 1 for obtaining the first data are performed. Directly using the aligned data as multiple first codewords without de-interleaving can improve the data transmission speed.

[0124] Method 3 for obtaining the first data. The first module obtains the first data, including: the first module receives multiple first sub-data sent by the second module. The multiple first sub-data are data encoded with the first FEC code type, subjected to interleaving processing, and distributed by the physical medium attachment sublayer (PMA); the first module aligns the multiple first sub-data to obtain the first data.

[0125] In Method 3 for obtaining the first data, the first module is located on the first chip, and the second module is located on the second chip. The first module receives multiple first sub-data sent by the second module, including but not limited to the first module receiving multiple first sub-data sent by the second module through multiple channels of an Attachment Unit Interface (AUI). Exemplarily, one first sub-data is sent through one AUI channel.

[0126] Since the multiple first sub-data are data encoded with the first FEC code type, subjected to interleaving processing, and distributed by PMA, after the first module receives the multiple first sub-data, it can no longer perform interleaving processing and only needs to align the multiple first sub-data. Thus, the steps for obtaining the first codewords can be saved, and the delay and power consumption can be further saved. In Method 3 for obtaining the first data, since the first sub-data have been subjected to interleaving processing, but no interleaving processing is performed within the first module, therefore, interleaving processing is performed within the second module, and no outer code interleaving is performed within the first module.

[0127] The methods for aligning multiple first sub-data include, but are not limited to, AM locking and deskewing.

[0128] It should be noted that in the above-mentioned Method 1 to Method 3 for obtaining the first data, when the first module obtains the first data, it receives multiple first sub-data sent through multiple channels of the AUI from the second module. Optionally, the first module can also receive multiple first sub-data sent by the second module through one channel of the AUI. For details, see Method 4 for obtaining the first data below.

[0129] Method 4 for obtaining the first data: The first module is located on the first chip. The first module obtains the first data, including: The first module receives multiple first sub-data sent by the second module through one channel of one AUI. The second module is located on the second chip. The multiple first sub-data are data encoded with the first FEC code type and distributed by PMA, or the multiple first sub-data are data encoded with the first FEC code type, processed by interleaving, and distributed by PMA; The first module performs AM locking on the multiple first sub-data and obtains the first data according to the data after AM locking.

[0130] Exemplarily, the first module performs AM locking on the multiple first sub-data and obtains the first data according to the data after AM locking, including: The first module performs AM locking on the multiple first sub-data to obtain multiple first codewords; The first module performs interleaving processing on the multiple first codewords to obtain the first data.

[0131] In Method 4 for obtaining the first data, since the multiple first sub-data are sent through one channel of one AUI, and these multiple first sub-data are not only encoded with the first FEC code type but also distributed by PMA. For the case where the multiple first sub-data are not processed by interleaving, in order to obtain the first data processed by interleaving, after the first module receives the multiple first sub-data, it performs AM locking on the multiple first sub-data to obtain multiple first codewords, and then performs interleaving processing on the multiple first codewords to obtain the first data. In Method 4 for obtaining the first data, since the first sub-data are not processed by interleaving, but the first chip performs interleaving processing on the multiple first codewords. In the embodiments of the present application, the interleaving processing performed by the first module on the multiple first codewords is referred to as outer code interleaving. Therefore, in Method 4 for obtaining the first data, no interleaving processing is performed inside the second module, and outer code interleaving is performed inside the first module.

[0132] In a possible implementation, multiple first sub-data in the fourth method for obtaining the first data are sent by one channel of an AUI. Moreover, these multiple first sub-data are not only encoded using the first FEC code pattern, but also undergo interleaving processing and PMA distribution. For the case where multiple first sub-data undergo interleaving processing, since interleaving processing is still required after obtaining multiple first codewords, in the fourth method for obtaining the first data, when the first module performs AM locking on multiple first sub-data to obtain multiple first codewords, it may include a de-interleaving operation, or it may directly perform interleaving processing on multiple first codewords without de-interleaving.

[0133] Exemplarily, the first module performs AM locking on multiple first sub-data to obtain multiple first codewords, including: the first module performs AM locking on multiple first sub-data, de-interleaves the data after AM locking, and obtains multiple first codewords according to the de-interleaving result. For example, if the interleaving performed in the second module is interleaving of two codewords, then the first module obtains multiple first sub-data, performs AM locking on multiple first sub-data, and obtains data with a length of 2*n codewords. In the case of de-interleaving, the data with a length of 2*n codewords is de-interleaved, and multiple first codewords are obtained according to the de-interleaving result, and then interleaving processing is performed on multiple first codewords.

[0134] Alternatively, the first module performs AM locking on multiple first sub-data to obtain multiple first codewords, including: the first module performs AM locking on multiple first sub-data, and uses the data after AM locking as multiple first codewords. For example, if the interleaving performed in the second module is interleaving of two codewords, then the first module obtains multiple first sub-data, performs AM locking on multiple first sub-data, and obtains data with a length of 2*n codewords. In the case of not de-interleaving, the data with a length of 2*n codewords is used as 2*n codewords, that is, multiple first codewords, and then interleaving processing is performed on multiple first codewords.

[0135] In addition, for the method of performing interleaving processing on multiple first codewords, reference can be made to the descriptions of outer code interleaving methods 1 to 3 in the first method for obtaining the first data above, which will not be elaborated here.

[0136] In a possible implementation, multiple first sub-data are data encoded using the first FEC code pattern and undergoing interleaving processing and physical medium attachment (PMA) sublayer distribution. The first module performs AM locking on multiple first sub-data and obtains the first data according to the data after AM locking, including: the first module performs AM locking on multiple first sub-data, and uses the data after AM locking as the first data.

[0137] For example, the first module is located on the first chip, and the second module is located on the second chip. The first module obtains first data, including: the first module receives a plurality of first sub-data sent by the second module through a channel of an AUI. The plurality of first sub-data are data encoded using a first FEC code type, subjected to interleaving processing, and PMA distribution; the first module performs alignment flag AM locking on the plurality of first sub-data, and uses the data after AM locking as the first data.

[0138] 202, the first module encodes the first data according to a second FEC code type to obtain a plurality of second codewords.

[0139] Regardless of which of the above methods 1 to 4 for obtaining the first data is used to obtain the first data, in order to further improve the error correction performance and implement concatenated coding, after the first module obtains the first data, it encodes the first data according to the second FEC code type to obtain a plurality of second codewords. Encoding the first data can be referred to as inner code encoding, and the second codewords are referred to as inner code codewords. This inner code encoding occurs in the first module.

[0140] Among them, the second FEC code type includes but is not limited to any one of RS code, BCH code, Fire code, turbo code, turbo product code, staircase code, and LDPC code. The embodiments of the present application do not limit the type of the second FEC code type. Exemplarily, if the code rate of the second codeword is R (R = k / n), and the rate of the first data before encoding is D, then the rate after encoding is D / R. Wherein, k is the length of the codeword information bit, n is the codeword length, and the codeword length is the sum of the information bit length and the parity bit length. For example, if the rate of the first data before encoding is D = 425 Gb / s, and R = 17 / 18 is selected, then the rate after encoding is D / R = 450 Gb / s. If R = 239 / 256, then the rate D / R after encoding is approximately 455.23 Gb / s.

[0141] In a possible implementation manner, the first module encodes the first data according to the second FEC code type to obtain a plurality of second codewords, including: the first module distributes the first data to obtain a plurality of second sub-data, and the first module encodes the plurality of second sub-data respectively according to the second FEC code type to obtain a plurality of second codewords.

[0142] Exemplarily, the first module distributes the first data to obtain a plurality of second sub-data, including: the first module distributes the first data through a physical coding sublayer (PCS) channel to obtain a plurality of second sub-data; or, the first module distributes the first data through PMA to obtain a plurality of second sub-data. The embodiments of the present application do not limit the number of second sub-data obtained by the first module through distribution. For example, the number of second sub-data obtained through distribution can be determined based on the application scenario or experience.

[0143] 203, the first module performs a second process on multiple second codewords to obtain second data.

[0144] In a possible implementation manner, the manner in which the first module performs a second process on multiple second codewords to obtain second data includes, but is not limited to, the following two.

[0145] The first way to obtain second data: The first module performs a second process on multiple second codewords to obtain second data, including: The first module performs an interleaving process on multiple second codewords, groups the interleaving result according to symbols or at least one bit required for data modulation, and distributes the grouped data to corresponding data channels; based on the data in each data channel, second data is obtained.

[0146] In the first way to obtain second data, by performing an interleaving process on multiple second codewords, burst errors on the link can be handled, and the error correction performance is further improved. The embodiments of the present application do not limit the manner of performing an interleaving process on multiple second codewords. After the interleaving process, the second codewords generate P paths of data, where P is an integer greater than or equal to 1. Each path of data corresponds to an inner code encoder. For example, as Figure 9 shown, outer code interleaving is implemented through an outer code interleaver, inner code interleaving is implemented through an inner code interleaver, and each path of data corresponds to an inner code encoder. Exemplarily, performing an interleaving process on multiple second codewords includes, but is not limited to, the following three interleaving process manners.

[0147] The first inner code interleaving manner: Interleave the second codewords from the same encoder among multiple second codewords.

[0148] In this first inner code interleaving manner, the number of second codewords from the same encoder among multiple second codewords is M', and the M' second codewords can be interleaved according to the interleaving granularity K'. As Figure 10 shown, taking the M' codewords from the same encoder as codeword A, codeword B, codeword C, and codeword D as an example, where the content of codeword A includes A0, A1, A2, A3, A4, A5..., the content of codeword B includes B0, B1, B2, B3, B4, B5..., the content of codeword C includes C0, C1, C2, C3, C4, C5..., and the content of codeword D includes D0, D1, D2, D3, D4, D5.... After interleaving codeword A, codeword B, codeword C, and codeword D with the interleaving granularity K', send A0, B0, C0, D0, A1, B1, C1, D1, A2, B2... in the direction indicated by the arrow in Figure 10 , and so on. Figure 10Among them, a single cell such as A0 and B0 represents the interleaving granularity. The embodiments of the present application do not limit the interleaving granularity K', including but not limited to 1 bit, 1 QAM16 symbol, or multiple bits and multiple symbols.

[0149] Inner code interleaving method 2 interleaves multiple second codewords from multiple encoders among multiple second codewords.

[0150] In this inner code interleaving method 2, since multiple second codewords from multiple encoders are interleaved among multiple second codewords, the number of codewords participating in the interleaving is equal to the number of encoders. For example, Figure 11 As shown, taking the interleaving of 4 second codewords from encoder A, encoder B, encoder C, and encoder D as an example, these 4 second codewords are codeword A, codeword B, codeword C, and codeword D respectively. Among them, the content of codeword A includes A0, A1, A2, A3, A4, A5..., the content of codeword B includes B0, B1, B2, B3, B4, B5..., the content of codeword C includes C0, C1, C2, C3, C4, C5..., and the content of codeword D includes D0, D1, D2, D3, D4, D5.... After interleaving codeword A, codeword B, codeword C, and codeword D with the interleaving granularity K', send A0, B0, C0, D0, A1, B1, C1, D1, A2, B2... in the direction indicated by the arrow in Figure 11 and so on.

[0151] Inner code interleaving method 3 interleaves the second codewords from the same encoder among multiple second codewords, and re-interleaves multiple data streams from multiple encoders obtained after interleaving.

[0152] This inner code interleaving method 3 is a combination of the above inner code interleaving method 1 and inner code interleaving method 2. First, interleave the second codewords from the same encoder among multiple second codewords. After the second codewords from different encoders are respectively interleaved, multiple data streams are obtained, and one data stream is obtained for one encoder. Then, re-interleave multiple data streams from multiple encoders obtained after interleaving. Since this inner code interleaving method 3 uses two-dimensional interleaving, the error correction performance of the second data obtained after inner code interleaving is better.

[0153] Regardless of whether the above inner code interleaving method 1 or method 2 is adopted, this method 1 for obtaining the second data can obtain a data stream through inner code interleaving. Then, it can be grouped according to the symbols required for data modulation and distributed to the data channels corresponding to two polarization directions. For example, for consecutive 8-bit data, the first 4 bits are assigned to the X polarization, and the last 4 bits are assigned to the Y polarization.

[0154] In addition, it should be noted that in the above-mentioned inner code interleaving methods 1 to 3, whether it is interleaving the second codewords from the same encoder, or interleaving multiple data streams from multiple encoders, or interleaving multiple second codewords from multiple encoders, any one of the direct interleaving, staggered interleaving and convolutional interleaving methods described in the above-mentioned outer code interleaving methods 1 to 3 can be used for interleaving. The specific interleaving method to be used is not limited in the embodiments of the present application.

[0155] The second method for obtaining the second data is that the first module performs a second processing on multiple second code words to obtain the second data, including: the first module groups the multiple second code words according to the symbols or at least one bit required for data modulation, and distributes the grouped data to the corresponding data channel; and obtains the second data based on the data in each data channel.

[0156] In the second method for obtaining the second data, the first module does not perform interleaving processing on the second codeword, and can directly group multiple second codewords according to the symbol required for data modulation or at least one bit, thereby saving the delay and power consumption of inner code interleaving. For example, when grouping according to the symbols required for data modulation and distributing them to data channels corresponding to two polarization directions, the first 4 bits of the continuous 8-bit data can be divided into X polarization and the last 4 bits can be divided into Y polarization.

[0157] In a possible implementation, the method provided in the embodiment of the present application can be applied to a coherent link. Considering the data stream after the inner code and outer code overhead, when inserting a training sequence (TS) / pilot symbol on the coherent link, a method of making up a frequency point can be adopted. Therefore, the second processing includes but is not limited to inserting at least one of the training sequence and pilot symbol required for the coherent link.

[0158] Optionally, at least one of the first processing and the second processing further includes inserting data for adjusting the frequency. The embodiment of the present application does not limit the type and content of the data for adjusting the frequency. The data for adjusting the frequency may be inserted periodically according to a fixed length. The fixed length and period may be determined based on the application scenario or experience, and the embodiment of the present application does not limit this. If the frequency is not suitable, or the frequency does not meet the requirements, the first processing and the second processing may both include inserting data for adjusting the frequency, or the first processing or the second processing may include inserting data for adjusting the frequency. If the frequency is suitable, the first processing and the second processing may not insert data for adjusting the frequency.

[0159] In addition, the embodiments of the present application do not limit the order of inserting the training sequence and pilot symbols required for the coherent link and inserting the data for adjusting the frequency.

[0160] For example, obtaining the second data based on the data in each data channel includes: inserting the training sequence and pilot symbols required for the coherent link into the data in each data channel to obtain the processed data, and inserting the data for adjusting the frequency point into the processed data to obtain the second data.

[0161] Alternatively, obtaining the second data based on the data in each data channel includes: inserting the data for adjusting the frequency point into the data in each data channel to obtain the processed data, and inserting the training sequence and pilot symbols required for the coherent link into the processed data to obtain the second data.

[0162] It should be noted that the embodiments of the present application do not limit the inserted training sequence and pilot symbols. For example, the inserted training sequence and pilot symbols can be pre-configured and configured based on the application scenario or experience. If the frequency point is already appropriate after the training sequence and pilot symbols are inserted, there is no need to perform the frequency point adjustment step, that is, there is no need to insert the data for adjusting the frequency point. For example, Figure 12 In, TS corresponds to the training sequence, PS corresponds to the pilot symbol, and OH corresponds to the additional data added without adjusting the frequency point. Exemplarily, the first symbol of TS is a part of the PS sequence.

[0163] For example, when t = t1 = 0 (that is, there is no TS and OH), then K = 0. Then the encoded rate is: D / R * (P + 1) / P. If P = 72, the final rate is 456.25 Gb / s. Under DP-QAM16 modulation, this code rate corresponds to a baud rate of 57.03125 GBd, which is 365 times the fundamental frequency of 156.25 MHz.

[0164] Another example is when t ≠ 0, that is, when there is TS, it is necessary to consider that the baud rate corresponding to D_out is also an integer multiple frequency. For example, t = 10, t1 = 63, T = 100, T1 = 1, then D_out = 457.5 Gb / s. Under DP-QAM16 modulation, the baud rate is 366 times the frequency.

[0165] It should be noted that the value of t1 above can be greater than P. At this time, the OH content may span one or more PSs.

[0166] 204, the first module transmits the second data.

[0167] In a possible implementation manner, the first module transmits the second data, including: the first module distributes the second data to obtain a plurality of third sub-data, and sends the plurality of third sub-data through a plurality of logical channels.

[0168] The embodiments of the present application do not limit the number of third sub - data obtained by the first module distributing the second data. For example, the number of third sub - data obtained by distribution can be determined based on the application scenario or experience.

[0169] The method provided by the embodiments of the present application is based on the first module for transmitting data to re - encode the acquired first data encoded with the first FEC code type through the second FEC code type to obtain the second data with concatenated encoding, so that the second data has a higher coding gain. When transmitting in a channel prone to bit errors, it can effectively correct the bit - error data, thereby improving the quality of data transmission. Since the second data is directly encoded based on the first data, the implementation process of this method is relatively simple, improving the efficiency of data transmission. Moreover, since the first data is data obtained through interleaving processing, it can eliminate the correlation of error bits within the codeword corrected by the second FEC code, improving the error - correction performance. In addition, by simultaneously using outer - code interleaving and inner - code interleaving, the error - correction performance can be further improved.

[0170] Next, in combination with the above Figure 2 shown method flow, taking the first module located in the first chip and the second module located in the second chip as examples for the following several scenarios, the data transmission method provided by the embodiments of the present application will be illustrated.

[0171] Scenario 1: The second chip does not perform interleaving processing, and the first chip performs outer - code interleaving and inner - code interleaving.

[0172] This Scenario 1 is Figure 2 the combination of the first way to obtain the first data and the first way to obtain the second data in the shown embodiment, that is, the second chip does not perform interleaving processing, and the first chip performs interleaving processing on both the first codeword and the second codeword. The implementation environment of this scenario can be as Figure 13 shown, and the process of data transmission is as follows.

[0173] The second chip performs outer - code encoding on the original data, that is, encodes it with FEC1 (the first FEC code type), and distributes the encoded data through PMA to obtain multiple first sub - data, and then sends the multiple first sub - data to the first chip through AUI. The multiple first sub - data are data encoded with the first FEC code type and distributed through PMA. After receiving the multiple first sub - data, the first chip performs AM locking and de - skewing on the multiple first sub - data to achieve the alignment operation and obtain multiple first codewords. Then, the first chip performs interleaving processing on the multiple first codewords, that is, outer - code interleaving, to obtain the first data.

[0174] Further, after the first chip encodes the first data according to the second FEC code type to obtain multiple second codewords, it performs interleaving processing on the multiple second codewords, that is, inner code interleaving, and then groups the interleaved result according to the symbols required for data modulation, and distributes the grouped data to the corresponding data channels; the second data is obtained based on the data in each data channel. Finally, the second data is modulated and sent.

[0175] Scenario 2: The second chip does not perform interleaving processing, the first chip performs outer code interleaving and inner code interleaving, and the first chip performs frequency point adjustment and TS / Pilot insertion.

[0176] This Scenario 2 is based on Scenario 1 and adds operations of frequency point adjustment and TS / Pilot insertion. Therefore, this Scenario 2 can also be Figure 2 a combination of the first method for obtaining the first data and the first method for obtaining the second data in the shown embodiment, that is, the second chip does not perform interleaving processing, and the first chip performs interleaving processing on both the first codewords and the second codewords. The implementation environment of this scenario can be as Figure 14 shown, and the process of data transmission is as follows.

[0177] The second chip performs outer code encoding on the original data, that is, encodes using FEC1 (the first FEC code type), and distributes the encoded data through PMA to obtain multiple first sub-data, and then sends the multiple first sub-data to the first chip through AUI. The multiple first sub-data are data encoded using the first FEC code type and distributed through PMA. After the first chip receives the multiple first sub-data, it performs AM locking and de-skewing on the multiple first sub-data to achieve alignment operation and obtain multiple first codewords. Then, the first chip performs interleaving processing on the multiple first codewords, that is, outer code interleaving, to obtain the first data.

[0178] Further, after the first chip encodes the first data according to the second FEC code type to obtain multiple second codewords, it performs interleaving processing on the multiple second codewords, that is, inner code interleaving, and then groups the interleaved result according to the symbols required for data modulation, and distributes the grouped data to the corresponding data channels; the second data is obtained based on the data in each data channel. Finally, the second data is modulated and sent.

[0179] Among them, in Scenario 2, obtaining the second data based on the data in each data channel includes: inserting the training sequence and pilot symbols required for the coherent link into the data in each data channel to obtain the processed data, and inserting the data for adjusting the frequency point into the processed data to obtain the second data.

[0180] Alternatively, obtaining the second data based on the data in each data channel includes: inserting data for adjusting the frequency point into the data in each data channel to obtain processed data, and inserting the training sequence and pilot symbols required for the coherent link into the processed data to obtain the second data.

[0181] Scenario 3: The second chip does not perform interleaving processing, the first chip performs outer code interleaving but does not perform inner code interleaving, and the first chip performs frequency point adjustment and TS / Pilot insertion.

[0182] Compared with Scenario 2, this Scenario 3 reduces the operation of the first chip for inner code interleaving. This Scenario 3 is Figure 2 a combination of the first method for obtaining the first data and the second method for obtaining the second data in the illustrated embodiment, that is, the second chip does not perform interleaving processing, and the first chip only performs outer code interleaving on the first codeword. The implementation environment of this scenario can be as Figure 15 shown, and the process of data transmission is as follows.

[0183] The second chip performs outer code encoding on the original data, that is, encodes using FEC1 (the first FEC code type), and distributes the encoded data through PMA to obtain multiple first sub-data, and then sends the multiple first sub-data to the first chip through AUI. The multiple first sub-data are data encoded using the first FEC code type and distributed through PMA. After receiving the multiple first sub-data, the first chip performs AM locking and de-skewing on the multiple first sub-data to achieve alignment operation and obtain multiple first codewords. Then, the first chip performs interleaving processing, that is, outer code interleaving, on the multiple first codewords to obtain the first data.

[0184] Further, after the first chip encodes the first data according to the second FEC code type to obtain multiple second codewords, the first chip groups the multiple second codewords according to the symbols required for data modulation, and distributes the grouped data to the corresponding data channels; the second data is obtained based on the data in each data channel. Finally, the second data is modulated and sent.

[0185] Among them, in Scenario 3, obtaining the second data based on the data in each data channel includes: inserting the training sequence and pilot symbols required for the coherent link into the data in each data channel to obtain processed data, and inserting data for adjusting the frequency point into the processed data to obtain the second data.

[0186] Alternatively, obtaining the second data based on the data in each data channel includes: inserting data for adjusting the frequency point into the data in each data channel to obtain processed data, and inserting the training sequence and pilot symbols required for the coherent link into the processed data to obtain the second data.

[0187] Scenario 4: The second chip performs interleaving, the first chip performs outer code interleaving and inner code interleaving, and the first chip performs frequency adjustment and TS / Pilot insertion.

[0188] This scenario four can be Figure 2 In the embodiment shown, the second method for obtaining the first data is combined with the first method for obtaining the second data, that is, the second chip performs interleaving processing, and the first chip performs interleaving processing on both the first codeword and the second codeword. The implementation environment of this scenario can be as follows Figure 16 As shown, the process of data transmission is as follows.

[0189] The second chip performs outer code encoding on the original data, that is, encoding using FEC1 (first FEC code type), and performs outer code interleaving on the encoded data, and performs PMA distribution on the interleaved data stream to obtain multiple first sub-data, and then sends the multiple first sub-data to the first chip through AUI. The multiple first sub-data are data encoded using the first FEC code type and are interleaved and distributed by the physical medium access sublayer PMA. After receiving the multiple first sub-data, the first chip performs AM locking and de-skew on the multiple first sub-data to achieve alignment operations, and then obtains multiple first code words through deinterleaving. After that, the first chip performs interleaving processing on the multiple first code words, that is, outer code interleaving, to obtain the first data.

[0190] Furthermore, the first chip encodes the first data according to the second FEC code type, obtains multiple second code words, performs interleaving processing on the multiple second code words, i.e., inner code interleaving, and then groups the interleaving results according to the symbols required for data modulation, distributes the grouped data to the corresponding data channel, obtains the second data based on the data in each data channel, and finally modulates the second data for transmission.

[0191] Among them, in scenario four, the second data is obtained based on the data in each data channel, including: inserting the training sequence and pilot symbols required by the coherent link into the data in each data channel to obtain processed data, and inserting data for adjusting the frequency into the processed data to obtain the second data.

[0192] Alternatively, obtaining the second data based on the data in each data channel includes: inserting data for adjusting the frequency into the data in each data channel to obtain processed data, and inserting the training sequence and pilot symbol required by the coherent link into the processed data to obtain the second data.

[0193] Scenario 5: The second chip performs interleaving, the first chip performs outer code interleaving but does not perform inner code interleaving, and the first chip performs frequency adjustment and TS / Pilot insertion.

[0194] This scene five can beFigure 2 In the embodiment shown, the second method for obtaining the first data is combined with the second method for obtaining the second data, that is, the second chip performs interleaving processing, and the first chip only performs interleaving processing on the first codeword, and does not perform interleaving processing on the second codeword. The implementation environment of this scenario can be as follows Figure 17 As shown, the process of data transmission is as follows.

[0195] The second chip performs outer code encoding on the original data, that is, encoding using FEC1 (first FEC code type), and performs outer code interleaving on the encoded data, and performs PMA distribution on the interleaved data stream to obtain multiple first sub-data, and then sends the multiple first sub-data to the first chip through AUI. The multiple first sub-data are data encoded using the first FEC code type and are interleaved and distributed by the physical medium access sublayer PMA. After receiving the multiple first sub-data, the first chip performs AM locking and de-skew on the multiple first sub-data to achieve alignment operations, and then obtains multiple first code words through deinterleaving. After that, the first chip performs interleaving processing on the multiple first code words, that is, outer code interleaving, to obtain the first data.

[0196] Furthermore, the first chip encodes the first data according to the second FEC code type to obtain multiple second code words. The first chip then groups the multiple second code words according to the symbols required for data modulation and distributes the grouped data to corresponding data channels; and obtains the second data based on the data in each data channel.

[0197] Among them, in scenario five, the second data is obtained based on the data in each data channel, including: inserting the training sequence and pilot symbols required by the coherent link into the data in each data channel to obtain processed data, and inserting data for adjusting the frequency into the processed data to obtain the second data.

[0198] Alternatively, obtaining the second data based on the data in each data channel includes: inserting data for adjusting the frequency into the data in each data channel to obtain processed data, and inserting the training sequence and pilot symbol required by the coherent link into the processed data to obtain the second data.

[0199] Scenario 6: The second chip performs interleaving, the first chip does not perform outer code interleaving, but performs inner code interleaving, and the first chip performs frequency adjustment and TS / Pilot insertion.

[0200] This scene six can be Figure 2 The second method for obtaining the first data and the first method for obtaining the second data in the embodiment shown are combined, that is, the second chip performs interleaving processing, and the first chip does not perform interleaving processing on the first codeword, but performs interleaving processing on the second codeword. The implementation environment of this scenario can be as follows Figure 18As shown, the process of data transmission is as follows.

[0201] The second chip performs outer code encoding on the original data, that is, encoding using FEC1 (first FEC code type), and performs outer code interleaving on the encoded data, and performs PMA distribution on the interleaved data stream to obtain multiple first sub-data, and then sends the multiple first sub-data to the first chip through AUI. The multiple first sub-data are data encoded using the first FEC code type and interleaved and distributed by the physical medium access sublayer PMA. After receiving the multiple first sub-data, the first chip performs AM locking and de-skew on the multiple first sub-data to achieve alignment operations, and then obtains multiple first code words through deinterleaving. After that, the first chip performs interleaving processing on the multiple first code words, that is, outer code interleaving, to obtain the first data.

[0202] Furthermore, the first chip encodes the first data according to the second FEC code type to obtain multiple second code words. The first chip then interleaves the multiple second code words, groups the interleaving results according to the symbols required for data modulation, and distributes the grouped data to corresponding data channels; and obtains the second data based on the data in each data channel.

[0203] Among them, in scenario six, the second data is obtained based on the data in each data channel, including: inserting the training sequence and pilot symbols required by the coherent link into the data in each data channel to obtain processed data, and inserting data for adjusting the frequency into the processed data to obtain the second data.

[0204] Alternatively, obtaining the second data based on the data in each data channel includes: inserting data for adjusting the frequency into the data in each data channel to obtain processed data, and inserting the training sequence and pilot symbol required by the coherent link into the processed data to obtain the second data.

[0205] Scenario 7: The second chip performs interleaving, the first chip does not perform outer code interleaving, nor does it perform inner code interleaving, but the first chip performs frequency adjustment and TS / Pilot insertion.

[0206] This scene seven can be Figure 2 The third method for obtaining the first data and the second method for obtaining the second data in the embodiment shown are combined, that is, the second chip performs interleaving processing, and the first chip does not perform interleaving processing on the first codeword, but performs interleaving processing on the second codeword. The implementation environment of this scenario can be as follows Figure 18 As shown, the process of data transmission is as follows.

[0207] The second chip performs outer code encoding on the original data, that is, FEC1 (first FEC code type) encoding, and performs outer code interleaving on the encoded data, and performs PMA distribution on the interleaved data stream to obtain multiple first sub-data, and then sends the multiple first sub-data to the first chip through AUI. The multiple first sub-data are data encoded by the first FEC code type and are interleaved and distributed by the physical medium access sublayer PMA. After receiving the multiple first sub-data, the first chip performs AM locking on the multiple first sub-data to achieve alignment operation, and then obtains the first data by deinterleaving.

[0208] Furthermore, the first chip encodes the first data according to the second FEC code type to obtain multiple second code words. The first chip then groups the multiple second code words according to the symbols required for data modulation and distributes the grouped data to corresponding data channels; and obtains the second data based on the data in each data channel.

[0209] Among them, in scenario seven, the second data is obtained based on the data in each data channel, including: inserting the training sequence and pilot symbols required by the coherent link into the data in each data channel to obtain processed data, and inserting data for adjusting the frequency into the processed data to obtain the second data.

[0210] Alternatively, obtaining the second data based on the data in each data channel includes: inserting data for adjusting the frequency into the data in each data channel to obtain processed data, and inserting the training sequence and pilot symbol required by the coherent link into the processed data to obtain the second data.

[0211] It should be noted that the above scenarios 1 to 7 correspond to Figures 13 - 19 In the embodiment, the outer code encoding (FEC1) can be implemented inside the PCS, or can be independently implemented outside the PCS by a separate encoding module, which is not limited in the embodiment of the present application.

[0212] Another point that needs to be explained is that TS / Pilot in the embodiments of the present application can be understood as TS and / or Pilot.

[0213] The above takes the first module as an example to illustrate the method of data transmission. Next, the data transmission process will be described after the first module sends the second data. Figure 20 As shown, the data transmission method includes the following steps.

[0214] 2001, the third module obtains second data, the second data is data obtained by encoding the first data with the second FEC code type and performing a second process, the first data is data encoded with the first FEC code type and subjected to a first process, and the first process includes an interleaving process.

[0215] Combined with Figure 1 the illustrated implementation environment, the third module obtains the second data sent by the first module. Combined with Figure 2 the illustrated embodiments, there are various ways for the first module to obtain the second data, which are not elaborated one by one in the embodiments of the present application. For details, refer to the content of the above Figure 2 illustrated embodiments. For the case where the first module distributes the second data to obtain multiple third sub-data and sends the multiple third sub-data through multiple logical channels, the third module obtaining the second data includes: the third module receives the multiple third sub-data and restores the second data based on the multiple third sub-data.

[0216] In 2002, the third module decodes the second data according to the second FEC code type to obtain the decoded data.

[0217] Since there are various ways for the first module to obtain the second data, there are also various situations for the second data. For different situations of the second data, the third module can adopt different processing methods, including but not limited to decoding the second data according to the second FEC code type to obtain the decoded data.

[0218] After that, the third module can further process the decoded data. The embodiments of the present application do not limit the processing method of the second data by the third module. For example, the decoded data is continuously sent to other modules. Or, if the second data is obtained after outer code interleaving and inner code interleaving, before the third module decodes the second data according to the second FEC code type, the second data is first de-interleaved to obtain the second codeword, then the second codeword is decoded with the second FEC code type to obtain the decoded data, and then the decoded data is de-interleaved again to obtain the first codeword.

[0219] In addition, the third module may be located in the third chip, and the first module is located in the first chip. The third module receives the second data sent by the first module through the AUI.

[0220] The embodiments of the present application also provide a data transmission device. Figure 21 is a schematic structural diagram of a data transmission device provided by the embodiments of the present application. Based on Figure 21 the following multiple units shown, the Figure 21 illustrated data transmission device can perform all or part of the operations performed by the first module. It should be understood that the device may include more additional units than the shown units or omit some of the shown units, and the embodiments of the present application do not limit this. As Figure 21 shown, the device includes:

[0221] An acquisition unit 2101, configured to acquire first data, where the first data is data that is encoded using a first forward error correction (FEC) code type and has undergone first processing, and the first processing includes interleaving processing;

[0222] An encoding unit 2102, configured to encode the first data according to a second FEC code type to obtain a plurality of second codewords;

[0223] A processing unit 2103, configured to perform second processing on the plurality of codewords to obtain second data;

[0224] A transmission unit 2104, configured to transmit the second data.

[0225] In a possible implementation manner, the second processing includes inserting at least one of a training sequence and pilot symbols required for a coherent link.

[0226] In a possible implementation manner, at least one of the first processing and the second processing further includes inserting data for adjusting a frequency point.

[0227] In a possible implementation manner, the acquisition unit 2101 is configured to receive a plurality of first sub-data sent by a second module, where the plurality of first sub-data are data that is encoded using a first FEC code type and has undergone physical medium attachment (PMA) layer distribution; align the plurality of first sub-data to obtain a plurality of first codewords; and perform interleaving processing on the plurality of first codewords to obtain first data.

[0228] In a possible implementation manner, the acquisition unit 2101 is configured to receive a plurality of first sub-data sent by a second module, where the plurality of first sub-data are data that is encoded using a first FEC code type and has undergone interleaving processing and PMA layer distribution; align the plurality of first sub-data to obtain a plurality of first codewords; and perform interleaving processing on the plurality of first codewords to obtain first data.

[0229] In a possible implementation manner, the acquisition unit 2101 is configured to align the plurality of first sub-data, de-interleave the aligned data, and obtain a plurality of first codewords according to the result of the de-interleaving; or, align the plurality of first sub-data and use the aligned data as the plurality of first codewords.

[0230] In a possible implementation manner, the acquisition unit 2101 is configured to receive a plurality of first sub-data sent by a second module, where the plurality of first sub-data are data that is encoded using a first FEC code type and has undergone interleaving processing and PMA layer distribution; align the plurality of first sub-data to obtain first data.

[0231] In a possible implementation, the first module is located on the first chip, and the second module is located on the second chip. The acquisition unit 2101 is configured to receive a plurality of first sub-data sent by the second module through a plurality of channels of an attachment unit interface (AUI).

[0232] In a possible implementation, the first module is located on the first chip, and the acquisition unit 2101 is configured to receive a plurality of first sub-data sent by the second module through one channel of an attachment unit interface (AUI). The second module is located on the second chip. The plurality of first sub-data are data encoded with a first forward error correction (FEC) code type and distributed through a physical medium attachment (PMA) sublayer, or the plurality of first sub-data are data encoded with a first FEC code type and subjected to interleaving processing and PMA distribution; perform alignment mark (AM) locking on the plurality of first sub-data to obtain a plurality of first codewords; perform interleaving processing on the plurality of first codewords to obtain first data.

[0233] In a possible implementation, the plurality of first sub-data are data encoded with a first FEC code type and subjected to interleaving processing and physical medium attachment (PMA) sublayer distribution. The acquisition unit 2101 is configured to perform AM locking on the plurality of first sub-data, de-interleave the data after AM locking, and obtain a plurality of first codewords according to the result of de-interleaving; or perform AM locking on the plurality of first sub-data, and use the data after AM locking as the plurality of first codewords.

[0234] In a possible implementation, the first module is located on the first chip, and the acquisition unit 2101 is configured to receive a plurality of first sub-data sent by the second module through one channel of an attachment unit interface (AUI). The second module is located on the second chip. The plurality of first sub-data are data encoded with a first FEC code type and subjected to interleaving processing and physical medium attachment (PMA) sublayer distribution; perform alignment mark (AM) locking on the plurality of first sub-data, and use the data after AM locking as first data.

[0235] In a possible implementation, the processing unit 2103 is configured to perform interleaving processing on a plurality of second codewords, group the interleaving result according to symbols or at least one bit required for data modulation, and distribute the grouped data to corresponding data channels; obtain second data based on the data in each data channel.

[0236] In a possible implementation, the processing unit 2103 is configured to group a plurality of second codewords according to symbols or at least one bit required for data modulation, and distribute the grouped data to corresponding data channels; obtain second data based on the data in each data channel.

[0237] In a possible implementation, the processing unit 2103 is configured to insert the training sequence and pilot symbols required for the coherent link into the data in each data channel to obtain processed data, and insert data for adjusting the frequency point into the processed data to obtain second data.

[0238] In a possible implementation, the processing unit 2103 is configured to insert data for adjusting the frequency point into the data in each data channel to obtain processed data, and insert the training sequence and pilot symbols required for the coherent link into the processed data to obtain second data.

[0239] In a possible implementation, the obtaining unit 2101 is configured to directly interleave a plurality of first codewords, and the number of interleaved codewords is the number of codewords participating in the interleaving; or, stagger-interleave a plurality of first codewords at a reference interval, and the number of interleaved codewords is the number of codewords participating in the interleaving, and the reference interval is the number of code blocks staggered between two codewords; or, perform convolutional interleaving on a plurality of first codewords, and the number of interleaved codewords is the number of codewords participating in the interleaving.

[0240] In a possible implementation, the processing unit 2103 is configured to interleave the second codewords from the same encoder among a plurality of second codewords; or, interleave a plurality of second codewords from a plurality of encoders; or, interleave the second codewords from the same encoder among a plurality of second codewords, and re-interleave the plurality of data streams from a plurality of encoders obtained after the interleaving.

[0241] In a possible implementation, the encoding unit 2102 is configured to distribute first data to obtain a plurality of second sub-data, and encode the plurality of second sub-data according to a second FEC code type to obtain a plurality of second codewords.

[0242] In a possible implementation, the encoding unit 2102 is configured to distribute first data through a Physical Coding Sublayer (PCS) channel to obtain a plurality of second sub-data; or, distribute first data through a Physical Medium Attachment (PMA) sublayer to obtain a plurality of second sub-data.

[0243] In a possible implementation, the transmission unit 2104 is configured to distribute second data to obtain a plurality of third sub-data, and send the plurality of third sub-data through a plurality of logical channels.

[0244] Figure 22 is a schematic structural diagram of a data transmission device provided by an embodiment of the present application. Based on Figure 22 the following multiple units shown, the Figure 22The data transmission device shown can perform all or part of the operations performed by the third module. It should be understood that the device may include more additional units than those shown or omit some of the units shown, and the embodiments of the present application do not limit this. As Figure 22 shown, the device includes:

[0245] An acquisition unit 2201, configured to acquire second data, where the second data is data obtained by encoding first data using a second forward error correction (FEC) code type and performing a second process, the first data being data encoded using a first FEC code type and having undergone a first process, and the first process including an interleaving process;

[0246] A decoding unit 2202, configured to decode the second data according to the second FEC code type to obtain the decoded data.

[0247] In a possible implementation manner, the acquisition unit 2201 is configured to receive a plurality of third sub-data and recover the second data based on the plurality of third sub-data.

[0248] It should be understood that the above Figure 21 、 Figure 22 When the provided device implements its functions, only the above division of each functional module is used for illustration. In actual applications, the above functions may be allocated to different functional units according to needs, that is, the internal structure of the device is divided into different functional units to complete all or part of the above-described functions. In addition, the device provided in the above embodiments and the method embodiments belong to the same concept, and the specific implementation process is detailed in the method embodiments and will not be repeated here.

[0249] The embodiments of the present application provide a data transmission device, which includes: a processor, the processor is coupled to a memory, and at least one program instruction or code is stored in the memory, and the at least one program instruction or code is loaded and executed by the processor so that the data transmission device implements the method in the above method embodiments.

[0250] See Figure 23 , Figure 23 which shows a schematic structural diagram of a data transmission device 1100 provided by an exemplary embodiment of the present application. The data transmission device 1100 is a transmitting side / receiving side device. Figure 23 The data transmission device 1100 shown is used to execute the above Figure 2Operations involved in the data transmission method shown. The data transmission device 1100 is, for example, a network device such as a switch or a router, and other devices including such a chip cascading mode (such as a server, a PC, etc.). The hardware structure of the data transmission device 1100 includes a communication interface 1101 and a processor 1102. Optionally, the communication interface 1101 and the processor 1102 are connected through a bus 1104. Among them, the communication interface 1101 is used to obtain the first data and transmit the second data. The processor may store instructions or program codes, and execute the functions performed by the first module or the third module by calling the instructions or program codes. Optionally, the network device further includes a memory 1103, and the instructions or program codes are stored in the memory 1103. The processor 1102 is used to call the instructions or program codes in the memory 1103 to enable the network device to execute the relevant processing steps of the first module in the above method embodiments. In a specific embodiment, the data transmission device 1100 in the embodiment of the present application may include the first module in each of the above method embodiments. The processor 1102 in the data transmission device 1100 reads the instructions or program codes in the memory 1103, so that Figure 23 the data transmission device 1100 shown can perform all or part of the operations performed by the first module.

[0251] In a specific embodiment, the data transmission device 1100 in the embodiment of the present application includes the third module in each of the above method embodiments. The processor 1102 in the data transmission device 1100 reads the instructions or program codes in the memory 1103, so that Figure 23 the data transmission device 1100 shown can perform all or part of the operations performed by the third module.

[0252] Exemplarily, the processor 1102 is, for example, a general-purpose central processing unit (CPU), a digital signal processor (DSP), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits for implementing the solutions of this application. For example, the processor 1102 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. It can implement or execute various logic blocks, modules, and circuits described in connection with the disclosed content of the embodiments of the present invention. The processor can also be a combination for implementing computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and so on.

[0253] Optionally, the data transmission device 1100 further includes a bus. The bus is used to transfer information between the components of the data transmission device 1100. The bus can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 23 only a thick line is shown in the figure, but it does not mean that there is only one bus or one type of bus. Figure 23 In the figure, in addition to being connected by a bus between the components of the data transmission device 1100, other connection methods can also be used. The embodiments of the present invention do not limit the connection methods of the components.

[0254] The memory 1103 is, for example, a read-only memory (ROM) or other type of static storage device that can store static information and instructions, such as a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, such as an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM), or other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media, or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 1103 exists independently, for example, and is connected to the processor 1102 through a bus. The memory 1103 can also be integrated with the processor 1102.

[0255] The communication interface 1101 uses any device such as a transceiver to communicate with other devices or communication networks, and the communication network can be an Ethernet, a radio access network (RAN), or a wireless local area network (WLAN), etc. The communication interface 1101 can include a wired communication interface and can also include a wireless communication interface. Specifically, the communication interface 1101 can be an Ethernet interface, a fast Ethernet (FE) interface, a gigabit Ethernet (GE) interface, an asynchronous transfer mode (ATM) interface, a wireless local area network (WLAN) interface, a cellular network communication interface, or a combination thereof. The Ethernet interface can be an optical interface, an electrical interface, or a combination thereof. In the embodiments of the present application, the communication interface 1101 can be used for the device 1100 for data transmission to communicate with other devices.

[0256] In a specific implementation, as an embodiment, the processor 1102 can include one or more CPUs. Each of these processors can be a single-CPU processor or a multi-CPU processor. Here, the processor can refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0257] In a specific implementation, as an embodiment, the data transmission device 1100 may include multiple processors. Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). The processor here may refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0258] In a specific implementation, as an embodiment, the data transmission device 1100 may further include an output device and an input device. The output device communicates with the processor 1102 and can display information in various ways. For example, the output device may be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector, etc. The input device communicates with the processor 1102 and can receive user input in various ways. For example, the input device may be a mouse, a keyboard, a touch screen device, or a sensing device, etc.

[0259] In some embodiments, the memory 1103 is used to store the program code for executing the solution of this application, and the processor 1102 can execute the program code stored in the memory 1103. That is, the data transmission device 1100 can implement the data transmission method provided by the method embodiment through the program code in the processor 1102 and the memory 1103. The program code may include one or more software modules. Optionally, the processor 1102 itself can also store the program code or instructions for executing the solution of this application.

[0260] In a specific embodiment, the data transmission device 1100 of the embodiment of this application may include the first chip in each of the above method embodiments. The processor 1102 in the data transmission device 1100 reads the program code stored in the memory 1103 or the program code or instructions stored by the processor 1102 itself, so that Figure 23 the data transmission device 1100 shown can perform all or part of the operations performed by the first network device.

[0261] In a specific embodiment, the data transmission device 1100 of the embodiment of this application may include the third module in each of the above method embodiments. The processor 1102 in the data transmission device 1100 reads the program code stored in the memory 1103 or the program code or instructions stored by the processor 1102 itself, so that Figure 23 the data transmission device 1100 shown can perform all or part of the operations performed by the third module.

[0262] The device 1100 for data transmission may also correspond to the above Figure 21 , 22 shown device, Figure 21 , 22 and each functional unit of the shown device is implemented by the software of the device 1100 for data transmission. In other words, Figure 21 , 22 the functional units included in the shown device are generated after the processor 1102 of the device 1100 for data transmission reads the program code stored in the memory 1103.

[0263] Among them, Figure 2 each step of the data transmission method shown is completed by the integrated logic circuit of the hardware in the processor of the device 1100 for data transmission or the instructions in the form of software. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as being executed and completed by the hardware processor, or executed and completed by a combination of the hardware and software modules in the processor. The software module may be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. This storage medium is located in the memory, and the processor reads the information in the memory and combines its hardware to complete the steps of the above method. To avoid repetition, it will not be described in detail here.

[0264] The embodiments of the present application also provide a data transmission system, which includes: a first device for data transmission and a second device for data transmission; the first device for data transmission is used to execute Figure 2 the method executed by the first module shown, and the second device for data transmission is used to execute Figure 2 the method executed by the third module shown.

[0265] The respective functions of the first device for data transmission and the second device for data transmission of this system can refer to the relevant descriptions shown above Figure 2 and will not be elaborated here one by one.

[0266] It should be understood that the above-mentioned processor can be a central processing unit (CPU), or can also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor, etc. It is worth noting that the processor can be a processor that supports the advanced RISC machines (ARM) architecture.

[0267] Further, in an alternative embodiment, the above-mentioned memory can include a read-only memory and a random access memory, and provide instructions and data to the processor. The memory can also include a non-volatile random access memory. For example, the memory can also store information about the device type.

[0268] The memory can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available. For example, static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus random access memory (DR RAM).

[0269] A computer-readable storage medium is also provided, in which at least one program instruction or code is stored. When the program instruction or code is loaded and executed by a processor, the computer can implement the data transmission method as described above. Figure 2 shown.

[0270] This application provides a computer program. When the computer program is executed by a computer, it can cause the processor or the computer to execute the corresponding steps and / or processes in the above method embodiments.

[0271] A chip is provided, including a processor for calling and running instructions stored in the memory from the memory, so that a device equipped with the chip executes the method in the above aspects.

[0272] Another chip is provided, including: an input interface, an output interface, a processor, and a memory. The input interface, the output interface, the processor, and the memory are connected through an internal connection path. The processor is used to execute the code in the memory. When the code is executed, the processor is used to execute the method in the above aspects.

[0273] A device is provided, including the chip in any one of the above solutions.

[0274] A device is provided, including the first chip in any one of the above solutions, and / or the third chip in any one of the above solutions.

[0275] In some embodiments, Figures 13 - 19 in, the second chip may be a sending-side device, such as a physical layer (PHY) chip in a router, a switch, or a server. The first chip may be an interface of a receiving-side device, such as a chip in an optical module or a CDR / retimer chip. The third chip may be an interface of a receiving-side device, such as a chip in an optical module or a CDR / retimer chip. The PHY chip may be a chip located on a single board of a computing device, and the chip may be one or any combination of a CPU, a network processor (NP), a neural network processing unit (NPU), a field programmable gate array (FPGA), a programmable logic controller (PLC), etc.

[0276] In some embodiments, the first chip communicates with the second chip via AUI; in some embodiments, the third chip communicates with the first chip via AUI.

[0277] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in accordance with the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (such as coaxial cable, optical fiber, digital subscriber line) or wireless (such as infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid-state disk).

[0278] The specific embodiments described above further elaborate on the purpose, technical solutions, and beneficial effects of the present application. It should be understood that the above description is only the specific embodiments of the present application and is not used to limit the protection scope of the present application. Any modifications, equivalent replacements, improvements, etc. made on the basis of the technical solutions of the present application shall be included in the protection scope of the present application.

[0279] Those of ordinary skill in the art can realize that, in combination with the method steps and modules described in the embodiments disclosed herein, they can be implemented by software, hardware, firmware, or any combination thereof. To clearly illustrate the interchangeability of hardware and software, the steps and components of each embodiment have been generally described according to their functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those of ordinary skill in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0280] Those of ordinary skill in the art can understand that all or part of the steps of implementing the above embodiments can be completed by hardware, or can be completed by a program instructing relevant hardware. The program can be stored in a computer-readable storage medium, and the above-mentioned storage medium can be a read-only memory, a magnetic disk or an optical disc, etc.

[0281] When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer program instructions. As an example, the method of the embodiments of the present application can be described in the context of machine-executable instructions, such as program modules executed in devices included in a target real or virtual processor. Generally speaking, program modules include routines, programs, libraries, objects, classes, components, data structures, etc., which perform specific tasks or implement specific abstract data structures. In the embodiments, the functions of the program modules can be merged or split among the described program modules. The machine-executable instructions for the program modules can be executed within local or distributed devices. In a distributed device, the program modules can be located in both local and remote storage media.

[0282] The computer program code for implementing the method of the embodiments of the present application can be written in one or more programming languages. These computer program codes can be provided to the processor of a general-purpose computer, a special-purpose computer or other programmable data processing devices, so that when the program codes are executed by the computer or other programmable data processing devices, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The program codes can be executed entirely on the computer, partially on the computer, as an independent software package, partially on the computer and partially on a remote computer, or entirely on a remote computer or server.

[0283] In the context of the embodiments of the present application, the computer program code or related data can be carried by any suitable carrier so that the device, apparatus or processor can execute the various processes and operations described above. Examples of carriers include signals, computer-readable media, etc.

[0284] Examples of signals can include electrical, optical, radio, acoustic or other forms of propagated signals, such as carrier waves, infrared signals, etc.

[0285] A machine-readable medium can be any tangible medium that contains or stores a program for use in or in connection with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. More specific examples of machine-readable storage media include electrical connections with one or more wires, portable computer disks, hard disks, random access memories (RAMs), read-only memories (ROMs), erasable programmable read-only memories (EPROMs or flash memories), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0286] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and modules described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be elaborated herein.

[0287] In several embodiments provided in the present application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the module is only a logical function division, and there may be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed couplings or direct couplings or communication connections to each other can be indirect couplings or communication connections through some interfaces, devices, or modules, and can also be electrical, mechanical, or other forms of connection.

[0288] The module described as a separate component may or may not be physically separated, and the component displayed as a module may or may not be a physical module, that is, it may be located in one place, or may be distributed to multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the embodiments of the present application.

[0289] In addition, the functional modules in the various embodiments of the present application can be integrated into one processing module, or each module can exist physically alone, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or in the form of software functional modules.

[0290] When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in various embodiments of this application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.

[0291] In this application, terms such as "first" and "second" are used to distinguish identical or similar items with basically the same functions and effects. It should be understood that there is no logical or chronological dependency between "first", "second", and "nth", nor are the quantity and execution order limited. It should also be understood that although the following description uses terms like first and second to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of various described examples, the first network device can be referred to as the second network device, and similarly, the second network device can be referred to as the first network device. The first network device and the second network device can both be network devices, and in some cases, they can be separate and different network devices.

[0292] It should also be understood that in various embodiments of this application, the magnitude of the sequence numbers of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of this application.

[0293] In this application, the meaning of the term "at least one" refers to one or more, and the meaning of the term "multiple" refers to two or more. For example, multiple second messages refer to two or more second messages. In this article, the terms "system" and "network" are often used interchangeably.

[0294] It should be understood that the terms used in the description of various described examples in this article are only for describing specific examples and are not intended to be restrictive. As used in the description of various described examples and the appended claims, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly indicates otherwise.

[0295] It should also be understood that the term "comprising" (also referred to as "includes", "including", "comprises" and / or "comprising") when used in this specification specifies the presence of the stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0296] It should also be understood that the terms "if" and "when" can be interpreted to mean "when" ("when" or "upon") or "in response to determining" or "in response to detecting". Similarly, depending on the context, the phrases "if determined..." or "if [stated condition or event] is detected" can be interpreted to mean "when determining..." or "in response to determining..." or "when [stated condition or event] is detected" or "in response to detecting [stated condition or event]".

[0297] It should be understood that determining B based on A does not mean determining B solely based on A, and B can also be determined based on A and / or other information.

[0298] It should also be understood that the "one embodiment", "an embodiment", "a possible implementation" mentioned throughout the specification mean that the specific features, structures or characteristics related to the embodiment or implementation are included in at least one embodiment of this application. Therefore, the "in one embodiment" or "in an embodiment", "a possible implementation" that appear throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner.

Claims

1. A method for data transmission, characterized in that, The method includes: The first module obtains first data sent by the second module. The first data is data that is encoded using a first forward error correction (FEC) code type and has undergone first processing. The first processing includes first outer code interleaving processing. The first module and the second module communicate through an Attachment Unit Interface (AUI). The first module is a chip in an optical module, and the second module is a Physical Layer (PHY) chip. The first module performs third processing on the first data to obtain encoded data. Among them, the third processing includes second outer code interleaving processing and inner code encoding processing. The second outer code interleaving processing includes convolutional interleaving, and the inner code encoding processing is an encoding processing implemented according to a second FEC code type. The first module performs second processing on the encoded data to obtain second data. The first module transmits the second data.

2. The method according to claim 1, characterized in that The second processing includes inserting at least one of a training sequence and pilot symbols.

3. The method according to claim 1, characterized in that, The second processing includes grouping the encoded data according to symbols required for modulation.

4. The method according to claim 1, wherein The inner code encoding processing is implemented by a plurality of inner code encoders. The encoded data includes multiple paths of data, and the multiple paths of data correspond one-to-one with the plurality of inner code encoders.

5. The method according to any one of claims 1-4, characterized in that, At least one of the first processing and the second processing further includes inserting data for adjusting the frequency point.

6. The method according to any one of claims 1-4, characterized in that The second FEC code type is a Bose–Chaudhuri–Hocquenghem (BCH) code.

7. The method according to any one of claims 1-4, characterized in that, The first module obtaining the first data sent by the second module includes: The first module receives a plurality of first sub-data sent by the second module. The first data includes the plurality of first sub-data, and the plurality of first sub-data are data that are encoded using a first FEC code type and have undergone Physical Medium Attachment (PMA) distribution.

8. The method according to claim 7, wherein The first module obtaining the first data sent by the second module includes: The first module receives the plurality of first sub-data sent by the second module through a plurality of channels of the AUI.

9. The method according to any one of claims 1 to 4, characterized in that, The third processing further includes de-skew processing.

10. The method according to any one of claims 1-4, characterized in that, The third processing further includes Alignment Mark (AM) lock processing.

11. The method according to any one of claims 1 to 4, characterized in that The first FEC code type is used for outer code encoding in concatenated encoding, and the second FEC code type is used for inner code encoding in concatenated encoding.

12. The method according to claim 1, characterized in that, Convolutional interleaving includes: Polling and distributing the first data in units of p bits into a plurality of registers with different lengths of delay. The data blocks from the registers that have undergone unequal delays converge into the same data stream to form an interleaved bit stream. There is one register among the registers that does not delay the bit stream.

13. A device for data transmission, characterized in that, The device for data transmission is used to execute the method according to any one of claims 1-12.

14. The device according to claim 13, characterized in that, The device for data transmission includes an optical module.

15. A data transmission system, characterized in that, The data transmission system includes a first module and a second module. The first module is used to execute the method according to any one of claims 1-12, and the second module is used to send first data to the first module.

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