A multi-buffer graphics display method, system, medium, program product and device

Abstract

The present application provides a multi-buffer graphics display method, system, medium, program product and device. By setting a number of offline buffers, namely the buffers managed by the four queues of busy queue, shadow queue, ready queue and idle queue, and calling the aforementioned offline buffers through registers, the close sequential association between graphics drawing and graphics display is untied, so that the graphics engine can continuously draw, and the LCD display hardware can generate an interrupt when a vertical synchronization event occurs, so as to display the drawn graphics in sequence. In addition, the present invention uses offline buffers for graphics drawing and graphics display, omitting the process of copying the data of the offline buffer to the online buffer for display, thereby reducing the occupation of the CPU and data bus bandwidth.

Description

Technical Field

[0001] The present application relates to the field of image display technology, and in particular to a multi-buffer graphics display method, system, medium, program product and device. Background Art

[0002] The LCD display system is a technology used to display graphics and text. It is widely used in various devices, including computer monitors, televisions, mobile phones, and instrument panels. Many high-performance MCU chips also have LCD display subsystem hardware.

[0003] The working principle of the existing LCD display system is as follows: the graphics library or user interface (UI) library first draws graphics in the offline buffer in the memory. When the graphics are drawn, the system copies the graphics from the offline buffer to the online buffer. The LCD display system hardware then reads the graphics data from the online buffer for display. In order to avoid the "image tearing" phenomenon, this process needs to be completed in a short time window after the vertical synchronization (Vsync) event occurs and before the display system starts scanning from the top of the screen in a new refresh cycle. Due to the large amount of graphics data, the data copying process of copying the graphics from the offline buffer to the online buffer will occupy a large amount of CPU and data bus bandwidth. In addition, the graphics engine can only start drawing the next frame of graphics after it completes the drawing of a frame of graphics and copies it from the offline buffer to the online buffer. This operation sequence leads to relatively low efficiency in graphics drawing, because the graphics drawing process must wait for the data copy to be completed before it can start, which in turn affects the overall drawing speed and response time of the system. Summary of the invention

[0004] In view of the shortcomings of the prior art described above, the purpose of the present application is to provide a multi-buffer graphics display method, system, medium, program product and device, which are used to solve the problems in the prior art that the CPU and data bus bandwidth occupied by the LCD display system when drawing graphics is too large and the drawing efficiency is low.

[0005] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides a multi-buffer graphics display method, which is applied to a processor of an LCD display system, and the steps of the method include: setting a busy queue, a shadow queue, a ready queue and an idle queue; setting an update register to indicate whether there is new data in the shadow register that needs to be displayed; a graphics engine calls an idle buffer in the idle queue to perform graphics drawing to obtain a busy buffer containing graphics data; storing the memory address of the busy buffer in the shadow queue or the ready queue; wherein the shadow queue is checked, and if the shadow queue is empty, the memory address of the busy buffer is stored in the shadow queue, and the memory address of the busy buffer is stored in the shadow register, and the value of the update register is set to indicate that there is new data that needs to be updated and displayed; if the shadow queue is not empty, the memory address of the busy buffer is stored in the ready queue; when a vertical synchronization event occurs, the value of the update register is checked, and graphics are displayed.

[0006] In one embodiment of the first aspect of the present application, the value of the update register is checked and graphical display is performed, including: setting a busy register to call data in a busy buffer in a busy queue; checking the value of the update register, and when the value of the update register indicates that there is no new data that needs to be updated and displayed, calling the busy buffer memory address stored in the busy queue corresponding to the busy register for graphical display by the LCD display system hardware.

[0007] In one embodiment of the first aspect of the present application, the value of the update register is checked and graphically displayed, including: setting a busy register for calling data in a busy buffer in a busy queue; checking the value of the update register, and when the value of the update register indicates that new data needs to be updated and displayed, storing the memory address of the busy buffer stored in the shadow queue into the busy queue; providing the busy register for graphical display after calling it from the busy queue; setting the value of the update register to indicate that there is no new data that needs to be updated and displayed; and generating an interrupt.

[0008] In an embodiment of the first aspect of the present application, generating an interrupt includes: determining whether the shadow queue is empty; if the shadow queue is empty, retaining the memory address of the busy buffer stored in the busy queue.

[0009] In an embodiment of the first aspect of the present application, the generating of the interrupt includes: determining whether the shadow queue is empty; if the shadow queue is not empty, clearing the data of the busy buffer stored in the busy queue to form an idle buffer, and storing the memory address of the cleared idle buffer into the idle queue; storing the memory address of the busy buffer of the shadow queue into the busy queue, and calling the memory address of the busy buffer in the busy queue by the busy register for graphic display by the LCD display system hardware.

[0010] In one embodiment of the first aspect of the present application, after the LCD display system hardware performs graphic display, it is checked whether the memory address of the busy buffer is stored in the ready queue; if so, the memory address of the busy buffer is stored in the shadow queue, and the memory address of the busy buffer is stored in the shadow register, and the value of the update register is set to indicate that there is new data that needs to be updated for display.

[0011] To achieve the above-mentioned purpose and other related purposes, the second aspect of the present application provides a multi-buffer graphics display system, including: a layer control unit, which can implement any of the methods described above; a layer overlay unit, which is used to overlay the output graphics of the layer control unit; a raster processing unit, which is used to perform raster processing on the data output by the layer overlay unit; a screen physical interface unit, which is used to convert the result of the raster processing into a specific interface timing; and a system control unit, which is used to control the opening, closing and interruption functions of the LCD display system hardware.

[0012] To achieve the above-mentioned purpose and other related purposes, the third aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, and the computer program implements any of the above-mentioned methods when executed by a processor.

[0013] To achieve the above-mentioned purpose and other related purposes, the fourth aspect of the present application provides a computer program product, which includes a computer program code. When the computer program code runs on a computer, the computer implements any of the above-mentioned methods.

[0014] To achieve the above-mentioned purpose and other related purposes, the fifth aspect of the present application provides a computer device, including a memory, a processor and a computer program stored in the memory, characterized in that the processor executes the computer program to implement any of the above-mentioned methods.

[0015] As described above, the multi-buffer graphics display method, system, medium, program product and device of the present application have the following beneficial effects:

[0016] The method for implementing graphic display in LCD display system in the prior art is that after the graphics engine draws the graphics in the offline buffer, the drawn result data is sent to the online buffer for real-time call and display by the LCD display system hardware. In order to avoid the "image tearing" phenomenon, the graphics data needs to be copied from the offline buffer to the online buffer when the vertical synchronization event occurs. Since the amount of graphics data is large, copying in such a short time often takes up a lot of CPU and data bus bandwidth, and the graphics engine needs to complete the copy before starting to draw the next frame of graphics, so its drawing efficiency is low.

[0017] The present invention sets several offline buffers, namely, buffers managed by four queues, namely, busy queue, shadow queue, ready queue and idle queue, and calls the aforementioned offline buffers through registers to untie the close sequential association between graphics drawing and graphics display, so that the graphics engine can continuously draw graphics, and the LCD display hardware can generate an interrupt when a vertical synchronization event occurs, so as to display the drawn graphics in sequence. In addition, the present invention uses offline buffers for graphics drawing and graphics display, omitting the process of copying data from the offline buffer to the online buffer for display, thereby reducing the occupation of CPU and data bus bandwidth.

[0018] Specifically, the present invention is divided into four implementation steps: basic information setting, graphics drawing, moving into the queue to be displayed and graphics display. The process of queue setting is to set the busy queue, shadow queue, ready queue and idle queue; set the update register to indicate whether there is new data in the shadow register that needs to be displayed; wherein, the value of the update register is 1, indicating that there is new data that needs to be updated and displayed, and the value of the update register is 0, indicating that there is no new data that needs to be updated and displayed. The process of graphics drawing is that the graphics engine calls the idle buffer in the idle queue to perform graphics drawing to obtain a busy buffer containing graphics data. The process of moving into the queue to be displayed is to store the memory address of the busy buffer in the shadow queue or the ready queue; wherein, the shadow queue is checked, if the shadow queue is empty, the memory address of the busy buffer is stored in the shadow queue, and the memory address of the busy buffer is stored in the shadow register, and the value of the update register is set to 1; if the shadow queue is not empty, the memory address of the busy buffer is stored in the ready queue. The process of display is to check the value of the update register when a vertical synchronization event occurs, and perform graphics display. The graphics drawing engine can continuously draw a large amount of graphics data in the graphics drawing process, and save it in the shadow queue to be displayed or the ready queue for the LCD display hardware to call. The LCD display hardware displays through interrupts when certain display conditions are met. For example, in order to avoid the "image tearing" phenomenon, it displays when the vertical synchronization event occurs. On the one hand, it does not need to occupy the CPU and data bus bandwidth; on the other hand, it enables the graphics drawing engine to continue to draw graphics, improving the drawing efficiency; and interrupts and displays when the vertical synchronization event occurs, avoiding the "image tearing" phenomenon. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Shown is a schematic diagram of the framework of a multi-buffer graphics display system of the present application.

[0020] Figure 2 Shown is a timing diagram of a multi-buffer graphics display method of the present application.

[0021] Figure 3 The workflow of a multi-buffer graphics display method of this application is shown as follows: Figure 1 .

[0022] Figure 4 The workflow of a multi-buffer graphics display method of this application is shown as follows: Figure 2 .

[0023] Figure 5 The workflow of a multi-buffer graphics display method of this application is shown as follows: Figure 3 .

[0024] Figure 6aThe display is a functional demonstration diagram of a multi-buffer graphics display method of the present application. Figure 1 .

[0025] Figure 6b The display is a functional demonstration diagram of a multi-buffer graphics display method of the present application. Figure 2 .

[0026] Figure 7 Shown is a schematic diagram of the framework of a multi-buffer graphics display computer device of the present application. DETAILED DESCRIPTION

[0027] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0028] A first aspect of the present application provides a multi-buffer graphics display method, which is applied to a processor of an LCD display system. The method comprises the following steps:

[0029] S1: Set up busy queue, shadow queue, ready queue, and idle queue.

[0030] The busy queue is used to store the memory address of the busy buffer being called by the LCD display hardware; the shadow queue is used to store the memory address of the busy buffer to be displayed; the ready queue is also used to store the memory address of the busy buffer to be displayed; the data stored in the shadow queue is displayed in priority to the ready queue; the idle queue is used to store the memory address of the idle buffer. There is one busy queue and one shadow queue, and several ready queues can be set according to the speed of graphics drawing, and several idle queues can also be set.

[0031] S2: Set the update register to indicate whether there is new data in the shadow register that needs to be displayed.

[0032] In one embodiment, the value of the update register may be set to 1 to indicate that there is new data that needs to be updated for display, and the value of the update register may be set to 0 to indicate that there is no new data that needs to be updated for display.

[0033] Set up a shadow register and an update register. The shadow register is used to store the memory address pointing to the buffer to be displayed. This address points to the image data to be displayed in the next frame, rather than the current frame image data being called by the LCD hardware. The shadow register itself does not determine whether the data stored in it is empty, but its state will reflect whether there is new data to be displayed. The main function of the update register is to indicate whether there is new data to be displayed in the shadow register. It is usually expressed in the form of a Boolean value: a value of 0 indicates that there is no new data, and a value not 0 (which can be set to 1 in some embodiments of the present invention) indicates that there is new data that needs to be updated.

[0034] S3: The graphics engine calls the free buffer in the free queue to obtain the busy buffer containing the graphics data for graphics drawing.

[0035] like Figure 4 As shown, the graphics engine first obtains an idle buffer in the idle queue, and after successful acquisition, graphics are drawn in the idle buffer; if the acquisition is unsuccessful, it continues to wait for an idle buffer to appear in the idle queue. After the graphics engine draws graphics on the idle buffer, a busy buffer is obtained.

[0036] It should be understood that the free buffer means that there is no image data in use, or the previous graphics display task has been completed and is ready to accept new graphics data. In other words, the free buffer is a buffer that is not currently occupied. The busy buffer means that the graphics data in the buffer is waiting to be displayed or is being displayed, which means that this buffer cannot be overwritten by other graphics data until the current display task is completed. When the graphics are drawn, the buffer already contains complete image data. At this time, the state of the free buffer changes, and the state of the buffer changes from "free" to "busy", so it is transformed into a busy buffer.

[0037] S4: Storing the memory address of the busy buffer in the shadow queue or the ready queue; wherein, checking the shadow queue, if the shadow queue is empty, storing the memory address of the busy buffer in the shadow queue, storing the memory address of the busy buffer in the shadow register, and setting the value of the update register to indicate that there is new data that needs to be updated and displayed (in some embodiments, the value of the update register can be set to 1); if the shadow queue is not empty, storing the memory address of the busy buffer in the ready queue.

[0038] like Figure 4As shown, after the graphics engine draws graphics on the free buffer, the state of the shadow queue is judged. If the shadow queue is empty, the memory address of the busy buffer storing the graphics data is added to the shadow queue; if the shadow queue is not empty, the memory address of the busy buffer is added to the ready queue. The graphics data corresponding to the memory address of the busy buffer stored in the shadow queue is the next frame of image, and the graphics data corresponding to the memory address of the busy buffer stored in the ready queue is the subsequent image of the next frame of image.

[0039] After the busy buffer is added to the shadow queue (i.e., the memory address of the busy buffer is stored in the shadow queue), the shadow register of the LCD hardware display module is synchronously stored in the memory address of the busy buffer in the shadow queue. After the shadow queue stores the aforementioned memory address, the value of the update register is correspondingly set to 1, that is, there is new image data to be displayed and updated in the shadow register.

[0040] S5: When a vertical synchronization event occurs, the value of the update register is checked and the graphics are displayed.

[0041] like Figure 2 As shown, Vsync is the vertical synchronization period, which refers to the time period after each frame is displayed, when the display returns from the last line to the first line to prepare for the next frame display. During this period, no image content is usually displayed, and it is mainly used to synchronize the display signal. VBP is the vertical blanking period, which is the period from the end of Vsync to the actual display of the next frame of image. During this period, the display is preparing to move from the bottom to the top of a frame of image. VBP is usually used to provide the display controller with some extra time to handle other tasks to avoid conflicts with display scanning. Pixel is the pixel display period, which refers to the period of time when a frame of image is actually drawn on the screen. During this period, the display scans and displays image data line by line, that is, the main process of displaying a frame of image. VBF is the vertical front porch period, which is the period from the end of a frame of image to the start of Vsync. During this period, the display still displays the last row of pixels, but has not yet entered the vertical synchronization period. VBF is also used to provide synchronization adjustment of the display system to ensure the display preparation of the next frame.

[0042] It should be understood that the vertical synchronization event refers to a specific time point in the display refresh process, which is used to ensure that a new frame of image data can be displayed from beginning to end when the display starts to display, avoiding image tearing. In an LCD display system, the display usually refreshes the screen content at a fixed frequency, scanning from the top of the screen to the bottom of the screen line by line. Each refresh will display a complete frame of the image. If the image data changes during the process of the display scanning and displaying a frame of the image, it may cause the upper and lower parts of the screen to display unsynchronized image content. This phenomenon is called "image tearing". In order to avoid image tearing, the display system synchronizes the image data displayed on the screen with the refresh of the display when a vertical synchronization (Vsync) event occurs. The Vsync event usually occurs after the display has just completed the display of a frame and before it is ready to start displaying the next frame. When the Vsync event occurs, the system will check whether there is new image data to be displayed. If so, the new image will be displayed in the next refresh cycle; if not, the current frame will continue to be displayed. This ensures that each frame of the image is consistent from beginning to end, and there will be no image tearing.

[0043] Step S5 can be decomposed into two sub-steps, S51 and S52.

[0044] S51: Set a busy register to call the data in the busy buffer in the busy queue; check the value of the update register, and when the value of the update register indicates that there is no new data that needs to be updated and displayed (in some embodiments, the value of the update register can be set to 0), call the busy buffer memory address stored in the busy queue corresponding to the busy register for graphic display by the LCD display system hardware.

[0045] S52: Setting a busy register to call the data in the busy buffer in the busy queue; checking the value of the update register, and when the value of the update register indicates that new data needs to be updated and displayed (in some embodiments, the value of the update register can be set to 1), storing the memory address of the busy buffer stored in the shadow queue into the busy queue; for the busy register to be called from the busy queue for graphical display; setting the value of the update register to indicate that there is no new data that needs to be updated and displayed (in some embodiments, the value of the update register can be set to 0); generating an interrupt.

[0046] like Figure 3As shown, when a vertical synchronization event occurs, the value of the update register is checked. If the value of the update register is 0, it indicates that the shadow register does not store the memory address of the busy buffer corresponding to the next frame of graphics display. Therefore, the shadow register retrieves the memory address of the busy buffer stored in the shadow queue that stores the next frame of graphics information from its corresponding shadow queue. After the shadow register stores the memory address of the busy buffer for displaying the next frame of graphics, the corresponding update register value is set to 1, indicating that the shadow register has stored the memory address of the busy buffer corresponding to the next frame of graphics display. At this time, the system generates an interrupt and displays the next frame of graphics.

[0047] When a vertical synchronization event occurs, the value of the update register is checked. If the value of the update register is 1, it means that the memory address of the busy buffer with the next frame of graphics information has been stored in the shadow register. Therefore, the system directly generates an interrupt at this time to display the next frame of graphics.

[0048] It should be understood that the busy register calls the memory address of the busy buffer stored in the busy queue to obtain the graphics information of the current frame and display the graphics of the current frame. After the graphics display of the current frame is completed, the memory address of the busy buffer stored in the shadow queue is moved to the busy queue, and the busy register calls the memory address of the busy buffer in the busy queue to display the graphics of the next frame.

[0049] S52 can be decomposed into two sub-steps, S521 and S522.

[0050] S521: The generating of the interruption includes: determining whether the shadow queue is empty; if the shadow queue is empty, retaining the memory address of the busy buffer stored in the busy queue.

[0051] The specific process of system interruption is as follows Figure 5 As shown, after the interruption starts, it is first determined whether the shadow queue is empty. If the shadow queue is empty, the memory address of the busy buffer stored in the busy queue is retained, that is, the graphics of the current frame are still displayed, and the next frame of graphics is not displayed.

[0052] S522: generating an interruption includes:

[0053] S522a: Determine whether the shadow queue is empty.

[0054] S522b: If the shadow queue is not empty, clear the data in the busy buffer stored in the busy queue to form an idle buffer, and store the memory address of the cleared idle buffer in the idle queue.

[0055] S522c: Storing the memory address of the busy buffer of the shadow queue into the busy queue, and calling the memory address of the busy buffer in the busy queue by the busy register, so as to provide graphics display for the LCD display system hardware.

[0056] S522d: Check whether the memory address of the busy buffer is stored in the ready queue; if so, store the memory address of the busy buffer in the shadow queue, and store the memory address of the busy buffer in the shadow register, and set the value of the update register to indicate that there is new data that needs to be updated and displayed (in some embodiments, the value of the update register can be set to 1).

[0057] like Figure 5 As shown, after the interruption starts, first determine whether the shadow queue is empty. If the shadow queue is empty, determine whether the busy queue is empty. When the busy queue is not empty, the graphics data in the busy buffer stored in the busy queue needs to be cleared. After the clearing is completed, the busy buffer becomes an idle buffer again. At this time, the idle buffer is added back to the idle queue and the program waiting for the idle queue is notified.

[0058] When the shadow queue is empty but the busy queue is not empty, there is no need to move the buffer in the busy independent to the free queue. Therefore, the memory address of the busy buffer obtained in the shadow queue is directly stored in the busy queue.

[0059] Next, the busy buffer corresponding to the next frame of image data of the image corresponding to the busy buffer in the current busy queue is obtained from the ready queue. If the acquisition is successful, the memory address corresponding to the busy buffer in the ready queue is added to the shadow queue, and the shadow register and the update register are updated synchronously. It should be understood that the synchronous update of the shadow register and the update register means that after the memory address change of the busy buffer in the shadow queue is completed, the memory address of the busy buffer newly stored in the shadow queue is re-stored in the shadow register, and the value indicating the shadow register is correspondingly set to indicate that there is new data that needs to be updated for display (in some embodiments, the value of the update register can be modified to 1).

[0060] When the busy buffer corresponding to the next frame of image data of the image corresponding to the busy buffer in the current busy queue is obtained from the ready queue and the acquisition fails, the interruption process is directly terminated.

[0061] Figure 6a and Figure 6b What is shown is a functional demonstration diagram of a multi-buffer graphics display method of the present application. It should be understood that Figure 6a and Figure 6bThe PTR in is a pointer to a buffer, which is used to reference the location of the graphics data in memory so that the display system can access and process the data through the pointer. It is used to represent the buffer in the figure. NXT refers to the next frame. Therefore, in Figure 6a and Figure 6b In the , NXT and PTR together refer to the buffer where the next frame of image is stored.

[0062] like Figure 6a As shown, Figure 6a The top figure shows that the graphics engine first draws graphics in the idle queue and draws four busy buffers for subsequent frame graphics display, thus forming a state in which there are four busy buffers in the idle queue.

[0063] Figure 6a The middle figure shows the situation when the shadow queue is empty after drawing is completed. At this time, one of the busy buffers (the first buffer) that has been drawn is directly added to the shadow queue for the busy queue (BUSY) to call (this process is not shown). After the busy queue calls a busy buffer (the first buffer) in the shadow queue, it is determined that the shadow queue is empty again, and the busy buffer (the second buffer) in the idle queue is added to the shadow queue again, thus forming a state where there are two busy buffers in the idle queue, one busy buffer in the shadow queue, and one busy buffer in the busy queue.

[0064] Figure 6a The bottom figure shows that after the first busy buffer is called by the busy queue, the graphics data in it is cleared and added back to the idle queue to continue drawing the next frame of graphics; and the second busy buffer is added from the shadow queue to the busy queue for graphics display, thus forming a state in which there are three busy buffers in the idle queue and one busy buffer in the busy queue.

[0065] like Figure 6b As shown in the top figure, the graphics engine first draws graphics in the idle queue and draws three busy buffers for subsequent frame graphics display, but at this time there is already a busy buffer in the shadow queue, that is, the shadow queue is not empty. As a result, there are three busy buffers in the idle queue and one busy buffer in the shadow queue.

[0066] Figure 6b The middle diagram shows that when the shadow queue is not empty, the system moves the two busy buffers from the idle queue directly into the ready queue (rather than Figure 6aThus, there is one busy buffer in the idle queue, two busy buffers in the ready queue, and one busy buffer in the shadow queue.

[0067] Figure 6b The figure below shows that after the original busy buffer in the shadow queue is added to the busy queue, if the ready queue is not empty, a busy buffer is immediately taken out of the ready queue and added to the shadow queue; at the same time, the busy buffer of the free buffer is also added to the ready queue, thus forming a state in which there are two busy buffers in the ready queue, one busy buffer in the shadow queue, and one busy buffer in the busy queue.

[0068] It should be understood that when the busy buffer in the shadow queue is just added to the busy queue and the shadow queue is temporarily empty, there is no situation where the graphics engine determines that the shadow queue is empty and fills the busy buffer in the idle queue into the shadow queue. This is because steps S3, S4 and S5 are performed separately. Steps S3 and S4 belong to the graphics drawing link and will not be interrupted when the graphics are being drawn. Step S5 belongs to the graphics display link and is performed in the interrupt. When the interrupt is performed, it cannot be interrupted by the graphics drawing engine. Figure 1 As shown, the second aspect of the present invention provides a multi-buffer graphics display system, including: a layer control unit, which can implement any of the above methods; a layer overlay unit, which is used to overlay the output graphics of the layer control unit; a raster processing unit, which is used to perform raster processing on the data output by the layer overlay unit; a screen physical interface unit, which is used to convert the result of raster processing into a specific interface timing; and a system control unit, which is used to control the opening, closing and interruption functions of the LCD display system hardware.

[0069] It should be understood that the graphics stack is the overall structure of graphics processing components and technologies in a system from the bottom-level hardware to the high-level applications. It consists of multiple layers of hardware and software modules, each layer is responsible for different graphics processing tasks, and together supports the generation, processing and display of visual content such as images, videos, and UI.

[0070] The software module of the graphics stack includes two links: hardware function control and display queue processing. The hardware function control refers to the functional control of the hardware through software reading and writing registers. The hardware function control part involves the read and write operations of registers through software to achieve precise control of various hardware functions of the LCD display system. Specifically, these registers include shadow registers, busy registers, update registers, etc. By operating these registers, the software can control various details of the image display, such as layer switching, updating of display content, processing of vertical synchronization (Vsync) signals, etc. In addition, hardware function control also includes timing configuration, brightness adjustment, color calibration, etc. of the LCD controller, and these operations are usually implemented by writing instructions to specific registers or hardware interfaces. The display queue processing refers to a multi-buffer graphics display method described in the first aspect of the present application.

[0071] The hardware modules of the graphics stack include a layer control unit, a layer overlay unit, a raster processing unit, a screen physical interface unit, and a system control unit. The layer control unit is the core part of the entire system responsible for graphics drawing and management. It implements the functions of the multi-buffer graphics display method to ensure that the image is drawn and displayed efficiently and orderly. In a multi-buffer system, the layer control unit draws graphics in different buffers as needed and organizes these buffers into queues for display at the right time. By managing the allocation and use of buffers, it can avoid display problems such as image tearing and improve the display efficiency of the system. The layer overlay unit is responsible for overlaying the graphics data from the layer control unit. Different layers may contain different images or visual elements, and the layer overlay unit combines these images according to predetermined rules to finally generate a comprehensive display result. The layer overlay unit usually also processes the transparency (Alpha channel) of the layer to determine the display priority and transparency effect of each layer when it is overlaid. For example, if a layer is semi-transparent, it will be partially mixed with other layers to generate the final image. The raster processing unit converts the overlaid image data into a pixel-by-pixel display signal. This step converts the image data from a logical graphic to a signal that can be directly used by the display. The raster processing unit generates the color value of each pixel line by line according to the scanning order of the image (usually from top to bottom and from left to right), and converts these data into display signals. This process requires strict timing control to ensure that the image can be displayed correctly. The screen physical interface unit is responsible for converting the data after raster processing into physical signals that the display can understand. Different displays may use different interface standards (such as LVDS, HDMI, VGA, etc.), and the screen physical interface unit will generate corresponding timing signals according to these standards. The interface timing includes vertical synchronization (Vsync), horizontal synchronization (Hsync), data enable (DE) and other signals, which control key operations such as when the display starts to display the image and when to refresh the screen. The system control unit is the central management part of the entire LCD display system, responsible for controlling the operating status of the LCD hardware. It can turn on or off the LCD display system and handle various interrupt requests, such as vertical synchronization interrupt, update interrupt, etc. When the LCD display system needs to respond to external events or internal state changes (such as image refresh, display power management, etc.), the system control unit will respond in time through the interrupt mechanism to ensure the normal operation of the system.

[0072] A third aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer-readable storage medium stores a program code, and when the program code is run on a computer, the computer executes Figure 3 To the method of any one of the embodiments shown in Figure 6.

[0073] A fourth aspect of the present application provides a computer program product, the computer program product comprising: a computer program code, when the computer program code is run on a computer, the computer executes Figure 3 To the method of any one of the embodiments shown in Figure 6.

[0074] like Figure 7 As shown, the fifth aspect of the present application provides a computer device, including a memory, a processor and a computer program stored in the memory, characterized in that the processor executes the computer program to implement any of the above methods. The computer device includes: at least one processor 701, a memory 702, at least one network interface 703 and a user interface 705. The various components in the device are coupled together through a bus system 704. It can be understood that the bus system 704 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 704 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, in Figure 7 In the specification, various buses are labeled as bus systems.

[0075] The user interface 705 may include a display, a keyboard, a mouse, a trackball, a click gun, keys, buttons, a touch pad or a touch screen.

[0076] It is understood that the memory 702 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), which is used as an external cache. By way of exemplary but not limiting explanation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM). The memory described in the embodiments of the present invention is intended to include but is not limited to these and any other suitable categories of memory.

[0077] The memory 702 in the embodiment of the present invention is used to store various types of data to support the operation of the electronic terminal 700. Examples of these data include: any executable program used to operate on the electronic terminal 700, such as an operating system 7021 and an application 7022; the operating system 7021 includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application 7022 can include various applications, such as a media player (Media Player), a browser (Browser), etc., for implementing various application services. The method provided by the embodiment of the present invention can be included in the application 7022.

[0078] The method disclosed in the above embodiment of the present invention can be applied to the processor 701, or implemented by the processor 701. The processor 701 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit in the processor 701 or the instruction in the form of software. The above processor 701 may be a general processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 701 can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiment of the present invention. The general processor 701 may be a microprocessor or any conventional processor, etc. In combination with the steps of the accessory optimization method provided in the embodiment of the present invention, it can be directly embodied as a hardware decoding processor to execute, or it can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, which is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0079] In an exemplary embodiment, the electronic terminal 700 may be implemented by one or more application specific integrated circuits (ASIC), DSP, programmable logic device (PLD), complex programmable logic device (CPLD) to execute the aforementioned method.

[0080] It should be noted that in the embodiments of the present application, words such as "exemplary" or "for example" represent examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0081] In the embodiments of the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, ab, ac, bc or abc, where a, b, c can be single or multiple.

[0082] It should be understood that the division of modules in the embodiments of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation. In addition, each functional module in each embodiment of the present application may be integrated into a processor, or may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated modules may be implemented in the form of hardware or in the form of software functional modules.

[0083] The terms "component", "module", "system", etc. used in this specification are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program and / or a computer. By way of illustration, both applications running on a computing device and a computing device can be components. One or more components may reside in a process and / or an execution thread, and a component may be located on a computer and / or distributed between two or more computers. In addition, these components may be executed from various computer-readable media having various data structures stored thereon. Components may, for example, communicate through local and / or remote processes according to signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system and / or a network, such as the Internet interacting with other systems through signals).

[0084] Those of ordinary skill in the art will appreciate that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or in a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0085] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0086] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0087] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0088] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0089] In the above embodiments, the functions of each functional unit can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When loading and executing computer program instructions (programs) on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. Computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more available media integrations. Available media may be magnetic media (e.g., floppy disks, hard disks, tapes), optical media (e.g., high-density digital video discs (DVDs), or semiconductor media (e.g., solid state disks (SSDs), etc.).

[0090] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0091] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0092] In summary, the multi-buffer graphics display method, system, medium, program product and device provided by the present application effectively overcome the defects of the prior art that graphics display requires a large amount of CPU and data bus bandwidth and the efficiency of graphics drawing is relatively low, and has high industrial utilization value.

[0093] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A multi-buffer graphics display method, characterized in that: A processor applied to an LCD display system, wherein the steps of the method include: Set up busy queues, shadow queues, ready queues, and idle queues; Set the update register to indicate whether there is new data in the shadow register that needs to be displayed; The graphics engine calls the free buffer in the free queue to perform graphics drawing to obtain the busy buffer containing the graphics data; The memory address of the busy buffer is stored in the shadow queue or the ready queue; wherein the shadow queue is checked, and if the shadow queue is empty, the memory address of the busy buffer is stored in the shadow queue, and the memory address of the busy buffer is stored in the shadow register, and the value of the update register is set to indicate that there is new data that needs to be updated and displayed; if the shadow queue is not empty, the memory address of the busy buffer is stored in the ready queue; When a vertical sync event occurs, the value of the update register is checked and the graphics are displayed.

2. A multi-buffer graphics display method according to claim 1, characterized in that: Check and update register values ​​and display them graphically, including: Set the busy register to call the data in the busy buffer in the busy queue; Check the value of the update register. When the value of the update register indicates that there is no new data to be updated, call the busy buffer memory address stored in the busy queue corresponding to the busy register for LCD display system hardware to display graphics.

3. A multi-buffer graphics display method according to claim 1, characterized in that: Check and update register values ​​and display them graphically, including: Set the busy register to call the data in the busy buffer in the busy queue; checking the value of the update register, and when the value of the update register indicates that new data needs to be updated for display, storing the memory address of the busy buffer stored in the shadow queue into the busy queue for the busy register to call from the busy queue for graphic display; Setting the value of the update register to indicate that there is no new data to update the display; Generate an interrupt.

4. A multi-buffer graphics display method according to claim 3, characterized in that: The generating interruption comprises: Determine whether the shadow queue is empty. If the shadow queue is empty, retain the memory address of the busy buffer stored in the busy queue.

5. A multi-buffer graphics display method according to claim 3, characterized in that: The generating interruption comprises: Determine whether the shadow queue is empty; If the shadow queue is not empty, the data in the busy buffer stored in the busy queue is cleared to form an idle buffer, and the memory address of the cleared idle buffer is stored in the idle queue; the memory address of the busy buffer of the shadow queue is stored in the busy queue, and the busy register calls the memory address of the busy buffer in the busy queue for the LCD display system hardware to display graphics.

6. A multi-buffer graphics display method according to claim 5, characterized in that: After the LCD display system hardware performs graphic display, check whether the memory address of the busy buffer is stored in the ready queue; if so, store the memory address of the busy buffer in the shadow queue, store the memory address of the busy buffer in the shadow register, and set the value of the update register to indicate that new data needs to be updated for display.

7. A multi-buffer graphics display system, characterized in that: include: A layer control unit, wherein the layer control unit can implement the method described in any one of claims 1 to 6; A layer overlay unit, used to overlay the output graphics of the layer control unit; A raster processing unit, used for performing raster processing on the data output by the layer overlay unit; Screen physical interface unit, used to convert the result of raster processing into specific interface timing; The system control unit is used to control the opening, closing and interruption functions of the LCD display system hardware.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

9. A computer program product, characterized in that The computer program product includes a computer program code, and when the computer program code is executed on a computer, the computer is enabled to implement the method as described in any one of claims 1 to 6.

10. A computer device comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the method according to any one of claims 1 to 6.

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