Power Module Junction Temperature Estimation Method, Thermal Network Model Construction Method, Device, Equipment and Storage Medium

Abstract

The present application relates to a method for estimating the junction temperature of a power module, a method for constructing a thermal network model, a device, a computer device, a computer-readable storage medium, and a computer program product. The method includes: obtaining the power loss of a power semiconductor module and the real-time ambient temperature of the environment where the power semiconductor module is located; the power semiconductor module includes a plurality of chips; inputting the power loss and the real-time ambient temperature into a pre-constructed thermal network model, and predicting the temperature change parameters of the power semiconductor module through the thermal network model; wherein, the thermal network model is constructed according to first thermal network parameters and second thermal network parameters, and the first thermal network parameters are used to describe the thermal behavior of each chip inside the power semiconductor module; the second thermal network parameters are used to describe the coupled thermal behavior and heat dissipation behavior among multiple chips in the power semiconductor module. By using this method, the accuracy of junction temperature prediction of the power semiconductor module can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of junction temperature measurement of power semiconductor modules, and particularly to a method for estimating the junction temperature of a power module, a method for constructing a thermal network model, a device, a computer device, a computer-readable storage medium, and a computer program product. Background Art

[0002] Power semiconductor modules have been widely applied to various fields, such as new energy vehicles, wind power generation, inverters, photovoltaic solar energy systems, etc. As a core device in power electronic systems, the reliability of power semiconductor modules is particularly important. According to industrial usage and relevant reports, thermal cycling stress is the main cause of aging and failure of power semiconductor modules. In some extreme environments, such as in space or under the sea, overheating of power semiconductor modules will accelerate aging and failure. Therefore, accurately predicting their thermal behavior is extremely important.

[0003] However, with the increase in the power density of power semiconductor modules, the increase in the number of chips leads to complex heat dissipation paths, more complex thermal coupling between chips, and more complex dynamic changes in thermal behavior under complex external environments and frequent changes in working conditions. Existing junction temperature estimation methods cannot handle complex scenarios of multi-chip coupling and are difficult to accurately predict the junction temperature of power semiconductor modules. Summary of the Invention

[0004] Based on this, in view of the above technical problems, it is necessary to provide a method for estimating the junction temperature of a power module, a method for constructing a thermal network model, a device, a computer device, a computer-readable storage medium, and a computer program product that can improve the accuracy of predicting the junction temperature of a power semiconductor module.

[0005] In a first aspect, the present application provides a method for estimating the junction temperature of a power module, and the method includes:

[0006] Obtain the power loss of the power semiconductor module and the real-time ambient temperature of the environment where the power semiconductor module is located; the power semiconductor module includes multiple chips;

[0007] Input the power loss and the real-time ambient temperature into a pre-constructed thermal network model, and predict the temperature change parameters of the power semiconductor module through the thermal network model;

[0008] Wherein, the thermal network model is constructed according to first thermal network parameters and second thermal network parameters, and the first thermal network parameters are used to describe the thermal behavior of each chip inside the power semiconductor module; the second thermal network parameters are used to describe the coupled thermal behavior and heat dissipation behavior between multiple chips in the power semiconductor module.

[0009] In one embodiment, predicting the temperature change parameters of the power semiconductor module through the thermal network model includes:

[0010] Determine the circuit structure of the thermal network model, where the circuit structure includes a current source, a voltage source, and a thermal impedance;

[0011] Set the value of the current source according to the power loss, set the value of the voltage source according to the real-time ambient temperature, and set the value of the thermal impedance according to the first thermal network parameter and the second thermal network parameter;

[0012] Determine the voltage change parameter of a preset circuit node in the circuit structure according to the value of the current source, the value of the voltage source, and the value of the thermal impedance, and use the voltage change parameter as the temperature change parameter of the corresponding chip in the power semiconductor module.

[0013] In one embodiment, the construction process of the thermal network model includes:

[0014] Construct a finite element model of the power semiconductor module according to the size information of the power semiconductor module;

[0015] Apply a preset thermal power to each chip of the finite element model, and extract the first thermal network parameter and the second thermal network parameter of the finite element model; the preset thermal power is determined according to the power loss and the real-time ambient temperature;

[0016] Construct a thermal network model according to the first thermal network parameter and the second thermal network parameter.

[0017] In one embodiment, the power semiconductor module includes multiple structural layers, the first thermal network parameter includes the thermal resistance and heat capacity of each structural layer, and extracting the first thermal network parameter of the finite element model includes:

[0018] Obtain the temperature of each structural layer when the finite element model reaches a steady state under the preset thermal power, and determine the thermal resistance of each structural layer according to the temperature of each structural layer;

[0019] Obtain the equivalent heat conduction area of each structural layer, and determine the heat capacity of each structural layer according to the equivalent heat conduction area.

[0020] In one embodiment, the second thermal network parameter includes the self-thermal impedance of the chip itself and the mutual-thermal impedance between chips, and extracting the second thermal network parameter of the finite element model includes:

[0021] For any chip in the finite element model, apply a preset thermal power to the targeted chip alone, determine the first transient thermal impedance curve of the targeted chip, and fit the first transient thermal impedance curve with a preset functional formula to obtain the self-thermal impedance of the targeted chip.

[0022] Apply a preset thermal power to other chips respectively, determine the second transient thermal impedance curve of the targeted chip under the coupling effect of other chips, and fit the second transient thermal impedance curve with a preset functional formula to obtain the mutual thermal impedance of other chips to the targeted chip respectively.

[0023] In one embodiment, the step of applying a preset thermal power to other chips respectively, determining the second transient thermal impedance curve of the targeted chip under the coupling effect of other chips, and fitting the second transient thermal impedance curve with a preset functional formula to obtain the mutual thermal impedance of other chips to the targeted chip respectively includes:

[0024] Take any one of the chips other than the targeted chip as the current chip, apply a preset thermal power to the current chip, determine the second transient thermal impedance curve of the targeted chip under the coupling effect of the current chip, and fit the second transient thermal impedance curve with a preset functional formula to obtain the mutual thermal impedance of the current chip to the targeted chip.

[0025] Take the next chip of the current chip as the current chip for the next cycle, and return to the step of applying a preset thermal power to the current chip to continue execution until the current chip is the last chip, so as to obtain the mutual thermal impedance of other chips to the targeted chip respectively.

[0026] In one embodiment, the step of constructing a thermal network model according to the first thermal network parameter and the second thermal network parameter includes:

[0027] Construct a first model according to the first thermal network parameter;

[0028] Construct a second model according to the second thermal network parameter;

[0029] Connect the first model and the second model with the preset shell temperature point in the finite element model as the connection point to obtain a thermal network model.

[0030] In a second aspect, the present application further provides a method for constructing a thermal network model, and the method includes:

[0031] Construct a finite element model of the power semiconductor module according to the size information of the power semiconductor module; the power semiconductor module includes multiple chips;

[0032] Apply a preset thermal power to each chip in the finite element model, and extract the first thermal network parameter and the second thermal network parameter of the finite element model; the preset thermal power is determined according to the power loss of the power semiconductor module and the real-time ambient temperature of the environment where it is located; the first thermal network parameter is used to describe the thermal behavior of each chip inside the power semiconductor module; the second thermal network parameter is used to describe the coupled thermal behavior and heat dissipation behavior between multiple chips in the power semiconductor module;

[0033] Construct a thermal network model according to the first thermal network parameter and the second thermal network parameter; the thermal network model is used to predict the temperature change parameter of the power semiconductor module according to the power loss of the power semiconductor module and the real-time ambient temperature of the environment where it is located.

[0034] In a third aspect, the present application also provides a device for estimating the junction temperature of a power module, and the device includes:

[0035] An acquisition module, configured to acquire the power loss of the power semiconductor module and the real-time ambient temperature of the environment where the power semiconductor module is located; the power semiconductor module includes multiple chips;

[0036] A junction temperature prediction module, configured to input the power loss and the real-time ambient temperature into a pre-constructed thermal network model, and predict the temperature change parameter of the power semiconductor module through the thermal network model; wherein, the thermal network model is constructed according to the first thermal network parameter and the second thermal network parameter, and the first thermal network parameter is used to describe the thermal behavior of each chip inside the power semiconductor module; the second thermal network parameter is used to describe the coupled thermal behavior and heat dissipation behavior between multiple chips in the power semiconductor module.

[0037] In a fourth aspect, the present application also provides a device for constructing a thermal network model, and the device includes:

[0038] A finite element construction module, configured to construct a finite element model of the power semiconductor module according to the size information of the power semiconductor module; the power semiconductor module includes multiple chips;

[0039] A thermal network parameter extraction module, configured to apply a preset thermal power to each chip in the finite element model, and extract the first thermal network parameter and the second thermal network parameter of the finite element model; the preset thermal power is determined according to the power loss of the power semiconductor module and the real-time ambient temperature of the environment where it is located; the first thermal network parameter is used to describe the thermal behavior of each chip inside the power semiconductor module; the second thermal network parameter is used to describe the coupled thermal behavior and heat dissipation behavior between multiple chips in the power semiconductor module;

[0040] A thermal network model construction module is configured to construct a thermal network model according to the first thermal network parameter and the second thermal network parameter; the thermal network model is used to predict the temperature change parameter of the power semiconductor module according to the power loss of the power semiconductor module and the real-time ambient temperature of the environment where it is located.

[0041] In a fifth aspect, the present application further provides a computer device, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the steps of the above power module junction temperature estimation method and thermal network model construction method are implemented.

[0042] In a sixth aspect, the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above power module junction temperature estimation method and thermal network model construction method are implemented.

[0043] In a seventh aspect, the present application further provides a computer program product, including a computer program. When the computer program is executed by a processor, the steps of the above power module junction temperature estimation method and thermal network model construction method are implemented.

[0044] For the above power module junction temperature estimation method, thermal network model construction method, device, computer device, computer-readable storage medium and computer program product, a thermal network model is constructed in advance according to the first thermal network parameter and the second thermal network parameter. Among them, the first thermal network parameter is used to describe the thermal behavior of each chip inside the power semiconductor module, and the second thermal network parameter is used to describe the coupled thermal behavior and heat dissipation behavior between multiple chips in the power semiconductor module. The thermal network model constructed according to the first thermal network parameter and the second thermal network parameter can consider the thermal coupling effect between multiple chips in the power semiconductor module when predicting the junction temperature and accurately estimate the chip junction temperature of the power semiconductor module. Therefore, after obtaining the power loss of the power semiconductor module and the real-time ambient temperature of the environment where the power semiconductor module is located, inputting the power loss and the real-time ambient temperature into the pre-constructed thermal network model can accurately predict the temperature change parameter of the power semiconductor module, thereby improving the accuracy of junction temperature prediction of the power semiconductor module. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for describing the embodiments of the present application or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other related drawings can be obtained based on these drawings.

[0046] Figure 1Schematic flow chart of the junction temperature estimation method for a power module in an embodiment;

[0047] Figure 2 Schematic structural diagram of a power semiconductor module in an embodiment;

[0048] Figure 3 Schematic internal structure diagram of the FF150R12ME3G module in an embodiment;

[0049] Figure 4 Schematic diagram of the comparison result of junction temperature estimation of the thermal network model in an embodiment;

[0050] Figure 5 Schematic diagram of the form of the Cauer thermal network model in an embodiment;

[0051] Figure 6 Schematic diagram of the form of the Foster thermal network model in an embodiment;

[0052] Figure 7 Schematic network structure diagram of the thermal network model in an embodiment;

[0053] Figure 8 Schematic flow chart of the thermal network model construction method in an embodiment;

[0054] Figure 9 Schematic block diagram of the structure of the junction temperature estimation device for a power module in an embodiment;

[0055] Figure 10 Schematic block diagram of the structure of the thermal network model construction device in an embodiment;

[0056] Figure 11 Internal structure diagram of a computer device in an embodiment. Detailed implementation manners

[0057] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0058] With the increase in the power density of the power semiconductor module, the increase in the number of chips leads to a complex heat dissipation path, more complex thermal coupling between chips, and more complex dynamic changes in thermal behavior under complex external environments and frequent changes in working conditions. Existing junction temperature estimation methods cannot handle complex scenarios of multi-chip coupling and are difficult to accurately predict the junction temperature of the power semiconductor module.

[0059] Therefore, to solve the above problems, the thermal network model in the embodiments of the present application is constructed based on the first thermal network parameter and the second thermal network parameter. Among them, the first thermal network parameter is used to describe the thermal behavior of each chip inside the power semiconductor module, and the second thermal network parameter is used to describe the coupled thermal behavior and heat dissipation behavior between multiple chips in the power semiconductor module. Constructing the thermal network model according to the first thermal network parameter and the second thermal network parameter can enable the thermal network model to consider the thermal coupling effect between multiple chips in the power semiconductor module when predicting the junction temperature, and can accurately estimate the chip junction temperature of the power semiconductor module.

[0060] In one embodiment, as Figure 1 shown, a method for estimating the junction temperature of a power module is provided. In this embodiment, this method is exemplified by being applied to a terminal. It can be understood that this method can also be applied to a server, and can also be applied to a system including a terminal and a server, and is implemented through the interaction between the terminal and the server. In this embodiment, the method includes the following steps:

[0061] Step 102, obtain the power loss of the power semiconductor module and the real-time ambient temperature of the environment where the power semiconductor module is located; the power semiconductor module includes multiple chips.

[0062] Among them, the power semiconductor module is an electronic device used for processing and controlling the conversion, transmission, and management of electrical energy in a power electronic system. It is usually composed of multiple power semiconductor chips (such as IGBTs, MOSFETs, diodes, etc.) and other auxiliary components (such as inductors, capacitors, resistors, temperature sensors, etc.) encapsulated in a module. The power semiconductor module includes multiple structural layers, and different materials are arranged on each structural layer. Figure 2 For a schematic structural diagram of a power semiconductor module in one embodiment, as Figure 2 shown, generally, the power semiconductor module has a total of 7 layers, namely: chip layer, chip solder layer, upper copper layer, ceramic layer, lower copper layer, substrate solder layer, and substrate layer. Among them, multiple chips are arranged on the chip layer.

[0063] Power loss refers to the energy loss caused by the characteristics of semiconductor materials such as resistance, inductance, and capacitance, as well as other factors inside the module (such as thermal resistance, switching loss, etc.) during the conversion, transmission, and management of electrical energy. These losses are usually dissipated into the environment in the form of heat.

[0064] The real-time ambient temperature refers to the instantaneous temperature of the environment where the power semiconductor module is currently located. The real-time ambient temperature is crucial for the performance and reliability of the power semiconductor module because high temperatures may cause thermal failure or performance degradation of the internal components of the module. The real-time ambient temperature is usually monitored by a temperature sensor installed near the module.

[0065] Specifically, the terminal measures the power loss of the power semiconductor module under specific operating conditions (such as voltage, current, frequency, etc.) through a test device or simulation software. The terminal collects the real-time ambient temperature of the environment where the power semiconductor module is located through a temperature sensor.

[0066] Step 104: Input the power loss and the real-time ambient temperature into a pre-constructed thermal network model, and predict the temperature change parameters of the power semiconductor module through the thermal network model. Among them, the thermal network model is constructed based on the first thermal network parameters and the second thermal network parameters. The first thermal network parameters are used to describe the thermal behavior of each chip inside the power semiconductor module; the second thermal network parameters are used to describe the coupled thermal behavior and heat dissipation behavior among multiple chips in the power semiconductor module.

[0067] Among them, the thermal network model is a mathematical model used to describe and analyze the heat transfer behavior in the power semiconductor module. It abstracts various heat sources, thermal resistances, heat capacities, and other thermal elements in the power semiconductor module into nodes and branches, thus forming a network model similar to an electrical circuit. By solving the thermal network model, the temperature distribution and temperature change of the power semiconductor module under specific conditions can be predicted.

[0068] The first thermal network parameters are the parameters used to describe the thermal behavior of each chip inside the power semiconductor module. The thermal behavior of each chip inside the power semiconductor module is mainly the heat conduction of each layer of material, which is conducted from the chip to the substrate, and then the substrate conducts the heat out through an external heat dissipation device. The first thermal network parameters usually include the thermal resistance, heat capacity, heat source, etc. of each structural layer. Through the first thermal network parameters, the temperature change of a single structural layer under the action of power loss and ambient temperature, as well as the heat transfer and distribution inside the chip, can be analyzed.

[0069] The second thermal network parameters are the parameters used to describe the coupled thermal behavior and heat dissipation behavior among multiple chips in the power semiconductor module. Among them, the coupled thermal behavior among multiple chips refers to the mutual influence generated among multiple chips in the power semiconductor module due to heat transfer. For example, in addition to the thermal behavior of the chip itself, the coupled thermal behavior among multiple chips also includes the thermal coupling of other chips in the power semiconductor module to this chip. The heat dissipation behavior refers to the process of transferring the heat generated inside the power semiconductor module to the external environment, which is usually achieved through heat dissipation devices such as radiators, fans, and heat pipes. The second thermal network parameters usually include the self-thermal impedance of the chip itself and the mutual-thermal impedance between chips. Through the second thermal network parameters, the mutual influence generated among multiple chips due to heat transfer, as well as the heat exchange and heat dissipation performance between the module as a whole and the external environment, can be analyzed.

[0070] The temperature change parameter refers to a parameter that describes the temperature change of a power semiconductor module under different operating conditions. The temperature change parameter usually includes the change of the junction temperature (referring to the temperature inside the power semiconductor chip) and the change of the case temperature (referring to the temperature of the outer shell of the power semiconductor module), etc.

[0071] Specifically, the terminal inputs the obtained power loss and the real-time ambient temperature into a pre-constructed thermal network model, and sets the circuit parameters of the thermal network model according to the power loss, the real-time ambient temperature, the first thermal network parameter, and the second thermal network parameter. By solving the thermal network model, the temperature distribution parameter and the temperature change parameter of the power semiconductor module under specific conditions are obtained.

[0072] In the above power module junction temperature estimation method, a thermal network model is pre-constructed according to the first thermal network parameter and the second thermal network parameter. Among them, the first thermal network parameter is used to describe the thermal behavior of each chip inside the power semiconductor module, and the second thermal network parameter is used to describe the coupled thermal behavior and heat dissipation behavior between multiple chips in the power semiconductor module. The thermal network model constructed according to the first thermal network parameter and the second thermal network parameter can consider the thermal coupling effect between multiple chips in the power semiconductor module when predicting the junction temperature, and accurately estimate the chip junction temperature of the power semiconductor module. Therefore, after obtaining the power loss of the power semiconductor module and the real-time ambient temperature of the environment where the power semiconductor module is located, inputting the power loss and the real-time ambient temperature into the pre-constructed thermal network model can accurately predict the temperature change parameter of the power semiconductor module, thereby improving the accuracy of junction temperature prediction of the power semiconductor module.

[0073] In one embodiment, predicting the temperature change parameter of the power semiconductor module through the thermal network model includes:

[0074] First, determine the circuit structure of the thermal network model. The circuit structure includes a current source, a voltage source, and a thermal impedance.

[0075] Among them, the circuit structure of the thermal network model is an abstract concept that uses the principles and methods of circuit theory to simulate and analyze heat transfer and thermal behavior in power semiconductor modules. In the thermal network model, the components in the circuit structure (such as resistors, capacitors, inductors, etc.) are given thermal meanings and are used to simulate various physical phenomena in the heat transfer process. Specifically, the circuit structure of the thermal network model can include current sources, voltage sources, and thermal impedances. Among them, the current source is used to simulate the power loss of the power semiconductor module. The voltage source is used to simulate the real-time ambient temperature of the environment where the power semiconductor module is located. The thermal impedance is a physical quantity that describes the resistance encountered when heat propagates along the heat path. For example, the thermal impedance includes thermal resistance and heat capacity. Among them, the thermal resistance is similar to the resistance in the circuit, and the thermal resistance describes the resistance encountered when heat propagates along the heat path; the heat capacity is similar to the capacitor in the circuit, and the heat capacity describes the ability of an object to store thermal energy. The value and specific structure of the thermal impedance are determined by the first thermal network parameter and the second thermal network parameter.

[0076] Specifically, the terminal obtains the pre-constructed thermal network model and obtains the circuit structure of the thermal network model.

[0077] Second, according to the power loss, set the value of the current source, according to the real-time ambient temperature, set the value of the voltage source, and according to the first thermal network parameter and the second thermal network parameter, set the value of the thermal impedance.

[0078] Specifically, the terminal converts the power loss into a current value and sets the value of the current source according to this current value; the terminal determines the mapping relationship between temperature and voltage in advance through experiments or simulations, and according to this mapping relationship, determines the voltage value corresponding to the real-time ambient temperature, and sets the value of the voltage source according to this voltage value; the terminal sets the specific circuit structure and specific value of the thermal impedance according to the first thermal network parameter and the second thermal network parameter.

[0079] Third, according to the values of the current source, the voltage source, and the thermal impedance, determine the voltage change parameter of the preset circuit node in the circuit structure, and use the voltage change parameter as the temperature change parameter of the corresponding chip in the power semiconductor module.

[0080] Among them, the preset circuit node represents a specific position inside the power semiconductor module in the thermal network model, and usually corresponds to a chip or other key components. By monitoring the voltage change parameter of the preset circuit node, the temperature change of the corresponding chip can be indirectly inferred.

[0081] Specifically, after the terminal sets the values of the current source, the voltage source, and the thermal impedance, solve the circuit structure corresponding to the thermal network model, and according to needs, determine the voltage change parameter of the preset circuit node in the circuit structure, and use the voltage change parameter as the temperature change parameter of the corresponding chip in the power semiconductor module.

[0082] In this embodiment, by precisely setting the values of the current source, voltage source, and thermal impedance, the heat transfer and temperature change within the power semiconductor module can be more accurately simulated. Considering various factors (such as power loss, ambient temperature, material properties, etc.), the accuracy of the simulation is improved.

[0083] In one of the embodiments, the construction process of the thermal network model includes:

[0084] 1. According to the dimensional information of the power semiconductor module, a finite element model of the power semiconductor module is constructed.

[0085] Among them, the finite element model is a numerical model that accurately simulates the dynamic thermal behavior of the power semiconductor module and is a widely used technology for solving thermodynamic problems with complex geometries and boundary conditions. Partial differential equations are solved by the finite volume method, finite difference method, or finite element method to accurately simulate the actual thermal behavior. To construct the finite element model of a specific power semiconductor module, first, the dimensions of each layer of the power semiconductor module need to be measured, including length, width, and height. Usually, the power semiconductor module has a total of 7 layers, namely: chip layer, chip solder layer, upper copper layer, ceramic layer, lower copper layer, substrate solder layer, and substrate layer.

[0086] Specifically, the terminal obtains the dimensional information of the power semiconductor module, and then establishes a three-dimensional geometric model of the module according to the measured dimensional information. Finally, in the thermal simulation software, the three-dimensional geometric model of the power semiconductor module is meshed, the material properties of each layer are added, the boundary conditions are set, and the thermal power of the chip is applied to complete the establishment of the finite element model of the power semiconductor module.

[0087] 2. Apply a preset thermal power to each chip in the finite element model, and extract the first thermal network parameter and the second thermal network parameter of the finite element model; the preset thermal power is determined according to the power loss and the real-time ambient temperature.

[0088] Specifically, the terminal determines the preset thermal power corresponding to each chip according to the power loss and the real-time ambient temperature of each chip, and in the finite element model, a heat source is applied to each chip area, and the size of the heat source is equal to the preset thermal power corresponding to the chip. The terminal analyzes the temperature distribution and heat flow path in the finite element model, determines the circuit structure of the thermal network model according to the analysis results, and extracts the first thermal network parameter and the second thermal network parameter from the analysis results.

[0089] 3. Construct a thermal network model according to the first thermal network parameter and the second thermal network parameter.

[0090] Specifically, the terminal sets the value and specific structure of the thermal impedance in the circuit structure of the thermal network model according to the extracted first thermal network parameter and second thermal network parameter to obtain the constructed thermal network model.

[0091] In some embodiments, taking the power semiconductor module FF150R12ME3G as an example, a thermal network model of it is constructed to estimate the junction temperature of one of the chips. First, a finite element model of the FF150R12ME3G module is built. The thicknesses and material properties of each layer of the FF150R12ME3G module are shown in Table 1. A finite element model is established according to the physical properties of the FF150R12ME3G module, and the boundary condition of the model is considered that the equivalent heat dissipation coefficient of the substrate surface is 5000 W / m 2 , and the remaining surfaces are kept adiabatic conditions. Figure 3 is a schematic diagram of the internal structure of the FF150R12ME3G module in one embodiment, as shown in Figure 3 . There are a total of 6 IGBT chips inside the FF150R12ME3G, and 6 reverse diode chips, for a total of 12 chips.

[0092] Table 1

[0093]

[0094] Then, steady-state and transient thermal simulations are performed on the finite element model of the FF150R12ME3G module, the first thermal network parameters and the second thermal network parameters are extracted, and a thermal network model is built according to the extracted first thermal network parameters and the second thermal network parameters. For simple verification, only IGBT 1 and IGBT 2 are considered to be applied with heating power and the coupling effect between the two. Finally, 100 W of heating power is applied to IGBT 1 and IGBT 2 simultaneously, and the results of finite element simulation and circuit simulation are compared. Figure 4 is a schematic diagram of the comparison result of junction temperature estimation of the thermal network model in one embodiment, as shown in Figure 4 . The junction temperature of the chip estimated by the thermal network model is in good agreement with the junction temperature of the chip simulated by finite element simulation, indicating that the model can accurately estimate the junction temperature of the chips in the module.

[0095] In this embodiment, the thermal network model constructed according to the first thermal network parameters and the second thermal network parameters can consider the thermal coupling effect between multiple chips in the power semiconductor module when predicting the junction temperature, and accurately estimate the junction temperature of the chips in the power semiconductor module.

[0096] In one of the embodiments, as shown in Figure 2 , the power semiconductor module includes multiple structural layers, specifically divided into a chip layer, a chip solder layer, an upper copper layer, a ceramic layer, a lower copper layer, a substrate solder layer, and a substrate layer.

[0097] In the finite element model, the heat conduction inside the power semiconductor module can be described by Equation (1), where T represents temperature, x, y, and z represent the directions of heat conduction, k is the material conductivity, q v is the heat generated per unit volume, ρ is the density, c ρ is the specific heat capacity.

[0098]

[0099] In some embodiments, the first thermal network parameters include the thermal resistance and heat capacity of each structural layer. Extracting the first thermal network parameters of the finite element model includes:

[0100] 1. Obtain the temperatures of each structural layer when the finite element model reaches a steady state under a preset thermal power, and determine the thermal resistance of each structural layer according to the temperatures of each structural layer.

[0101] Among them, the thermal resistance is similar to the resistance in an electrical circuit, and the thermal resistance describes the resistance encountered when heat propagates along the heat path.

[0102] For the power semiconductor module, the steady state usually means that the excitation and recombination of electrons and holes in the power semiconductor module reach a dynamic equilibrium. When the power semiconductor module operates under a preset thermal power, its internal temperature will reach a stable value, and at the same time, the excitation and recombination of electrons and holes will also reach a dynamic equilibrium state. At this time, the performance parameters of the module such as voltage, current, power factor, etc. will also remain relatively stable, so as to ensure that the module can work stably and reliably.

[0103] Specifically, the terminal applies a preset thermal power to the corresponding chip in the finite element model, then records the temperatures of each layer when the finite element model reaches a steady state under this preset thermal power, and finally calculates the thermal resistance of each layer of the power semiconductor module according to the electro-thermal analogy theory.

[0104] In some embodiments, the electro-thermal analogy theory is represented by Equation (2), where P is the preset thermal power, and R th is the thermal resistance of the structural layer.

[0105]

[0106] 2. Obtain the equivalent heat conduction area of each structural layer, and determine the heat capacity of each structural layer according to the equivalent heat conduction area.

[0107] Among them, usually, the heat capacity of each structural layer can be extracted in transient thermal simulation, but the calculation process is relatively complex. In this embodiment, the heat capacity of each structural layer is calculated through the physical definition of heat capacity. In the case where the thermal resistance of each layer has been calculated in the previous step, calculate the equivalent heat conduction area A z of the material of each layer. After obtaining the equivalent heat conduction area of each layer, the heat capacity C of the material of each layer can be directly calculatedth 。

[0108] The equivalent thermal conduction area is used to describe the overall thermal conduction performance of the structural layer. The thermal conduction performance on the equivalent thermal conduction area is the same as that of the entire structural layer.

[0109] Specifically, for each structural layer, the terminal calculates the equivalent thermal conduction area of the targeted structural layer according to the thermal resistance of the targeted structural layer, and calculates the heat capacity of the targeted structural layer according to the equivalent thermal conduction area of the targeted structural layer.

[0110] In some embodiments, the terminal can use formula (3) to calculate the equivalent thermal conduction area A of the targeted structural layer z , where λ th is the material thermal conductivity and d is the material thickness.

[0111]

[0112] In some embodiments, the terminal can use formula (4) to calculate the heat capacity of the targeted structural layer, where ρ is the density and c ρ is the specific heat capacity.

[0113] C th = c ρ ·ρ·d·A z (4)

[0114] In this embodiment, through finite element model analysis, the temperature distribution of each structural layer can be simulated under a preset thermal power, so as to accurately determine the thermal resistance of each structural layer. By obtaining the equivalent thermal conduction area of each structural layer, the heat capacity of each structural layer can be further determined. Further, using the method of the finite element model and the equivalent thermal conduction area can obtain the first thermal network parameters faster and improve the design efficiency.

[0115] In one of the embodiments, the second thermal network parameters include the self-thermal impedance of the chip itself and the mutual-thermal impedance between the chips.

[0116] Among them, the self-thermal impedance is used to describe the influence of the heat generated by the chip itself on the temperature, including the self-thermal resistance and the self-thermal heat capacity. The self-thermal resistance describes the relationship between the temperature difference caused by heat generation inside the chip and the heat flow. The self-thermal heat capacity refers to the proportional relationship between the heat absorbed or released by the chip during the temperature change process and the temperature change.

[0117] Mutual thermal impedance is used to describe the mutual influence between multiple chips due to heat exchange, including mutual thermal resistance and mutual thermal capacitance. Mutual thermal resistance describes the relationship between the temperature difference and heat flux caused by heat transfer between multiple chips. Mutual thermal capacitance describes the heat storage capacity of multiple chips influencing each other during temperature changes, taking into account the thermal coupling effect between chips.

[0118] In some embodiments, extracting the second thermal network parameters of the finite element model includes:

[0119] First, for any chip of the finite element model, a preset thermal power is separately applied to the targeted chip, the first transient thermal impedance curve of the targeted chip is determined, and a preset functional formula is used to fit the first transient thermal impedance curve to obtain the self-thermal impedance of the targeted chip.

[0120] Among them, the first transient thermal impedance curve is a curve that describes the variation of thermal impedance with time of the chips of a power semiconductor module under different working conditions. It reflects the dynamic characteristics of temperature change and heat dissipation capacity of the power semiconductor module during operation.

[0121] The preset functional formula is a mathematical expression used to fit the first transient thermal impedance curve. Generally, the preset functional formula is selected based on heat conduction theory or empirical models, such as exponential functions, polynomial functions, etc.

[0122] Specifically, for any chip of the finite element model, the terminal separately applies a preset thermal power to the targeted chip, calculates the transient thermal impedance Z th of the targeted chip. According to the corresponding relationship between the transient thermal impedance Z th and time, the first transient thermal impedance curve Z th (t) of the targeted chip is generated. The terminal uses a preset functional formula to fit the first transient thermal impedance curve of the targeted chip, and the fitting order is generally 2 - 4 orders to obtain the self-thermal impedance Z self of the targeted chip. Among them, the more the order, the more accurately it can describe the transient thermal behavior of the module chip.

[0123] In some embodiments, the terminal can calculate the transient thermal impedance Z th of the targeted chip using formula (5), where T c0 is the initial temperature of the case temperature, T c (t) is the case temperature, and P is the preset thermal power applied to the chip. It can be understood that formula (5) characterizes the first transient thermal impedance curve of the targeted chip.

[0124]

[0125] In some embodiments, the transient thermal impedance characterizes the thermal properties of the chip and can be used to generate the relationship between the case temperature and time at any preset thermal power P. For example, Equation (6) describes the transient thermal behavior when heating the chip, that is, it characterizes the relationship between the case temperature and time at the preset thermal power P.

[0126]

[0127] In some embodiments, the preset functional formula can be used to fit the first transient thermal impedance curve of the targeted chip according to Equation (7). Among them, R thi represents the thermal resistance of the i-th structural layer; C thi represents the heat capacity of the i-th structural layer.

[0128]

[0129] In this embodiment, after applying the preset thermal power P to the targeted chip, according to the real-time case temperature and Equation (5), the transient thermal impedance is calculated. Then, based on the transient thermal impedance data, Equation (7) is used to fit the first transient thermal impedance curve of Equation (5) to obtain the parameters of the self-thermal impedance (i.e., thermal resistance and heat capacity) of the targeted chip.

[0130] Second, apply the preset thermal power to other chips respectively, determine the corresponding second transient thermal impedance curve of the targeted chip under the coupling action of other chips, and use the preset functional formula to fit the second transient thermal impedance curve to obtain the mutual thermal impedance of other chips to the targeted chip respectively.

[0131] Among them, the second transient thermal impedance curve refers to the curve of the thermal impedance of the targeted chip changing with time when the preset thermal power is applied to other chips in a multi-chip system. This curve reflects the transient thermal impedance characteristics of the targeted chip under the thermal power input of other chips.

[0132] Specifically, the terminal numbers all the chips. The terminal applies the preset thermal power to other chips and calculates the transient thermal impedance Z th-i , where i is the number of other chips. According to the corresponding relationship between the transient thermal impedance Z th-i and time, the corresponding second transient thermal impedance curve of the targeted chip under the coupling action of other chip i is generated. The terminal uses the preset functional formula to fit the second transient thermal impedance curve of the targeted chip, and the fitting order is generally 2-4 orders to obtain the mutual thermal impedance Z couple-i of other chip i to the targeted chip. Among them, the more orders, the more accurately the transient thermal behavior of the module chip can be described.

[0133] In this embodiment, the second thermal network parameters include the self-thermal impedance of the chip itself and the mutual-thermal impedance between chips. The self-thermal impedance describes the thermal behavior of the chip itself, and the mutual-thermal impedance describes the thermal coupling effect of other chips in the module on this chip. By introducing the self-thermal impedance and the mutual-thermal impedance into the second thermal network parameters, the coupled thermal behavior and heat dissipation of multiple chips can be described, thereby improving the accuracy of junction temperature prediction.

[0134] In one embodiment, a preset thermal power is applied to other chips respectively, and the second transient thermal impedance curve corresponding to the targeted chip under the coupling effect of other chips is determined. A preset functional formula is used to fit the second transient thermal impedance curve to obtain the mutual-thermal impedance of other chips to the targeted chip respectively, including:

[0135] 1. Take any one of the other chips except the targeted chip as the current chip, apply a preset thermal power to the current chip, determine the second transient thermal impedance curve of the targeted chip under the coupling effect of the current chip, and use a preset functional formula to fit the second transient thermal impedance curve to obtain the mutual-thermal impedance of the current chip to the targeted chip.

[0136] Specifically, the terminal numbers all chips, sets the targeted chip as chip 1, takes any one of the other chips except the targeted chip as the current chip, records the number of the current chip as i = 2, applies a preset thermal power to the current chip i, and calculates the transient thermal impedance Z th-i of the targeted chip. According to the corresponding relationship between the transient thermal impedance Z th-i and time, the second transient thermal impedance curve corresponding to the targeted chip 1 under the coupling effect of the other chip i is generated. The terminal uses a preset functional formula to fit the second transient thermal impedance curve of the targeted chip to obtain the mutual-thermal impedance Z couple-i of the current chip i to the targeted chip 1.

[0137] 2. Take the next chip of the current chip as the current chip in the next cycle, and return to the step of applying a preset thermal power to the current chip to continue execution until the current chip is the last chip, to obtain the mutual-thermal impedance of other chips to the targeted chip respectively.

[0138] Specifically, the terminal takes the next chip of the current chip as the current chip in the next cycle, that is, sets i = i + 1, selects the next chip as the current chip, returns to execute the step of applying a preset thermal power to the current chip to continue execution until the current chip is the last chip, to obtain the mutual-thermal impedance of other chips to the targeted chip respectively.

[0139] In some embodiments, take the power semiconductor module as the FF150R12ME3G module as an example. For the IGBT in the FF150R12ME3G module1 A thermal power of 100 W is applied to the chip, and a steady-state thermal simulation is performed. According to the steady-state temperatures of each layer and the physical properties, the first thermal network parameters are calculated. The specific parameters of the first thermal network parameters are shown in Table 2.

[0140] Table 2

[0141] Position Thermal Resistance Heat Capacity Chip Layer 0.010597279 0.027393226 Chip Solder Layer 0.036311979 0.018033197 Upper Copper Layer 0.011664254 0.06657377 Ceramic Layer 0.140077739 0.081807635 Lower Copper Layer 0.009690419 0.080134132 Substrate Solder Layer 0.025678223 0.025501027 Substrate Layer 0.045255601 1.715883355

[0142] For simple verification, only IGBTs are considered 1 and IGBTs 2 Two chips, and a thermal power of 100 W is applied to the IGBT 1 and IGBT 2 chips respectively. The transient thermal responses of the IGBT 1 case temperature points are recorded, and the second transient thermal response curve is fitted by a second-order curve to obtain the self-thermal impedance parameters and mutual-thermal impedance parameters of the IGBT 1 . The specific parameters are shown in Table 3.

[0143] Table 3

[0144] Thermal Impedance Thermal Resistance 1 Heat Capacity 1 Thermal Resistance 2 Heat Capacity 2 <![CDATA[IGBT 1 Self-heating impedance]]> 0.1140 2.9818 0.0798 29.1761 <![CDATA[IGBT 1 Mutual thermal impedance]]> 0.0149 292.0633 0.0053 710.1909

[0145] In this embodiment, by applying a preset thermal power to other chips and determining the mutual-thermal impedance between the chips according to the thermal coupling of other chips to the targeted chip, the thermal interaction of the multi-chip system can be accurately evaluated.

[0146] In some embodiments, according to the first thermal network parameters and the second thermal network parameters, a thermal network model is constructed, including:

[0147] 1. According to the first thermal network parameters, a first model is constructed.

[0148] Among them, as can be seen from the above embodiments, the first thermal network parameters include the thermal resistance and heat capacity of each structural layer, and the connection manner of the thermal resistance and heat capacity of each structural layer is related to the heat transfer path in the power semiconductor module. Therefore, by connecting the thermal resistance and heat capacity of each structural layer, the first model can be obtained.

[0149] The first model refers to an initial thermal network model constructed based on the first thermal network parameters. The first model is organized in a manner similar to a circuit network. In this circuit network, each component (such as thermal resistance, heat capacity, etc.) interacts with each other through a certain connection manner (such as series, parallel, etc.), jointly determining the overall behavior of the first model. For example, the first model can be a Cauer thermal network model. For a power semiconductor module with 7 structural layers, the Cauer thermal network model constructed according to the extracted first thermal network parameters is as Figure 5 shown.

[0150] Specifically, the terminal determines the connection modes of the thermal resistances and thermal capacitances in each structural layer according to the connection modes of the thermal resistances and thermal capacitances of each structural layer and the heat transfer path in the power semiconductor module, and connects the thermal resistances and thermal capacitances of each structural layer according to this connection mode, then the first model can be obtained.

[0151] II. Construct a second model according to the second thermal network parameters.

[0152] Among them, as can be seen from the above embodiments, the second thermal network parameters include the self-thermal impedance of the chip itself and the mutual-thermal impedance between chips. The connection modes of the self-thermal impedance and the mutual-thermal impedance are related to the coupling paths between multiple chips in the power semiconductor module. Therefore, according to the coupling paths between each chip, the self-thermal impedance and the mutual-thermal impedance are connected, then the second model can be obtained.

[0153] The second model refers to the initial thermal network model constructed based on the second thermal network parameters. The second model is organized in a way similar to a circuit network. In this circuit network, each component (such as thermal resistance, thermal capacitance, etc.) interacts with each other through certain connection modes (such as series, parallel, etc.), jointly determining the overall behavior of the second model. For example, the second model can be a Foster thermal network model. For a power semiconductor module with 7 structural layers, the Foster thermal network model constructed according to the extracted first thermal network parameters is as Figure 6 shown.

[0154] Specifically, the terminal determines the connection modes of the self-thermal impedance and the mutual-thermal impedance according to the coupling paths between multiple chips in the power semiconductor module, and connects the self-thermal impedance and the mutual-thermal impedance according to this connection mode, then the second model can be obtained.

[0155] III. Connect the first model and the second model with the preset shell temperature points in the finite element model as connection points to obtain the thermal network model.

[0156] Among them, the preset shell temperature point refers to the point that is preset on the shell of the power semiconductor module for measuring the shell temperature. The preset shell temperature point is generally set after the thermal resistance and thermal capacitance of the last structural layer of the first model. For example, as Figure 5 shown, the preset shell temperature point is set after the last group of thermal resistance and thermal capacitance.

[0157] It should be noted that: if the first model is the Cauer thermal network model and the second model is the Foster thermal network model, the following problems will be faced: the parameters of the Foster thermal network model are easy to extract, generally obtained by fitting the transient thermal response curve. The one-dimensional Foster network can only describe the thermal behavior of a single chip. To describe the thermal behavior of a multi-chip power semiconductor module, a two-dimensional or three-dimensional thermal network model is usually established. For the Foster thermal network model, there are mainly two defects. One is that the model does not have practical physical significance, and the change of its parameters cannot directly correspond to the aging failure of the module. The other is that as the number of chips in the module increases, the order of the model will increase sharply, resulting in an increase in the difficulty of thermal parameter extraction and model solution. The Cauer thermal network model has practical physical significance, but it is very challenging to establish a compact thermal network considering the coupling effect of multiple chips in the module. Usually, the form and parameter extraction of the compact Cauer thermal network model are relatively complex, difficult to accurately establish, and the coupling mechanism of multiple chips is not revealed.

[0158] Since there is basically no coupling effect between the chips inside the power semiconductor module, the main coupling effect is reflected in the external heat dissipation environment. Considering that it is relatively easy to describe the coupling between chips by the Foster model, and the parameter extraction is easy, but it has no physical significance, while the Cauer model has physical significance in describing the thermal behavior of the chips inside the module. Therefore, to integrate the advantages of the two thermal network models, in this embodiment, the Cauer thermal network model and the Foster thermal network model are combined to obtain a hybrid thermal network model, which can use the Cauer thermal network model to describe the internal chip thermal behavior, and also use the Foster thermal network to describe the coupled thermal behavior and heat dissipation situation of multiple chips in the external heat dissipation environment of the module. The two thermal models are connected through the module case temperature point to form a hybrid thermal network model. The hybrid thermal network model not only considers the coupling effect between multiple chips, but also has physical significance, and can realize the junction temperature estimation of the power semiconductor module. The overall hybrid thermal network model has a simple form, low parameter extraction difficulty, is easy to implement, can accurately estimate the junction temperature of the power semiconductor module, and solves the problems of complex thermal network form, difficult thermal parameter extraction and high solution difficulty in the prior art.

[0159] Specifically, the terminal obtains the network structure corresponding to the first model and the network structure corresponding to the second model, and connects the first model and the second model with a preset case temperature point in the finite element model to obtain a thermal network model.

[0160] Figure 7 For the schematic diagram of the network structure of the thermal network model in an embodiment, as Figure 7As shown, the power loss of the chip is equivalent to a current source, and the ambient temperature is equivalent to a voltage source. According to the extracted first thermal network parameters and second thermal network parameters, the values of resistors and capacitors are set to complete the construction of the thermal network. The junction temperature of the chip is the voltage of the corresponding circuit node, and the voltage change situation is the junction temperature change situation of the chip.

[0161] In some embodiments, as Figure 7 shown, according to the self-thermal impedance and mutual-thermal impedance corresponding to the chip, the case temperature corresponding to the chip is calculated, and the case temperature is summarized in the first model for junction temperature estimation. Taking chip 1 as the targeted chip, under the thermal coupling effect of other chips and the influence of the heat generated by chip 1 itself, the calculation formula for the case temperature corresponding to chip 1 is shown in formula (8). Among them, T c1 represents the case temperature of chip 1, P 1 represents the power applied to chip 1, P i represents the power applied to the i-th chip, n represents the number of chips, and T h represents the heat sink temperature.

[0162]

[0163] In this embodiment, according to the first thermal network parameters, a first model is constructed. According to the second thermal network parameters, a second model is constructed. Taking the preset case temperature points in the finite element model as connection points, the first model and the second model are connected to obtain a thermal network model. The thermal network model has a simple form, low difficulty in parameter extraction, is easy to implement, can accurately estimate the junction temperature of the power semiconductor module, and solves the problems of complex thermal network form, difficult thermal parameter extraction, and high solution difficulty in the prior art.

[0164] In one embodiment, as Figure 8 shown, a method for constructing a thermal network model is provided. In this embodiment, an example is given where this method is applied to a terminal. It can be understood that this method can also be applied to a server, and can also be applied to a system including a terminal and a server, and is implemented through the interaction between the terminal and the server. In this embodiment, the method includes the following steps:

[0165] Step 801, construct a finite element model of the power semiconductor module according to the size information of the power semiconductor module; the power semiconductor module includes multiple chips.

[0166] Among them, the finite element model is a numerical model that accurately simulates the dynamic thermal behavior of power semiconductor modules and is a widely used technology for solving thermodynamic problems with complex geometries and boundary conditions. The partial differential equations are solved by the finite volume method, the finite difference method, or the finite element method to accurately simulate the actual thermal behavior. To construct the finite element model of a specific power semiconductor module, it is first necessary to measure the dimensions of each layer of the power semiconductor module, including length, width, and height. Generally, there are 7 layers in a power semiconductor module, namely: chip layer, chip solder layer, upper copper layer, ceramic layer, lower copper layer, substrate solder layer, and substrate layer.

[0167] Specifically, the terminal obtains the dimension information of the power semiconductor module, and then establishes a three-dimensional geometric model of the module according to the measured dimension information. Finally, in the thermal simulation software, the three-dimensional geometric model of the power semiconductor module is meshed, the material properties of each layer are added, the boundary conditions are set, and the thermal power of the chip is applied to complete the establishment of the finite element model of the power semiconductor module.

[0168] Step 802: Apply a preset thermal power to each chip in the finite element model, and extract the first thermal network parameter and the second thermal network parameter of the finite element model; the preset thermal power is determined according to the power loss of the power semiconductor module and the real-time ambient temperature of the environment where it is located; the first thermal network parameter is used to describe the thermal behavior of each chip inside the power semiconductor module; the second thermal network parameter is used to describe the coupled thermal behavior and heat dissipation behavior between multiple chips in the power semiconductor module.

[0169] Among them, power loss refers to the energy loss caused by the resistance, inductance, capacitance and other characteristics of semiconductor materials and other factors inside the module (such as thermal resistance, switching loss, etc.) during the process of electric energy conversion, transmission and management. These losses are usually dissipated into the environment in the form of heat energy.

[0170] The real-time ambient temperature refers to the instant temperature of the environment where the power semiconductor module is currently located. The real-time ambient temperature is crucial for the performance and reliability of the power semiconductor module because high temperatures may cause thermal failure or performance degradation of the internal components of the module. The real-time ambient temperature is usually monitored by temperature sensors installed near the module.

[0171] The first thermal network parameter is a parameter used to describe the thermal behavior of each chip inside the power semiconductor module. The thermal behavior of each chip inside the power semiconductor module is mainly the heat conduction of each layer of material, which is conducted from the chip to the substrate, and then the substrate conducts the heat out through the external heat dissipation device. The first thermal network parameter usually includes the thermal resistance, heat capacity, heat source, etc. of each structural layer. Through the first thermal network parameter, the temperature change of a single structural layer under the action of power loss and ambient temperature, as well as the heat transfer and distribution inside the chip, can be analyzed.

[0172] The second thermal network parameter is a parameter used to describe the coupled thermal behavior and heat dissipation behavior among multiple chips in a power semiconductor module. Among them, the coupled thermal behavior among multiple chips refers to the mutual influence among multiple chips in a power semiconductor module due to heat transfer. For example, the coupled thermal behavior among multiple chips includes, in addition to the thermal behavior of the chips themselves, the thermal coupling of other chips in the power semiconductor module to this chip. The heat dissipation behavior refers to the process by which a power semiconductor module transfers the heat generated inside to the external environment, which is usually achieved through heat dissipation devices such as heat sinks, fans, and heat pipes. The second thermal network parameter usually includes the self-thermal resistance of the chip itself and the mutual thermal resistance between chips, etc. Through the second thermal network parameter, the mutual influence among multiple chips due to heat transfer, as well as the heat exchange and heat dissipation performance between the overall module and the external environment, can be analyzed.

[0173] Specifically, the terminal determines the preset thermal power corresponding to each chip according to the power loss and real-time ambient temperature of each chip, and in the finite element model, applies a heat source on each chip area, and the magnitude of the heat source is equal to the preset thermal power corresponding to the chip. The terminal analyzes the temperature distribution and heat flow path in the finite element model, and determines the circuit structure of the thermal network model according to the analysis result, and extracts the first thermal network parameter and the second thermal network parameter from the analysis result.

[0174] Step 803: Construct a thermal network model according to the first thermal network parameter and the second thermal network parameter; the thermal network model is used to predict the temperature change parameters of the power semiconductor module according to the power loss of the power semiconductor module and the real-time ambient temperature of the environment where it is located.

[0175] Among them, the thermal network model is a mathematical model used to describe and analyze the heat transfer behavior in a power semiconductor module. It abstracts various thermal elements such as heat sources, thermal resistances, and heat capacities in the power semiconductor module into nodes and branches, thus forming a network model similar to a circuit. By solving the thermal network model, the temperature distribution and temperature change of the power semiconductor module under specific conditions can be predicted.

[0176] The temperature change parameter is a parameter used to describe the temperature change situation of a power semiconductor module under different working conditions. The temperature change parameter usually includes the change situation of the junction temperature (referring to the temperature inside the power semiconductor chip) and the change situation of the case temperature (referring to the temperature of the outer shell of the power semiconductor module), etc.

[0177] Specifically, the terminal sets the value and specific structure of the thermal resistance in the circuit structure of the thermal network model according to the extracted first thermal network parameter and second thermal network parameter, and obtains the constructed thermal network model.

[0178] In this embodiment, the thermal network model constructed according to the first thermal network parameters and the second thermal network parameters can consider the thermal coupling effect among multiple chips in the power semiconductor module when predicting the junction temperature, and accurately estimate the chip junction temperature of the power semiconductor module.

[0179] In a detailed embodiment, a method for estimating the junction temperature of a power module includes the following steps:

[0180] I. Construct a finite element model of the power semiconductor module according to the size information of the power semiconductor module; the power semiconductor module includes multiple structural layers.

[0181] II. Apply a preset thermal power to each chip in the finite element model; the preset thermal power is determined according to the power loss and the real-time ambient temperature.

[0182] III. Obtain the temperatures of each structural layer when the finite element model reaches a steady state under the preset thermal power, and determine the thermal resistance of each structural layer according to the temperatures of each structural layer.

[0183] IV. Obtain the equivalent thermal conduction area of each structural layer, and determine the heat capacity of each structural layer according to the equivalent thermal conduction area.

[0184] V. For any chip in the finite element model, apply the preset thermal power to the targeted chip alone, determine the first transient thermal impedance curve of the targeted chip, and fit the first transient thermal impedance curve with a preset functional formula to obtain the self-thermal impedance of the targeted chip.

[0185] VI. Take any chip among the other chips except the targeted chip as the current chip, apply the preset thermal power to the current chip, determine the second transient thermal impedance curve of the targeted chip under the coupling effect of the current chip, and fit the second transient thermal impedance curve with a preset functional formula to obtain the mutual thermal impedance of the current chip to the targeted chip.

[0186] VII. Take the next chip of the current chip as the current chip for the next cycle, and return to the step of applying the preset thermal power to the current chip to continue execution until the current chip is the last chip, so as to obtain the mutual thermal impedance of each other chip to the targeted chip.

[0187] VIII. Construct a first model according to the first thermal network parameters; the first thermal network parameters include the thermal resistance and heat capacity of each structural layer.

[0188] IX. Construct a second model according to the second thermal network parameters; the second thermal network parameters include the self-thermal impedance of the chip itself and the mutual thermal impedance between chips.

[0189] 10. Connect the first model and the second model with the preset shell temperature points in the finite element model as connection points to obtain a thermal network model. The thermal network model is constructed based on the first thermal network parameters and the second thermal network parameters. The first thermal network parameters are used to describe the thermal behavior of each chip inside the power semiconductor module; the second thermal network parameters are used to describe the coupled thermal behavior and heat dissipation behavior among multiple chips in the power semiconductor module.

[0190] 11. Obtain the power loss of the power semiconductor module and the real-time ambient temperature of the environment where the power semiconductor module is located. The power semiconductor module includes multiple chips.

[0191] 12. Input the power loss and the real-time ambient temperature into the pre-constructed thermal network model, and determine the circuit structure of the thermal network model. The circuit structure includes a current source, a voltage source, and a thermal impedance.

[0192] 13. Set the value of the current source according to the power loss, set the value of the voltage source according to the real-time ambient temperature, and set the value of the thermal impedance according to the first thermal network parameters and the second thermal network parameters.

[0193] 14. Determine the voltage change parameter of the preset circuit node in the circuit structure according to the values of the current source, the voltage source, and the thermal impedance, and use the voltage change parameter as the temperature change parameter of the corresponding chip inside the power semiconductor module.

[0194] In this embodiment, a thermal network model is pre-constructed according to the first thermal network parameters and the second thermal network parameters. Among them, the first thermal network parameters are used to describe the thermal behavior of each chip inside the power semiconductor module, and the second thermal network parameters are used to describe the coupled thermal behavior and heat dissipation behavior among multiple chips in the power semiconductor module. The thermal network model constructed according to the first thermal network parameters and the second thermal network parameters can consider the thermal coupling effect among multiple chips inside the power semiconductor module when predicting the junction temperature and accurately estimate the chip junction temperature of the power semiconductor module. Therefore, after obtaining the power loss of the power semiconductor module and the real-time ambient temperature of the environment where the power semiconductor module is located, inputting the power loss and the real-time ambient temperature into the pre-constructed thermal network model can accurately predict the temperature change parameter of the power semiconductor module, thereby improving the accuracy of the junction temperature prediction of the power semiconductor module.

[0195] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are sequentially shown according to the indications of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0196] Based on the same inventive concept, an embodiment of the present application further provides a power module junction temperature estimation device for implementing the power module junction temperature estimation method involved above. The solution provided by this device to solve the problem is similar to the solution described in the above method. Therefore, the specific limitations in one or more embodiments of the power module junction temperature estimation device provided below can refer to the limitations on the power module junction temperature estimation method in the above text, and will not be repeated here.

[0197] In an exemplary embodiment, as Figure 9 shown, a power module junction temperature estimation device is provided, including:

[0198] An acquisition module 901, configured to acquire the power loss of the power semiconductor module and the real-time ambient temperature of the environment where the power semiconductor module is located; the power semiconductor module includes multiple chips.

[0199] A junction temperature prediction module 902, configured to input the power loss and the real-time ambient temperature into a pre-constructed thermal network model, and predict the temperature change parameters of the power semiconductor module through the thermal network model; wherein, the thermal network model is constructed according to first thermal network parameters and second thermal network parameters, and the first thermal network parameters are used to describe the thermal behavior of each chip inside the power semiconductor module; the second thermal network parameters are used to describe the coupled thermal behavior and heat dissipation behavior between multiple chips in the power semiconductor module.

[0200] In one embodiment, the junction temperature prediction module 902 is further configured to determine the circuit structure of the thermal network model, where the circuit structure includes a current source, a voltage source, and a thermal impedance; set the value of the current source according to the power loss, set the value of the voltage source according to the real-time ambient temperature, and set the value of the thermal impedance according to the first thermal network parameter and the second thermal network parameter; determine the voltage change parameter of a preset circuit node in the circuit structure according to the values of the current source, the voltage source, and the thermal impedance, and use the voltage change parameter as the temperature change parameter of the corresponding chip in the power semiconductor module.

[0201] In one embodiment, the junction temperature prediction module 902 is further configured to construct a finite element model of the power semiconductor module according to the size information of the power semiconductor module; apply a preset thermal power to each chip of the finite element model, and extract the first thermal network parameter and the second thermal network parameter of the finite element model; the preset thermal power is determined according to the power loss and the real-time ambient temperature; construct a thermal network model according to the first thermal network parameter and the second thermal network parameter.

[0202] In one embodiment, the power semiconductor module includes multiple structural layers, and the first thermal network parameter includes the thermal resistance and heat capacity of each structural layer. The junction temperature prediction module 902 is further configured to obtain the temperature of each structural layer when the finite element model reaches a steady state under the preset thermal power, and determine the thermal resistance of each structural layer according to the temperature of each structural layer; obtain the equivalent heat conduction area of each structural layer, and determine the heat capacity of each structural layer according to the equivalent heat conduction area.

[0203] In one embodiment, the second thermal network parameter includes the self-thermal impedance of the chip itself and the mutual-thermal impedance between chips. The junction temperature prediction module 902 is further configured to, for any chip of the finite element model, separately apply a preset thermal power to the targeted chip, determine the first transient thermal impedance curve of the targeted chip, fit the first transient thermal impedance curve with a preset functional formula to obtain the self-thermal impedance of the targeted chip; separately apply a preset thermal power to other chips, determine the second transient thermal impedance curve of the targeted chip under the coupling effect of other chips, and fit the second transient thermal impedance curve with a preset functional formula to obtain the mutual-thermal impedance of other chips to the targeted chip respectively.

[0204] In one embodiment, the junction temperature prediction module 902 is further configured to use any one of the other chips except the targeted chip as the current chip, apply a preset thermal power to the current chip, determine a second transient thermal impedance curve of the targeted chip under the coupling effect of the current chip, fit the second transient thermal impedance curve with a preset functional formula to obtain the mutual thermal impedance of the current chip to the targeted chip; use the next chip of the current chip as the current chip in the next cycle, and return to the step of applying the preset thermal power to the current chip to continue execution until the current chip is the last chip, so as to obtain the mutual thermal impedance of each of the other chips to the targeted chip.

[0205] In one embodiment, the junction temperature prediction module 902 is further configured to construct a first model according to the first thermal network parameters; construct a second model according to the second thermal network parameters; connect the first model and the second model with a preset shell temperature point in the finite element model to obtain a thermal network model.

[0206] In an exemplary embodiment, as Figure 10 shown, a power module junction temperature estimation device is provided, including:

[0207] A finite element construction module 1001, configured to construct a finite element model of the power semiconductor module according to the size information of the power semiconductor module; the power semiconductor module includes a plurality of chips;

[0208] A thermal network parameter extraction module 1002, configured to apply a preset thermal power to each chip in the finite element model, and extract first thermal network parameters and second thermal network parameters of the finite element model; the preset thermal power is determined according to the power loss of the power semiconductor module and the real-time ambient temperature of the environment where it is located; the first thermal network parameters are used to describe the thermal behavior of each chip inside the power semiconductor module; the second thermal network parameters are used to describe the coupled thermal behavior and heat dissipation behavior between multiple chips in the power semiconductor module;

[0209] A thermal network model construction module 1003, configured to construct a thermal network model according to the first thermal network parameters and the second thermal network parameters; the thermal network model is used to predict the temperature change parameters of the power semiconductor module according to the power loss of the power semiconductor module and the real-time ambient temperature of the environment where it is located.

[0210] Each module in the above power module junction temperature estimation device can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in the processor of the computer device in hardware form or be independent of it, or can be stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to the above modules.

[0211] In an exemplary embodiment, a computer device is provided. The computer device may be a terminal, and its internal structural diagram may be as shown in Figure 11 . The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit, and an input device. Among them, the processor, the memory, and the input / output interface are connected through a system bus, and the communication interface, the display unit, and the input device are connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used for exchanging information between the processor and external devices. The communication interface of the computer device is used for communicating with external terminals in a wired or wireless manner. The wireless manner can be implemented through WIFI, a mobile cellular network, near field communication (NFC), or other technologies. When the computer program is executed by the processor, it implements a method for estimating the junction temperature of a power module. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer covering the display screen, or a button, a trackball, or a touchpad provided on the housing of the computer device, or an external keyboard, touchpad, or mouse, etc.

[0212] Those skilled in the art can understand that Figure 11 the structure shown in

[0213] is only a block diagram of some structures related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.

[0214] In an embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, it implements the steps in the above method embodiments.

[0215] In an embodiment, a computer program product is provided, including a computer program. When the computer program is executed by a processor, it implements the steps in the above method embodiments.

[0216] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data need to comply with relevant regulations.

[0217] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in this application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in this application can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, data processing logics based on quantum computing, artificial intelligence (AI) processors, etc., without limitation.

[0218] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this application.

[0219] The above-described embodiments merely represent several implementation manners of this application. The description is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of this application. It should be noted that for those of ordinary skill in the art, without departing from the concept of this application, several modifications and improvements can still be made, and these all belong to the protection scope of this application. Therefore, the protection scope of this application shall be subject to the appended claims.

Claims

1. A method for estimating junction temperature of a power module, characterized in that: The method comprises: Acquiring power loss of a power semiconductor module and real-time ambient temperature of an environment in which the power semiconductor module is located; the power semiconductor module includes a plurality of chips; The power loss and the real-time ambient temperature are input into a pre-built thermal network model, and the temperature variation parameters of the power semiconductor module are predicted by the thermal network model; the thermal network model includes a first model and a second model; the thermal network model calculates the shell temperature corresponding to the chip according to the self-heating thermal impedance and mutual-heating thermal impedance corresponding to the chip, and summarizes the shell temperature into the first model for junction temperature estimation, so as to obtain the temperature variation parameters of the chip in the power semiconductor module; Wherein, the thermal network model is constructed based on the first thermal network parameter and the second thermal network parameter, the first model refers to the initial thermal network model constructed based on the first thermal network parameter; the second model refers to the initial thermal network model constructed based on the second thermal network parameter; the first thermal network parameter is used to describe the thermal behavior of each chip inside the power semiconductor module; the power semiconductor module includes multiple structural layers, and the first thermal network parameter includes the thermal resistance and thermal capacitance of each structural layer; the second thermal network parameter is used to describe the coupled thermal behavior and heat dissipation behavior between multiple chips in the power semiconductor module; the second thermal network parameter includes the self-heating thermal impedance of the chip itself and the mutual thermal impedance between chips, the self-heating thermal impedance Impedance is used to describe the influence of the heat generated by the chip itself on the temperature; the self-heating thermal impedance includes self-heating thermal resistance and self-heating heat capacity; the self-heating thermal resistance describes the relationship between the temperature difference caused by heat generation inside the chip and the heat flow; the self-heating heat capacity refers to the proportional relationship between the heat absorbed or released by the chip during the temperature change and the temperature change; the mutual thermal impedance is used to describe the mutual influence between multiple chips due to heat exchange; the mutual thermal impedance includes mutual thermal resistance and mutual thermal capacity; the mutual thermal resistance describes the relationship between the temperature difference caused by heat transfer between multiple chips and the heat flow; the mutual thermal capacity describes the heat storage capacity of multiple chips that influence each other during the temperature change.

2. The method according to claim 1, characterized in that The predicting the temperature variation parameter of the power semiconductor module by using the thermal network model includes: Determining a circuit structure of the thermal network model, wherein the circuit structure includes a current source, a voltage source, and a thermal impedance; According to the power loss, the value of the current source is set, according to the real-time ambient temperature, the value of the voltage source is set, and according to the first thermal network parameter and the second thermal network parameter, the value of the thermal impedance is set; According to the value of the current source, the value of the voltage source and the value of the thermal impedance, a voltage variation parameter of a preset circuit node in the circuit structure is determined, and the voltage variation parameter is used as a temperature variation parameter of a corresponding chip in the power semiconductor module.

3. The method according to claim 1, characterized in that The construction process of the thermal network model includes: Constructing a finite element model of the power semiconductor module according to the size information of the power semiconductor module; Applying a preset thermal power to each chip of the finite element model, and extracting a first thermal network parameter and a second thermal network parameter of the finite element model; the preset thermal power is determined according to the power loss and the real-time ambient temperature; A thermal network model is constructed according to the first thermal network parameter and the second thermal network parameter.

4. The method according to claim 3, characterized in that The extracting the first thermal network parameter of the finite element model comprises: Acquire the temperature of each structural layer when the finite element model reaches a steady state under the preset thermal power, and determine the thermal resistance of each structural layer according to the temperature of each structural layer; The equivalent heat conduction area of ​​each structural layer is obtained, and the heat capacity of each structural layer is determined according to the equivalent heat conduction area.

5. The method according to claim 3, characterized in that: The extracting the second thermal network parameter of the finite element model comprises: For any chip of the finite element model, a preset thermal power is applied to the targeted chip alone, a first transient thermal impedance curve of the targeted chip is determined, and the first transient thermal impedance curve is fitted using a preset function to obtain a self-heating thermal impedance of the targeted chip; Preset thermal power is applied to other chips respectively, a second transient thermal impedance curve corresponding to the targeted chip under the coupling effect of other chips is determined, and the second transient thermal impedance curve is fitted using a preset function to obtain the mutual thermal impedance of other chips to the targeted chip.

6. The method according to claim 5, characterized in that The method of applying preset thermal power to other chips respectively, determining a second transient thermal impedance curve corresponding to the targeted chip under the coupling effect of other chips, and fitting the second transient thermal impedance curve using a preset function to obtain mutual thermal impedances of other chips to the targeted chip respectively, includes: Taking any chip other than the targeted chip as the current chip, applying a preset thermal power to the current chip, determining a second transient thermal impedance curve of the targeted chip under the coupling effect of the current chip, and fitting the second transient thermal impedance curve using a preset function to obtain the mutual thermal impedance of the current chip to the targeted chip; The next chip of the current chip is used as the current chip of the next cycle, and the step of applying the preset thermal power on the current chip is returned to continue execution until the current chip is the last chip, and the mutual thermal impedance of other chips to the targeted chip is obtained.

7. The method according to claim 3, characterized in that The step of constructing a thermal network model according to the first thermal network parameter and the second thermal network parameter includes: constructing a first model according to the first thermal network parameters; constructing a second model according to the second thermal network parameters; The first model and the second model are connected using the preset shell temperature points in the finite element model as connection points to obtain a thermal network model.

8. A method for constructing a thermal network model, characterized in that: The method comprises: Constructing a finite element model of the power semiconductor module according to the size information of the power semiconductor module; the power semiconductor module includes a plurality of chips; A preset thermal power is applied to each chip of the finite element model, and a first thermal network parameter and a second thermal network parameter of the finite element model are extracted; the preset thermal power is determined according to the power loss of the power semiconductor module and the real-time ambient temperature of the environment; the first thermal network parameter is used to describe the thermal behavior of each chip inside the power semiconductor module; the power semiconductor module includes a plurality of structural layers, and the first thermal network parameter includes the thermal resistance and thermal capacitance of each structural layer; the second thermal network parameter is used to describe the coupled thermal behavior and heat dissipation behavior between multiple chips in the power semiconductor module; the second thermal network parameter includes the self-thermal thermal impedance of the chip itself and the mutual thermal impedance between chips, and the self-thermal thermal impedance Used to describe the influence of the heat generated by the chip itself on the temperature; the self-heating thermal impedance includes self-heating thermal resistance and self-heating thermal capacitance; the self-heating thermal resistance describes the relationship between the temperature difference caused by heat generation inside the chip and the heat flow; the self-heating thermal capacitance refers to the proportional relationship between the heat absorbed or released by the chip during the temperature change and the temperature change; the mutual thermal impedance is used to describe the mutual influence between multiple chips due to heat exchange; the mutual thermal impedance includes mutual thermal resistance and mutual thermal capacitance; the mutual thermal resistance describes the relationship between the temperature difference caused by heat transfer between multiple chips and the heat flow; the mutual thermal capacitance describes the heat storage capacity of multiple chips that influence each other during the temperature change; A thermal network model is constructed according to the first thermal network parameter and the second thermal network parameter; the thermal network model is used to predict the temperature change parameters of the power semiconductor module according to the power loss of the power semiconductor module and the real-time ambient temperature of the environment in which it is located; the thermal network model includes a first model and a second model; the thermal network model calculates the shell temperature corresponding to the chip according to the self-thermal thermal impedance and mutual thermal impedance corresponding to the chip, and summarizes the shell temperature in the first model to estimate the junction temperature, so as to obtain the temperature change parameters of the chip in the power semiconductor module; the first model refers to an initial thermal network model constructed based on the first thermal network parameters; the second model refers to an initial thermal network model constructed based on the second thermal network parameters.

9. A power module junction temperature estimation device, characterized in that: The device comprises: An acquisition module, used for acquiring the power loss of a power semiconductor module and the real-time ambient temperature of the environment in which the power semiconductor module is located; the power semiconductor module includes a plurality of chips; A junction temperature prediction module is used to input the power loss and the real-time ambient temperature into a pre-constructed thermal network model, and predict the temperature change parameters of the power semiconductor module through the thermal network model; the thermal network model includes a first model and a second model; the thermal network model calculates the shell temperature corresponding to the chip according to the self-thermal thermal impedance and mutual thermal impedance corresponding to the chip, and summarizes the shell temperature into the first model for junction temperature estimation to obtain the temperature change parameters of the chip in the power semiconductor module; wherein the thermal network model is constructed based on the first thermal network parameter and the second thermal network parameter, the first model refers to the initial thermal network model constructed based on the first thermal network parameter; the second model refers to the initial thermal network model constructed based on the second thermal network parameter; the first thermal network parameter is used to describe the thermal behavior of each chip inside the power semiconductor module; the power semiconductor module includes multiple structural layers, and the first thermal network parameter includes the thermal resistance of each structural layer and heat capacity; the second thermal network parameter is used to describe the coupled thermal behavior and heat dissipation behavior between multiple chips in the power semiconductor module; the second thermal network parameter includes the self-thermal thermal impedance of the chip itself and the mutual thermal impedance between the chips, the self-thermal thermal impedance is used to describe the influence of the heat generated by the chip itself on the temperature; the self-thermal thermal impedance includes self-thermal thermal resistance and self-thermal thermal capacitance; the self-thermal thermal resistance describes the relationship between the temperature difference and the heat flow caused by heat generation inside the chip; the self-thermal thermal capacitance refers to the proportional relationship between the heat absorbed or released by the chip during the temperature change and the temperature change; the mutual thermal impedance is used to describe the mutual influence between multiple chips due to heat exchange; the mutual thermal impedance includes mutual thermal resistance and mutual thermal capacitance; the mutual thermal resistance describes the relationship between the temperature difference and the heat flow caused by heat transfer between multiple chips; the mutual thermal capacitance describes the heat storage capacity of multiple chips that influence each other during the temperature change.

10. A thermal network model building device, characterized in that: The device comprises: A finite element construction module, used to construct a finite element model of the power semiconductor module according to the size information of the power semiconductor module; the power semiconductor module includes a plurality of chips; A thermal network parameter extraction module is used to apply a preset thermal power to each chip of the finite element model and extract the first thermal network parameter and the second thermal network parameter of the finite element model; the preset thermal power is determined according to the power loss of the power semiconductor module and the real-time ambient temperature of the environment; the first thermal network parameter is used to describe the thermal behavior of each chip inside the power semiconductor module; the power semiconductor module includes multiple structural layers, and the first thermal network parameter includes the thermal resistance and thermal capacitance of each structural layer; the second thermal network parameter is used to describe the coupled thermal behavior and heat dissipation behavior between multiple chips in the power semiconductor module; the second thermal network parameter includes the self-thermal thermal impedance of the chip itself and the mutual thermal impedance between chips, The self-heating thermal impedance is used to describe the influence of the heat generated by the chip itself on the temperature; the self-heating thermal impedance includes self-heating thermal resistance and self-heating heat capacity; the self-heating thermal resistance describes the relationship between the temperature difference caused by the heat generation inside the chip and the heat flow; the self-heating heat capacity refers to the proportional relationship between the heat absorbed or released by the chip during the temperature change and the temperature change; the mutual thermal impedance is used to describe the mutual influence between multiple chips due to heat exchange; the mutual thermal impedance includes mutual thermal resistance and mutual thermal capacity; the mutual thermal resistance describes the relationship between the temperature difference caused by heat transfer between multiple chips and the heat flow; the mutual thermal capacity describes the heat storage capacity of multiple chips that influence each other during the temperature change; A thermal network model construction module is used to construct a thermal network model according to the first thermal network parameters and the second thermal network parameters; the thermal network model is used to predict the temperature change parameters of the power semiconductor module according to the power loss of the power semiconductor module and the real-time ambient temperature of the environment in which it is located; the thermal network model includes a first model and a second model; the thermal network model calculates the shell temperature corresponding to the chip according to the self-thermal thermal impedance and mutual thermal impedance corresponding to the chip, and summarizes the shell temperature in the first model for junction temperature estimation to obtain the temperature change parameters of the chip in the power semiconductor module; the first model refers to an initial thermal network model constructed based on the first thermal network parameters; the second model refers to an initial thermal network model constructed based on the second thermal network parameters.

11. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 8 are implemented.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

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