A driving method of a display panel and a display device

Abstract

The application discloses a display panel driving method and a display device, and relates to the technical field of display panel driving. When the i-th row of pixel circuits is in a data writing stage, the method detects whether the data signal provided to the data signal line corresponding to each column of pixel circuits of the i-th row is greater than a preset threshold value. If yes, the j-th column of pixel circuits of the k-th row in a bias stage of a holding frame at this time is queried. If the data signal provided to the data signal line corresponding to the j-th column of pixel circuits of the i-th row jumps to a time point at which the j-th column of pixel circuits of the k-th row is in an effective level period of the light-emitting control signal in the holding frame, the display brightness of the light-emitting element driven by the j-th column of pixel circuits of the k-th row is compensated by providing a compensation data signal smaller than the configured data signal to the data signal line corresponding to the j-th column of pixel circuits of the k-th row when the k-th row of pixel circuits is in the data writing stage, so that the display effect is improved.

Description

Technical Field

[0001] This application relates to the field of display panel driving technology, and in particular to a driving method for a display panel and a display device. Background Technology

[0002] In a display panel, the pixel circuit provides the driving current required for the light-emitting element to display and controls whether the light-emitting element enters the light-emitting stage. It is an indispensable component in most self-emissive display panels.

[0003] However, as the display panel is used for a longer period of time, the internal characteristics of the driving transistors in the pixel circuit change slowly, causing the threshold voltage of the driving transistors to drift, affecting the overall characteristics of the driving transistors, and thus affecting the uniformity of the display.

[0004] To address this issue, current methods involve biasing the source and / or drain of the driving transistor to balance changes in its threshold voltage and ensure display uniformity. However, with the increasing demand for high-precision frequency conversion, the driving transistor needs to be biased multiple times within one cycle of scanning the entire display panel to maintain the biasing effect. This can lead to a replication phenomenon on the display panel; that is, when a black block is displayed in one area, a replicated black block will appear in other areas, affecting the display quality. Summary of the Invention

[0005] To address the aforementioned technical problems, embodiments of this application provide a driving method for a display panel and a display device to compensate for data signals in the replicated area, thereby improving the display effect.

[0006] To achieve the above objectives, the embodiments of this application provide the following technical solutions:

[0007] The first aspect of this application provides a method for driving a display panel;

[0008] The display panel includes an array of pixel circuits, light-emitting elements driven by the pixel circuits, and data signal lines that transmit data signals to each column of pixel circuits.

[0009] The pixel circuit includes a driving module, a data writing module, a light emission control module, a bias module, and a reset module. The driving module includes a driving transistor. The light emission control module selectively causes the light-emitting element to enter the light emission stage under the control of the light emission control signal.

[0010] One data write cycle of the display panel includes S frames to refresh the screen, S≥2, one frame includes an effective level period and an ineffective level period of the light control signal, and S frames include a data write frame and at least one hold frame;

[0011] In the data writing frame, the invalid level period of the light emission control signal corresponds to the pre-stage, and the valid level period corresponds to the light emission stage; the pre-stage includes the data writing stage, in which the data writing module writes the data signal transmitted on the data signal line corresponding to the pixel circuit into the gate of the driving transistor.

[0012] The invalid level period of the light emission control signal in the pre-set stage and at least one holding frame includes a bias stage, in which the bias module writes a bias signal to the first and / or second pole of the driving transistor, and the reset module provides a reset signal to the light emission element.

[0013] The driving methods for the display panel in a data write cycle include:

[0014] When the pixel circuit in the i-th row is in the data writing stage, detect whether the data signal provided to the data signal line corresponding to each column pixel circuit in the i-th row is greater than a preset threshold.

[0015] If the data signal provided to the data signal line corresponding to the pixel circuit in row i and column j is greater than the preset threshold, then the pixel circuit in row k and column j is queried. When the pixel circuit in row i is in the data writing stage, the pixel circuit in row k is in the bias stage of holding the frame.

[0016] Detect whether the moment when the data signal provided to the data signal line corresponding to the pixel circuit in row i and column j jumps to a level lower than a preset threshold corresponds to the effective level period of the light emission control signal in the holding frame for the pixel circuit in row k and column j; if so, when the pixel circuit in row k is in the data writing stage, provide a compensation data signal that is lower than the configured data signal to the data signal line corresponding to the pixel circuit in row k and column j.

[0017] A second aspect of this application provides a display device, including a display panel and a driver integrated circuit, wherein the driver integrated circuit drives the display panel to display in each data writing cycle using the above-described display panel driving method.

[0018] Compared with existing technologies, the above technical solution has the following advantages:

[0019] The display panel driving method provided in this application embodiment includes a bias module in the pixel circuit. Within a data writing cycle, a bias phase is set in both the pre-writing phase of the data writing frame and the invalid level period of the light emission control signal in at least one holding frame. This allows the bias module to write a bias signal to the first and / or second terminals of the driving transistor to balance the threshold voltage change of the driving transistor. Based on this, and the reset module in the pixel circuit providing a reset signal to the light-emitting element, when the i-th row pixel circuit is in the data writing phase, it detects whether the data signal provided to the data signal lines corresponding to each column of the i-th row pixel circuit is greater than a preset threshold. If the data signal provided to the data signal lines corresponding to the j-th column of the i-th row pixel circuit is greater than the preset threshold, it indicates that the light-emitting element driven by the i-th row and j-th column pixel circuit displays a low grayscale, and then the k-th row and j-th column pixel circuit, which is currently in the bias phase of the holding frame, is located. Although the i-th row pixel circuit is in the data writing phase... During the initial phase, since the k-th row pixel circuit is in the bias phase of the hold frame, its reset module resets the anode of the light-emitting element, so that the light-emitting element driven by the k-th row and j-th column pixel circuit is not affected. However, if the data signal provided to the data signal line corresponding to the i-th row and j-th column pixel circuit jumps to a time lower than the preset threshold, corresponding to the effective level of the light emission control signal in the hold frame of the k-th row and j-th column pixel circuit, the anode current of the light-emitting element driven by the k-th row and j-th column pixel circuit will be affected by the data signal provided by the data signal line corresponding to the i-th row and j-th column pixel circuit (that is, the data signal line corresponding to the k-th row and j-th column pixel circuit) and the anode of the light-emitting element driven by the k-th row and j-th column pixel circuit due to coupling. This will cause the light-emitting element driven by the k-th row and j-th column pixel circuit to also display a low grayscale, replicating the display of the light-emitting element driven by the i-th row and j-th column pixel circuit.

[0020] Based on this, when the pixel circuit in the k-th row is in the data writing stage, a compensation data signal smaller than the configured data signal is provided to the data signal line corresponding to the pixel circuit in the k-th row and j-th column. This enables the light-emitting element driven by the pixel circuit in the k-th row and j-th column to display a higher grayscale, visually compensating for the low grayscale display of the light-emitting element driven by the pixel circuit in the k-th row and j-th column, thus improving the display effect. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a partial top view of a display panel;

[0023] Figure 2 This is a schematic diagram of the circuit structure of a pixel circuit;

[0024] Figure 3 This is a schematic diagram of another pixel circuit structure;

[0025] Figure 4 A schematic diagram illustrating the drift of the Id-Vg curve of the driving transistor;

[0026] Figure 5 for Figure 4 A timing diagram of the signals received by the pixel circuit shown;

[0027] Figure 6 A timing diagram for the emission control signal Emit and the scanning signal SPX received by different row pixel circuits;

[0028] Figure 7 Another timing diagram for the emission control signal Emit and the scan signal SPX received by a row pixel circuit;

[0029] Figure 8 Another timing diagram for the emission control signal Emit and the scan signal SPX received by a row pixel circuit;

[0030] Figure 9 This is a top-view diagram of a display panel in use.

[0031] Figure 10 This is a timing diagram showing the signals received by the pixel circuit located in region A1, the pixel circuit located in region A1' and in the same column as the pixel circuit in region A1, and the pixel circuit in the other normal display area A0.

[0032] Figure 11 This is a partial layout diagram of a display panel;

[0033] Figure 12 A schematic flowchart illustrating a driving method for a display panel provided in an embodiment of this application;

[0034] Figure 13 This is a schematic diagram illustrating data signal compensation for the A1' area of ​​a display panel using a driving method for a display panel provided in an embodiment of this application.

[0035] Figure 14 This is a timing diagram corresponding to the control signal TE and the data signal Vdata;

[0036] Figure 15A schematic diagram illustrating the specific process of a display panel driving method provided in this application embodiment, wherein when the pixel circuit in the k-th row is in the data writing stage, a compensation data signal smaller than the configured data signal is provided to the data signal line corresponding to the pixel circuit in the k-th row and j-th column.

[0037] Figures 16a-16f The diagram shows the display brightness of the display panel after providing compensation data signals of gray levels 0, 1, 2, 3, 4, and 5, which are less than the configured data signals, to the pixel circuit in the k-th row and j-th column in sequence.

[0038] Figure 17 This is another timing diagram corresponding to the control signal TE and the data signal Vdata;

[0039] Figure 18 This is a timing diagram showing the signals received by the pixel circuit located in region A1, the pixel circuit located in region A10' and in the same column as the pixel circuit in region A1, and the pixel circuit in the other normal display area A0.

[0040] Figure 19 This is a schematic flowchart illustrating the data signal compensation process for the pixel circuit in the h-th row and j-th column of a display panel driving method provided in an embodiment of this application.

[0041] Figure 20 This is a plan view of a display device provided in an embodiment of this application. Detailed Implementation

[0042] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0043] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0044] Figure 1 A partial top view of a display panel is shown, such as... Figure 1As shown, the display panel 100 includes pixel circuits 10 arranged in an array along the row direction X and the column direction Y, and also includes data signal lines 20 that transmit data signals to each column of pixel circuits 10. Pixel circuits 10 in the same column are connected to the same data signal lines 20. By scanning each row of pixel circuits 10, the data signals transmitted by the data signal lines 20 are sequentially written into each row of pixel circuits 10, enabling each row of pixel circuits 10 to provide the driving current required for the display of the light-emitting elements. Once all rows of pixel circuits 10 have been scanned, one data writing cycle of the display panel is completed.

[0045] Figure 2 A schematic diagram of the circuit structure of a pixel circuit 10 is shown, as follows: Figure 2 As shown, the pixel circuit 10 includes a driving module 11, a data writing module 12, a light emission control module 13, and a reset module 14.

[0046] The driving module 11 is used to provide driving current to the light-emitting element 30. The driving module 11 includes a driving transistor T3, the first terminal of the driving transistor T3 is connected to node N2, the second terminal of the driving transistor T3 is connected to node N3, and the gate of the driving transistor T3 is connected to node N1.

[0047] The data writing module 12 is used to selectively provide the data signal Vdata to the drive module 11 under the control of the scan signal SP. The data writing module 12 includes a data writing transistor T2, the first terminal of the data writing transistor T2 receives the data signal Vdata, the second terminal of the data writing transistor T2 is connected to node N2, and the gate of the data writing transistor T2 receives the scan signal SP.

[0048] The light-emitting control module 13 is used to selectively cause the light-emitting element 30 to enter the light-emitting stage under the control of the light-emitting control signal Emit. The light-emitting control module 13 includes a first light-emitting control transistor T1 and a second light-emitting control transistor T6. The first terminal of the first light-emitting control transistor T1 receives the power supply voltage PVDD, the second terminal of the first light-emitting control transistor T1 is connected to node N2, and the gate of the first light-emitting control transistor T1 receives the light-emitting control signal Emit. The first terminal of the second light-emitting control transistor T6 is connected to node N3, the second terminal of the second light-emitting control transistor T6 is connected to node N6, and the gate of the second light-emitting control transistor T6 receives the light-emitting control signal Emit.

[0049] The reset module 14 is used to selectively provide the reset signal Vref2 to the light-emitting element 30 under the control of the scan signal SPX, specifically to the anode of the light-emitting element 30; the reset module 14 includes an anode reset transistor T7, the first terminal of the anode reset transistor T7 receives the reset signal Vref2, the second terminal of the anode reset transistor T7 is connected to node N6, node N6 is connected to the anode of the light-emitting element 30, and the gate of the anode reset transistor T7 receives the scan signal SP.

[0050] like Figure 2 As shown, the pixel circuit 10 also includes a compensation module 15, an initialization module 16, and a storage capacitor Cst.

[0051] The compensation module 15 is used to compensate the threshold voltage of the driving transistor T3 under the control of the scan signal S2. The compensation module 15 includes a compensation transistor T4, the first terminal of the compensation transistor T4 is connected to node N3, the second terminal of the compensation transistor T4 is connected to node N1, and the gate of the compensation transistor T4 receives the scan signal S2.

[0052] The initialization module 16 is used to selectively provide an initialization signal Vref1 to the gate of the driving transistor T3 under the control of the scan signal S1; the initialization module 16 includes a gate initialization transistor T5, the first terminal of the gate initialization transistor T5 receives the initialization signal Vref1, the second terminal of the gate initialization transistor T5 is connected to node N1, and the gate of the gate initialization transistor T5 receives the scan signal S1.

[0053] The first plate of the storage capacitor Cst is connected to node N1, and the second plate of the storage capacitor Cst is at the same potential as the power supply voltage PVDD.

[0054] It is understandable that nodes N1-N6 can be either virtual connection nodes or actual connection nodes.

[0055] like Figure 2 As shown, the compensation transistor T4 and the gate initialization transistor T5 can be dual-gate transistors to reduce the leakage current of the transistors and improve the display effect of the display panel.

[0056] Optional, such as Figure 2As shown, in pixel circuit 10, compensation transistor T4 and gate initialization transistor T5 can be indium gallium zinc oxide (IGZO) thin-film transistors, and other thin-film transistors can be low-temperature polycrystalline (LTPS) thin-film transistors. Because IGZO thin-film transistors have low leakage current, pixel circuit 10 can achieve low-frequency driving, i.e., it is a low-frequency pixel circuit. In this case, each thin-film transistor in pixel circuit 10 can be a PMOS thin-film transistor, which is turned on when its gate receives a low-level signal.

[0057] Another option, such as Figure 3 As shown, each thin-film transistor in the pixel circuit 10 can also be an LTPS thin-film transistor. The compensation transistor T4 can include two series-connected sub-transistors T41 and T42, thus having a dual-gate structure. The connection point of sub-transistors T41 and T42 is the intermediate node N4 of the compensation transistor T4. Similarly, the gate initialization transistor T5 can also include two series-connected sub-transistors T51 and T52, thus having a dual-gate structure. The connection point of sub-transistors T51 and T52 is the intermediate node N5 of the gate initialization transistor T5. In this case, the compensation transistor T4 and the gate initialization transistor T5 can be NMOS thin-film transistors, which are turned on when the gate receives a high-level signal. The other thin-film transistors can be PMOS thin-film transistors, which are turned on when the gate receives a low-level signal.

[0058] refer to Figure 2 and Figure 3 As shown, the operation of the pixel circuit 10 generally includes a reset stage, a data writing stage, and a light emission stage. In the reset stage, the scan signal SPX is at an active level, which turns on the anode reset transistor T7 to reset node N6 (i.e., the anode of the light-emitting element 30); the scan signal S1 is at an active level, which turns on the gate initialization transistor T5 to initialize the gate of the driving transistor T3.

[0059] During the data writing phase, the scan signal S2 is active, turning on the compensation transistor T4; the scan signal SP is active, turning on the data writing transistor T2, and the data signal Vdata is written to the gate of the driving transistor T3.

[0060] During the light-emitting stage, the light-emitting control signal Emit is at an active level, turning on the first light-emitting control transistor T1 and the second light-emitting control transistor T2, and driving transistor T3 according to the driving current Id = (PVDD - Vdata). 2 Drive the light-emitting element 30 to emit light.

[0061] However, during the non-biased phases such as the light-emitting phase, the pixel circuit 10 may have a situation where the gate potential of the driving transistor T3 is greater than the drain potential of the driving transistor. If this setting is maintained for a long time, it will cause the ions inside the driving transistor to become polarized, thereby forming a built-in electric field inside the driving transistor, which will cause the threshold voltage Vth of the driving transistor to continuously increase. Figure 4 This is a schematic diagram of the drift of the Id-Vg curve of the driving transistor, as shown below. Figure 4 As shown, the Id-Vg curve shifts, causing the threshold voltage Vth of the driving transistor to drift, which in turn affects the driving current flowing into the light-emitting element and consequently affects the uniformity of the display.

[0062] To solve this problem, such as Figure 2 and Figure 3 As shown, a bias module 17 is added to the pixel circuit 10. The bias module 17 includes a bias transistor T8. The gate of the bias transistor T8 receives the scan signal SPX, the first terminal of the bias transistor T8 receives the bias signal DVH, and the second terminal of the bias transistor T8 is connected to at least one of the first and second terminals of the driving transistor T3. That is, the second terminal of the bias transistor T8 can be connected only to the first terminal of the driving transistor T3, or the second terminal of the bias transistor T8 can be connected only to the second terminal of the driving transistor T3, or the second terminal of the bias transistor T8 can be connected to both the first and second terminals of the driving transistor T3. Figure 2 and Figure 3 The example only illustrates the case where the second terminal of the bias transistor T8 is connected to the first terminal of the drive transistor T3.

[0063] Thus, when bias transistor T8 is turned on, it can transmit the bias signal DVH to the first and / or second terminals of driver transistor T3, thereby biasing the first and / or second terminals of driver transistor T3. This improves the brightness of the first frame during image display, preventing it from being too low and ensuring good consistency in image display. Furthermore, before initializing the gate of driver transistor T3, by controlling bias transistor T8 to turn on, the bias voltage provided by the bias signal line DVH can be written to the first and / or second terminals of driver transistor T3, refreshing their potential. This sets the device characteristics of driver transistor T3 to a defined initial state, eliminating the influence of the data signal written in the previous frame on the device characteristics of driver transistor T3. After writing data voltage to the driving transistor T3, leakage current will occur at the first and / or second terminals of the driving transistor T3, especially under low-frequency driving, where the leakage current is more obvious, causing a large potential shift at the first and / or second terminals of the driving transistor T3. At this time, by controlling the bias transistor T8 to conduct and writing bias voltage to the first and / or second terminals of the driving transistor T3 using the bias transistor T8, the bias state of the driving transistor T3 can be kept consistent with the bias state when the data voltage was just written, thereby improving the stability of the working state of the driving transistor T3, reducing low-frequency flicker, and thus improving the display effect of the display panel.

[0064] Figure 5 Taking the compensation transistor T4 and gate initialization transistor T5 as examples, both of which are NMOS thin-film transistors, and the other transistors as PMOS thin-film transistors, this illustrates the provision of... Figure 4 A timing diagram of the signals of the pixel circuit shown, combined with... Figure 4 and Figure 5 As shown, the operation of the pixel circuit 10 can be divided into the following five time periods:

[0065] During the OBS1 period, the scan signal S2 is at an active level (high level), which turns on the compensation transistor T4. At the same time, the scan signal SPX is at an active level (low level), which turns on the bias transistor T8. The bias signal DVH is written to the first and / or second terminals of the driving transistor T3, which refreshes the potential of the first and / or second terminals of the driving transistor T3. This sets the device characteristics of the driving transistor T3 to a defined initial state, eliminating the influence of the data signal written in the previous frame on the device characteristics of the driving transistor T3. At the same time, the scan signal SPX also turns on the anode reset transistor T7, which resets node N6 (i.e., the anode of the light-emitting element 30).

[0066] During time period T1, the scan signal S1 is at an active level (high level), which turns on the gate initialization transistor T5 to initialize node N1 (i.e., the gate of the driving transistor T3).

[0067] During time period T2, the scan signal S2 is active (high level), which turns on the compensation transistor T4. Also, the scan signal SP is active (low level), which turns on the data writing transistor T2, so that the data signal Vdata is written to the gate of the driving transistor T2 (also known as the threshold grabbing of the driving transistor T3).

[0068] During the OBS2 period, the scan signal SPX is at an active level (low level), which turns on the bias transistor T8 and writes the bias signal DVH to the first and / or second terminals of the driving transistor T3. By using the bias transistor T8 to write the bias voltage to the first and / or second terminals of the driving transistor T3, the bias state of the driving transistor T3 can be kept consistent with the bias state when the data voltage was just written, thereby improving the stability of the operating state of the driving transistor T3 and reducing low-frequency flicker. At the same time, the scan signal SPX also turns on the anode reset transistor T7, resetting node N6 (i.e., the anode of the light-emitting element 30).

[0069] During time period T3, the light emission control signal Emit is at an active level (low level), the first light emission control transistor T1 and the second light emission control transistor T6 are turned on, and the driving transistor T3 is driven according to the driving current Id = (PVDD - Vdata). 2 Drive the light-emitting element 40 to emit light.

[0070] It can be observed that the gate of the bias transistor T8 and the gate of the anode reset transistor T7 receive the same scan signal SPX. Therefore, when the scan signal SPX is at an effective level (such as a low level), the bias transistor T8 and the anode reset transistor T7 are turned on simultaneously. While the bias transistor T8 biases the first and / or second terminals of the driving transistor T3, the anode reset transistor T7 resets the anode of the light-emitting element 30.

[0071] This is because when the bias transistor T8 biases the first and / or second terminals of the driving transistor T3, it is essentially biasing the drain of the driving transistor T3. At this time, although the second light-emitting control transistor T6 is turned off, there may be a certain leakage current in the second light-emitting control transistor T6. Therefore, if the anode of the light-emitting element 30 does not receive a reset signal, the light-emitting element 30 may be at risk of stealth lighting when the bias transistor T8 biases the first and / or second terminals of the driving transistor T3. However, when the bias transistor T8 biases the first and / or second terminals of the driving transistor T3, resetting the anode of the light-emitting element 30 can further ensure that the light-emitting element 30 does not emit light, but emits light during the light-emitting stage.

[0072] As can be seen from the above, the invalid level period of the Emit light emission control signal can correspond to the OBS1 period, T1 period, T2 period and OBS2 period, and the valid level period of the Emit light emission control signal can correspond to the T3 period (i.e. the light emission stage).

[0073] In the display panel, the Emit control signal scans each row of pixel circuits at a fixed frequency. In other words, the frequency of the Emit control signal received by each row of pixel circuits is fixed. Figure 6 A timing diagram showing the emission control signal Emit and the scan signal SPX received by different row pixel circuits is shown, as follows: Figure 6 As shown, we define a frame as the total time period during which the Emit control signal experiences one effective level period and one ineffective level period. A frame that includes the data writing phase is called a data writing frame. The total time period during which the pixel circuits of each row in the display panel complete the writing of data signals is called a data writing cycle. Thus, a data writing cycle of the display panel includes S frames for refreshing the screen, where S≥2. The S frames include a data writing frame and at least one hold frame. In the data writing frame, the pixel circuits write new data signals and display a new frame. In the hold frame, the pixel circuits refresh normally, but retain the data signals of the previous frame and display the previous frame.

[0074] Combination Figure 5 and Figure 6 As shown, in the data writing frame, the invalid level period of the Emit control signal corresponds to the pre-stage, and the valid level period corresponds to the light-emitting stage. The pre-stage includes the data writing stage (i.e., the T2 period). In the data writing stage, the data writing module 12 (including the data writing transistor T2) writes the data signal Vdata transmitted on the data signal line 20 corresponding to the pixel circuit 10 into the gate of the driving transistor T3. The pre-stage also includes the bias stage (i.e., the OBS1 period and the OBS2 period). In the bias stage, the bias module 17 (including the bias transistor T8) writes the bias signal DVH into the first and / or second poles of the driving transistor T3. At the same time, the reset module 14 (including the anode reset transistor T7) provides the reset signal Vref2 to node N6 (i.e., the anode of the light-emitting element 30).

[0075] like Figure 6 As shown, there is at least one hold frame in one data write cycle of the display panel. When a row of pixel circuits is in a hold frame, the pixel circuits in that row hold the data signal of the data write frame, while the other row of pixel circuits is in a data write frame. In other words, when a row of pixel circuits is in a data write frame, the other row of pixel circuits is in a hold frame. In this way, the writing of the data signal of each row of pixel circuits is completed, which completes one data write cycle.

[0076] like Figure 6 As shown, the invalid level period of the light emission control signal Emit in at least one holding frame during a data write cycle may include a bias phase. The bias module 17 (including bias transistor T8) writes the bias signal DVH to the first and / or second poles of the driving transistor T3. At the same time, the reset module 14 (including anode reset transistor T7) provides the reset signal Vref2 to node N6 (i.e., the anode of the light emission element 30). In this way, while improving the bias effect on the first and / or second poles of the driving transistor T3, it also enables the scan signal SPX to achieve high-precision frequency conversion, improves the flicker level during low-frequency display, and improves the afterimage and the brightness optical effect of the first frame.

[0077] It should be noted that during the pre-processing phase of the data write frame, although the scan signal SPX transitions to an active level in both the OBS1 and OBS2 periods, in practical applications, the scan signal SPX can be considered to have one pulse during the pre-processing phase. The bias phase is set during at least one hold frame's invalid Emit level period within a data write cycle; that is, during at least one hold frame's invalid Emit level period within a data write cycle, the scan signal SPX also has one pulse. Thus, if the scan signal SPX also has one pulse during n-1 hold frames' invalid Emit level periods within a data write cycle, then the scan signal SPX has n pulses within a data write cycle. The frequency of the scan signal SPX is n times the frequency of the Emit level, where n ≥ 2, and n is an integer.

[0078] In summary, in the pixel circuit 10, both the bias module 17 and the reset module 14 are selectively turned on under the control of the scan signal SPX (i.e., both are in the bias phase); within a data writing cycle, the pre-processing phase of the data writing frame is set with a bias phase, and at least one holding frame has an invalid level period of the light emission control signal Emit also set with a bias phase. The frequency of the scan signal SPX is n times the frequency of the light emission control signal Emit, where n ≥ 2 and n is an integer.

[0079] For example, based on the Emit control signal having a frequency of 120Hz, such as Figure 6 As shown, in the first half of a data write cycle, specifically in the pre-construction phase of the data write frame, the bias phase is set (including the OBS1 and OBS2 periods); in the second half of a data write cycle, specifically in the invalid level period of the Emit control signal in a hold frame, the bias phase is set; thus, the frequency of the scan signal SPX can be 240Hz, and at this time, n=2.

[0080] Based on the Emit control signal having a frequency of 120Hz, such as Figure 7 As shown, in the first 1 / 3 of a data write cycle, specifically in the pre-frame stage of the data write frame, the bias stage is set (including the OBS1 and OBS2 periods); in the second 1 / 3 of a data write cycle, specifically in the invalid level period of the Emit control signal in a hold frame, the bias stage is set; in the third 1 / 3 of a data write cycle, specifically in the invalid level period of the Emit control signal in a hold frame, the bias stage is set; thus, the frequency of the scan signal SPX can be 360Hz, at which point n=3.

[0081] Based on the Emit control signal having a frequency of 120Hz, such as Figure 8 As shown, in the first quarter cycle of a data write cycle, specifically in the pre-frame stage of the data write frame, a bias phase is set (including the OBS1 and OBS2 periods); in the second quarter cycle of a data write cycle, specifically in the invalid level period of the Emit control signal in a hold frame, a bias phase is set; in the third quarter cycle of a data write cycle, specifically in the invalid level period of the Emit control signal in a hold frame, a bias phase is set; in the fourth quarter cycle of a data write cycle, specifically in the invalid level period of the Emit control signal in a hold frame, a bias phase is set; thus, the frequency of the scan signal SPX can be achieved to 480Hz, where n=4.

[0082] However, the inventors discovered that with the demand for high-precision frequency conversion, the driving transistor T3 is biased multiple times during a data writing cycle of scanning the entire display panel to ensure the bias effect, which can lead to a replica phenomenon in the display panel.

[0083] Specifically, Figure 9 A top-view schematic diagram of a display panel is shown. The frequency of the scanning signal SPX of the display panel is twice the frequency of the light emission control signal Emit. It can be seen that when a black block is displayed in the upper half of the screen A1 area, a replicated black block will appear in the corresponding A1' area of ​​the lower half of the screen along the column direction of the pixel circuit, affecting the display effect.

[0084] The inventors further discovered that this is because, as Figure 10 As shown, Figure 10 The diagram, from top to bottom, shows the timing of partial signals received by the pixel circuit in region A1, the pixel circuit in region A1' (coordinated with the pixel circuit in region A1), and the pixel circuit in the normal display region A0. It can be seen that for the pixel circuit in the normal display region A0, during the pre-write frame phase of a data write cycle, there is no current I at the anode of the light-emitting element.Anode The pre-processing stage includes a data writing stage and a biasing stage. During the data writing stage, the data signal Vdata on the data signal line corresponding to the pixel circuit is written to the gate of the driving transistor. During the biasing stage, while biasing the first and / or second terminals of the driving transistor in the pixel circuit, the anode of the light-emitting element is reset. Then, the light-emitting stage of the data writing frame begins, where the pixel circuit drives the light-emitting element to emit light, and a current I appears at the anode of the light-emitting element. Anode In fact, the driving current Id of the driving transistor and the anode current I of the light-emitting element are... Anode Equal; during the effective level period of the corresponding Emit control signal in the hold frame of the same data write cycle, the light-emitting element continues to emit light, and the brightness of the light-emitting element is the same as the brightness of the light emitted during the data write frame; during the ineffective level period of the corresponding Emit control signal in at least one hold frame of the same data write cycle, a bias stage is set, and while the first and / or second poles of the driving transistor in the pixel circuit are biased, the anode of the light-emitting element is reset.

[0085] like Figure 10 As shown, for the pixel circuit in region A1, because a low grayscale needs to be displayed, a data write frame pre-stage is performed within a data write cycle. Specifically, during the data write stage, the driving current Id = (PVDD - Vdata) is used. 2 It can be seen that the data signal Vdata transmitted on the corresponding data signal line received by the pixel circuit should jump from low to high, thereby reducing the driving current Id, and thus reducing the anode current I of the light-emitting element. Anode When the gray level is reduced, the light-emitting element displays a low grayscale, such as black. At this time, for the pixel circuits in the A1' area that are in the same column but not in the same row, they are in the bias phase of the invalid level period of the corresponding light emission control signal Emit in a hold frame of a data write cycle. Since the pixel circuits in the A1' area that are in the same column but not in the same row will reset the anode of the light-emitting element during the bias phase, the light-emitting element corresponding to the pixel circuits in the A1' area that are in the same column but not in the same row will not be affected temporarily.

[0086] However, when the data signal Vdata transmitted on the data signal line corresponding to the pixel circuit in region A1 jumps from high to low, if the pixel circuit in region A1' (in the same column but not in the same row) happens to be at the effective level of the Emit light emission control signal in a hold frame of a data write cycle, then since the pixel circuits in regions A1 and A1' are in the same column and correspond to the same data signal line, and the data signal Vdata transmitted on that data signal line jumps from high to low, the projection of that data signal line onto the anode of the light-emitting element corresponding to the pixel circuit in region A1' overlaps in a direction perpendicular to the plane of the display panel. This will couple with the anode of the light-emitting element corresponding to the pixel circuit in region A1', causing the anode current I of the light-emitting element corresponding to the pixel circuit in region A1' to increase. Anode The grayscale level is reduced, which causes the light-emitting element corresponding to the pixel circuit in region A1' to replicate the low grayscale display of region A1, continuously dimming until the pixel circuit in region A1' reaches the next bias stage, resetting the anode of the light-emitting element.

[0087] For ease of understanding, Figure 11 A partial layout diagram of a display panel is shown. It can be seen that the data signal lines 30 (specifically data1 and data2 in the figure) and the anodes of the light-emitting elements are projected and overlapped in a direction perpendicular to the plane of the display panel. Therefore, when the data signal Vdata transmitted on the data signal line 30 jumps from high to low, it will have a coupling effect on the anode current of the light-emitting elements whose projections overlap in a direction perpendicular to the plane of the display panel. Moreover, the pixel circuits corresponding to these light-emitting elements have just switched from the bias stage to the light-emitting stage.

[0088] Based on this, the embodiments of this application propose, as follows: Figure 12 As shown, the driving method for the display panel in one data write cycle includes:

[0089] S10: When the pixel circuit in the i-th row is in the data writing stage, detect whether the data signal provided to the data signal line corresponding to each column pixel circuit in the i-th row is greater than the preset threshold.

[0090] Understandably, based on the driving current Id = (PVDD - Vdata) 2 The larger the data signal Vdata, the smaller the driving current Id. When the data signal Vdata is greater than a certain preset threshold, the driving current Id is small enough to make the light-emitting element driven by the i-th row pixel circuit display a low grayscale, such as black.

[0091] S20: If the data signal provided to the data signal line corresponding to the pixel circuit in row i and column j is greater than the preset threshold, then the pixel circuit in row k and column j is queried. When the pixel circuit in row i is in the data writing stage, the pixel circuit in row k is in the bias stage of holding the frame.

[0092] S30: Detect whether the moment when the data signal provided to the data signal line corresponding to the pixel circuit in row i and column j jumps to a value lower than a preset threshold corresponds to the effective level period of the light emission control signal in the holding frame for the pixel circuit in row k and column j; if so, when the pixel circuit in row k is in the data writing stage, provide a compensation data signal that is less than the configured data signal to the data signal line corresponding to the pixel circuit in row k and column j.

[0093] As the foregoing analysis shows, if the data signal supplied to the data signal line corresponding to the i-th row and j-th column pixel circuit is greater than a preset threshold, meaning the light-emitting element driven by the i-th row and j-th column pixel circuit displays a low grayscale, then for the k-th row pixel circuit which is simultaneously in the bias phase of the hold frame, although the light-emitting element driven by the k-th row and j-th column pixel circuit will not be affected when the i-th row pixel circuit is in the data writing phase because the k-th row pixel circuit is in the bias phase of the hold frame, if the data signal supplied to the data signal line corresponding to the i-th row and j-th column pixel circuit jumps to a value lower than the preset threshold at the k-th row... When the pixel circuit in row j is at the effective level of the light emission control signal in the hold frame, the anode current of the light emission element driven by the pixel circuit in row j is affected by the data signal coupling provided by the data signal line corresponding to the pixel circuit in row i (that is, the data signal line corresponding to the pixel circuit in row k j) and the light emission element driven by the pixel circuit in row k j. As a result, the light emission element driven by the pixel circuit in row k j also displays a low grayscale, replicating the display of the light emission element driven by the pixel circuit in row i j.

[0094] Based on this, when the pixel circuit in the k-th row is in the data writing stage, a compensation data signal smaller than the configured data signal is provided to the data signal line corresponding to the pixel circuit in the k-th row and j-th column. This enables the light-emitting element driven by the pixel circuit in the k-th row and j-th column to display a higher grayscale, visually compensating for the low grayscale display of the light-emitting element driven by the pixel circuit in the k-th row and j-th column, thus improving the display effect.

[0095] To more vividly demonstrate the compensation of the replicated area by the display panel driving method provided in the embodiments of this application, such as Figure 13As shown, at time t1, the display panel displays a low grayscale because the pixel circuit in area A1 drives the corresponding light-emitting element to display a low grayscale, and when the data signal provided by the data signal line corresponding to the pixel circuit in area A1 jumps from high to low, the pixel circuit in area A1' is at the effective level of the light emission control signal Emit in the hold frame, causing area A2 to replicate the low grayscale of area A1. Then, at time t2, the display panel provides a compensation data signal smaller than the configured data signal to the pixel circuit in area A2 when the pixel circuit in area A2 is in the data writing stage, enabling the pixel circuit in area A2 to drive the corresponding light-emitting element to display a higher grayscale and brighter brightness. Thus, visually, the light-emitting element in area A2 displays normal brightness and does not display a low grayscale.

[0096] like Figure 14 As shown, during the effective level (low level) of the control signal TE, the display panel scans the pixel circuits of each row and writes data signals Vdata to each row of pixel circuits. It can be seen that in the A1 area, the data signal Vdata is at a high level, causing the pixel circuit in the A1 area to drive the corresponding light-emitting element to display a low grayscale, causing the light-emitting element driven by the pixel circuit in the A2 area to replicate the low grayscale. When the pixel circuit in the A2 area is scanned, a compensation data signal less than the configured data signal is provided, causing the pixel circuit in the A2 area to drive the corresponding light-emitting element to display a higher grayscale for compensation.

[0097] It is understandable that if the invalid level period of the Emit control signal in a hold frame of a data write cycle includes the bias phase, then the frequency of the scan signal SPX is twice the frequency of the Emit control signal. When the A1 area of ​​the display panel displays a low grayscale, an A1' area will replicate the low grayscale of the A1 area. Furthermore, if the various bias phases within a data write cycle are set at equal time intervals, then the A1 area and the A1' area are located in the upper and lower halves of the screen, respectively. Figure 9 As shown.

[0098] Similarly, if the invalid level period of the Emit control signal in the two holding frames of a data write cycle includes the bias phase, then the frequency of the scan signal SPX is three times the frequency of the Emit control signal. When the A1 area of ​​the display panel displays a low grayscale, two A1' areas will replicate the low grayscale of the A1 area. Furthermore, if the time intervals of each bias phase in a data write cycle are set equally, then the A1 area and the two A1' areas are located in the upper, middle, and lower 1 / 3 of the screen, respectively.

[0099] If the invalid level period of the Emit control signal in the three holding frames of a data write cycle includes the bias phase, then the frequency of the scan signal SPX is 4 times the frequency of the Emit control signal. When the A1 area of ​​the display panel displays a low grayscale, there will be three A1' areas that replicate the low grayscale of the A1 area. Furthermore, if the time intervals of each bias phase in a data write cycle are set equally, then the A1 area and the three A1' areas are respectively located in the upper, upper middle, lower middle, and lower 1 / 4 of the screen.

[0100] Similarly, if the invalid level period of the Emit control signal in the n-1 hold frames of a data write cycle includes the bias phase, then the frequency of the scan signal SPX is n times the frequency of the Emit control signal. When the A1 area of ​​the display panel displays a low grayscale, there will be n-1 A1' areas to replicate the low grayscale of the A1 area.

[0101] That is, when it is detected that the data signal provided to the data signal line corresponding to the i-th row and j-th column pixel circuit is greater than a preset threshold, the n-1 row pixel circuit will be in the bias stage of the hold frame, and the k-th row pixel circuit is one of the n-1 row pixel circuits; then, whether the moment when it is detected that the data signal provided to the data signal line corresponding to the i-th row and j-th column pixel circuit jumps to a value lower than the preset threshold corresponds to the n-1 row and j-th column pixel circuit being in the effective level period of the Emit light emission control signal in the hold frame, if so, when the n-1 row pixel circuit is in the data writing stage, a compensation data signal less than the configured data signal is provided to the data signal line corresponding to the n-1 row and j-th column pixel circuit.

[0102] Optionally, in some embodiments of this application, such as Figure 15 As shown, when the pixel circuit in the k-th row is in the data writing stage, providing a compensation data signal that is less than the configured data signal to the data signal line corresponding to the pixel circuit in the k-th row and j-th column includes:

[0103] S31: Obtain the gray level and gray value of the light-emitting element driven by the pixel circuit in the k-th row and j-th column.

[0104] Understandably, based on the driving current Id = (PVDD - Vdata) 2 The data signal Vdata received by the pixel circuit corresponds one-to-one with the driving current Id of the light-emitting element, and the driving current Id of the light-emitting element corresponds one-to-one with the display brightness of the light-emitting element. Therefore, the data signal Vdata received by the pixel circuit corresponds one-to-one with the display brightness of the light-emitting element. Thus, in the display panel, the data signal can be represented by grayscale, which directly corresponds to the display brightness of the light-emitting element.

[0105] The brightness of the display panel can be divided into different grayscale levels, as shown in Table 1 below, which lists 10 grayscale levels from Band 0 to Band 9. Band 0 corresponds to a display brightness of 0 nit-2 nit, Band 1 corresponds to a display brightness of 0 nit-5 nit, Band 2 corresponds to a display brightness of 0 nit-10 nit, Band 3 corresponds to a display brightness of 0 nit-20 nit, Band 4 corresponds to a display brightness of 0 nit-60 nit, Band 5 corresponds to a display brightness of 0 nit-90 nit, Band 6 corresponds to a display brightness of 0 nit-90.1 nit, Band 7 corresponds to a display brightness of 0 nit-200 nit, Band 8 corresponds to a display brightness of 0 nit-500 nit, and Band 9 corresponds to a display brightness of 0 nit-800 nit. Each grayscale level has a grayscale value of 0-255. Only a portion of the grayscale values ​​are listed in Table 1.

[0106] Table 1 shows the 10 grayscale levels on the display panel.

[0107]

[0108]

[0109]

[0110] S32: Determine whether the grayscale level to which the current brightness of the light-emitting element driven by the pixel circuit in row k and column j belongs is in the preset low brightness area.

[0111] If so, then a compensation data signal smaller than the configured data signal is provided to the pixel circuit in the k-th row and j-th column according to the first method;

[0112] If not, then a compensation data signal smaller than the configured data signal is provided to the pixel circuit in the k-th row and j-th column according to the second method.

[0113] It is understandable that if the grayscale level to which the current brightness of the light-emitting element driven by the pixel circuit in row k and column j belongs is in a preset low brightness region, then the effect of the light-emitting element driven by the pixel circuit in row k and column j continuously dimming due to the data signal provided by the data signal line corresponding to the pixel circuit in row i and column j (i.e., the data signal line corresponding to the pixel circuit in row k and column j) jumping to below the preset threshold (i.e., jumping from high to low) is more obvious. If the grayscale level to which the current brightness of the light-emitting element driven by the pixel circuit in row k and column j belongs is in a high brightness region, then the effect of the light-emitting element driven by the pixel circuit in row k and column j continuously dimming due to the data signal provided by the data signal line corresponding to the pixel circuit in row i and column j (i.e., the data signal line corresponding to the pixel circuit in row k and column j) jumping to below the preset threshold (i.e., jumping from high to low) is relatively small. Therefore, in this embodiment, different methods are used to provide compensation data signals smaller than the configured data signals to the pixel circuit in row k and column j to avoid poor compensation brightness or over-compensation, thereby further improving the display effect.

[0114] Optionally, the preset low-brightness areas can be Band0-Band2 in Table 1, i.e., below 10 nits.

[0115] The inventors further discovered that, at each grayscale level, if the current brightness of the light-emitting element driven by the pixel circuit in row k and column j is less than or equal to a certain grayscale value, then a compensation data signal with a larger grayscale value than the configured data signal needs to be provided to the pixel circuit in row k and column j to offset the effect of the light-emitting element driven by the pixel circuit in row k and column j continuously dimming caused by the data signal provided by the data signal line corresponding to the pixel circuit in row i and column j jumping to a value lower than a preset threshold (i.e., jumping from high to low). If the current grayscale of the light-emitting element driven by the pixel circuit in row k and column j is greater than a certain grayscale value, then a compensation data signal with a smaller grayscale value than the configured data signal needs to be provided to the pixel circuit in row k and column j to offset the effect of the light-emitting element driven by the pixel circuit in row k and column j continuously dimming caused by the data signal provided by the data signal line corresponding to the pixel circuit in row i and column j jumping to a value lower than a preset threshold (i.e., jumping from high to low).

[0116] Based on this, optionally, in some embodiments of this application, providing a compensation data signal smaller than the configured data signal to the pixel circuit in the k-th row and j-th column according to the first method includes:

[0117] S311: Determine whether the grayscale value of the current brightness of the light-emitting element driven by the pixel circuit in the k-th row and j-th column is less than or equal to the grayscale value of the preset brightness in the same grayscale level.

[0118] If so, then provide a compensation data signal of less than 2 gray levels of the configured data signal to the pixel circuit in the k-th row and j-th column;

[0119] If not, then provide a compensation data signal of less than 1 gray level to the pixel circuit in the k-th row and j-th column.

[0120] Optionally, the preset brightness can be 0.02 nit. In this embodiment, it is determined whether the grayscale value of the current brightness of the light-emitting element driven by the pixel circuit in the k-th row and j-th column is less than or equal to the grayscale value corresponding to 0.02 nit in the same grayscale level. For example, in the Band0 grayscale level in Table 1, 0.02 nit brightness corresponds to 32 grayscale levels. If yes, a compensation data signal of 2 grayscale levels less than the configured data signal is provided to the pixel circuit in the k-th row and j-th column; if no, a compensation data signal of 1 grayscale level less than the configured data signal is provided to the pixel circuit in the k-th row and j-th column. The 1 and 2 grayscale levels of the compensation are experimentally verified values.

[0121] It should be noted that when providing a compensation data signal with a value smaller than the configured data signal to the pixel circuit in row k and column j, overcompensation must be prevented. That is, if a compensation data signal with a large grayscale value smaller than the configured data signal is provided to the pixel circuit in row k and column j, the brightness of the light-emitting element driven by the pixel circuit in row k and column j will actually increase, which will also affect the display effect. Therefore, as long as a compensation data signal with a suitable grayscale value smaller than the configured data signal is provided to the pixel circuit in row k and column j, the effect of the light-emitting element driven by the pixel circuit in row k and column j continuously dimming caused by the data signal provided by the data signal line corresponding to the pixel circuit in row i and column j jumping to a value lower than the preset threshold (i.e., jumping from high to low) can be offset.

[0122] Specifically, the grayscale value of the current brightness of the light-emitting element driven by the pixel circuit in the k-th row and j-th column is in the Band0 grayscale range in Table 1 and is the 32 grayscale value corresponding to a brightness of 0.02 nit. Figures 16a-16f The diagram shows the display brightness of the display panel after providing compensation data signals of gray levels 0, 1, 2, 3, 4, and 5 (less than the configured data signal) to the pixel circuit in the k-th row and j-th column. It can be seen that when compensating for a gray level of 1, the A1' area can still be faintly seen as a low gray level area. When compensating for gray levels 3, 4, and 5, the A1' area has become a high gray level area, i.e., a high brightness area, indicating overcompensation. When compensating for a gray level of 2, the A1' area is no longer visible.

[0123] As previously known, if the current brightness of the light-emitting element driven by the pixel circuit in row k and column j belongs to a high-brightness grayscale region, then the effect of the light-emitting element driven by the pixel circuit in row k and column j continuously dimming due to the data signal provided by the data signal line corresponding to the pixel circuit in row i and column j (i.e., the data signal line corresponding to the pixel circuit in row k and column j) jumping to below a preset threshold (i.e., jumping from high to low) is relatively small. Based on this, optionally, in some embodiments of this application, providing a compensation data signal less than the configured data signal to the pixel circuit in row k and column j according to the second method includes:

[0124] S312: Provides a compensation data signal of less than 1 gray level to the pixel circuit in the k-th row and j-th column.

[0125] Among them, the compensated gray level 1 is the value verified by experiments.

[0126] In this embodiment, if the current brightness of the light-emitting element driven by the pixel circuit in row k and column j belongs to a gray level in the high brightness region, the effect of the light-emitting element driven by the pixel circuit in row k and column j continuously dimming due to the data signal provided by the data signal line corresponding to the pixel circuit in row i and column j jumping to a value lower than the preset threshold (i.e., jumping from high to low) is relatively small. Therefore, directly providing a compensation data signal with a gray level less than the configured data signal to the pixel circuit in row k and column j can achieve a better compensation effect.

[0127] like Figure 9 As shown, the display panel includes a display area AA and a non-display area NA that at least partially surrounds the display area. The non-display area NA includes a frame region PA located on at least one side of the display area AA along the pixel circuit column direction. In practical applications, the frame region PA also includes pixel circuits. Figure 17 This diagram illustrates a timing sequence of data signals transmitted by a data signal line during one data write cycle. It shows that, under the control of the control signal TE, the data signal line distinguishes between providing data signals to the pixel circuits in the frame area PA and the pixel circuits in the display area AA. Furthermore, since the frame area PA is a non-display area, the data signal Vdata provided by the data signal line to the pixel circuits in the frame area PA is a low grayscale (i.e., high level) data signal, while the data signal provided to the pixel circuits in the display area AA is a high grayscale (i.e., low level) data signal, causing the pixel circuits in the display area AA to drive the corresponding light-emitting elements to display different grayscale levels.

[0128] It is understandable that, similar to areas A1 and A1', because the pixel circuit within the frame area PA receives low grayscale (i.e., high-level) data signals from the data signal lines, and these signals enter the display area AA from the frame area PA, the data signal lines switch from providing low grayscale (i.e., high-level, greater than a preset threshold) data signals to providing high grayscale (i.e., low-level, less than a preset threshold) data signals. Therefore, as... Figure 9 As shown, the display area AA includes shadow box regions PA' extending along the pixel circuit row direction. Furthermore, the frequency of the scan signal SPX is n times the frequency of the emission control signal Emit, where n ≥ 2 and n is an integer. Therefore, there are n-1 shadow box regions PA' in the display area AA. If the offset stages within a data write cycle are set at equal time intervals, then the n-1 shadow box regions PA' will equally divide the display area AA into n intervals along the pixel circuit column direction.

[0129] Specifically, when the pixel circuit of the frame region PA is in the data writing stage, the data signal provided by the data signal line corresponding to the pixel circuit of the frame region PA is greater than the preset threshold. At the same time, the pixel circuit of the shadow frame region PA' is in the bias stage of the holding frame. Furthermore, when the data signal provided by the data signal line corresponding to the pixel circuit of the frame region PA jumps to a level lower than the preset threshold, the shadow frame region PA' is in the effective level period of the light emission control signal in the holding frame, and the shadow frame region PA' displays a low grayscale.

[0130] Based on this, the driving method for the display panel in a data write cycle also includes:

[0131] S40: When the pixel circuit of the shadow frame area PA' of the display area AA is in the data writing stage, a compensation data signal with a fixed grayscale value lower than the configured data signal is provided to the pixel circuit of the shadow frame area PA' of the display area AA.

[0132] It should be noted that because the data signal provided to the pixel circuit of the frame area PA is a fixed low grayscale (i.e., high level) data signal, the low grayscale displayed by the light-emitting element of the shadow frame area PA' of the display area AA is also fixed. Therefore, when the pixel circuit of the shadow frame area PA' of the display area AA is in the data writing stage, providing a compensation data signal with a fixed grayscale value lower than the configured data signal to the pixel circuit of the shadow frame area PA' of the display area AA can achieve a better compensation effect.

[0133] exist Figure 9 In this example, if the frequency of the scanning signal SPX is twice that of the light emission control signal Emit (i.e., n=2), a shadow frame area PA' will be formed in the middle of the display area AA for the frame area PA located at the top of the display area AA.

[0134] like Figure 9As shown, the non-display area NA includes a corner region RA located at any corner of the display area AA. The display area AA has a first side Z1 extending along the pixel circuit column direction, and the corner region RA is located on one side of the first side Z1 along the pixel circuit column direction. It can be seen that the display area AA has two first sides Z1, and the non-display area NA can include four corner regions RA' located at the four corners of the display area AA.

[0135] In practical applications, the corner area RA also includes pixel circuits. Since the corner area RA is a non-display area, the data signal Vdata provided by the data signal line to the pixel circuit of the corner area RA is a low grayscale (i.e., high level) data signal. When the data signal line enters the display area AA from the corner area RA, it switches from providing a low grayscale (i.e., high level, greater than a preset threshold) data signal to providing a high grayscale (i.e., low level, lower than a preset threshold) data signal. Furthermore, the frequency of the scan signal SPX is n times the frequency of the emission control signal Emit, where n ≥ 2 and n is an integer. Therefore, similar to areas A1 and A1', as... Figure 9 As shown, the display area AA includes n-1 shadow corner regions RA' arranged along the first side Z1. If the offset stages within a data write cycle are set at equal time intervals, the n-1 shadow corner regions RA' will divide the first side Z1 into n segments at equal intervals along the pixel circuit column direction.

[0136] Specifically, when the pixel circuit of the corner region RA is in the data writing stage, the data signal provided by the data signal line corresponding to the pixel circuit of the corner region RA is greater than the preset threshold. At the same time, the pixel circuit of the shadow corner region RA is in the bias stage of the holding frame. Furthermore, when the data signal provided by the data signal line corresponding to the pixel circuit of the corner region RA jumps to a value lower than the preset threshold, the shadow corner region RA' is in the effective level period of the light emission control signal in the holding frame, and the shadow corner region RA' displays a low grayscale.

[0137] Based on this, the driving method for the display panel in a data write cycle also includes:

[0138] S50: When the pixel circuit of the shadow corner area RA' of the display area AA is in the data writing stage, a compensation data signal with a fixed gray level value smaller than the configured data signal is provided to the pixel circuit of the shadow corner area RA' of the display area AA.

[0139] It should be noted that because the data signal provided to the pixel circuit of the corner area RA is a fixed low grayscale (i.e., high level) data signal, the low grayscale displayed by the light-emitting element of the shadow corner area RA' of the display area AA is also fixed. Therefore, when the pixel circuit of the shadow corner area RA' of the display area AA is in the data writing stage, providing a compensation data signal with a fixed grayscale value lower than the configured data signal to the pixel circuit of the shadow corner area RA' of the display area AA can achieve a better compensation effect.

[0140] exist Figure 9 In the example where the frequency of the scanning signal SPX is twice that of the light emission control signal Emit (i.e., n=2), for the two corner regions RA located at the top of the display area AA, two shadow corner regions RA' will be formed in the middle region of the display area AA.

[0141] like Figure 9 As shown, the display area AA includes a hole area A2, which is used to house the under-display camera. In practical applications, the hole area A2 also includes pixel circuitry. Since the hole area A2 is used to house the under-display camera, the data signal provided by the data signal line to the pixel circuitry in the hole area A2 is a low grayscale (i.e., high level) data signal. Furthermore, when the data signal line enters the display area AA from the hole area A2, it switches from providing a low grayscale (i.e., high level, greater than a preset threshold) data signal to providing a high grayscale (i.e., low level, less than a preset threshold) data signal. Also, the frequency of the scan signal SPX is n times the frequency of the emission control signal Emit, where n ≥ 2 and n is an integer. Therefore, similar to areas A1 and A1', as... Figure 9 As shown, the display area also includes n-1 shadow hole regions A2'. If the offset stages within a data write cycle are set at equal time intervals, then the hole regions A2 and the n-1 shadow hole regions A2' are arranged sequentially at equal intervals along the pixel circuit column direction.

[0142] Specifically, when the pixel circuit of aperture region A2 is in the data writing stage, the data signal provided by the data signal line corresponding to the pixel circuit of aperture region A2 is greater than the preset threshold. At the same time, the pixel circuit of shadow aperture region A2' is in the bias stage of the holding frame. Furthermore, when the data signal provided by the data signal line corresponding to the pixel circuit of aperture region A2 jumps to a value lower than the preset threshold, the shadow aperture region A2' is in the effective level period of the light emission control signal in the holding frame, and the shadow aperture region A2' displays a low grayscale.

[0143] Based on this, the driving method for the display panel in a data write cycle also includes:

[0144] S60: When the pixel circuit of the shadow hole area A2' of the display area AA is in the data writing stage, a compensation data signal with a fixed grayscale value lower than the configured data signal is provided to the pixel circuit of the shadow hole area A2' of the display area AA.

[0145] It should be noted that because the data signal provided to the pixel circuit of the hole area A2 is a fixed low grayscale (i.e., high level) data signal, the low grayscale displayed by the light-emitting element of the shadow hole area A2' of the display area AA is also fixed. Therefore, when the pixel circuit of the shadow hole area A2' of the display area AA is in the data writing stage, providing a compensation data signal with a fixed grayscale value lower than the configured data signal to the pixel circuit of the shadow hole area A2' of the display area AA can achieve a better compensation effect.

[0146] exist Figure 9 In the example where the frequency of the scanning signal SPX is twice that of the light emission control signal Emit (i.e., n=2), when the hole area A2 is located in the upper half of the display panel, the shadow hole area A2' is located in the lower half of the display panel.

[0147] The inventors also discovered that, for example Figure 9 As shown, in the display panel, when area A1 displays a low grayscale (such as black), in addition to area A1' in the same column but not in the same row replicating the low grayscale of area A1, area A10' in the same column but not in the same row will also be highlighted.

[0148] This is because, such as Figure 18 As shown, Figure 18 The diagram, from top to bottom, shows the timing of partial signals received by the pixel circuit in region A1, the pixel circuit in region A10' (coordinated with the pixel circuit in region A1), and the pixel circuit in the normal display region A0. It can be seen that when the pixel circuit in the normal display region A0 is in a hold frame, as long as it is not in the bias phase, the anode current I of the light-emitting element... Anode The brightness of the light-emitting element remains unchanged, the same as the brightness when data is written to the frame.

[0149] like Figure 18As shown, for the pixel circuit in area A1, because it needs to display low grayscale, in the pre-stage of the data write frame of a data write cycle, specifically during the data write stage, the data signal Vdata transmitted on the corresponding data signal line should jump from low to high. At this time, for the pixel circuit in area A10' (in the same column but not in the same row), it is in the invalid level period of the corresponding light emission control signal Emit in a hold frame of a data write cycle, and does not correspond to the bias stage. Thus, the light emission element corresponding to the pixel circuit in area A10' (in the same column but not in the same row) is displaying the light emission brightness during its data write frame. Since the pixel circuit in area A1 and the corresponding pixel circuit in area A10' are in the same column and correspond to the same data signal line, and the data signal Vdata transmitted on this data signal line jumps from low to high, the projection of this data signal line and the anode of the light emission element corresponding to the pixel circuit in area A10' overlaps in the direction perpendicular to the plane of the display panel, thereby coupling the anode of the light emission element corresponding to the pixel circuit in area A10', causing the anode current I of the light emission element corresponding to the pixel circuit in area A10' to increase. Anode The light-emitting element corresponding to the pixel circuit in region A10' is raised, causing it to light up until the data signal Vdata transmitted on the data signal line jumps from high to low, at which point the light-emitting element corresponding to the pixel circuit in region A10' displays normally.

[0150] Similar to compensation for the data signal of the pixel circuit in region A1', such as Figure 19 As shown, the driving method for the display panel in a data write cycle also includes:

[0151] S70: When the pixel circuit in the i-th row enters the data writing stage, detect whether the data signal provided to the data signal line corresponding to each column pixel circuit in the i-th row has changed from below the preset threshold to above the preset threshold.

[0152] S80: If the data signal provided to the data signal line corresponding to the pixel circuit in row i and column j changes from below the preset threshold to above the preset threshold, then the pixel circuit in row h and column j is found. When the pixel circuit in row i enters the data writing stage, the pixel circuit in row h is in the invalid level period of the light emission control signal in the holding frame, and the pixel circuit in row h is not in the bias stage.

[0153] S90: When the pixel circuit in the h-th row is in the data writing stage, a compensation data signal greater than the configured data signal is provided to the data signal line corresponding to the pixel circuit in the h-th row and j-th column.

[0154] As the foregoing analysis shows, if the data signal supplied to the data signal line corresponding to the pixel circuit in row i and column j jumps from below a preset threshold to above a preset threshold, and the pixel circuit in row h and column j, which is in the same column but not in the same row, is in the invalid level period of the light emission control signal in the hold frame, and the pixel circuit in row h is not in the bias stage, then the anode current of the light-emitting element corresponding to the pixel circuit in row h and column j will be affected by the coupling effect of the data signal supplied to the pixel circuit in row i and column j jumping from below a preset threshold to above a preset threshold, causing the light-emitting element corresponding to the pixel circuit in row h and column j to light up. Based on this, when the pixel circuit in row h is in the data writing stage, a compensation data signal greater than the configured data signal is supplied to the data signal line corresponding to the pixel circuit in row h and column j, thereby causing the light-emitting element driven by the pixel circuit in row h and column j to display a low grayscale, that is, to appear dark, visually compensating for the light-emitting element driven by the pixel circuit in row h and column j to light up, thus improving the display effect.

[0155] Accordingly, embodiments of this application also provide a display device. Figure 20 A plan view of a display device provided in an embodiment of this application is shown, such as... Figure 20 As shown, the display device 300 includes a display panel 100 and a driver integrated circuit 200. In practical applications, the driver integrated circuit 200 is bent to the back of the display panel 100. The driver integrated circuit 200 drives the display panel 100 to display in each data writing cycle using the display panel driving method provided in any of the above embodiments.

[0156] The display device 300 can be any electronic device with display capabilities, such as a touch screen, mobile phone, tablet computer, laptop computer, e-reader, or television.

[0157] The various parts of this manual are described in a combination of parallel and progressive methods. Each part focuses on the differences between the other parts, and the same or similar parts can be referred to each other.

[0158] The features described above regarding the disclosed embodiments can be substituted or combined with each other to enable those skilled in the art to implement or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A driving method for a display panel, characterized in that, The display panel includes an array of pixel circuits, light-emitting elements driven by the pixel circuits, and data signal lines that transmit data signals to each column of the pixel circuits. The pixel circuit includes a driving module, a data writing module, a light emission control module, a bias module, and a reset module. The driving module includes a driving transistor. The light emission control module selectively causes the light-emitting element to enter the light emission stage under the control of the light emission control signal. One data write cycle of the display panel includes S frames for refreshing the screen, where S≥2. One frame includes an effective level period and an ineffective level period of the light emission control signal. The S frames include a data write frame and at least one hold frame. In the data writing frame, the invalid level period of the light emission control signal corresponds to the pre-stage, and the valid level period corresponds to the light emission stage; the pre-stage includes a data writing stage, in which the data writing module writes the data signal transmitted on the data signal line corresponding to the pixel circuit into the gate of the driving transistor. The invalid level period of the light emission control signal in the pre-stage and at least one of the holding frames includes a bias stage, in which the bias module writes a bias signal to the first and / or second pole of the driving transistor, and the reset module provides a reset signal to the light emission element. The driving method for the display panel in one data write cycle includes: When the pixel circuit in the i-th row is in the data writing stage, it is detected whether the data signal provided to the data signal line corresponding to each column of the pixel circuit in the i-th row is greater than a preset threshold. If the data signal provided to the data signal line corresponding to the pixel circuit in row i and column j is greater than the preset threshold, then the pixel circuit in row k and column j is queried. When the pixel circuit in row i is in the data writing stage, the pixel circuit in row k is in the bias stage of the holding frame. If the moment when the data signal provided to the data signal line corresponding to the pixel circuit in row i and column j jumps to a value lower than the preset threshold corresponds to the effective level period of the light emission control signal in the holding frame for the pixel circuit in row k and column j, then when the pixel circuit in row k is in the data writing stage, a compensation data signal less than the configured data signal is provided to the data signal line corresponding to the pixel circuit in row k and column j.

2. The driving method for the display panel according to claim 1, characterized in that, When the pixel circuit in row k is in the data writing phase, providing a compensation data signal smaller than the configured data signal to the data signal line corresponding to the pixel circuit in row k and column j includes: Obtain the gray level and gray level value of the light-emitting element driven by the pixel circuit in the kth row and jth column; Determine whether the grayscale level to which the current brightness of the light-emitting element driven by the pixel circuit in the k-th row and j-th column belongs is in a preset low brightness region; If so, then a compensation data signal smaller than the configured data signal is provided to the pixel circuit in the k-th row and j-th column according to the first method; If not, then a compensation data signal smaller than the configured data signal is provided to the pixel circuit in the k-th row and j-th column according to the second method.

3. The driving method for the display panel according to claim 2, characterized in that, The compensation data signal provided to the pixel circuit in the k-th row and j-th column according to the first method, which is less than the configured data signal, includes: Determine whether the grayscale value of the current brightness of the light-emitting element driven by the pixel circuit in the kth row and jth column is less than or equal to the grayscale value of the preset brightness in the same grayscale level. If so, then a compensation data signal with a gray level less than 2 gray levels of the configured data signal is provided to the pixel circuit in the k-th row and j-th column; If not, then a compensation data signal of less than 1 gray level of the configured data signal is provided to the pixel circuit in the k-th row and j-th column.

4. The driving method for the display panel according to claim 2, characterized in that, The compensation data signal provided to the pixel circuit in the k-th row and j-th column according to the second method, which is less than the configured data signal, includes: Provide a compensation data signal of less than 1 gray level to the pixel circuit in the k-th row and j-th column.

5. The driving method for the display panel according to claim 3, characterized in that, The preset brightness is 0.02 nits.

6. The driving method for a display panel according to claim 1, characterized in that, In the pixel circuit, the bias module and the reset module are selectively turned on under the control of the same scanning signal. The frequency of the scanning signal is n times the frequency of the light emission control signal, where n ≥ 2 and n is an integer. The time intervals of each bias stage within a data writing cycle are equal. The display panel includes a display area and a non-display area that at least partially surrounds the display area, the non-display area including a frame region located on at least one side of the display area along the pixel circuit column direction; The display area includes a shadow frame region extending along the row direction of the pixel circuit. There are n-1 shadow frame regions, and the n-1 shadow frame regions divide the display area into n intervals at equal intervals along the column direction of the pixel circuit. The driving method for the display panel in one data write cycle also includes: When the pixel circuit in the shadow frame region of the display area is in the data writing stage, a compensation data signal with a smaller grayscale value than the configured data signal is provided to the pixel circuit in the shadow frame region of the display area.

7. The driving method for a display panel according to claim 1, characterized in that, In the pixel circuit, the bias module and the reset module are selectively turned on under the control of the same scanning signal. The frequency of the scanning signal is n times the frequency of the light emission control signal, where n ≥ 2 and n is an integer. The time intervals of each bias stage within a data writing cycle are equal. The display panel includes a display area and a non-display area that at least partially surrounds the display area, the non-display area including a corner region located at any corner of the display area; The display area has a first side extending along the direction of the pixel circuit column, the corner region is located on one side of the first side along the direction of the pixel circuit column, and the display area includes n-1 shadow corner regions arranged along the first side, the n-1 shadow corner regions dividing the first side into n segments at equal intervals along the direction of the pixel circuit column; The driving method for the display panel in one data write cycle also includes: When the pixel circuit in the shadow corner region of the display area is in the data writing stage, a compensation data signal with a smaller grayscale value than the configured data signal is provided to the pixel circuit in the shadow corner region of the display area.

8. The driving method for a display panel according to claim 1, characterized in that, In the pixel circuit, both the bias module and the reset module are selectively activated under the control of the scan signal. The frequency of the scan signal is n times the frequency of the light emission control signal, where n ≥ 2 and n is an integer. The time intervals between each bias stage within a data writing cycle are equal. The display panel includes a display area, and the display area includes a hole area for setting an under-display camera. The display area further includes n-1 shadow hole regions, and the hole regions and the n-1 shadow hole regions are arranged sequentially at equal intervals along the direction of the pixel circuit column; The driving method for the display panel in one data write cycle also includes: When the pixel circuit in the shadow hole region of the display area is in the data writing stage, a compensation data signal with a smaller grayscale value than the configured data signal is provided to the pixel circuit in the shadow hole region of the display area.

9. The driving method for a display panel according to any one of claims 6-8, characterized in that, The frequency of the light emission control signal is 120Hz, and the frequency of the scanning signal is 240Hz, 360Hz, or 480Hz, where n=2, 3, or 4.

10. The driving method for a display panel according to claim 1, characterized in that, The driving method for the display panel in one data write cycle also includes: When the pixel circuit in the i-th row enters the data writing stage, it is detected whether the data signal provided to the data signal line corresponding to the pixel circuit in each column of the i-th row jumps from below the preset threshold to above the preset threshold. If the data signal provided to the data signal line corresponding to the pixel circuit in row i and column j changes from below the preset threshold to above the preset threshold, then the pixel circuit in row h and column j is found. When the pixel circuit in row i enters the data writing stage, the pixel circuit in row h is in the invalid level period of the light emission control signal in the holding frame, and the pixel circuit in row h is not in the bias stage. When the pixel circuit in row h is in the data writing stage, a compensation data signal greater than the configured data signal is provided to the data signal line corresponding to the pixel circuit in row h and column j.

11. A display device, characterized in that, It includes a display panel and a driver integrated circuit, wherein the driver integrated circuit drives the display panel to display in each data writing cycle using the driving method of the display panel according to any one of claims 1-10.

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