Array substrate, display panel

Abstract

Embodiments of the present application disclose an array substrate and a display panel, the array substrate comprising a substrate, a first wire and a second wire above the substrate, and the first wire and the second wire having an overlapping area in a film thickness direction; wherein a vertical distance between the first wire and the second wire in the overlapping area is greater than 3 microns; by increasing the vertical distance between the first wire and the second wire in the overlapping area, yield loss caused by electrostatic discharge breakdown is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate and a display panel. BACKGROUND

[0002] The problem of pressure drop is one of the important technical difficulties in the existing display panel. The current process mainly reduces the wiring impedance by setting multiple metal layers, but the overlapping position of different wirings of the array substrate at the wire changing position is prone to electro-static discharge (ESD) injury, which needs to be solved urgently.

[0003] Therefore, the existing array substrate has the technical problem of serious electro-static discharge at the overlapping position of different wirings. SUMMARY

[0004] Embodiments of the present application provide an array substrate and a display panel, which can alleviate the technical problem of serious electro-static discharge at the overlapping position of different wirings in the existing array substrate.

[0005] Embodiments of the present application provide an array substrate, comprising:

[0006] a substrate;

[0007] a first wiring and a second wiring located above the substrate, the first wiring and the second wiring have an overlapping area in the film thickness direction;

[0008] wherein, in the overlapping area, the vertical distance between the first wiring and the second wiring is greater than 3 microns.

[0009] Optionally, in some embodiments of the present application, comprising:

[0010] a substrate;

[0011] a second metal layer disposed on one side of the substrate, the second metal layer comprising a first pole and a second pole disposed in insulation;

[0012] a second planar layer disposed on the side of the second metal layer away from the substrate;

[0013] a third metal layer disposed on the side of the second planar layer away from the substrate, the third metal layer comprising a third pole and a fourth pole disposed in the same layer and insulation, the third pole being connected to the first pole through a first via hole penetrating at least the second planar layer, and the fourth pole being connected to the second pole through a second via hole penetrating at least the second planar layer

[0014] a third planar layer disposed on the side of the third metal layer away from the substrate;

[0015] a fourth metal layer disposed on a side of the third planar layer away from the substrate, the fourth metal layer comprising a fifth pole, the fifth pole connected to the third pole through a third via hole penetrating at least the third planar layer;

[0016] wherein the first pole, the third pole, and the fifth pole are connected to each other to form a first trace, the second pole and the fourth pole are connected to each other to form a second trace, the first trace and the second trace are arranged in a spaced manner, and the fifth pole and the second pole are arranged to have an overlapping area in a film thickness direction.

[0017] Optionally, in some embodiments of the present application, the first pole and the fourth pole are arranged to be misaligned in the film thickness direction, and the second pole and the third pole are arranged to be misaligned in the film thickness direction.

[0018] Optionally, in some embodiments of the present application, the present application comprises:

[0019] a second metal layer disposed on a side of the substrate, the second metal layer comprising a first pole and a second pole arranged in an insulating manner;

[0020] a second planar layer disposed on a side of the second metal layer away from the substrate, the second planar layer having a thickness ranging from 3 microns to 5 microns;

[0021] a third metal layer disposed on a side of the second planar layer away from the substrate, the third metal layer comprising a third pole and a fourth pole arranged in an insulating manner, the third pole connected to the first pole through a first via hole penetrating at least the second planar layer, and the fourth pole connected to the second pole through a second via hole penetrating at least the second planar layer;

[0022] wherein the first pole and the fourth pole are arranged to have the overlapping area in the film thickness direction, or the second pole and the third pole are arranged to have the overlapping area in the film thickness direction.

[0023] Optionally, in some embodiments of the present application, the second planar layer further comprises a first slot hole arranged in a continuous manner, the first slot hole penetrating the second planar layer, the first pole and the third pole connected through the first slot hole, and the first slot hole having a cross-sectional shape of any one of a square and an ellipse.

[0024] Optionally, in some embodiments of the present application, the second planar layer further comprises a second slot hole arranged in a continuous manner, the second slot hole penetrating the second planar layer, the second pole and the fourth pole connected through the second slot hole, and the second slot hole having a cross-sectional shape of any one of a square and an ellipse.

[0025] Optionally, in some embodiments of this application, the cross-sectional shape of the first slot and the second slot is either rectangular or circular.

[0026] Optionally, in some embodiments of this application, the second metal layer further includes a first contact electrode, the first electrode and the second electrode being co-layered with and insulated from the first contact electrode; the third metal layer further includes a second contact electrode, the third electrode and the fourth electrode being co-layered with and insulated from the second contact electrode; the fourth metal layer further includes a third contact electrode, and the fifth electrode being co-layered with and insulated from the third contact electrode; wherein the first contact electrode and the second contact electrode are connected through a fourth via penetrating the second planarization layer, and the second contact electrode and the third contact electrode are connected through a fifth via penetrating the third planarization layer.

[0027] Optionally, in some embodiments of this application,

[0028] An active layer is disposed on the substrate;

[0029] A first gate insulating layer is disposed on the side of the active layer away from the substrate;

[0030] A first gate is disposed on the side of the first gate insulating layer away from the substrate;

[0031] A second gate insulating layer is disposed on the side of the first gate away from the substrate;

[0032] The second gate is disposed on the side of the second gate insulating layer away from the substrate;

[0033] An interlayer insulating layer is disposed on the side of the second gate away from the substrate;

[0034] A first metal layer is disposed on the side of the interlayer insulating layer away from the substrate. The first metal layer includes a source and a drain disposed at intervals, and the source and drain are respectively connected to the active layer.

[0035] Optionally, in some embodiments of this application, the first metal layer and the second metal layer are disposed in the same layer; or

[0036] The array substrate includes a first planarization layer disposed on the side of the first metal layer opposite to the substrate, and a second metal layer disposed on the side of the first planarization layer opposite to the substrate.

[0037] Embodiments of this application provide a display panel including an array substrate as described in any of the above embodiments.

[0038] Beneficial effect: increase the vertical distance of the first trace and the second trace in the overlapping area, so that the vertical distance is greater than 3 microns, thereby alleviating the technical problem of serious electrostatic discharge of different traces in the overlapping area of the existing array substrate. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0040] Figure 1 is the first cross-sectional schematic diagram of the array substrate provided by the present application;

[0041] Figure 2 is the top view schematic diagram of the slot hole in the array substrate provided by the present application;

[0042] Figure 3 is the top view schematic diagram of the first via hole and the second via hole in the array substrate provided by the present application;

[0043] Figure 4 is the second cross-sectional schematic diagram of the array substrate provided by the present application;

[0044] Figure 5 is the third cross-sectional schematic diagram of the array substrate provided by the present application.

[0045] Explanation of reference signs:

[0046]

[0047] DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the present application will be described below in combination with the drawings in the embodiments of the present application. The technical solutions described below are only used to explain and illustrate the idea of the present application, and should not be regarded as limiting the protection scope of the present application.

[0049] In addition, the terms "first", "second" and similar words do not represent any order, quantity or importance, but are only used to distinguish different technical features. The term "multiple" and similar words represent two or more, unless otherwise explicitly limited.

[0050] Please refer to Figure 1 , Figure 2 , Figure 3The array substrate 1 provided in the present application includes a substrate 10, a first trace and a second trace located above the substrate, and the first trace and the second trace have an overlapping area in the film thickness direction, wherein the vertical distance between the first trace and the second trace in the overlapping area is greater than 3 microns.

[0051] In the present embodiment, the vertical distance between the first trace and the second trace in the overlapping area is increased to be greater than 3 microns, thereby improving the yield loss caused by electrostatic discharge breakdown.

[0052] The technical solutions of the present application will be described in combination with specific embodiments.

[0053] The embodiments of the present application mainly take Figure 1 Mini LED and Micro LED as examples for illustration, and the technical solutions are also applicable to other display panels; for example, when the display panel is in a 3T1C architecture or other architectures with more wiring space of the first metal layer, the scheme as shown in Figure 4 may be adopted, that is, a part of the first trace and the second trace is arranged in the same layer as the first metal layer, so that the fourth metal layer is not needed, thereby reducing the overall film thickness of the display panel.

[0054] When the display panel is in a 7T1C or 13T2C architecture or other architectures with less wiring space available for the first metal layer, the scheme as shown in Figure 1 may be adopted.

[0055] Please refer to Figure 1 , Figure 2 , Figure 3 In one embodiment, the array substrate 1 includes a substrate 10, an array driving layer 20, a first planar layer 60, a second metal layer 40, a second planar layer 70, a third metal layer 50, a third planar layer 110, a fourth metal layer 100, the first metal layer 30 includes a source electrode 301 and a drain electrode 302 arranged in the same layer, the second metal layer 40 includes a first electrode 303 and a second electrode 304 arranged in the same layer and insulated, the third metal layer 50 includes a third electrode 402 and a fourth electrode 403 arranged in the same layer and insulated, the third electrode 402 is connected to the first electrode 303 through a first via hole 150 penetrating through the second planar layer 60, the fourth electrode 403 is connected to the second electrode 304 through a second via hole 160 penetrating through the second planar layer 60, the fourth metal layer 100 includes a fifth electrode 502, the fifth electrode 502 is connected to the third electrode 402 through a third via hole penetrating through the third planar layer 70; wherein the first electrode 303, the third electrode 402 and the fifth electrode 502 are connected to each other to form a first trace, the second electrode 304 and the fourth electrode 403 are connected to each other to form a second trace, the first trace and the second trace are arranged in a spaced manner, and the fifth electrode 502 and the second electrode 304 have an overlapping area 2 in the film thickness direction.

[0056] In the embodiment, the first trace includes the first pole 303, the third pole 402 and the fifth pole 502 located at different layers and connected with each other, and the second trace includes the second pole 304 and the fourth pole 403 located at different layers and connected with each other. By arranging the fifth pole 502 of the first trace to the fourth metal layer 100, the distance between the fifth pole 502 and the second pole 304 in the overlapping area 2 is increased, thereby improving the yield loss caused by electrostatic discharge breakdown.

[0057] In an embodiment, the first trace is one of the high-frequency power line and the low-frequency power line, and the second trace is the other of the high-frequency power line and the low-frequency power line.

[0058] In an embodiment, the first pole 303 and the fourth pole 403 are arranged in a staggered manner in the film thickness direction, and the second pole 304 and the third pole 402 are arranged in a staggered manner in the film thickness direction.

[0059] It can be understood that the portions of the first trace located at the second metal layer 40 and the third metal layer 50 are arranged in a staggered manner with the portions of the second trace located at the second metal layer 40 and the third metal layer 50. Since there is no overlap between the first trace and the second trace at the second metal layer 40 and the third metal layer 50, there is no electrostatic discharge breakdown defect.

[0060] It should be noted that the electrostatic discharge phenomenon only exists between the fifth pole 502 and the second pole 304 in the overlapping area 2. However, since the fifth pole 502 in the overlapping area 2 is located at the fourth metal layer 100, and the second pole 304 is located at the second metal layer 40, the second flat layer 70 and the third flat layer 110 are arranged between the fifth pole 502 and the second pole 304, and the vertical distance between the fifth pole 502 and the second pole 304 is large, thereby alleviating the yield loss caused by electrostatic discharge breakdown.

[0061] In an embodiment, the thickness of the second flat layer 60 can be greater than the thickness of the third flat layer 70.

[0062] In the embodiment, the first pole 303 and the fourth pole 403, or the second pole 304 and the third pole 402 overlap in the film thickness direction.

[0063] It can be understood that, since the first pole 303 and the third pole 402 belong to the first trace, the greater the line width of the first pole 303 and the third pole 402, the smaller the impedance of the first trace, and the pressure drop of the first trace can be reduced; since the second pole 304 and the fourth pole 403 belong to the first trace, the greater the line width of the second pole 304 and the fourth pole 403, the smaller the impedance of the second trace, and the pressure drop of the second trace can be reduced, therefore, in order to make the line width of the first pole 303, the second pole 304, the third pole 402 and the fourth pole 403 greater, it is inevitable that there may be partial overlap between the first pole 303 and the fourth pole 403, and between the second pole 304 and the third pole 402, therefore, the second flat layer 70 needs to be increased to prevent serious electrostatic discharge at the overlapping position.

[0064] It can be understood that, since the vertical distance between the second metal layer 40 and the third metal layer 50 is close, when the first trace and the second trace overlap between the second metal layer 40 and the third metal layer 50, the electrostatic discharge phenomenon is more serious, therefore, by increasing the thickness of the second flat layer 70 between the second metal layer 40 and the third metal layer 50, the electrostatic discharge injury between the second metal layer 40 and the third metal layer 50 can be alleviated.

[0065] In an embodiment, referring to Figure 5 , the second metal layer 40 is arranged on one side of the substrate, the second metal layer 40 includes the first pole 303 and the second pole 304 arranged in insulation, the second flat layer 70 is arranged on the side of the second metal layer 40 away from the substrate, the thickness of the second flat layer 70 ranges from 3 microns to 5 microns, the third metal layer 50 is arranged on the side of the second flat layer 70 away from the substrate, the third metal layer 50 includes the third pole 402 and the fourth pole 403 arranged in insulation, the third pole 402 is connected with the first pole 303 through a first via hole penetrating at least the second flat layer 70, and the fourth pole 403 is connected with the second pole 304 through a second via hole penetrating at least the second flat layer 70; wherein the first pole 303 and the fourth pole 403 are arranged with the overlapping area in the film thickness direction, or the second pole 304 and the third pole 402 are arranged with the overlapping area in the film thickness direction.

[0066] It can be understood that the thickness of the flat layer in the prior art is generally 1.5-2.5 microns. By increasing the thickness of the second flat layer 70, the thickness of the second flat layer 70 between the first and fourth poles 303, 403 and the second and third poles 304, 402 is directly increased, thereby increasing the vertical distance between the first and fourth poles 303, 403 and the second and third poles 304, 402 in the overlapping area in the film thickness direction, and weakening the electrostatic discharge strength of the first and fourth poles 303, 403 and the second and third poles 304, 402 at the overlapping area.

[0067] In the prior art, multiple parallel circular holes are usually used to connect metal layers in different layers to realize conduction. By arranging multiple circular holes, the conduction capacity can be improved. Due to the hole preparation process, the larger the depth of the hole, the larger the aperture area at the top of the hole.

[0068] Referring to Figure 5 In the embodiment, the thickness of the second flat layer 70 is set to be larger. If multiple parallel circular holes are used, not only a large wiring space will be occupied by the circular holes, but also the conduction performance of the via holes will be reduced.

[0069] Therefore, in the embodiment, referring to Figure 2 The second flat layer 70 can further include a first slot hole 140 arranged continuously, the first slot hole 140 penetrating through the second flat layer 70, the first and third poles 303, 402 being connected through the first slot hole 140, and the cross-sectional shape of the first slot hole 140 being any one of a square and an ellipse.

[0070] It can be understood that when the size of the hole formed by etching is small, the cross-sectional shape of the hole is circular, and when the size of the hole formed by etching is large, the cross-sectional shape of the hole is any one of a square and an ellipse. Here, the cross-sectional shape of the first slot hole is any one of a square and an ellipse, which means that the aperture and size of the first slot hole 140 are larger than those of the circular hole in the prior art, so that the cross-sectional shape is any one of a square and an ellipse. By arranging a square or elliptical hole with a larger aperture and size, the conduction capacity of the metal layer can be enhanced, and the problem of abnormal process caused by the increase in the thickness of the second flat layer 70 can be alleviated.

[0071] Similarly, in an embodiment, referring to Figure 1 and Figure 4 The second flat layer 70 can further include a second slot hole arranged continuously, the second slot hole penetrating through the second flat layer 70, the second and fourth poles 304, 403 being connected through the second slot hole, the cross-sectional shape of the second slot hole being any one of a square and an ellipse, and the aperture and size of the second slot hole being larger than those of the circular hole.

[0072] In an embodiment, the second metal layer 40 comprises a first contact electrode 401, the first electrode 303 and the second electrode 304 are in the same layer as the first contact electrode 401 and are insulatively arranged, the third metal layer 50 further comprises a second contact electrode 501, the third electrode 402 and the fourth electrode 403 are in the same layer as the second contact electrode 501 and are insulatively arranged, the fourth metal layer 100 further comprises a third contact electrode 503, and the fifth electrode 502 is in the same layer as the third contact electrode 503 and is insulatively arranged, wherein the first contact electrode 401 and the second contact electrode 501 are connected by a fourth via hole penetrating the second flat layer 70, and the second contact electrode 501 and the third contact electrode 503 are connected by a fifth via hole penetrating the third flat layer 110.

[0073] It can be understood that the array substrate 1 comprises a pixel electrode, the pixel electrode comprises a first contact electrode 401, a second contact electrode 501 and a third contact electrode 503 in a multi-layer stack design, and the first contact electrode 401, the second contact electrode 501 and the third contact electrode 503 are connected, which can reduce the contact impedance between the contact electrodes and the source electrode and the drain electrode, and reduce the voltage drop.

[0074] In an embodiment, the array substrate 1 further comprises a first passivation layer 80, a second passivation layer 90 and a third passivation layer 120, the first passivation layer 80 is arranged on the side surface of the first flat layer 60 away from the substrate 10, the second passivation layer 90 is arranged on the side surface of the second flat layer 70 away from the substrate 10, and the third passivation layer 120 is arranged on the side surface of the third flat layer 110 away from the substrate 10.

[0075] It can be understood that by arranging multiple passivation layers, each passivation layer is arranged on the side surface of each flat layer away from the substrate 10, and the passivation layer can prevent damage to the flat layer caused by etching.

[0076] In an embodiment, the array driving layer 20 further comprises a first gate electrode 204, a second gate electrode 206, a first gate insulating layer 203, a second gate insulating layer 205 and an interlayer insulating layer 207, the first gate insulating layer 203 is arranged on the side of the active layer 202 away from the substrate 10, the first gate electrode 204 is arranged on the side of the first gate insulating layer 203 away from the substrate 10, the second gate insulating layer 205 is arranged on the side of the first gate electrode 204 away from the substrate 10, the second gate electrode 206 is arranged on the side of the second gate insulating layer 205 away from the substrate 10, and the interlayer insulating layer 207 is arranged on the side of the second gate electrode 206 away from the substrate 10.

[0077] In an embodiment, referring to Figure 1 , the display panel can also be a micro light emitting diode display panel (Micro Light Emitting Diode; Micro LED).

[0078] The display panel further comprises a third planar layer 110 located on the side of the third metal layer 50 away from the substrate 10, a third passivation layer 120 located on the side of the third planar layer 110 away from the substrate 10, and a fourth metal layer 100 located on the side of the third passivation layer 120 away from the substrate 10. The fourth metal layer 100 further comprises a third contact electrode 503, and a fifth electrode 502 can be arranged in the same layer as the third contact electrode 503. The third contact electrode 503 is connected to the second contact electrode 501 and the first contact electrode 401.

[0079] The fourth metal layer 100 further comprises a fourth passivation layer 130 located on the side of the fourth metal layer 100 away from the substrate 10.

[0080] It can be understood that, since the micro light-emitting diode display panel can be of a 13T2C architecture, the wiring of the first metal layer 30 is relatively full, and the first trace and the second trace cannot be additionally arranged. Therefore, the first electrode 303 and the second electrode 304 can be arranged in the same layer as the second metal layer 40, the third electrode 402 and the fourth electrode 403 can be arranged in the same layer as the third metal layer 50, and the fifth electrode 502 can be arranged in the same layer as the fourth metal layer 100.

[0081] In an embodiment, the array driving layer 20 further comprises a buffer layer 201 arranged above the substrate 10, an active layer 202 located on the side of the buffer layer 201 away from the substrate 10, a first gate insulating layer 203 located on the side of the active layer 202 away from the substrate 10, a first gate electrode 204 located on the side of the first gate insulating layer 203 away from the substrate 10, a second gate insulating layer 205 located on the side of the first gate electrode 204 away from the substrate 10, a second gate electrode 206 located on the side of the second gate insulating layer 205 away from the substrate 10, and an interlayer insulating layer 207 located on the side of the second gate electrode 206 away from the substrate 10.

[0082] The first trace further comprises the fifth electrode 502, and although the fifth electrode 502 and the second electrode 304 of the second trace overlap in an overlapping area 2, there are two planar layers between the fifth electrode 502 and the second electrode 304. The two planar layers can increase the vertical distance between the fifth electrode 502 and the second electrode 304, improve the yield loss caused by electrostatic discharge breakdown, and alleviate the defect of serious electrostatic discharge at the overlapping position of different traces.

[0083] The application further provides a display panel, a display module, and a terminal device. The display panel, the display module, and the terminal device all comprise the array substrate described above. The terminal device includes, but is not limited to, a mobile phone, a notebook computer, and a tablet computer.

[0084] The array substrate provided by the embodiment of the present application comprises a substrate 10, an array driving layer 20, a first planar layer 60, a second metal layer 40, a second planar layer 70, a third metal layer 50, a third planar layer 110, a fourth metal layer 100, the first metal layer 30 comprises a source electrode 301 and a drain electrode 302 arranged in the same layer, the second metal layer 40 comprises a first electrode 303 and a second electrode 304 arranged in the same layer and insulated, the third metal layer 50 comprises a third electrode 402 and a fourth electrode 403 arranged in the same layer and insulated, the third electrode 402 is connected with the first electrode 303 through a first via hole 150 penetrating through the second planar layer 60, the fourth electrode 403 is connected with the second electrode 304 through a second via hole 160 penetrating through the second planar layer 60, the fourth metal layer 100 comprises a fifth electrode 502, the fifth electrode 502 is connected with the third electrode 402 through a third via hole penetrating through the third planar layer 70, the first electrode 303, the third electrode 402 and the fifth electrode 502 are connected with each other to form a first wire, the second electrode 304 and the fourth electrode 403 are connected with each other to form a second wire, the first wire and the second wire are arranged in a spaced manner, the fifth electrode 502 and the second electrode 304 are arranged to have an overlapping area 2 in the film thickness direction, the first wire comprises the first electrode 303, the third electrode 402 and the fifth electrode 502 arranged in different layers and connected with each other, the second wire comprises the second electrode 304 and the fourth electrode 403 arranged in different layers and connected with each other, by arranging the fifth electrode 502 of the first wire to the fourth metal layer 100, the distance between the fifth electrode 502 and the second electrode 304 in the overlapping area 2 is increased, thereby improving the yield loss caused by electrostatic discharge breakdown.

[0085] The array substrate provided by the embodiment of the present application is introduced in detail above. Those skilled in the art can make various corresponding changes and modifications according to the present application without departing from the spirit and essential characteristics of the present application, and these corresponding changes and modifications shall all belong to the protection scope of the claims attached to the present application.

Claims

1. An array substrate, characterized in that, include: Substrate; A first trace and a second trace are located above the substrate, and the first trace and the second trace have an overlapping region in the film thickness direction; In the overlapping region, the vertical distance between the first trace and the second trace is greater than 3 micrometers; A second metal layer is disposed on one side of the substrate, and the second metal layer includes a first electrode and a second electrode that are insulated from each other. A third metal layer is disposed on the side of the second metal layer away from the substrate, and the third metal layer includes a third electrode and a fourth electrode that are insulated from each other; A fourth metal layer is disposed on the side of the third metal layer away from the substrate, and the fourth metal layer includes a fifth electrode; The first electrode, the third electrode, and the fifth electrode are interconnected to form the first trace, the second electrode and the fourth electrode are interconnected to form the second trace, and the fifth electrode and the second electrode have an overlapping area in the film thickness direction.

2. The array substrate as described in claim 1, characterized in that, include: The second planarization layer is disposed on the side of the second metal layer away from the substrate; the third metal layer is disposed on the side of the second planarization layer away from the substrate; the third electrode is connected to the first electrode through a first via that at least penetrates the second planarization layer; and the fourth electrode is connected to the second electrode through a second via that at least penetrates the second planarization layer. A third planarization layer is disposed on the side of the third metal layer away from the substrate; a fourth metal layer is disposed on the side of the third planarization layer away from the substrate; and the fifth electrode is connected to the third electrode through a third via that penetrates at least the third planarization layer.

3. The array substrate as described in claim 2, characterized in that, The first electrode and the fourth electrode are offset in the film thickness direction, and the second electrode and the third electrode are offset in the film thickness direction.

4. The array substrate as described in claim 1, characterized in that, include: A second metal layer is disposed on one side of the substrate, and the second metal layer includes a first electrode and a second electrode that are insulated from each other. A second planarization layer is disposed on the side of the second metal layer away from the substrate, and the thickness of the second planarization layer ranges from 3 micrometers to 5 micrometers; A third metal layer is disposed on the side of the second planarization layer away from the substrate. The third metal layer includes an insulating third electrode and a fourth electrode. The third electrode is connected to the first electrode through a first via that penetrates at least the second planarization layer, and the fourth electrode is connected to the second electrode through a second via that penetrates at least the second planarization layer. Wherein, the first electrode and the fourth electrode have an overlapping region in the film thickness direction, or the second electrode and the third electrode have an overlapping region in the film thickness direction.

5. The array substrate as described in claim 4, characterized in that, The second planarization layer further includes a first slot that is continuously arranged and penetrates the second planarization layer. The first pole and the third pole are connected through the first slot. The cross-sectional shape of the first slot is either square or elliptical.

6. The array substrate as described in claim 4, characterized in that, The second planarization layer further includes a second slot that is continuously arranged and penetrates the second planarization layer. The second pole and the fourth pole are connected through the second slot. The cross-sectional shape of the second slot is either square or elliptical.

7. The array substrate as described in claim 2, characterized in that, The second metal layer further includes a first contact electrode. The first electrode and the second electrode are in the same layer as the first contact electrode and are insulated from each other. The third metal layer further includes a second contact electrode. The third electrode and the fourth electrode are in the same layer as the second contact electrode and are insulated from each other. The fourth metal layer further includes a third contact electrode. The fifth electrode is in the same layer as the third contact electrode and is insulated from each other. The first contact electrode and the second contact electrode are electrically connected through a fourth via penetrating the second planarization layer. The second contact electrode and the third contact electrode are electrically connected through a fifth via penetrating the third planarization layer.

8. The array substrate as claimed in claim 1, characterized in that, The array substrate further includes: An active layer is disposed on the substrate; A first gate insulating layer is disposed on the side of the active layer away from the substrate; A first gate is disposed on the side of the first gate insulating layer away from the substrate; A second gate insulating layer is disposed on the side of the first gate away from the substrate; The second gate is disposed on the side of the second gate insulating layer away from the substrate; An interlayer insulating layer is disposed on the side of the second gate away from the substrate; A first metal layer is disposed on the side of the interlayer insulating layer away from the substrate. The first metal layer includes a source and a drain disposed at intervals, and the source and drain are respectively connected to the active layer.

9. The array substrate as described in claim 8, characterized in that, The first metal layer and the second metal layer are disposed in the same layer; or The array substrate includes a first planarization layer disposed on the side of the first metal layer opposite to the substrate, and a second metal layer disposed on the side of the first planarization layer opposite to the substrate.

10. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1 to 9.

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