A linear soft start circuit and soft start method thereof

Abstract

The present invention discloses a linear soft start circuit and a soft start method thereof, comprising a buffer unit, a switch tube, a low pass filter unit and a control unit, wherein the input end of the buffer unit is connected to a reference voltage V REF , the first output end of the buffer unit is connected to the first input end of the switch tube, the second output end of the buffer unit is connected to the first input end of the control unit, the first output end of the switch tube is connected to the first input end of the low-pass filter unit, the second output end of the switch tube is connected to the first output end of the low-pass filter unit and the second input end of the control unit, the second input end of the low-pass filter unit and the third input end of the control unit are connected to the enable signal EN, the first output end of the control unit is connected to the second input end of the switch tube, and the second output end of the control unit is connected to the third input end of the switch tube. The present invention can control the establishment speed of the output voltage in the soft start stage and realize the linear and smooth start of the output voltage.

Description

Technical Field

[0001] The invention relates to a soft start circuit and a soft start method thereof, in particular to a linear soft start circuit and a soft start method thereof, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] At present, the share of efficient portable electronic products in the communication and computer fields has increased dramatically, and the requirements for power chips are getting higher and higher. During the startup process, the power chip needs to charge the large output load capacitor, which will generate a large peak current and cause damage to the electronic system. In order to improve the reliability of the power chip, a soft start circuit is needed to allow the output to build smoothly, thereby reducing the surge current.

[0003] Chinese patent publication number CN117639472A discloses a reference soft start circuit and soft start method that are independent of the power supply startup speed. In order to reduce the noise of the output voltage and improve the power supply rejection characteristics of the output voltage, a low-pass RC filter needs to be added to the output of the buffer. Although the patent uses an acceleration circuit to achieve reference soft start regardless of whether the power supply startup speed is fast or slow with a simple circuit structure, in the early stage of soft start, the output voltage establishment slope is not low enough, and there will still be a large startup impact current, which will cause damage to the subsequent circuit. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a linear soft start circuit and a soft start method thereof, so as to realize linear and smooth start of the output voltage.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0006] A linear soft start circuit includes a buffer unit, a switch tube, a low-pass filter unit and a control unit. The input end of the buffer unit is connected to a reference voltage V REF The first output end of the buffer unit is connected to the first input end of the switch tube, the second output end of the buffer unit is connected to the first input end of the control unit, the first output end of the switch tube is connected to the first input end of the low-pass filter unit, the second output end of the switch tube is connected to the first output end of the low-pass filter unit and the second input end of the control unit, the second input end of the low-pass filter unit and the third input end of the control unit are connected to the enable signal EN, the first output end of the control unit is connected to the second input end of the switch tube, and the second output end of the control unit is connected to the third input end of the switch tube.

[0007] Furthermore, the buffer unit comprises an operational amplifier A1, a PMOS tube MP1, resistors R1, R2 and R3, and the reverse input terminal of the operational amplifier A1 is used as the input terminal of the buffer unit and is connected to the reference voltage V REF The output end of the operational amplifier A1 is connected to the gate of the PMOS tube MP1, the source of the PMOS tube MP1 is connected to the power supply VIN, the drain of the PMOS tube MP1 is connected to one end of the resistor R3 and serves as the first output end of the buffer unit, the other end of the resistor R3 is connected to one end of the resistor R2 and serves as the second output end of the buffer unit, the other end of the resistor R2 is connected to one end of the resistor R1 and the same-direction input end of the operational amplifier A1, and the other end of the resistor R1 is grounded.

[0008] Furthermore, the switch tube includes a current source I1, an NMOS tube MN1 and an NMOS tube MN2, the drain of the NMOS tube MN1 serves as the first output end of the switch tube, the source of the NMOS tube MN1 serves as the first input end of the switch tube, the gate of the NMOS tube MN1 serves as the second input end of the switch tube, one end of the current source I1 is connected to the power supply VIN, the other end of the current source I1 is connected to the drain of the NMOS tube MN2, the source of the NMOS tube MN2 serves as the second output end of the switch tube, and the gate of the NMOS tube MN2 serves as the third input end of the switch tube.

[0009] Furthermore, the low-pass filtering unit includes an NMOS tube MN3, a capacitor C1, a resistor R4 and an inverter INV1, one end of the resistor R4 serves as a first input end of the low-pass filtering unit, the other end of the resistor R4 is connected to one end of the capacitor C1 and the drain of the NMOS tube MN3 and serves as a first output end of the low-pass filtering unit, the other end of the capacitor C1 and the source of the NMOS tube MN3 are grounded, the gate of the NMOS tube MN3 is connected to the output end of the inverter INV1, and the input end of the inverter INV1 serves as a second input end of the low-pass filtering unit and is connected to an enable signal EN.

[0010] Further, the control unit includes a PMOS tube MP2, a comparator COMP1, a NAND gate NAND1, a NAND gate NAND2 and an inverter INV2, the same-direction input end of the comparator COMP1 serves as the first input end of the control unit, the reverse input end of the comparator COPM1 serves as the second input end of the control unit, the output end of the comparator COPM1 is connected to the drain of the PMOS tube MP2 and the first input end of the NAND gate NAND1, the source of the PMOS tube MP2 is connected to the power supply VIN, the gate of the PMOS tube MP2 is connected to the first input end of the NAND gate NAND2 and serves as the third input end of the control unit to connect to the enable signal EN, the second input end of the NAND gate NAND1 is connected to the output end of the NAND gate NAND2, the output end of the NAND gate NAND1 is connected to the input end of the inverter INV2 and the second input end of the NAND gate NAND2 and serves as the first output end of the control unit, and the output end of the inverter INV2 serves as the second output end of the control unit.

[0011] Furthermore, the first output terminal of the buffer unit outputs a voltage signal V REF_PRE , the second output terminal of the buffer unit outputs a voltage signal V COMP , the second input terminal of the control unit inputs a voltage signal V REF_RC The first input terminal of the NAND gate NAND1 inputs a voltage signal S0, the second input terminal of the NAND gate NAND1 inputs a voltage signal S1, the output terminal of the NAND gate NAND1 outputs a voltage signal S2, and the output terminal of the inverter INV2 outputs a voltage signal S3.

[0012] A linear soft start method based on a linear soft start circuit comprises the following steps:

[0013] Low enable stage: When the enable signal EN is low, the NMOS tube MN3 and the PMOS tube MP2 are turned on, the voltage signal S0 and the voltage signal S1 are both high, then the voltage signal S2 is low, and the voltage signal S3 is high, so the NMOS tube MN1 is turned off, the NMOS tube MN2 is turned on, and the current source I1 is discharged to the ground through the NMOS tube MN2 and the NMOS tube MN3, and the voltage signal V REF_RC is 0;

[0014] Soft start stage: The enable signal EN is high, the NMOS tube MN3 and the PMOS tube MP2 are turned off, and when the voltage signal V REF_RC Less than the voltage signal V COMP When the voltage signal S0 is high, the voltage signal S1, the voltage signal S2 and the voltage signal S3 remain in their original state, the NMOS tube MN1 is turned off, the NMOS tube MN2 is turned on, the current source I1 charges the capacitor C1 through the NMOS tube MN2, and the voltage signal V REF_RCIt is gradually built up, and its speed of establishment is:

[0015]

[0016] The voltage signal V is controlled by adjusting the value of the current source I1 and the capacitor C1 REF_RC The speed of establishment;

[0017] Soft start end stage: enable signal EN is high level, NMOS tube MN3 and PMOS tube MP2 are turned off, and the voltage signal V is set by setting the resistance values ​​of resistors R1, R2 and R3. COMP Lower than V REF_PRE ; When the voltage signal V REF_RC Greater than the voltage signal V COMP When the voltage signal S0 is low, the voltage signal S2 is high, the voltage signal S1 is low, the voltage signal S3 is low, the NMOS tube MN1 is turned on, the NMOS tube MN2 is turned off, and the current source I1 no longer charges the capacitor C1; the voltage signal V REF_PRE After passing through the low-pass filter network composed of resistor R4 and capacitor C1, a voltage signal V with low noise and high power supply rejection ratio is obtained. REF_RC .

[0018] Compared with the prior art, the present invention has the following advantages and effects: a linear soft start circuit and a soft start method of the present invention can control the output voltage establishment speed in the soft start stage, realize the linear smooth start of the output voltage, thereby improving the reliability of the system in the soft start stage. The circuit structure is different from the traditional soft start circuit in that the slope of the output voltage establishment can be sufficiently low in the early stage of soft start, effectively reducing the surge current of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a principle diagram of a linear soft start circuit of the present invention.

[0020] Figure 2 The invention discloses a circuit diagram of a linear soft start circuit.

[0021] Figure 3 It is a signal waveform diagram of a linear soft start circuit of the present invention.

[0022] Figure 4 This is a typical application schematic diagram of a linear soft start circuit of the present invention. DETAILED DESCRIPTION

[0023] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0024] like Figure 1 As shown, a linear soft start circuit of the present invention comprises a buffer unit, a switch tube, a low-pass filter unit and a control unit, and the input end of the buffer unit is connected to a reference voltage V REF The first output end of the buffer unit is connected to the first input end of the switch tube, the second output end of the buffer unit is connected to the first input end of the control unit, the first output end of the switch tube is connected to the first input end of the low-pass filter unit, the second output end of the switch tube is connected to the first output end of the low-pass filter unit and the second input end of the control unit, the second input end of the low-pass filter unit and the third input end of the control unit are connected to the enable signal EN, the first output end of the control unit is connected to the second input end of the switch tube, and the second output end of the control unit is connected to the third input end of the switch tube.

[0025] like Figure 2 As shown, the buffer unit includes an operational amplifier A1, a PMOS tube MP1, a resistor R1, a resistor R2 and a resistor R3. The reverse input end of the operational amplifier A1 is used as the input end of the buffer unit and is connected to the reference voltage V REF The output end of the operational amplifier A1 is connected to the gate of the PMOS tube MP1, the source of the PMOS tube MP1 is connected to the power supply VIN, the drain of the PMOS tube MP1 is connected to one end of the resistor R3 and serves as the first output end of the buffer unit, the other end of the resistor R3 is connected to one end of the resistor R2 and serves as the second output end of the buffer unit, the other end of the resistor R2 is connected to one end of the resistor R1 and the same-direction input end of the operational amplifier A1, and the other end of the resistor R1 is grounded.

[0026] The switch tube includes a current source I1, an NMOS tube MN1 and an NMOS tube MN2, the drain of the NMOS tube MN1 serves as the first output end of the switch tube, the source of the NMOS tube MN1 serves as the first input end of the switch tube, the gate of the NMOS tube MN1 serves as the second input end of the switch tube, one end of the current source I1 is connected to the power supply VIN, the other end of the current source I1 is connected to the drain of the NMOS tube MN2, the source of the NMOS tube MN2 serves as the second output end of the switch tube, and the gate of the NMOS tube MN2 serves as the third input end of the switch tube

[0027] The low-pass filter unit includes an NMOS tube MN3, a capacitor C1, a resistor R4 and an inverter INV1. One end of the resistor R4 serves as a first input end of the low-pass filter unit. The other end of the resistor R4 is connected to one end of the capacitor C1 and the drain of the NMOS tube MN3 and serves as a first output end of the low-pass filter unit. The other end of the capacitor C1 and the source of the NMOS tube MN3 are grounded. The gate of the NMOS tube MN3 is connected to the output end of the inverter INV1. The input end of the inverter INV1 serves as a second input end of the low-pass filter unit and is connected to an enable signal EN.

[0028] The control unit includes a PMOS tube MP2, a comparator COMP1, a NAND gate NAND1, a NAND gate NAND2 and an inverter INV2, wherein the same-direction input end of the comparator COMP1 serves as the first input end of the control unit, the reverse input end of the comparator COPM1 serves as the second input end of the control unit, the output end of the comparator COPM1 is connected to the drain of the PMOS tube MP2 and the first input end of the NAND gate NAND1, the source of the PMOS tube MP2 is connected to the power supply VIN, the gate of the PMOS tube MP2 is connected to the first input end of the NAND gate NAND2 and serves as the third input end of the control unit to connect to the enable signal EN, the second input end of the NAND gate NAND1 is connected to the output end of the NAND gate NAND2, the output end of the NAND gate NAND1 is connected to the input end of the inverter INV2 and the second input end of the NAND gate NAND2 and serves as the first output end of the control unit, and the output end of the inverter INV2 serves as the second output end of the control unit.

[0029] The first output terminal of the buffer unit outputs a voltage signal V REF_PRE , the second output terminal of the buffer unit outputs a voltage signal V COMP , the second input terminal of the control unit inputs a voltage signal V REF_RC , the first input terminal of the NAND gate NAND1 inputs the voltage signal S0, the second input terminal of the NAND gate NAND1 inputs the voltage signal S1, the output terminal of the NAND gate NAND1 outputs the voltage signal S2, and the output terminal of the inverter INV2 outputs the voltage signal S3. By setting the resistance values ​​of the resistors R1, R2 and R3, the voltage signal V COMP Slightly lower than the voltage signal V REF_PRE .

[0030] like Figure 3 As shown, a linear soft start method based on a linear soft start circuit includes the following steps:

[0031] Low enable stage: When the enable signal EN is low, the NMOS tube MN3 and the PMOS tube MP2 are turned on, the voltage signal S0 and the voltage signal S1 are both high, then the voltage signal S2 is low, and the voltage signal S3 is high, so the NMOS tube MN1 is turned off, the NMOS tube MN2 is turned on, and the current source I1 is discharged to the ground through the NMOS tube MN2 and the NMOS tube MN3, and the voltage signal V REF_RC is 0.

[0032] Soft start stage: The enable signal EN is high, the NMOS tube MN3 and the PMOS tube MP2 are turned off, and when the voltage signal V REF_RC Less than the voltage signal V COMP When the voltage signal S0 is high, the voltage signal S1, the voltage signal S2 and the voltage signal S3 remain in their original state, the NMOS tube MN1 is turned off, the NMOS tube MN2 is turned on, the current source I1 charges the capacitor C1 through the NMOS tube MN2, and the voltage signal V REF_RC It is gradually built up, and its speed of establishment is:

[0033]

[0034] The voltage signal V is controlled by adjusting the value of the current source I1 and the capacitor C1 REF_RC speed of establishment.

[0035] Soft start end stage: enable signal EN is high level, NMOS tube MN3 and PMOS tube MP2 are turned off, and the voltage signal V is set by setting the resistance values ​​of resistors R1, R2 and R3. COMP Lower than V REF_PRE ; When the voltage signal V REF_RC Greater than the voltage signal V COMP When the voltage signal S0 is low, the voltage signal S2 is high, the voltage signal S1 is low, the voltage signal S3 is low, the NMOS tube MN1 is turned on, the NMOS tube MN2 is turned off, and the current source I1 no longer charges the capacitor C1; the voltage signal V REF_PRE After passing through the low-pass filter network composed of resistor R4 and capacitor C1, a voltage signal V with low noise and high power supply rejection ratio is obtained. REF_RC .

[0036] like Figure 4 FIG. 1 is a typical application of a linear soft start circuit of the present invention. Operational amplifier A2 is used to clamp the output voltage V OUT And the voltage signal V REF_RC , so that the output voltage V OUT And the voltage signal V REF_RC The value of is always the same, so the output voltage V OUT And the voltage signal VREF_RC With the same settling speed, the surge current of the whole system is:

[0037]

[0038] By controlling the value of current source I1 and capacitor C1, not only can the output voltage V OUT Linear smooth start, and the output voltage V OUT The build-up slope is low enough to effectively reduce the inrush current.

[0039] A linear soft start circuit and a soft start method of the present invention can not only realize the linear smooth start of the output voltage with a simple circuit structure, but also control the start speed of the output voltage. The present invention can make the slope of the output voltage sufficiently low in the initial stage of soft start, thereby effectively reducing the surge current of the system. The present invention allows the output voltage to have low noise and high power supply rejection ratio characteristics through a low-pass filter network.

[0040] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A linear soft start circuit, characterized in that: It includes a buffer unit, a switch tube, a low-pass filter unit and a control unit. The input end of the buffer unit is connected to the reference voltage V REF , the first output end of the buffer unit is connected to the first input end of the switch tube, the second output end of the buffer unit is connected to the first input end of the control unit, the first output end of the switch tube is connected to the first input end of the low-pass filter unit, the second output end of the switch tube is connected to the first output end of the low-pass filter unit and the second input end of the control unit, the second input end of the low-pass filter unit and the third input end of the control unit are connected to the enable signal EN, the first output end of the control unit is connected to the second input end of the switch tube, and the second output end of the control unit is connected to the third input end of the switch tube; The buffer unit comprises an operational amplifier A1, a PMOS tube MP1, resistors R1, R2 and R3. The reverse input end of the operational amplifier A1 is used as the input end of the buffer unit and is connected to the reference voltage V REF , the output end of the operational amplifier A1 is connected to the gate of the PMOS tube MP1, the source of the PMOS tube MP1 is connected to the power supply VIN, the drain of the PMOS tube MP1 is connected to one end of the resistor R3 and serves as the first output end of the buffer unit, the other end of the resistor R3 is connected to one end of the resistor R2 and serves as the second output end of the buffer unit, the other end of the resistor R2 is connected to one end of the resistor R1 and the same-direction input end of the operational amplifier A1, and the other end of the resistor R1 is grounded; The switch tube comprises a current source I1, an NMOS tube MN1 and an NMOS tube MN2, the drain of the NMOS tube MN1 serves as a first output end of the switch tube, the source of the NMOS tube MN1 serves as a first input end of the switch tube, the gate of the NMOS tube MN1 serves as a second input end of the switch tube, one end of the current source I1 is connected to a power source VIN, the other end of the current source I1 is connected to a drain of the NMOS tube MN2, the source of the NMOS tube MN2 serves as a second output end of the switch tube, and the gate of the NMOS tube MN2 serves as a third input end of the switch tube; The low-pass filter unit comprises an NMOS tube MN3, a capacitor C1, a resistor R4 and an inverter INV1, one end of the resistor R4 serves as a first input end of the low-pass filter unit, the other end of the resistor R4 is connected to one end of the capacitor C1 and the drain of the NMOS tube MN3 and serves as a first output end of the low-pass filter unit, the other end of the capacitor C1 and the source of the NMOS tube MN3 are grounded, the gate of the NMOS tube MN3 is connected to the output end of the inverter INV1, and the input end of the inverter INV1 serves as a second input end of the low-pass filter unit and is connected to an enable signal EN; The control unit comprises a PMOS tube MP2, a comparator COMP1, a NAND gate NAND1, a NAND gate NAND2 and an inverter INV2, wherein the same-direction input end of the comparator COMP1 serves as a first input end of the control unit, the reverse input end of the comparator COMP1 serves as a second input end of the control unit, the output end of the comparator COMP1 is connected to the drain of the PMOS tube MP2 and the first input end of the NAND gate NAND1, the source of the PMOS tube MP2 is connected to a power supply VIN, the gate of the PMOS tube MP2 is connected to the first input end of the NAND gate NAND2 and serves as a third input end of the control unit to connect to an enable signal EN, the second input end of the NAND gate NAND1 is connected to the output end of the NAND gate NAND2, the output end of the NAND gate NAND1 is connected to the input end of the inverter INV2 and the second input end of the NAND gate NAND2 and serves as a first output end of the control unit, and the output end of the inverter INV2 serves as a second output end of the control unit; The first output terminal of the buffer unit outputs a voltage signal V REF_PRE , the second output terminal of the buffer unit outputs a voltage signal V COMP , the second input terminal of the control unit inputs a voltage signal V REF_RC The first input terminal of the NAND gate NAND1 inputs a voltage signal S0, the second input terminal of the NAND gate NAND1 inputs a voltage signal S1, the output terminal of the NAND gate NAND1 outputs a voltage signal S2, and the output terminal of the inverter INV2 outputs a voltage signal S3.

2. A linear soft start method based on the linear soft start circuit of claim 1, characterized in that The following steps are involved: Low enable stage: When the enable signal EN is low, the NMOS tube MN3 and the PMOS tube MP2 are turned on, the voltage signal S0 and the voltage signal S1 are both high, then the voltage signal S2 is low, and the voltage signal S3 is high, so the NMOS tube MN1 is turned off, the NMOS tube MN2 is turned on, and the current source I1 is discharged to the ground through the NMOS tube MN2 and the NMOS tube MN3, and the voltage signal V REF_RC is 0; Soft start stage: The enable signal EN is high, the NMOS tube MN3 and the PMOS tube MP2 are turned off, and when the voltage signal V REF_RC Less than the voltage signal V COMP When the voltage signal S0 is high, the voltage signal S1, the voltage signal S2 and the voltage signal S3 remain in their original state, the NMOS tube MN1 is turned off, the NMOS tube MN2 is turned on, the current source I1 charges the capacitor C1 through the NMOS tube MN2, and the voltage signal V REF_RC It is gradually built up, and its speed of establishment is: ； The voltage signal V is controlled by adjusting the value of the current source I1 and the capacitor C1 REF_RC The speed of establishment; Soft start end stage: enable signal EN is high level, NMOS tube MN3 and PMOS tube MP2 are turned off, and the voltage signal V is set by setting the resistance values ​​of resistors R1, R2 and R3. COMP Lower than V REF_PRE ; When the voltage signal V REF_RC Greater than the voltage signal V COMP When the voltage signal S0 is low, the voltage signal S2 is high, the voltage signal S1 is low, the voltage signal S3 is low, the NMOS tube MN1 is turned on, the NMOS tube MN2 is turned off, and the current source I1 no longer charges the capacitor C1; the voltage signal V REF_PRE After passing through the low-pass filter network composed of resistor R4 and capacitor C1, a voltage signal V with low noise and high power supply rejection ratio is obtained. REF_RC .

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