Successive approximation ADC, chip and analog-to-digital conversion method based on common mode voltage

Abstract

The present application relates to a successive approximation ADC, chip and analog-to-digital conversion method based on common-mode voltage. The method includes: a DAC capacitor array; the DAC capacitor array includes a positive capacitor array, a negative capacitor array, a random number generator and a common-mode voltage generating circuit, the upper plates of each capacitor in the positive capacitor array and the negative capacitor array are connected in parallel and connected to the common-mode voltage generating circuit; the positive capacitor array and the negative capacitor array include a high-order capacitor array and a low-order capacitor array, the high-order capacitor array includes a number of thermometer-weighted high-order capacitors, the low-order capacitor array includes a number of binary-weighted low-order capacitors, and the high-order capacitor array is connected to the random number generator; the lower plates of the high-order capacitor and the low-order capacitor are respectively connected to the reference voltage, the differential input voltage or the ground through a three-way gate switch. The use of this method can reduce the power consumption of the SAR ADC and reduce the impact of mismatch.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design, and in particular to a successive approximation ADC, a chip and an analog-to-digital conversion method based on common-mode voltage. Background Art

[0002] As a bridge between analog and digital conversion, the performance of ADC is receiving widespread attention. In the SOC (System On Chip) system, ADC is also an indispensable part. It can be used not only to measure voltage but also to detect temperature. In SOC design, ADC is generally required to be small in size and low in power consumption. In order to reduce the load on the front stage, the ADC input capacitor is often required to be very small, which puts more stringent requirements on the area and power consumption of ADC. Compared with other types of ADCs such as pipeline ADC, SAR ADC has the advantage of low power consumption. As an ultra-low power SOC system, the passive UHF tag chip with integrated temperature sensor has very strict requirements on power consumption. Therefore, the power consumption of SAR ADC has become an important indicator of research.

[0003] However, the traditional SAR ADC structure is difficult to increase the effective number of bits due to capacitor mismatch. The traditional SAR ADC requires an independent common-mode voltage generation circuit, which greatly increases power consumption and the possibility of noise interference. Summary of the invention

[0004] Based on this, it is necessary to provide a successive approximation ADC, chip and analog-to-digital conversion method based on common-mode voltage to address the above technical problems.

[0005] A successive approximation ADC based on common mode voltage, the ADC comprising:

[0006] A digital-to-analog conversion module; the digital-to-analog conversion module includes a DAC capacitor array; the DAC capacitor array includes a positive capacitor array, a negative capacitor array, a random number generator and a common-mode voltage generating circuit, the upper plates of each capacitor in the positive capacitor array and the negative capacitor array are connected in parallel and connected to the common-mode voltage generating circuit to access the common-mode voltage in the sampling phase;

[0007] The positive capacitor array and the negative capacitor array include a high-order capacitor array and a low-order capacitor array, wherein the high-order capacitor array includes a plurality of thermometer-weighted high-order capacitors, and the low-order capacitor array includes a plurality of binary-weighted low-order capacitors, wherein the high-order capacitor array is connected to the random number generator, and when comparing phases, the high-order capacitors of corresponding bits are selected according to the output of the random number generator to access the reference voltage;

[0008] The lower plates of the high-order capacitor and the low-order capacitor are respectively connected to a reference voltage, a differential input voltage or ground via a three-way selection switch;

[0009] The DAC capacitor array is used to sample the input signal according to the differential input voltage and the common mode voltage connected in the sampling phase to obtain a sampling value, and to make a difference between the sampling value and the reference voltage according to the reference voltage connected in the comparison phase to obtain the output voltage of the DAC capacitor array, and to complete the analog-to-digital conversion of the ADC according to the output voltage.

[0010] In one embodiment, it also includes: a buffer, a first voltage-dividing capacitor, a second voltage-dividing capacitor, a first switch, a second switch and a third switch; the buffer is connected to the second connection ends of the first voltage-dividing capacitor and the second voltage-dividing capacitor respectively, the first connection end of the first switch is connected to VDD, the second connection end of the first switch is connected to the first connection end of the second switch, the first connection end of the third switch is connected to the second connection end of the second switch, the first connection end of the second switch is connected to the first connection end of the first voltage-dividing capacitor, and the second connection end of the second switch is connected to the second connection end of the second voltage-dividing capacitor; the first connection end of the first voltage-dividing capacitor is connected to the upper board of each capacitor in the positive capacitor array, and the first connection end of the second voltage-dividing capacitor is connected to the upper board of each capacitor in the negative capacitor array.

[0011] In one of the embodiments, it also includes: a dynamic comparison module and an asynchronous SAR logic module; the digital-to-analog conversion module is connected to the dynamic comparison module and the asynchronous SAR logic module respectively, and the dynamic comparison module is connected to the asynchronous SAR logic module; the dynamic comparison module is used to output a logic state holding signal when the output voltage of the DAC capacitor array is greater than a threshold value in the comparison phase, and output a logic state reset signal when the output voltage of the DAC capacitor array is less than the threshold value; the asynchronous SAR logic module is used to generate a control signal according to the output result of the dynamic comparison module; the control signal is used to control the conduction and disconnection of each switch in the DAC capacitor array to redistribute the charge on the output ends of the positive capacitor array and the negative capacitor array.

[0012] In one of the embodiments, the upper plate of each capacitor in the positive capacitor array is also connected to the positive input terminal of the dynamic comparison module, and the upper plate of each capacitor in the negative capacitor array is also connected to the negative input terminal of the dynamic comparison module.

[0013] In one of the embodiments, the ADC further includes an internal timing control module; the internal timing control module is connected to the dynamic comparison module and the asynchronous SAR logic module to generate a clock signal to perform timing control on the dynamic comparison module and the asynchronous SAR logic module.

[0014] In one of the embodiments, it also includes: the DAC capacitor array also includes a positive dummy capacitor and a negative dummy capacitor: the upper plate of the positive dummy capacitor is connected in parallel with the lowest capacitor in the positive capacitor array and is connected to the first connection end of the first voltage-dividing capacitor; the upper plate of the negative dummy capacitor is connected in parallel with the lowest capacitor in the negative capacitor array and is connected to the first connection end of the second voltage-dividing capacitor; the lower plates of the positive dummy capacitor and the negative dummy capacitor are respectively connected to the reference voltage, the differential input voltage or the ground through a three-way selection switch.

[0015] In one embodiment, the output voltage of the DAC capacitor array is:

[0016] ,

[0017] ,

[0018] ,

[0019] in, is the output voltage of the DAC capacitor array, is the input voltage, is the number of bits of resolution, , is the number of bits of resolution of the ADC, is the total capacitance of the DAC capacitor array, is the unit capacitance, is the reference voltage, is the total charge of the DAC capacitor array, is the common mode voltage, is the operating voltage, It is the output value of the dynamic comparison module.

[0020] In one embodiment, the common mode voltage is:

[0021] ;

[0022] in, is the output voltage at the positive output or negative output of the DAC capacitor array.

[0023] In one of the embodiments, a chip including the common-mode voltage-based successive approximation ADC is also provided.

[0024] An analog-to-digital conversion method, the analog-to-digital conversion method comprising:

[0025] The input signal is sampled by the DAC capacitor array according to the differential input voltage and the common mode voltage connected to the sampling phase to obtain a sampling value;

[0026] According to the reference voltage connected in the comparison phase, the sampling value and the reference voltage are subtracted to obtain the output voltage of the DAC capacitor array, and the analog-to-digital conversion of the ADC is completed according to the output voltage.

[0027] The above-mentioned successive approximation ADC, chip and analog-to-digital conversion method based on common-mode voltage can reduce the parasitic and noise interference caused by VCM routing by constructing positive capacitor arrays and negative capacitor arrays, and respectively connect the upper plates of each capacitor in each capacitor array in parallel and connect them to the common-mode voltage generating circuit, while reducing power consumption and noise interference. The positive capacitor array and the negative capacitor array both include a high-order capacitor array and a low-order capacitor array, and the high-order capacitor array includes a number of thermometer-weighted high-order capacitors, and the low-order capacitor array includes a number of binary-weighted low-order capacitors. It is possible to obtain better static indicators of differential nonlinearity (DNL) and integral nonlinearity (INL) without a complex capacitor mismatch calibration algorithm. The embodiment of the present invention provides a new SAR ADC architecture that can reduce power consumption and reduce the impact of mismatch. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a structural schematic diagram of a successive approximation ADC based on common mode voltage in one embodiment;

[0029] Figure 2 A schematic diagram of the structure of a DAC capacitor array in one embodiment;

[0030] Figure 3 A schematic diagram of converting a thermometer code to a binary code in one embodiment;

[0031] Figure 4 It is a circuit status diagram of the comparison phase digital-to-analog conversion module. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0033] In one embodiment, Figure 1As shown, a successive approximation ADC based on common-mode voltage is provided, including:

[0034] A digital-to-analog conversion module; the digital-to-analog conversion module includes a DAC capacitor array; the DAC capacitor array includes a positive capacitor array, a negative capacitor array, a random number generator and a common-mode voltage generating circuit, the upper plates of each capacitor in the positive capacitor array and the negative capacitor array are connected in parallel and connected to the common-mode voltage generating circuit to access the common-mode voltage in the sampling phase;

[0035] The positive capacitor array and the negative capacitor array include a high-order capacitor array and a low-order capacitor array, the high-order capacitor array includes a number of thermometer-weighted high-order capacitors, the low-order capacitor array includes a number of binary-weighted low-order capacitors, the high-order capacitor array is connected to a random number generator, and when comparing phases, a high-order capacitor with a corresponding number of bits is selected according to the output of the random number generator to access a reference voltage;

[0036] The lower plates of the high-order capacitor and the low-order capacitor are respectively connected to the reference voltage, the differential input voltage or the ground through a three-way selection switch;

[0037] The DAC capacitor array is used to sample the input signal according to the differential input voltage and common-mode voltage connected in the sampling phase to obtain the sampling value. According to the reference voltage connected in the comparison phase, the sampling value and the reference voltage are subtracted to obtain the output voltage of the DAC capacitor array, and the analog-to-digital conversion of the ADC is completed according to the output voltage.

[0038] In the above-mentioned successive approximation ADC based on common-mode voltage, by constructing a positive capacitor array and a negative capacitor array, and respectively connecting the upper plates of each capacitor in each capacitor array in parallel and connected to the common-mode voltage generating circuit, the parasitic and noise interference caused by the VCM routing can be reduced, and the power consumption and noise interference are reduced at the same time. The positive capacitor array and the negative capacitor array both include a high-order capacitor array and a low-order capacitor array. The high-order capacitor array includes a number of thermometer-weighted high-order capacitors, and the low-order capacitor array includes a number of binary-weighted low-order capacitors. In the absence of a complex capacitor mismatch calibration algorithm, better static indicators of differential nonlinearity (DNL) and integral nonlinearity (INL) can be obtained. The embodiment of the present invention provides a new SAR ADC architecture that can reduce power consumption and reduce the impact of mismatch.

[0039] like Figure 1 The schematic diagram of the structure of the successive approximation ADC based on the common mode voltage is shown in the figure. The digital-to-analog conversion module also includes a sample-and-hold circuit. The sample-and-hold circuit is connected to the DAC capacitor array. The sample-and-hold circuit includes a multiplexer and a boost switch (BoostStrap Swich). The multiplexer is connected to the input end of the ADC. The input end of the ADC is used to input multiple input signals. When multiple input signals are input to the ADC, one of the input signals is selected by configuring the multiplexer, and the input signal is converted into a differential signal, the differential signal includes a first differential input signal and a second differential input signal, and the differential signal enters the boost switch for sampling and holding to convert the time-continuous signal into a time-discrete signal, so as to facilitate the subsequent modules to quantize the discrete sampling signal.

[0040] In a specific embodiment, Figure 2 As shown, a structural schematic diagram of a DAC capacitor array is provided, wherein the forward capacitor array includes a forward high-order capacitor array, a forward low-order capacitor array, and a forward dummy capacitor, wherein the upper plates of each capacitor in the forward capacitor array are connected in parallel and connected to a common-mode voltage generating circuit, and are also connected to a positive input terminal of a dynamic comparison module, and the lower plates of each capacitor are connected to a three-way selection switch, wherein the three selection terminals of the three-way selection switch are respectively connected to a first differential input voltage, a first reference voltage, and ground, and the three-way selection switch is equivalently replaced by three switches, wherein the first connection terminals of the three switches are connected to each other and to the lower plates of the corresponding capacitors, and the second connection terminals of the three switches are correspondingly connected to the first differential input voltage, the first reference voltage, and ground.

[0041] The negative capacitor array includes a negative high-position capacitor array, a negative low-position capacitor array and a negative dummy capacitor. The upper plates of each capacitor in the negative capacitor array are connected in parallel and connected to the common-mode voltage generating circuit, and are also connected to the negative input terminal of the dynamic comparison module. The lower plates of each capacitor are connected to a three-way selection switch. The three selection terminals of the three-way selection switch are respectively connected to GND, a second reference voltage and a second differential input voltage. The three-way selection switch uses three switches for equivalent replacement. The first connection terminals of the three switches are connected to each other and to the lower plates of the corresponding capacitors. The second connection terminals of the three switches are correspondingly connected to GND, the second reference voltage and the second differential input voltage.

[0042] Both the positive capacitor array and the negative capacitor array are 12-bit capacitor arrays. The positive high-order capacitor array and the negative high-order capacitor array are located in the upper 6 bits of the 12-bit capacitor array, and the positive low-order capacitor array and the negative low-order capacitor array are located in the lower 6 bits of the 12-bit capacitor array. The lower 6-bit capacitor array adopts binary coding, including 6 groups of capacitors, and the upper 6-bit capacitor array adopts thermometer coding, including 63 groups of capacitors of the same size, such as Figure 3 Thermometer code conversion to binary code diagram shown in the figure, when the binary code value increases by 1, the thermometer code unit capacitance increases by 1, from Figure 3It can be seen that the thermometer coding is in a step-like shape, and the binary weight scheme cannot guarantee monotonicity. At some critical conversion points, the error may exceed one LSB, and the thermometer coding changes a capacitor each time, which can greatly improve the static index of the ADC. The present invention adds a random mechanism to the selection of capacitors to solve the error problem caused by capacitor mismatch. Since the INL of the DAC is the accumulation of errors, adding a random mechanism can convert the error into noise, thereby averaging the error.

[0043] The common-mode voltage generating circuit includes a buffer, a first voltage-dividing capacitor, a second voltage-dividing capacitor, a first switch, a second switch and a third switch. The buffer is respectively connected to the second connection ends of the first voltage-dividing capacitor and the second voltage-dividing capacitor. The first connection end of the first voltage-dividing capacitor is connected to the upper board of each capacitor in the positive capacitor array, the first connection end of the second voltage-dividing capacitor is connected to the upper board of each capacitor in the negative capacitor array, the first connection end of the first switch is connected to VDD, the second connection end of the first switch is connected to the first connection end of the second switch, the first connection end of the third switch is connected to the second connection end of the second switch, the first connection end of the second switch is connected to the first connection end of the first voltage-dividing capacitor, and the second connection end of the second switch is connected to the second connection end of the second voltage-dividing capacitor.

[0044] Figure 2 The structural schematic diagram of the DAC capacitor array shown can also represent a circuit state schematic diagram of a sampling phase digital-to-analog conversion module. In the sampling phase, the lower plates of each capacitor in the positive capacitor array select the first differential input voltage through a three-way selection switch, and the lower plates of each capacitor in the negative capacitor array select the second differential input voltage through a three-way selection switch, and the first switch, the second switch and the third switch are closed.

[0045] like Figure 4 The circuit state diagram of the comparison phase digital-to-analog conversion module shown in the figure shows that, in the comparison phase, the three switches of the three-way selection switch are disconnected, namely, the first switch, the second switch and the third switch are disconnected.

[0046] Specifically, , sampling phase charge:

[0047] ,

[0048] ,

[0049] in, is the operating voltage, is the sampling phase charge, is the total capacitance of the single-sided capacitor array,

[0050] Comparison phase:

[0051] ,

[0052] when Sometimes:

[0053] ,

[0054] ,

[0055] Therefore, the switched capacitor .

[0056] like Figure 1 The structural diagram of the successive approximation ADC based on common-mode voltage is shown. The successive approximation ADC based on common-mode voltage also includes an internal timing control circuit. The internal timing control circuit is connected to the clock signal, and the output end is respectively connected to the dynamic prevention circuit, the dynamic comparator, the data latch circuit, and the asynchronous SAR logic circuit.

[0057] like Figure 1 The structural schematic diagram of the successive approximation ADC based on common-mode voltage is shown, the dynamic comparison module includes a dynamic pre-amplifier circuit and a dynamic comparator circuit, the positive input terminal of the dynamic prevention large circuit is connected to the upper plate of each capacitor in the positive capacitor array, the negative input terminal of the dynamic prevention large circuit is connected to the upper plate of each capacitor in the negative capacitor array, the positive and negative output terminals of the dynamic prevention large circuit are correspondingly connected to the positive and negative input terminals of the dynamic comparator to amplify the access signal, in each clock cycle, the dynamic comparator performs a comparison, outputs a logic state hold signal when the sampled value is greater than the reference voltage, and outputs a logic state reset signal when the sampled value is less than the reference voltage, and the comparison result is output to the asynchronous SAR logic module.

[0058] like Figure 1 The structural schematic diagram of the successive approximation ADC based on common-mode voltage is shown in the figure. The asynchronous SAR logic module includes a data latch circuit, an asynchronous SAR logic circuit and a data output register. The asynchronous SAR logic circuit is respectively connected to the data latch circuit, the digital-to-analog conversion module and the data output register. The output value of the dynamic comparator is saved through the data latch circuit. The data latch locks the input signal on the output port until the next clock pulse is received, and then outputs it to the asynchronous SAR logic circuit. The asynchronous SAR logic circuit outputs a sampling control signal in the sampling stage and outputs a successive comparison control signal in the successive comparison stage. The asynchronous SAR logic circuit selects to output a reference voltage or a low level by judging the output value of the dynamic comparator. If the dynamic comparator outputs a high logic state, the asynchronous SAR logic circuit selects to output a low level. If the dynamic comparator outputs a low logic state, the asynchronous SAR logic circuit selects to output a reference voltage. The data output register stores the final 12-bit output data.

[0059] Among them, the output value calculation process of the DAC capacitor array is as follows:

[0060] The total capacitance of the positive capacitor array and the negative capacitor array in the digital-to-analog conversion module is:

[0061] ,

[0062] in, is the total capacitance of the positive capacitor array and the negative capacitor array, is the number of bits of resolution of the ADC, is the unit capacitance.

[0063] In the sampling phase, the input signal is sampled through the lower plate of each capacitor in the capacitor array, and the upper plate is equivalent to the common mode voltage The total charge of the DAC capacitor array is:

[0064] ,

[0065] After sampling, the ADC enters the conversion state. During the first conversion, the thermometer coding capacitor array corresponding to the highest bit is connected to , and the rest remain grounded. After the final conversion is completed, the output voltage of the DAC capacitor array is:

[0066] ,

[0067] in, is the output voltage of the DAC capacitor array, is the input voltage, is the number of bits of resolution, , is the total capacitance of the DAC capacitor array, is the unit capacitance, is the reference voltage, is the total charge of the DAC capacitor array, is the common mode voltage, , is the operating voltage, is the output value of the dynamic comparison module, and its attenuation factor is:

[0068] ,

[0069] in is the total parasitic capacitance of the top plate of the capacitor.

[0070] In one embodiment, the DAC capacitor array is used to sample the input signal according to the differential input voltage and the common mode voltage connected in the sampling phase to obtain the sampled value, and to make a difference between the sampled value and the reference voltage according to the reference voltage connected in the comparison phase to obtain the output voltage of the DAC capacitor array, and to complete the analog-to-digital conversion of the ADC according to the output voltage. Specifically, the process includes the following:

[0071] In the sampling phase, the DAC capacitor array controls the capacitor lower plates of the positive capacitor array and the negative capacitor array according to the control signal to select the first differential input signal and the second differential input signal respectively, and the first switch, the second switch and the third switch of the common mode voltage generating circuit are closed. At this time, the capacitor upper plates of the positive capacitor array and the negative capacitor array are equivalently connected to the common mode voltage. In this working state, the DAC capacitor array samples the input signal to obtain a sampled value.

[0072] In the successive comparison stage, the DAC capacitor array controls the first switch, the second switch and the third switch of the common mode voltage generating circuit according to the control signal to open, and the three-way selection switch of the positive capacitor array and the negative capacitor array performs corresponding switch switching under the control of the control signal. In the first comparison, if the lower plate of the highest capacitor of the positive capacitor array is connected to the first reference voltage, the capacitors on the remaining positions of the positive capacitor array are all grounded, the lower plate of the highest capacitor of the negative capacitor array is grounded, and the capacitors on the remaining positions of the negative capacitor array are connected to the second reference voltage. At this time, the DAC capacitor array makes a difference between the sampling value and the reference voltage. If the difference is greater than 0, the dynamic comparator outputs a logic state holding signal. If the difference is less than 0, the dynamic comparator outputs a logic state reset signal. The dynamic comparator sends the output result to the asynchronous SAR logic module. The asynchronous SAR logic module outputs a corresponding control signal according to the output result of the dynamic comparator. According to the logic state holding signal, the current position logic state set to 1 in the control signal remains unchanged, and according to the logic state reset signal, the current position logic state set to 1 in the control signal is reset. In the subsequent comparison process, if the lower plate of the corresponding capacitor of the positive capacitor array is connected to the reference voltage, the lower plate of the corresponding upper capacitor of the negative capacitor array is grounded.

[0073] In one embodiment, a chip is further provided, comprising: the successive approximation ADC based on common mode voltage in the above embodiment.

[0074] In one embodiment, a method for analog-to-digital conversion is also provided, the method comprising the following steps:

[0075] The input signal is sampled according to the differential input voltage and the common mode voltage connected to the DAC capacitor array in the sampling phase to obtain a sampling value;

[0076] The DAC capacitor array is used to access the reference voltage in the comparison phase, and the sampling value and the reference voltage are subtracted to obtain the output voltage of the DAC capacitor array, and the analog-to-digital conversion of the ADC is completed according to the output voltage.

[0077] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0078] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A successive approximation ADC based on common-mode voltage, characterized in that: The ADC comprises: A digital-to-analog conversion module; the digital-to-analog conversion module includes a DAC capacitor array; the DAC capacitor array includes a positive capacitor array, a negative capacitor array, a random number generator and a common-mode voltage generating circuit, the upper plates of each capacitor in the positive capacitor array and the negative capacitor array are connected in parallel and connected to the common-mode voltage generating circuit to access the common-mode voltage in the sampling phase; The positive capacitor array and the negative capacitor array include a high-order capacitor array and a low-order capacitor array, wherein the high-order capacitor array includes a plurality of thermometer-weighted high-order capacitors, and the low-order capacitor array includes a plurality of binary-weighted low-order capacitors, wherein the high-order capacitor array is connected to the random number generator, and when comparing phases, the high-order capacitors of corresponding bits are selected according to the output of the random number generator to access the reference voltage; The lower plates of the high-order capacitor and the low-order capacitor are respectively connected to the reference voltage, the differential input voltage or the ground through a three-way selection switch; The DAC capacitor array is used to sample the input signal according to the differential input voltage and the common mode voltage connected in the sampling phase to obtain a sampling value, and to make a difference between the sampling value and the reference voltage according to the reference voltage connected in the comparison phase to obtain the output voltage of the DAC capacitor array, and to complete the analog-to-digital conversion of the ADC according to the output voltage; The common mode voltage generating circuit comprises: A buffer, a first voltage-dividing capacitor, a second voltage-dividing capacitor, a first switch, a second switch, and a third switch; The input end of the buffer is grounded, the output end of the buffer is connected to the second connection end of the first voltage-dividing capacitor and the second connection end of the second voltage-dividing capacitor, the first connection end of the first switch is connected to the working voltage VDD, the second connection end of the first switch is connected to the first connection end of the second switch, the first connection end of the third switch is connected to the second connection end of the second switch, the first connection end of the second switch is connected to the first connection end of the first voltage-dividing capacitor, and the second connection end of the second switch is connected to the second connection end of the second voltage-dividing capacitor; The first connection end of the first voltage-dividing capacitor is connected to the upper plate of each capacitor in the positive capacitor array, and the first connection end of the second voltage-dividing capacitor is connected to the upper plate of each capacitor in the negative capacitor array.

2. The common-mode voltage-based successive approximation ADC according to claim 1, characterized in that: The ADC further comprises: Dynamic comparison module and asynchronous SAR logic module; The digital-to-analog conversion module is respectively connected to the dynamic comparison module and the asynchronous SAR logic module, and the dynamic comparison module is connected to the asynchronous SAR logic module; The dynamic comparison module is used to output a logic state holding signal when the output voltage of the DAC capacitor array is greater than a threshold value during a comparison phase, and output a logic state reset signal when the output voltage of the DAC capacitor array is less than the threshold value; The asynchronous SAR logic module is used to generate a control signal according to the output result of the dynamic comparison module; the control signal is used to control the conduction and disconnection of each switch in the DAC capacitor array to redistribute the charge at the output ends of the positive capacitor array and the negative capacitor array.

3. The common-mode voltage-based successive approximation ADC according to claim 2, characterized in that: The upper plate of each capacitor in the positive capacitor array is also connected to the positive input terminal of the dynamic comparison module, and the upper plate of each capacitor in the negative capacitor array is also connected to the negative input terminal of the dynamic comparison module.

4. The common-mode voltage-based successive approximation ADC according to claim 2, characterized in that: The ADC also includes an internal timing control module; the internal timing control module is connected to the dynamic comparison module and the asynchronous SAR logic module, and is used to generate a clock signal to perform timing control on the dynamic comparison module and the asynchronous SAR logic module.

5. The common-mode voltage-based successive approximation ADC according to claim 1, characterized in that: The DAC capacitor array also includes a positive dummy capacitor and a negative dummy capacitor: The upper plate of the forward dummy capacitor is connected in parallel with the lowest capacitor in the forward capacitor array and is connected to the first connection end of the first voltage-dividing capacitor; The upper plate of the negative dummy capacitor is connected in parallel with the lowest capacitor in the negative capacitor array, and is connected to the first connection end of the second voltage-dividing capacitor; The lower plates of the positive dummy capacitor and the negative dummy capacitor are respectively connected to a reference voltage, a differential input voltage or ground via a three-way selection switch.

6. The common-mode voltage-based successive approximation ADC according to claim 1, characterized in that: The output voltage of the DAC capacitor array is: ， ， ， in, is the output voltage of the DAC capacitor array, is the input voltage, is the number of bits of resolution, , is the number of bits of resolution of the ADC, is the total capacitance of the DAC capacitor array, is the unit capacitance, is the reference voltage, is the total charge of the DAC capacitor array, is the common mode voltage, is the operating voltage, It is the output value of the dynamic comparison module.

7. The common-mode voltage-based successive approximation ADC according to claim 6, characterized in that: The common mode voltage is: in, is the output voltage at the positive output or negative output of the DAC capacitor array.

8. A chip, characterized in that: include: The common-mode voltage-based successive approximation ADC according to any one of claims 1 to 7.

9. An analog-to-digital conversion method implemented in the chip as claimed in claim 8, characterized in that: The analog-to-digital conversion method comprises: The input signal is sampled according to the differential input voltage and the common mode voltage connected to the DAC capacitor array in the sampling phase to obtain a sampling value; The DAC capacitor array is connected to a reference voltage in a comparison phase, the sampling value and the reference voltage are subtracted to obtain the output voltage of the DAC capacitor array, and the analog-to-digital conversion of the ADC is completed according to the output voltage.

Images