Display panel and display device

Abstract

This application provides a display panel and a display device. The display panel includes a substrate and a driving circuit layer. The driving circuit layer includes multiple pixel driving circuits. Each pixel driving circuit includes a switching transistor, a driving transistor, a first light-emitting control transistor, and a first reset transistor. By placing a shielding portion on the side of the light-emitting control signal line away from the substrate, and placing a first connecting portion on the side of the shielding portion away from the light-emitting control signal line, and ensuring that the orthographic projection of the overlapping portion of the first connecting portion and the light-emitting control signal line on the shielding portion is located within the shielding portion, the shielding portion is used to separate the first connecting portion from the light-emitting control signal line, thereby reducing the parasitic capacitance between the light-emitting control signal line and the first connecting portion. This reduces the impact of voltage changes in the light-emitting control signal line on the voltages of the first and third nodes of the pixel driving circuit, thereby improving the uniformity of brightness of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Organic light-emitting diode (OLED) display technology is a new type of display technology that has gradually attracted attention due to its unique advantages such as low power consumption, high saturation, fast response time and wide viewing angle, and has occupied a certain position in the field of panel display technology.

[0003] Currently, parasitic capacitance exists between the nodes connecting the driving transistor, switching transistor, and light-emitting control transistor in the pixel driving circuit and the light-emitting control signal line. When pulse width modulation (PWM) mode is enabled, the frequency of the light-emitting control signal increases. This causes multiple couplings between the light-emitting control signal line and the nodes connecting the driving transistor, switching transistor, and light-emitting control transistor, resulting in voltage changes at these nodes and causing uneven brightness in the displayed image.

[0004] Therefore, it is necessary to provide a display panel and display device to improve this deficiency. Summary of the Invention

[0005] The embodiments of this application provide a display panel and a display device that can improve the uniformity of brightness of the display panel.

[0006] To achieve the above objectives, embodiments of this application provide a display panel, including a substrate and a driving circuit layer. The driving circuit layer is disposed on one side of the substrate and includes a plurality of pixel driving circuits, each pixel driving circuit comprising:

[0007] A switching transistor, wherein the first electrode of the switching transistor is connected to a data signal line, the second electrode of the switching transistor is connected to a first node, and the switching gate of the switching transistor is connected to a first scan signal line;

[0008] A driving transistor, wherein the first electrode of the driving transistor is connected to the first node, the second electrode of the driving transistor is connected to the second node, and the driving gate of the driving transistor is connected to the third node;

[0009] A first light-emitting control transistor, wherein the first electrode of the first light-emitting control transistor is connected to a first power signal line, the second electrode of the first light-emitting control transistor is connected to the first node, and the first light-emitting control gate of the first light-emitting control transistor is connected to a light-emitting control signal line;

[0010] A first reset transistor, wherein the first electrode of the first reset transistor is connected to a first reset signal line, the second electrode of the first reset transistor is connected to the first node, and the first reset gate of the first reset transistor is connected to a second scan signal line;

[0011] The driving circuit layer further includes a first connection portion and a shielding portion. The first connection portion is connected between the second electrode of the first reset transistor and the first node. The light-emitting control signal line is disposed on one side of the substrate. The shielding portion is disposed on the side of the light-emitting control signal line away from the substrate. The first connection portion is disposed on the side of the shielding portion away from the light-emitting control signal line. The orthographic projection of the first connection portion on the substrate partially overlaps with the orthographic projection of the light-emitting control signal line on the substrate. The orthographic projection of the overlapping portion of the first connection portion and the light-emitting control signal line on the shielding portion is located within the shielding portion.

[0012] Optionally, the shielding portion is connected to the first power signal line.

[0013] Optionally, the driving circuit layer includes:

[0014] A first active layer is disposed on one side of the substrate;

[0015] A first gate layer is disposed on the side of the first active layer away from the substrate, and the gate layer includes the light emission control signal line;

[0016] An oxide semiconductor layer is disposed on the side of the first gate layer away from the first active layer;

[0017] A second gate layer is disposed on the side of the oxide semiconductor layer away from the first gate layer; and

[0018] The first source-drain layer is disposed on the side of the second gate layer away from the oxide semiconductor layer;

[0019] The oxide semiconductor layer includes the shielding portion, and the first source / drain layer includes the first connection portion.

[0020] Optionally, the pixel driving circuit further includes a storage capacitor, wherein the first storage plate of the storage capacitor is connected to the third node, and the second storage plate of the storage capacitor is connected to the first power signal line.

[0021] The first gate layer includes a first memory electrode, the oxide semiconductor layer includes a second memory electrode, and the shielding portion is continuously disposed with the second memory electrode.

[0022] Optionally, the first scanning signal line, the light emission control signal line, and the second scanning signal line extend along a first direction, and the first scanning signal line, the light emission control signal line, and the second scanning signal line are spaced apart along a second direction, wherein the first direction and the second direction are different.

[0023] Wherein, the orthographic projection of the second storage electrode on the substrate is disposed between the orthographic projection of the first scanning signal line on the substrate and the orthographic projection of the light emission control signal line on the substrate, and the orthographic projection of the shielding portion on the substrate is disposed on the side of the orthographic projection of the second storage electrode on the substrate close to the orthographic projection of the light emission control signal line on the substrate.

[0024] Optionally, the first connection portion includes a first sub-connection portion and a second sub-connection portion. The first sub-connection portion extends along the first direction, and the second sub-connection portion extends along the second direction. The first sub-connection portion is connected between the second electrode of the first light-emitting control transistor and the second sub-connection portion, and the second sub-connection portion is connected between the first sub-connection portion and the second electrode of the first reset transistor.

[0025] Optionally, the orthographic projection of the first sub-connection portion on the substrate partially overlaps with the orthographic projection of the second storage electrode on the substrate, a portion of the orthographic projection of the second sub-connection portion on the substrate overlaps with the orthographic projection of the second storage electrode on the substrate, and another portion of the orthographic projection of the second sub-connection portion on the substrate overlaps with the orthographic projection of the shielding portion on the substrate.

[0026] Optionally, the orthographic projection of the first connection portion on the substrate overlaps with the orthographic projection of the first storage electrode plate on the substrate.

[0027] Optionally, the width of the shielding portion along the first direction is greater than the width of the second sub-connecting portion along the first direction.

[0028] Optionally, the width of the shielding portion along the second direction is greater than the width of the light-emitting control signal line along the second direction.

[0029] Optionally, the pixel driving circuit further includes:

[0030] A compensation transistor, wherein the first electrode of the compensation transistor is connected to the third node, the second electrode of the compensation transistor is connected to the second node, and the compensation gate of the compensation transistor is connected to the third scan signal line;

[0031] The second reset transistor has its first electrode connected to the second reset signal line, its second electrode connected to the third node, and its second reset gate connected to the fourth scan signal line.

[0032] The second light-emitting control transistor has a first electrode connected to the second node, a second electrode connected to the fourth node, and a second light-emitting control gate connected to the light-emitting control signal line.

[0033] The third reset transistor has a first electrode connected to a third reset signal line, a second electrode connected to a fourth node, and a second light-emitting control gate connected to the second scan signal line.

[0034] A boost capacitor, wherein the first boost plate of the boost capacitor is connected to the third node, and the second boost plate of the boost capacitor is connected to the first scan signal line.

[0035] Embodiments of this application also provide a display device, which includes a display panel as described above.

[0036] In the display panel of this application embodiment, by setting the shielding portion on the side of the light-emitting control signal line away from the substrate, setting the first connecting portion on the side of the shielding portion away from the light-emitting control signal line, and making the orthographic projection of the overlapping portion of the first connecting portion and the light-emitting control signal line on the shielding portion located inside the shielding portion, the shielding portion is used to separate the first connecting portion from the light-emitting control signal line, thereby reducing the parasitic capacitance between the light-emitting control signal line and the first connecting portion, thereby reducing the impact of voltage changes of the light-emitting control signal line on the voltage of the first node and the third node of the pixel driving circuit, thereby improving the uniformity of brightness of the display panel.

[0037] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0040] Figure 1 A circuit diagram of a pixel driving circuit in a display panel provided for an embodiment of this application;

[0041] Figure 2 A schematic diagram of the film layer structure of a display panel provided for an embodiment of this application;

[0042] Figure 3 This is a film layer diagram of the first active layer in the display panel of this application;

[0043] Figure 4 This is a film layer diagram of the first gate layer in the display panel of this application;

[0044] Figure 5 This is a stack-up diagram of the first active layer and the first gate layer in the display panel of this application;

[0045] Figure 6 This is a film layer diagram of the oxide semiconductor layer in the display panel of this application;

[0046] Figure 7 This is a stack-up diagram of the first active layer, the first gate layer, and the oxide semiconductor layer in the display panel of this application.

[0047] Figure 8 This is a film layer diagram of the second gate layer in the display panel of this application;

[0048] Figure 9 This is a stack-up diagram of the first active layer, the first gate layer, the oxide semiconductor layer, and the second gate layer in the display panel of this application.

[0049] Figure 10 This is a schematic diagram of the openings in the display panel of this application;

[0050] Figure 11 This is a film diagram of the first source / drain layer in the display panel of this application;

[0051] Figure 12 This is a stack-up diagram of the first active layer, first gate layer, oxide semiconductor layer, second gate layer and first source / drain layer in the display panel of this application;

[0052] Figure 13 This is a schematic diagram of the structure of a display device provided in an embodiment of this application.

[0053] Explanation of reference numerals in the attached figures:

[0054] 1. Substrate;

[0055] 2. Driving circuit layer; 201. Barrier layer; 2011. First barrier layer; 2012. Second barrier layer; 202. Shielding layer; 203. Buffer layer; 204. First active layer; 2041. First active part; 205. First gate insulating layer; 206. First gate layer; 207. First interlayer dielectric layer; 208. Oxide semiconductor layer; 209. Second gate insulating layer; 210. Second gate layer; 211. Second interlayer dielectric layer; 212. First source-drain layer; 213. First planarization layer; 214. Second source-drain layer; 215. Second planarization layer;

[0056] 3. Light-emitting device layer; 301. Anode layer; 302. Pixel definition layer; 303. Spacer layer;

[0057] T1, driving transistor; T2, switching transistor; T3, compensation transistor; T4, second reset transistor; T5, first light-emitting control transistor; T6, second light-emitting control transistor; T7, third reset transistor; T8, first reset transistor; Cst, storage capacitor; Cboost, boost capacitor;

[0058] Pscan1, First scan signal line; Pscan1, Second scan signal line; Nscan1, Third scan signal line; Nscan2, Fourth scan signal line; VDD, First power supply signal line; VSS, Second power supply signal line; Vi1, First reset signal line; Vi-Gate, Second reset signal line; EM, Light emission control signal line; Vi-Ano, Third reset signal line.

[0059] 1000, Display device; 100, Display panel; 200, Housing. Detailed Implementation

[0060] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0061] Embodiments of this application provide a display panel, combined with Figure 1 and Figure 2 As shown, Figure 1 A circuit diagram of a pixel driving circuit in a display panel provided for an embodiment of this application. Figure 2This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of this application. The display panel 100 includes a substrate 1 and a driving circuit layer 2. The driving circuit layer 2 is disposed on one side of the substrate 1 and includes a plurality of pixel driving circuits 20. The display panel 100 also includes a plurality of light-emitting devices 21. Each pixel driving circuit 20 is electrically connected to a corresponding light-emitting device 21.

[0062] In embodiments of this application, the pixel driving circuit 20 includes a switching transistor T2, a driving transistor T1, a first light-emitting control transistor T5, and a first reset transistor T8. The first electrode of the switching transistor T2 is connected to the data signal line Data, the second electrode of the switching transistor T2 is connected to the first node A, and the switching gate of the switching transistor T2 is connected to the first scan signal line Pscan1. The first electrode of the driving transistor T1 is connected to the first node A, the second electrode of the driving transistor T1 is connected to the second node B, and the driving gate of the driving transistor T1 is connected to the third node Q. The first electrode of the first light-emitting control transistor T5 is connected to the first power signal line VDD, the second electrode of the first light-emitting control transistor T5 is connected to the first node A, and the first light-emitting control gate of the first light-emitting control transistor T5 is connected to the light-emitting control signal line EM. The first electrode of the first reset transistor T8 is connected to the first reset signal line Vi1, the second electrode of the first reset transistor T8 is connected to the first node A, and the first reset gate of the first reset transistor T8 is connected to the second scan signal line Pscan2.

[0063] In embodiments of this application, the driving circuit layer 2 further includes a first connection portion and a shielding portion. The first connection portion is connected between the second electrode of the first reset transistor T8 and the first node A. The light-emitting control signal line EM is disposed on one side of the substrate 1, and the shielding portion is disposed on the side of the light-emitting control signal line EM away from the substrate 1. The first connection portion is disposed on the side of the shielding portion away from the light-emitting control signal line EM. The orthographic projection of the first connection portion on the substrate 1 overlaps with the orthographic projection of the light-emitting control signal line EM on the substrate 1, and the orthographic projection of the overlapping portion of the first connection portion and the light-emitting control signal line EM on the shielding portion is located within the shielding portion.

[0064] This application addresses the issue of parasitic capacitance between the light-emitting control signal line EM and the first connection portion by placing a shielding portion on the side of the shielding portion away from the substrate and placing the first connection portion on the side of the shielding portion away from the light-emitting control signal line EM. The projection of the overlapping portion of the first connection portion and the light-emitting control signal line EM onto the shielding portion is located within the shielding portion. This utilizes the shielding portion to separate the first connection portion from the light-emitting control signal line EM, thereby reducing the impact of voltage changes in the light-emitting control signal line EM on the voltages of the first node A and the third node Q of the pixel driving circuit, thus improving the uniformity of brightness in the display panel.

[0065] In some embodiments, the light-emitting device 21 can be any one of a light-emitting diode, an organic light-emitting diode, a mini light-emitting diode, a micro light-emitting diode chip, and other light sources.

[0066] In some embodiments, such as Figure 1 As shown, the pixel driving circuit 20 includes a switching transistor T2, a driving transistor T1, a compensation transistor T3, a second reset transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a third reset transistor T7, a first reset transistor T8, a storage capacitor Cst, and a boost capacitor Cboost.

[0067] like Figure 1As shown, the first electrode of switching transistor T2 is connected to the data signal line Data, the second electrode of switching transistor T2 is connected to the first node A, and the switching gate of switching transistor T2 is connected to the first scan signal line Pscan1. The first electrode of driving transistor T1 is connected to the first node A, the second electrode of driving transistor T1 is connected to the second node B, and the driving gate of driving transistor T1 is connected to the third node Q. The first electrode of compensation transistor T3 is connected to the third node Q, the second electrode of compensation transistor T3 is connected to the second node B, and the compensation gate of compensation transistor T3 is connected to the third scan signal line Nscan1. The first electrode of the second reset transistor T4 is connected to the second reset signal line Vi-Gate, the second electrode of the second reset transistor T4 is connected to the third node Q, and the first reset gate of the second reset transistor T4 is connected to the fourth scan signal line Nscan2. The first electrode of the first light-emitting control transistor T5 is connected to the first power supply signal line VDD, the second electrode of the first light-emitting control transistor T5 is connected to the first node A, and the first light-emitting control gate of the first light-emitting control transistor T5 is connected to the light-emitting control signal line EM. The first electrode of the second light-emitting control transistor T6 is connected to the second node B, the second electrode of the second light-emitting control transistor T6 is connected to the fourth node C, and the second light-emitting control gate of the second light-emitting control transistor T6 is connected to the light-emitting control signal line EM. The first electrode of the third reset transistor T7 is connected to the third reset signal line Vi-Ano, the second electrode of the third reset transistor T7 is connected to the fourth node C, and the third reset gate of the third reset transistor T7 is connected to the second scan signal line Pscan2. The first electrode of the first reset transistor T8 is connected to the first reset signal line Vi1, the second electrode of the first reset transistor T8 is connected to the first node A, and the first reset gate of the first reset transistor T8 is connected to the second scan signal line Pscan2. The first storage plate of the storage capacitor Cst is connected to the first power supply signal line VDD, and the second storage plate of the storage capacitor Cst is connected to the third node Q. The first boost plate of the boost capacitor Cboost is connected to the first scan signal line Pscan1, and the second boost plate of the boost capacitor Cboost is connected to the third node Q. The anode of the light-emitting device 21 is connected to the fourth node C, and the cathode of the light-emitting device 21 is connected to the second power supply signal line VSS.

[0068] In the embodiments of this application, the first source signal line VDD is a DC high-voltage power supply signal line, which is used to provide a constant voltage high-level signal to the pixel driving circuit 20. The second power supply signal line VSS is a DC low-voltage power supply signal line, which is used to provide a constant voltage low-level signal to the pixel driving circuit 20.

[0069] In the embodiments of this application, the driving transistor T1, the switching transistor T2, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the third reset transistor T7, and the first reset transistor T8 can be either P-type transistors or N-type transistors, and the compensation transistor T3 and the second reset transistor T4 can be either P-type transistors or N-type transistors. This application uses an example where the driving transistor T1, the switching transistor T2, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the third reset transistor T7, and the first reset transistor T8 are P-type transistors, and the compensation transistor T3 and the second reset transistor T4 are N-type transistors.

[0070] It should be noted that in the embodiments of this application, the first electrode of the transistor is one of the source and the drain, and the second electrode is the other of the source and the drain. Furthermore, the first electrode and the second electrode of each transistor may be the same or different.

[0071] It should also be noted that in the following embodiments, the angle between the first direction X and the second direction Y is greater than 0° and less than or equal to 90°. For example, the first direction X is horizontal and the second direction Y is vertical.

[0072] In some embodiments, the shielding portion is connected to the first power signal line VDD. This connection can mean either a direct connection or a connection via another conductive trace, allowing the shielding portion to receive a DC high-voltage power signal. Since the DC high-voltage power signal transmitted via the first power signal line VDD is highly stable, the shielding portion connected to the DC high-voltage power signal can effectively shield the high-frequency light-emitting control signal transmitted via the light-emitting control signal line EM, thereby effectively reducing the coupling capacitance between the first node A and the light-emitting control signal line EM.

[0073] In practical applications, the shielding part can be connected not only to the first power signal line VDD, but also to the second reset signal line Vi-Gate that transmits DC signals. This can also effectively reduce the coupling capacitance between the first node A and the light emission control signal line EM.

[0074] The following is about Figure 1 The circuit structure shown describes the film structure of the pixel driving circuit of this application.

[0075] In some embodiments, the display panel includes a substrate 1, a first gate layer 206, an oxide semiconductor layer 208, a second gate layer 210, and a first source-drain layer 212. The first gate layer 206 is disposed on one side of the substrate 1 and includes a light-emitting control signal line EM. The oxide semiconductor layer 208 is disposed on the side of the first gate layer 206 away from the substrate 1, the second gate layer 210 is disposed on the side of the oxide semiconductor layer 208 away from the first gate layer 206, and the first source-drain layer 212 is disposed on the side of the second gate layer 210 away from the oxide semiconductor layer 208. The oxide semiconductor layer 208 includes a shielding portion, and the first source-drain layer 212 includes a first connection portion.

[0076] like Figure 2 As shown, the display panel includes a substrate 1, a barrier layer 201 disposed on the substrate 1, a shielding layer 202 disposed on the barrier layer 201, a buffer layer 203 disposed on the shielding layer 202, a first active layer 204 disposed on the buffer layer 203, a first gate insulating layer 205 disposed on the first active layer 204, a first gate layer 206 disposed on the first gate insulating layer 205, a first interlayer dielectric layer 207 disposed on the first gate layer 206, and an oxide semiconductor disposed on the first interlayer dielectric layer 207. The structure includes a conductor layer 208, a second gate insulating layer 209 disposed on the oxide semiconductor layer 208, a second gate layer 210 disposed on the second gate insulating layer 209, a second interlayer dielectric layer 211 disposed on the second gate layer 210, a first source-drain layer 212 disposed on the second interlayer dielectric layer 211, a first planarization layer 213 disposed on the first source-drain layer 212, a second source-drain layer 214 disposed on the first planarization layer 213, and a second planarization layer 215 disposed on the second source-drain layer 214.

[0077] like Figure 2 As shown, the barrier layer 201 is disposed on the substrate 1, and the buffer layer 203 is disposed on the barrier layer 201. The barrier layer 201 and the buffer layer 203 are used to isolate the shielding layer 202 and the upper metal material. Both the barrier layer 201 and the buffer layer 203 can be a single-layer structure or a stacked structure formed of at least one of silicon nitride, silicon oxide and silicon oxynitride.

[0078] In some embodiments, such as Figure 2 As shown, the barrier layer 201 is a stacked structure formed by stacking the first barrier layer 2011 and the second barrier layer 2012. The material of the first barrier layer 2011 is one of silicon nitride and silicon oxide, and the material of the second barrier layer 2012 is the other of silicon nitride and silicon oxide. The shielding layer 202 is disposed between the first barrier layer 2011 and the second barrier layer 2012.

[0079] like Figure 2As shown, the first active layer 204 is disposed on the surface of the buffer layer 203 away from the barrier layer 201. The material of the first active layer 204 includes silicon semiconductor material, which may specifically be amorphous silicon or low-temperature polycrystalline silicon.

[0080] like Figure 2 As shown, a first gate insulating layer 205 is disposed on the surface of the first active layer 204 away from the buffer layer 203, a first interlayer dielectric layer 207 is disposed on the surface of the first gate layer 206 away from the first gate insulating layer 205, a second gate insulating layer 209 is disposed on the surface of the oxide semiconductor layer 208 away from the first interlayer dielectric layer 207, and a second interlayer dielectric layer 211 is disposed on the surface of the second gate layer 210 away from the second gate insulating layer 209. The first gate insulating layer 205, the first interlayer dielectric layer 207, the second gate insulating layer 209, and the second interlayer dielectric layer 211 can all be single-layer structures or stacked structures formed of at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0081] In the embodiments of this application, the first gate insulating layer 205 and the second gate insulating layer 209 are single-layer structures formed of silicon oxide material, and the first interlayer dielectric layer 207 and the second interlayer dielectric layer 211 are stacked structures formed of silicon oxide and silicon nitride material, with the silicon nitride material layer located on the side of the silicon oxide material layer away from the oxide semiconductor layer 208.

[0082] like Figure 2 As shown, the first gate layer 206 is disposed on the surface of the first gate insulating layer 205 away from the first active layer 204, the second gate layer 210 is disposed on the surface of the second gate insulating layer 209 away from the oxide semiconductor layer 208, the first source-drain layer 212 is disposed on the surface of the second interlayer dielectric layer 211 away from the second gate layer 210, and the second source-drain layer 214 is disposed on the surface of the first planarization layer 213 away from the first source-drain layer 212. The first gate layer 206, the second gate layer 210, the first source-drain layer 212, and the second source-drain layer 214 are respectively disposed on the corresponding insulating layer or interlayer dielectric layer. The first gate layer 206, the second gate layer 210, the first source-drain layer 212, and the second source-drain layer 214 can be a single-layer structure formed by at least one of copper, molybdenum, titanium, aluminum, silver, etc., or a stacked structure formed by at least two of the above-mentioned metal materials.

[0083] like Figure 2 As shown, the oxide semiconductor layer 208 is disposed on the surface of the first interlayer dielectric layer 207 away from the first gate layer 206, and the material of the oxide semiconductor layer 208 can be indium gallium zinc oxide.

[0084] like Figure 2As shown, the first planarization layer 213 is disposed on the first source-drain layer 212, and the second planarization layer 215 is disposed on the second source-drain layer 214. The materials of the first planarization layer 213 and the second planarization layer 215 can be at least one inorganic insulating material selected from silicon nitride, silicon oxide, or silicon oxynitride, or they can be organic insulating materials with leveling properties.

[0085] like Figure 2 As shown in the embodiments of this application, the display panel further includes a light-emitting device layer 3. The light-emitting device layer 3 is disposed on the side of the second planarization layer 215 away from the second source-drain layer 214. The light-emitting device layer 3 includes an anode layer 301 disposed on the second planarization layer 215, a pixel definition layer 302 disposed on the anode layer 301, a spacer layer 303 disposed on the pixel definition layer 302, a light-emitting material layer and a cathode layer (not shown in the figure) disposed on the pixel definition layer 302.

[0086] like Figure 3 As shown, Figure 3 This is a film layer diagram of the first active layer in the display panel of this application. The first active layer 204 includes a driving active portion T1A of a driving transistor T1, a switching active portion T2A of a switching transistor T2, a first light-emitting control active portion T5A of a first light-emitting control transistor T5, a second light-emitting control active portion T6A of a second light-emitting control transistor T6, a third reset active portion T7A of a third reset transistor T7, and a first reset active portion T8A of a first reset transistor T8.

[0087] like Figure 3 As shown, the driving active part T1A, the switching active part T2A, the first light-emitting control active part T5A, the second light-emitting control active part T6A, and the third reset active part T7A are connected to each other. The first reset active part T8A is separated from the other active parts. The switching active part T2A, the first light-emitting control active part T5A, and the first reset active part T8A are all elongated and extend along the second direction Y. The second light-emitting control active part T6A and the second reset active part T7A are both "L" shaped. The driving active part T1A is "U" shaped and is located between the first light-emitting control active part T5A and the second light-emitting control active part T6A.

[0088] like Figure 3 As shown, the first terminal of the active switch TA2, the first terminal of the active drive T1A, and the first terminal of the first light-emitting control transistor T5A are all connected to the first connection point P1. The second terminal of the active drive T1A and the first terminal of the second light-emitting control active transistor T6A are connected to the second connection point P2. The second terminal of the first light-emitting control active transistor T5A and the second terminal of the second light-emitting control active transistor T6A are connected to the third connection point P3.

[0089] In this embodiment, the first connection point P1 is the first node A, the second connection point P2 is the second node B, and the third connection point P3 is the location of the anode of the light-emitting device 21, that is, the third connection point P3 is the fourth node C.

[0090] like Figure 4 As shown, Figure 4 The first gate layer 206 in the display panel of this application is a film layer diagram. The first gate layer 206 includes the driving gate T1G of the driving transistor T1, the switching gate T2G of the switching transistor T2, the first light-emitting control gate T5G of the first light-emitting control transistor T5, the second light-emitting control gate T6G of the second light-emitting control transistor T6, the third reset gate T7G of the third reset transistor T7, the first reset gate T8G of the first reset transistor T8, the first storage plate Cst1 of the storage capacitor Cst, the first boost plate Cboost1 of the boost capacitor Cboost, the first scan signal line Pscan1, the second scan signal line Pscan2, the light-emitting control signal line EM, and the third reset signal line Vi-Ano.

[0091] like Figure 4 As shown, the first scan signal line Pscan1, the second scan signal line Pscan2, the light emission control signal line EM, and the third reset signal line Vi-Ano all extend along the first direction X, and are arranged at intervals along the second direction Y. The driving gate T1G and the first memory plate Cst1 are both disposed between the first scan signal line Pscan1 and the light emission control signal line EM. The second scan signal line Pscan2 is disposed on the side of the light emission control signal line EM away from the driving gate T1G, and the third reset signal line Vi-Ano is disposed on the side of the second scan signal line Pscan2 away from the light emission control signal line EM. The first light emission control gate T5G is connected to the second light emission control gate T6G and the light emission control signal line EM, and the second reset gate T7G is connected to the first reset gate T8G and the first scan signal line Pscan1.

[0092] In this embodiment, the driving gate T1G can be reused as the first storage plate Cst1 of the storage capacitor Cst, the light emission control signal line EM can be directly used as the first light emission control gate T5G and the second light emission control gate T6G, the first scan signal line Pscan1 can be directly used as the switching gate T2G and the first boost plate Cboost1 of the boost capacitor Cboost, and the second scan signal line Pscan2 can be directly used as the second reset gate T7G and the first reset gate T8G.

[0093] Combination Figure 4 and Figure 5As shown, Figure 5 This is a stack-up diagram of the first active layer and the first gate layer in the display panel of this application. The driving gate T1G partially overlaps with the driving active portion T1A, and the overlapping portion of the driving gate T1G and the active portion T1A forms the channel of the driving active portion T1A. The switching gate T2G partially overlaps with the switching active portion T2A, and the overlapping portion of the switching gate T2G and the switching active portion T2A forms the channel of the switching active portion T2A. The first light-emitting control gate T5G partially overlaps with the first light-emitting control active portion T5A, and the overlapping portion of the first light-emitting control gate T5G and the first light-emitting control active portion T5A forms the channel of the first light-emitting control active portion T5A. The second light-emitting control gate T6G partially overlaps with the second light-emitting control active portion T6A, and the overlapping portion of the second light-emitting control gate T6G and the second light-emitting control active portion T6A forms the channel of the second light-emitting control active portion T6A. The second reset gate T7G partially overlaps with the second reset active portion T7A, and the overlapping portion of the second reset gate T7G and the second reset active portion T7A forms the channel of the second reset active portion T7A. The first reset gate T8G partially overlaps with the first reset active portion T8A, and the overlapping portion of the first reset gate T8G and the first reset active portion T8A forms the channel of the first reset active portion T8A.

[0094] like Figure 6 As shown, Figure 6 This is a film layer diagram of the oxide semiconductor layer in the display panel of this application. The oxide semiconductor layer 208 includes the compensation active part T3A of the compensation transistor T3, the second reset active part T4A of the second reset transistor T4, the second storage plate Cst2 of the storage capacitor Cst, the second boost plate Cboost2 of the boost capacitor Cboost, and the shielding part 2081.

[0095] like Figure 6 As shown, the compensation active part T13A and the second reset active part T4A extend along the second direction Y. The second storage electrode Cst2 has a block structure, and the shielding part 2081 has a block structure. The apex corners of the second storage electrode Cst2 and the shielding part 2081 can be right angles or be chamfered. In the same pixel driving circuit, the compensation active part T13A and the second reset active part T14A are arranged continuously, as are the second storage electrode Cst2 and the shielding part 2081. In two adjacent pixel driving circuits, the second storage electrode Cst2 of one pixel driving circuit is arranged continuously with the second storage electrode Cst2 of the adjacent pixel driving circuit.

[0096] Combination Figure 6 and Figure 7 As shown, Figure 7This is a stack-up diagram of the first active layer, the first gate layer, and the oxide semiconductor layer in the display panel of this application. The first storage plate Cst1 and the second storage plate Cst2 are overlapped to form a storage capacitor Cst. The area of ​​the second storage plate Cst2 is larger than the area of ​​the first storage plate Cst1. The orthographic projection of the first storage plate Cst1 onto the substrate 1 lies within the orthographic projection of the second storage plate Cst2 onto the substrate 1. The second storage plate Cst2 has a first hole H1 that penetrates through it and exposes the underlying driving gate T1G. The portion of the first scan signal line Pscan1 that overlaps with the second boost plate Cboost2 can serve as the first boost plate Cboost1. The first boost plate Cboost1 and the second boost plate Cboost2 together constitute the boost capacitor Cboost.

[0097] like Figure 7 As shown, the orthographic projection of the second storage plate Cst1 on the substrate 1 is positioned between the orthographic projection of the first scan signal line Pscan1 on the substrate 1 and the orthographic projection of the light emission control signal line EM on the substrate 1. The orthographic projection of the shielding portion 2081 on the substrate 1 is positioned on the side of the second storage plate Cst2 on the substrate 1 closest to the orthographic projection of the light emission control signal line EM on the substrate 1, and the orthographic projection of the shielding portion 2081 on the substrate 1 partially overlaps with the orthographic projection of the light emission control signal line EM on the substrate 1. The shielding portion 2081 extends from the side of the light emission control signal line EM closest to the first scan signal line Pscan1 to the side of the light emission control signal line EM furthest from the first scan signal line Pscan1, and partially overlaps with the light emission control signal line EM.

[0098] like Figure 8 As shown, Figure 8 The image shows a film layer diagram of the second gate layer in the display panel of this application. The second gate layer 210 includes the compensation gate T3G of the compensation transistor T3, the second reset gate T4G of the second reset transistor T4, the third scan signal line Nscan1, the fourth scan signal line Nscan2, and the first reset signal line Vi1.

[0099] like Figure 8 As shown, the third scan signal line Nscan1, the fourth scan signal line Nscan2, and the first reset signal line Vi1 extend along the first direction X, and are spaced apart along the second direction Y. The first scan signal line Nscan1 is located between the fourth scan signal line Nscan2 and the first reset signal line Vi1. The third scan signal line Nscan1 can be multiplexed as the compensation gate T3G of the compensation transistor T3, and the fourth scan signal line Nscan2 can be multiplexed as the second reset gate T4G of the second reset transistor T4.

[0100] Combination Figure 8 and Figure 9 As shown, Figure 9 This is a stack-up diagram of the first active layer, the first gate layer, the oxide semiconductor layer, and the second gate layer in the display panel of this application. The compensation gate T3G partially overlaps with the compensation active portion T3A, and the overlapping portion of the compensation gate T3G and the compensation active portion T3A forms the channel of the compensation active portion T3A. The second reset gate T4G partially overlaps with the second reset active portion T4A, and the overlapping portion of the second reset gate T4G and the second reset active portion T4A forms the channel of the second reset active portion T4A.

[0101] like Figure 9 As shown, the orthographic projection of the third scan signal line Nscan1 on substrate 1 is positioned between the orthographic projection of the first scan signal line Pscan1 on substrate 1 and the orthographic projection of the second memory plate Cst2 on substrate 1. The orthographic projection of the fourth scan signal line Nscan2 on substrate 1 is positioned between the orthographic projection of the first scan signal line Pscan1 on substrate 1 and the orthographic projection of the third reset signal line Vi-Ano on substrate 1.

[0102] Combination Figures 10 to 12 As shown, Figure 10 This is a schematic diagram of the openings in the display panel of this application. Figure 11 This is a film layer diagram of the first source / drain layer in the display panel of this application. Figure 12 This is a stack-up diagram of the first active layer, the first gate layer, the oxide semiconductor layer, the second gate layer, and the first source-drain layer in the display panel of this application. The first source-drain layer 212 includes a first connection portion 2121, which is connected between the second electrode of the first reset transistor T8 and the first node A.

[0103] like Figure 11 As shown, the first end of the first connecting portion 2121 is connected to the first end of the first light-emitting control active portion T5A, the first end of the switching active portion T2A, and the first end of the driving active portion T1A through the second hole H2. The second end of the first connecting portion 2121 is connected to the first end of the first reset active portion T8A through the third hole H3. The orthographic projection of the first connecting portion 2121 on the substrate 1 partially overlaps with the orthographic projection of the light-emitting control signal line EM on the substrate 1. The orthographic projection of the overlapping portion of the first connecting portion 2121 and the light-emitting control signal line EM on the shielding portion 2081 is located inside the shielding portion 2081.

[0104] Combination Figure 1 and Figure 11As shown, when the pulse width modulation mode is enabled, the frequency of the light emission control signal transmitted by the light emission control signal line EM becomes higher. Since the first connection part 2121 connected to the first node A partially overlaps with the light emission control signal line EM, the light emission control signal line EM indirectly couples to the first node A multiple times by coupling to the first connection part 2121, causing the potential of the first node A to change. Due to the gate-source parasitic capacitance of the driving transistor T1, the potential of the third node Q also changes, thereby directly affecting the current of the driving transistor T1, which exacerbates the uneven brightness of the display panel when displaying low grayscale images. In this embodiment, a shielding portion 2081 is added between the first connecting portion 2121 and the light-emitting control signal line EM. The shielding portion 2081 separates the first connecting portion 2121 and the light-emitting control signal line EM, thereby reducing the vertical coupling capacitance between the first connecting portion 2121 and the light-emitting control signal line EM, that is, reducing the coupling capacitance between the first node A and the light-emitting control signal line EM. This reduces the proportion of the total capacitance of the coupling capacitance between the light-emitting control signal line EM and the first node A at the first node A, thereby mitigating the impact of the increased frequency of the light-emitting control signal on the potential of the first node A and preventing voltage coupling changes at the first node A from affecting the potential of the third node Q, thus improving the uniformity of the brightness of the display panel.

[0105] In this embodiment, the shielding portion 2081 and the second storage plate Cst2 are continuously disposed. The shielding portion 2081 and the second storage plate Cst2 can be regarded as two parts of the same oxide semiconductor pattern. This embodiment can also be regarded as increasing the area of ​​the second storage plate Cst2 so that the second storage plate Cst2 extends between the first connecting portion 2121 and the light-emitting control signal line EM. Since the second storage plate Cst2 is connected to the first power signal line VDD, the DC high-voltage power signal transmitted by the first power signal line VDD has high stability. Thus, the second storage plate Cst2 can be used to shield the high-frequency light-emitting control signal transmitted by the light-emitting control signal line EM, thereby effectively reducing the vertical coupling capacitance and part of the lateral capacitance between the first node A and the light-emitting control signal line EM.

[0106] In this embodiment, the second hole H2 penetrates the second interlayer dielectric layer 211, the second gate insulating layer 209, the first interlayer dielectric layer 207, and the first gate insulating layer 205, and the third hole H3 penetrates the second interlayer dielectric layer 211, the second gate insulating layer 209, the first interlayer dielectric layer 207, and the first gate insulating layer 205.

[0107] Combination Figures 10 to 12As shown, the first connection portion 2121 includes a first sub-connection portion 21211 and a second sub-connection portion 21212. The first sub-connection portion 21211 extends along a first direction X, and the second sub-connection portion 21212 extends along a second direction Y. The first sub-connection portion 21211 is connected between the second electrode of the first light-emitting control transistor T5 and the second sub-connection portion 21212, and the second sub-connection portion 21212 is connected between the first sub-connection portion 21211 and the second electrode of the first reset transistor T8.

[0108] In this embodiment, the first electrode and the second electrode of the first light-emitting control transistor T5 can be formed by a conductor-forming process from the first terminal and the second terminal of the first light-emitting control active portion T5A. Therefore, the first terminal and the second terminal of the first light-emitting control active portion T5A can be regarded as the first electrode and the second electrode of the first light-emitting control transistor T5. The same applies to other transistors, which will not be described in detail here.

[0109] Combination Figures 10 to 12 As shown, the orthographic projection of the first sub-connection portion 21211 on the substrate 1 partially overlaps with the orthographic projection of the second storage plate Cst2 on the substrate 1. A portion of the orthographic projection of the second sub-connection portion 21212 on the substrate 1 overlaps with the orthographic projection of the second storage plate Cst2 on the substrate 1. The other portion of the orthographic projection of the second sub-connection portion 21212 on the substrate 1 overlaps with the orthographic projection of the shielding portion 2081 on the substrate 1.

[0110] In this embodiment, by increasing the area of ​​the second storage plate Cst2 and changing the orientation of the first connecting portion 2121, the overlap area between the first connecting portion 2121 and the second storage plate Cst2 is increased. This not only allows the portion of the first connecting portion 2121 that overlaps with the light-emitting control signal line EM to overlap with the shielding portion 2081, thereby reducing the vertical coupling capacitance between the first node A and the light-emitting control signal line EM, but also allows the portion of the first connecting portion 2121 that does not overlap with the light-emitting control signal line EM to overlap with the shielding portion 2081 or the second storage plate Cst2. This reduces the lateral coupling capacitance between the first node A and the light-emitting control signal line EM, thereby further reducing the coupling capacitance between the first node A and the light-emitting control signal line EM, and further improving the uniformity of brightness of the display panel in pulse width modulation mode.

[0111] In some embodiments, the orthographic projection of the first connection portion 2121 on the substrate 1 overlaps with the orthographic projection of the first storage electrode on the substrate.

[0112] Combination Figures 10 to 12As shown, the first sub-connection 21211 of the first connection portion 2121 extends above the first storage electrode Cst1 along the first direction X and partially overlaps with the first storage electrode Cst1 in the thickness direction. The second sub-connection 21212 extends above the first storage electrode Cst1 along the second direction Y and partially overlaps with the first storage electrode Cst1 in the thickness direction. The portion of the first connection portion 2121 that overlaps with the first storage electrode Cst1 also overlaps with the second storage electrode Cst2. In this way, by changing the orientation of the first connection portion 2121, the first connection portion 2121 can be routed more towards the first storage electrode Cst1 and the second storage electrode Cst2, thereby further increasing the overlap area between the first connection portion 2121 and the second storage electrode Cst2. This increases the shielding area of ​​the second storage electrode Cst2 and the shielding portion 2081 on the first connection portion 2121, thereby further reducing the lateral coupling capacitance between the first node A and the light-emitting control signal line EM.

[0113] like Figure 12 As shown, the width of the shielding portion 2081 along the first direction X is greater than the width of the second sub-connecting portion 21212 along the first direction X. The width of the second sub-connecting portion 21212 along the first direction X is the line width of the second sub-connecting portion 21212. By making the width of the shielding portion 2081 along the first direction X greater than the line width of the second sub-connecting portion 21212, the shielding portion 2081 can block the areas on both sides of the second sub-connecting portion 21212, thereby further reducing the lateral coupling capacitance between the first connecting portion 2121 and the light emission control signal line EM.

[0114] Combination Figure 7 and Figure 12 As shown, the width of the shielding portion 2081 along the second direction Y is greater than the width of the light-emitting control signal line EM along the second direction Y. It should be noted that the width of the light-emitting control signal line EM along the second direction Y refers to the width of the portion of the light-emitting control signal line EM overlapping with the first connecting portion 2121 along the second direction Y. That is, the width of the shielding portion 2081 along the second direction Y is greater than the line width of the overlapping portion of the light-emitting control signal line EM and the first connecting portion 2121. In this way, the shielding portion 2081 can block the areas on both sides of the light-emitting control signal line EM, thereby further reducing the lateral coupling capacitance between the first connecting portion 2121 and the light-emitting control signal line EM.

[0115] Combination Figures 10 to 12As shown, the first source-drain layer 212 includes a second connection portion 2122, which is elongated along a direction intersecting the first direction X and the second direction Y. The first end of the second connection portion 2122 is connected to the driving gate T1G through a fourth hole H4, and the second end of the second connection portion 2122 is connected to the first end of the compensation active portion T3A, the first end of the second reset active portion T4A, and the first boost plate Cboost1 through a fifth hole H5.

[0116] In this embodiment, the fourth hole H4 penetrates the second interlayer dielectric layer 211, the second gate insulating layer 209, and the first interlayer dielectric layer 207, and the fifth hole H5 penetrates the second interlayer dielectric layer 211, the second gate insulating layer 209, the first interlayer dielectric layer 207, and the first gate insulating layer 205.

[0117] Combination Figures 10 to 12 As shown, the first source-drain layer 212 includes a third connection portion 2123, which is elongated along the second direction Y. The first end of the third connection portion 2123 is connected to the second end of the compensation active portion T3A through a sixth hole H6, and the second end of the third connection portion 2123 is connected to the first end of the driving active portion T1A and the first end of the second light-emitting control active portion T6A through a seventh hole H7.

[0118] In this embodiment, the sixth hole penetrates the second interlayer dielectric layer 211 and the second gate insulating layer 209, and the seventh hole H7 penetrates the second interlayer dielectric layer 211, the second gate insulating layer 209, the first interlayer dielectric layer 207 and the first gate insulating layer 205.

[0119] Combination Figures 10 to 12 As shown, the first source-drain layer 212 includes a second reset signal line Vi-Gate and a first power signal line VDD, which extend along a first direction X. The first power signal line VDD is connected to the second storage plate Vst2 through the eighth hole H8, and to the second end of the first light-emitting control active part T5A through the ninth hole H9. The second reset signal line Vi-Gate is connected to the second end of the second reset active part T14A through the sixteenth hole H16.

[0120] In this embodiment, the eighth hole H8 penetrates the second interlayer dielectric layer 211 and the second gate insulating layer 209, and the ninth hole H9 penetrates the second interlayer dielectric layer 211, the second gate insulating layer 209, the first interlayer dielectric layer 207 and the first gate insulating layer 205.

[0121] Combination Figures 10 to 12As shown, the first source-drain layer 212 also includes a fourth connection portion 2124. The fourth connection portion 2124 is a block structure and is rectangular in shape. The top corner of the rectangle can be a right angle or be chamfered. The fourth connection portion 2124 is connected to the second end of the active switching portion T2A through the tenth hole H10.

[0122] In this embodiment, the tenth hole H10 penetrates the second interlayer dielectric layer 211, the second gate insulating layer 209, the first interlayer dielectric layer 207, and the first gate insulating layer 205.

[0123] Combination Figures 10 to 12 As shown, the first source-drain layer 212 further includes a fifth connection portion 2125 and a sixth connection portion 2126. The fifth connection portion 2125 has a block-shaped structure, and the sixth connection portion 2126 has an elongated strip-shaped structure extending along the first direction X. The fifth connection portion 2125 is connected to the second end of the second light-emitting control active portion T6A and the first end of the third reset active portion T7A through the eleventh hole H11. The first end of the sixth connection portion 2126 is connected to the second end of the third reset active portion T7A through the twelfth hole H12, and the second end of the sixth connection portion 2126 is connected to the third reset signal line Vi-Ano through the thirteenth hole H13.

[0124] In this embodiment, the eleventh hole H11 penetrates the second interlayer dielectric layer 211, the second gate insulating layer 209, the first interlayer dielectric layer 207, and the first gate insulating layer 205; the twelfth hole H12 penetrates the second interlayer dielectric layer 211, the second gate insulating layer 209, the first interlayer dielectric layer 207, and the first gate insulating layer 205; and the thirteenth hole H13 penetrates the second interlayer dielectric layer 211, the second gate insulating layer 209, and the first interlayer dielectric layer 207.

[0125] Combination Figures 10 to 12 As shown, the first source-drain layer 212 also includes a seventh connection portion 2127. The seventh connection portion 2127 is a long strip structure extending along the first direction X. The first end of the seventh connection portion 2127 is connected to the second end of the first reset active portion T8A through the fourteenth hole H14, and the second end of the seventh connection portion 2127 is connected to the first reset signal line Vi1 through the fifteenth hole H15.

[0126] In this embodiment, the fourteenth hole H14 penetrates the second interlayer dielectric layer 211, the second gate insulating layer 209, the first interlayer dielectric layer 207 and the first gate insulating layer 205, and the fifteenth hole H15 penetrates the second interlayer dielectric layer 211.

[0127] In an embodiment of this application, the second source-drain layer 214 includes a data signal line Data, which extends along the second direction Y and is spaced apart along the first direction X.

[0128] In some embodiments, the first scan signal line Pscan1 is the first scan signal line Pscan(n), the second scan signal line Pscan2 is the second scan signal line Pscan(n-1), the third scan signal line Nscan1 is the third scan signal line Nscan(n), and the fourth scan signal line Nscan2 is the fourth scan signal line Nscan(n-5), where n is a positive integer.

[0129] Embodiments of this application also provide a display device, combined with Figure 13 As shown, Figure 13 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. The display device 1000 includes a display panel 100 and a housing 200. The display panel 100 is disposed on the housing 200. The display panel 100 can be any of the display panels 100 provided in the above embodiments. The display device 1000 can be a mobile display device, such as a smartphone, smartwatch, tablet computer, or laptop computer. The display device 1000 can also be a fixed display device, such as a television or desktop computer.

[0130] The beneficial effects of the embodiments of this application are as follows: The embodiments of this application provide a display panel, which includes a substrate and a driving circuit layer. The driving circuit layer includes multiple pixel driving circuits. Each pixel driving circuit includes a switching transistor, a driving transistor, a first light-emitting control transistor, and a first reset transistor. By placing a shielding portion on the side of the light-emitting control signal line away from the substrate, and placing a first connecting portion on the side of the shielding portion away from the light-emitting control signal line, and ensuring that the orthographic projection of the overlapping portion of the first connecting portion and the light-emitting control signal line on the shielding portion is located within the shielding portion, the shielding portion is used to separate the first connecting portion from the light-emitting control signal line, thereby reducing the parasitic capacitance between the light-emitting control signal line and the first connecting portion. This reduces the impact of voltage changes in the light-emitting control signal line on the voltages of the first and third nodes of the pixel driving circuit, thereby improving the uniformity of the brightness of the display panel.

[0131] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0132] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0133] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0134] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, The device includes a substrate and a driving circuit layer. The driving circuit layer is disposed on one side of the substrate. The driving circuit layer includes a first active layer, a first gate layer, an oxide semiconductor layer, a second gate layer, a first source-drain layer, and a plurality of pixel driving circuits. The first active layer is disposed on one side of the substrate. The first gate layer is disposed on the side of the first active layer away from the substrate, and the gate layer includes light emission control signal lines. The oxide semiconductor layer is disposed on the side of the first gate layer away from the first active layer. The second gate layer is disposed on the side of the oxide semiconductor layer away from the first gate layer. The first source-drain layer is disposed on the side of the second gate layer away from the oxide semiconductor layer. The pixel driving circuit includes: A switching transistor, wherein the first electrode of the switching transistor is connected to a data signal line, the second electrode of the switching transistor is connected to a first node, and the switching gate of the switching transistor is connected to a first scan signal line; A driving transistor, wherein the first electrode of the driving transistor is connected to the first node, the second electrode of the driving transistor is connected to the second node, and the driving gate of the driving transistor is connected to the third node; A first light-emitting control transistor, wherein the first electrode of the first light-emitting control transistor is connected to a first power signal line, the second electrode of the first light-emitting control transistor is connected to the first node, and the first light-emitting control gate of the first light-emitting control transistor is connected to the light-emitting control signal line; A first reset transistor, wherein the first electrode of the first reset transistor is connected to a first reset signal line, the second electrode of the first reset transistor is connected to the first node, and the first reset gate of the first reset transistor is connected to a second scan signal line; The oxide semiconductor layer includes a shielding portion and a second storage electrode of a storage capacitor. The shielding portion and the second storage electrode are continuously disposed, and the shielding portion is connected to the first power signal line. The first source-drain layer includes a first connection portion, which is connected between the second electrode of the first reset transistor and the first node. The light-emitting control signal line is disposed on one side of the substrate. The shielding portion is disposed on the side of the light-emitting control signal line away from the substrate, and the first connection portion is disposed on the side of the shielding portion away from the light-emitting control signal line. The orthographic projection of the first connection portion on the substrate partially overlaps with the orthographic projection of the light-emitting control signal line on the substrate, and the orthographic projection of the overlapping portion of the first connection portion and the light-emitting control signal line on the shielding portion is located within the shielding portion.

2. The display panel as described in claim 1, characterized in that, The first gate layer includes the storage capacitor, the first storage plate of the storage capacitor is connected to the third node, and the second storage plate of the storage capacitor is connected to the first power signal line.

3. The display panel as described in claim 2, characterized in that, The first scanning signal line, the light emission control signal line, and the second scanning signal line extend along a first direction, and are spaced apart along a second direction, wherein the first direction and the second direction are different. Wherein, the orthographic projection of the second storage electrode on the substrate is disposed between the orthographic projection of the first scanning signal line on the substrate and the orthographic projection of the light emission control signal line on the substrate, and the orthographic projection of the shielding portion on the substrate is disposed on the side of the orthographic projection of the second storage electrode on the substrate close to the orthographic projection of the light emission control signal line on the substrate.

4. The display panel as described in claim 3, characterized in that, The first connection portion includes a first sub-connection portion and a second sub-connection portion. The first sub-connection portion extends along the first direction, and the second sub-connection portion extends along the second direction. The first sub-connection portion is connected between the second electrode of the first light-emitting control transistor and the second sub-connection portion, and the second sub-connection portion is connected between the first sub-connection portion and the second electrode of the first reset transistor.

5. The display panel as described in claim 4, characterized in that, The orthographic projection of the first sub-connection portion on the substrate partially overlaps with the orthographic projection of the second storage electrode on the substrate. The orthographic projection of a portion of the second sub-connection portion on the substrate overlaps with the orthographic projection of the second storage electrode on the substrate. The orthographic projection of another portion of the second sub-connection portion on the substrate overlaps with the orthographic projection of the shielding portion on the substrate.

6. The display panel as described in claim 5, characterized in that, The orthographic projection of the first connecting portion on the substrate overlaps with the orthographic projection of the first storage electrode on the substrate.

7. The display panel as described in claim 5, characterized in that, The width of the shielding portion along the first direction is greater than the width of the second sub-connecting portion along the first direction.

8. The display panel as described in claim 5, characterized in that, The width of the shielding portion along the second direction is greater than the width of the light-emitting control signal line along the second direction.

9. The display panel as described in any one of claims 1 to 8, characterized in that, The pixel driving circuit also includes: A compensation transistor, wherein the first electrode of the compensation transistor is connected to the third node, the second electrode of the compensation transistor is connected to the second node, and the compensation gate of the compensation transistor is connected to the third scan signal line; The second reset transistor has its first electrode connected to the second reset signal line, its second electrode connected to the third node, and its second reset gate connected to the fourth scan signal line. The second light-emitting control transistor has a first electrode connected to the second node, a second electrode connected to the fourth node, and a second light-emitting control gate connected to the light-emitting control signal line. The third reset transistor has a first electrode connected to a third reset signal line, a second electrode connected to a fourth node, and a second light-emitting control gate connected to the second scan signal line. A boost capacitor, wherein the first boost plate of the boost capacitor is connected to the third node, and the second boost plate of the boost capacitor is connected to the first scan signal line.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 9.

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