Driving circuit and method thereof for photoelectric conversion chip, receiving module, laser radar and electronic device

Abstract

The application discloses a driving circuit of a photoelectric conversion chip, which comprises a photoelectric conversion chip, a power supply circuit and a buffer circuit. The photoelectric conversion chip comprises a plurality of photoelectric conversion devices, and the photoelectric conversion devices are used for outputting a sudden avalanche signal in response to avalanche effect of photons. The power supply circuit is connected to the photoelectric conversion chip to supply power to the photoelectric conversion chip. The buffer circuit is arranged between the photoelectric conversion chip and the power supply circuit, and the buffer circuit is used for slowing down the sudden change of the avalanche signal output by the photoelectric conversion device. The application also provides a receiving module, a laser radar, an electronic device and a driving method comprising the above-mentioned photoelectric conversion chip driving circuit.

Description

Drive circuits and methods for photoelectric conversion chips, receiving modules, lidar and electronic equipment Technical Field

[0001] This application relates to the field of photoelectric sensing technology, and in particular to photoelectric conversion chip driving circuits and methods for photoelectric sensing, receiving modules, lidar and electronic devices. Background Technology

[0002] In recent years, LiDAR has begun to be commercialized on a large scale in fields such as 3D machine vision, smart manufacturing, intelligent driving navigation, and 3D mapping. Among these, its highest commercial value and greatest development potential lies in providing real-time road information as a light detection device for intelligent driving. LiDAR uses photoelectric conversion devices, such as single-photon avalanche diodes (SPADs), to count single photons for distance information sensing. SPADs respond to the avalanche effect of a single photon and output an avalanche signal to count the responding photons.

[0003] However, with the increasing popularity of lidar, it is becoming more and more common for lidars on different devices to shoot at each other during actual use. This causes the avalanche signal output by the SPAD to be severely overshooted under the illumination of high-power beams, which can damage the circuits connected to the SPAD and increase the failure rate of the lidar. Summary of the Invention

[0004] In view of this, this application provides a driving circuit and method for a photoelectric conversion chip, a receiving module, a lidar, and an electronic device that can solve the above-mentioned technical problems.

[0005] To solve the above-mentioned technical problems, the first technical solution adopted in this application is: to provide a driving circuit for a photoelectric conversion chip, comprising:

[0006] A photoelectric conversion chip includes multiple photoelectric conversion devices, which are used to output a sudden avalanche signal in response to the avalanche effect of photons.

[0007] A power supply circuit is connected to the photoelectric conversion chip to supply power to the photoelectric conversion chip; and

[0008] A buffer circuit is disposed between the photoelectric conversion chip and the power supply circuit. The buffer circuit is used to mitigate the avalanche signal output by the photoelectric conversion device.

[0009] To address the aforementioned technical problems, the second technical solution adopted in this application is: providing a receiving module for a lidar, including a driving circuit for the photoelectric conversion chip as described above. The receiving module obtains corresponding distance information based on the processing and analysis of the avalanche signal.

[0010] To solve the above-mentioned technical problems, the third technical solution adopted in this application is: to provide a laser radar, comprising:

[0011] The transmitting module is used to transmit sensing light signals to a preset field of view according to a preset time sequence; and

[0012] The receiving module as described above.

[0013] To solve the above-mentioned technical problems, the fourth technical solution adopted in this application is to provide an electronic device, including the lidar as described above.

[0014] To solve the above-mentioned technical problems, the fifth technical solution adopted in this application is: to provide a driving method for a photoelectric conversion chip, including the following steps:

[0015] A driving signal is provided to a photoelectric conversion chip; wherein the photoelectric conversion chip includes a plurality of photoelectric conversion devices, the photoelectric conversion devices being used to output a sudden avalanche signal in response to the avalanche effect of photons;

[0016] Before the driving signal reaches the photoelectric conversion chip, the driving signal is low-pass filtered to mitigate the response of the driving signal to the avalanche signal.

[0017] The beneficial effects of this application are as follows: Unlike the prior art, by setting a buffer circuit between the power supply circuit and the photoelectric conversion chip to delay the change of the drive signal following the avalanche signal, the abrupt change duration of the avalanche signal generated by the photoelectric conversion device under the irradiation of a high-power through-beam is weakened, thereby reducing the overshoot of the avalanche signal output by the photoelectric conversion device under the irradiation of a high-power through-beam, so as to reduce the adverse effects on the circuit connected to the photoelectric conversion device and improve the reliability of the photoelectric conversion chip and the entire lidar and electronic equipment. Attached Figure Description

[0018] Figure 1 is a schematic block diagram of the structure of an embodiment of the electronic device of this application;

[0019] Figure 2 is a schematic block diagram of the structure of a lidar embodiment of this application;

[0020] Figure 3 is a schematic diagram of the circuit structure of an embodiment of the driving circuit of the photoelectric conversion chip of this application;

[0021] Figure 4 is a schematic diagram of the circuit structure of an embodiment of the driving circuit of the photoelectric conversion chip of this application;

[0022] Figure 5 is a schematic diagram of the circuit structure of an embodiment of the driving circuit of the photoelectric conversion chip of this application;

[0023] Figure 6 is a schematic diagram of the equivalent driving circuit of one of the photoelectric conversion devices in the photoelectric conversion chip of this application.

[0024] Figure 7 is a schematic diagram of the buffer circuit in the driving circuit of the photoelectric conversion chip of this application, which mitigates the sudden change of avalanche signal.

[0025] Figure 8 is a schematic diagram showing the relationship between the buffer circuit configuration and the active circuit connection method in one embodiment of the driving circuit of the photoelectric conversion chip of this application.

[0026] Figure 9 is a schematic diagram showing the relationship between the buffer circuit configuration and the active circuit connection method in one embodiment of the driving circuit of the photoelectric conversion chip of this application.

[0027] Figure 10 is a schematic diagram of the circuit structure of a buffer circuit in the driving circuit of the photoelectric conversion chip of this application.

[0028] Figure 11 is a schematic diagram of the circuit structure of a buffer circuit in the driving circuit of the photoelectric conversion chip of this application.

[0029] Figure 12 is a schematic diagram of the circuit structure of a buffer circuit in the driving circuit of the photoelectric conversion chip of this application.

[0030] Figure 13 is a schematic diagram of the circuit structure of a buffer circuit in the driving circuit of the photoelectric conversion chip of this application.

[0031] Figure 14 is a schematic diagram of the circuit structure of a buffer circuit in the driving circuit of the photoelectric conversion chip of this application.

[0032] Figure 15 is a schematic diagram of the circuit structure of a buffer circuit in the driving circuit of the photoelectric conversion chip of this application.

[0033] Figure 16 is a schematic diagram of the circuit structure of a buffer circuit in the driving circuit of the photoelectric conversion chip of this application.

[0034] Figure 17 is a schematic diagram of the circuit structure of a buffer circuit in the driving circuit of the photoelectric conversion chip of this application.

[0035] Figure 18 is a schematic diagram of the circuit structure of a buffer circuit in the driving circuit of the photoelectric conversion chip of this application.

[0036] Figure 19 is a schematic diagram of the circuit structure of a buffer circuit in the driving circuit of the photoelectric conversion chip of this application.

[0037] Figure 20 is a schematic diagram of the circuit structure of a buffer circuit in the driving circuit of the photoelectric conversion chip of this application.

[0038] Figure 21 is a schematic diagram of the circuit structure of a buffer circuit in the driving circuit of the photoelectric conversion chip of this application.

[0039] Figure 22 is a schematic diagram of the circuit structure of a buffer circuit in the driving circuit of the photoelectric conversion chip of this application.

[0040] Figure 23 is a schematic diagram of the circuit structure of a buffer circuit in the driving circuit of the photoelectric conversion chip of this application.

[0041] Figure 24 is a schematic diagram of the circuit structure of a buffer circuit in the driving circuit of the photoelectric conversion chip of this application.

[0042] Figure 25 is a schematic diagram of the circuit structure of a buffer circuit in the driving circuit of the photoelectric conversion chip of this application.

[0043] Figure 26 is a schematic diagram of the circuit structure of a buffer circuit in the driving circuit of the photoelectric conversion chip of this application.

[0044] Figure 27 is a schematic diagram of the circuit structure of a buffer circuit in the driving circuit of the photoelectric conversion chip of this application.

[0045] Figure 28 is a schematic diagram of the circuit structure of a buffer circuit in the driving circuit of the photoelectric conversion chip of this application.

[0046] Figure 29 is a schematic diagram of the circuit structure of a buffer circuit in the driving circuit of the photoelectric conversion chip of this application.

[0047] Figure 30 is a schematic diagram of the circuit structure of a buffer circuit in the driving circuit of the photoelectric conversion chip of this application.

[0048] Figure 31 is a schematic diagram of the circuit structure of a buffer circuit in the driving circuit of the photoelectric conversion chip of this application.

[0049] Figure 32 is a schematic diagram of the circuit structure of a buffer circuit in the driving circuit of the photoelectric conversion chip of this application.

[0050] Figure 33 is a schematic diagram of the circuit structure of a buffer circuit in the driving circuit of the photoelectric conversion chip of this application.

[0051] Figure 34 is a schematic diagram of the circuit structure of a buffer circuit in the driving circuit of the photoelectric conversion chip of this application.

[0052] Figure 35 is a schematic diagram of the circuit structure of a buffer circuit in the driving circuit of the photoelectric conversion chip of this application.

[0053] Figure 36 is a schematic diagram of the circuit structure of a buffer circuit in the driving circuit of the photoelectric conversion chip of this application.

[0054] Figure 37 is a schematic diagram of the circuit structure of a buffer circuit in the driving circuit of the photoelectric conversion chip of this application.

[0055] Figure 38 is a flowchart illustrating the steps of the driving method for the photoelectric conversion chip of this application. Detailed Implementation

[0056] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0057] The term "connection (or coupling, parallel, series, etc.)" is used extensively throughout the description (including the claims) of this application and should be understood to cover both direct and indirect connections or couplings between elements. For example, if this application describes a first circuit element connected (or coupled, parallel, series) to a port or node in a circuit of a second circuit element, it should be interpreted as the first circuit element being directly connected to the second circuit element, or the first circuit element being indirectly connected to the second circuit element through other elements or a circuit node. Furthermore, terms such as "first" and "second" used throughout the description (including the claims) of this application are used only to name elements or distinguish different embodiments or scopes, and are not intended to limit the upper or lower limit of the number of elements, nor are they intended to limit the order of elements. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In addition, elements / components / steps having the same reference numerals represent the same or similar parts in the drawings and embodiments. Elements / components / symbols having the same reference numerals in different embodiments can be referred to in the relevant description. Furthermore, the technical solutions of the various embodiments can be combined with each other, but only if they are based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0058] Embodiments of this application provide a driving circuit for a photoelectric conversion chip, comprising:

[0059] A photoelectric conversion chip includes multiple photoelectric conversion devices, which are used to output a sudden avalanche signal in response to the avalanche effect of photons.

[0060] A power supply circuit is connected to the photoelectric conversion chip to supply power to the photoelectric conversion chip; and

[0061] A buffer circuit is disposed between the photoelectric conversion chip and the power supply circuit. The buffer circuit is used to mitigate the avalanche signal output by the photoelectric conversion device.

[0062] In some embodiments, the photoelectric conversion chip includes a first power port and a second power port, the photoelectric conversion device includes a positive electrode and a negative electrode disposed opposite to each other, the positive electrodes of multiple photoelectric conversion devices are connected in parallel to the first power port, and the negative electrodes of multiple photoelectric conversion devices are connected in parallel to the second power port. The power supply circuit applies a lower first voltage to the first power port and a higher second voltage to the second power port to make the photoelectric conversion device operate in a reverse biased state. The buffer circuit is disposed between the power supply circuit and the first power port and / or the buffer circuit is disposed between the power supply circuit and the second power port.

[0063] In some embodiments, the buffer circuit includes at least one inductor, one end of which is connected to a power supply circuit, and the other end of which is connected to a first power supply port of the photoelectric conversion chip.

[0064] In some embodiments, the buffer circuit includes at least one inductor, one end of which is connected to a power supply circuit, and the other end of which is connected to a second power supply port of the photoelectric conversion chip.

[0065] In some embodiments, the buffer circuit includes a diode, the positive terminal of which is connected to the first power supply port, and the negative terminal of which is connected to the power supply circuit.

[0066] In some embodiments, the buffer circuit includes a diode, the negative terminal of which is connected to the second power supply port, and the positive terminal of which is connected to the power supply circuit.

[0067] In some embodiments, the buffer circuit further includes an inductor connected in series with the diode, the inductor being disposed between the diode and the power supply circuit; or,

[0068] The inductor is positioned between the diode and the photoelectric conversion chip.

[0069] In some embodiments, the buffer circuit includes a switching device, which includes a first connection terminal, a second connection terminal, and a control terminal for controlling the connection and disconnection between the first connection terminal and the second connection terminal. The first connection terminal is connected to a power supply circuit, the second connection terminal is connected to the first power supply port, and the control terminal is connected to the second connection terminal.

[0070] In some embodiments, the buffer circuit further includes at least one inductor, and the control terminal is connected to the second connection terminal through the inductor.

[0071] In some embodiments, the buffer circuit includes a switching device, which includes a first connection terminal, a second connection terminal, and a control terminal for controlling the connection and disconnection between the first connection terminal and the second connection terminal. The first connection terminal is connected to a power supply circuit, the second connection terminal is connected to a second power supply port, and the control terminal is connected to the first connection terminal.

[0072] In some embodiments, the buffer circuit further includes at least one inductor, and the control terminal is connected to the first connection terminal through the inductor.

[0073] In some embodiments, the buffer circuit further includes at least one inductor connected in series with the switching device, the inductor being disposed between the switching device and the power supply circuit; or,

[0074] The inductor is positioned between the switching device and the photoelectric conversion chip.

[0075] In some embodiments, the switching device is a gallium nitride switch or a metal-oxide-semiconductor field-effect transistor switch.

[0076] In some embodiments, the buffer circuit includes an NPN transistor, which includes a base, an emitter, and a collector. The emitter is connected to a power supply circuit, the collector is connected to a first power supply port, and the base is connected to the collector.

[0077] In some embodiments, the buffer circuit includes an NPN transistor, which includes a base, an emitter, and a collector. The emitter is connected to a second power supply port, the collector is connected to a power supply circuit, and the base is connected to the collector.

[0078] In some embodiments, the buffer circuit includes a PNP transistor, which includes a base, an emitter, and a collector. The emitter is connected to a power supply circuit, the collector is connected to a second power supply port, and the base is connected to the collector.

[0079] In some embodiments, the buffer circuit includes a PNP transistor, which includes a base, an emitter, and a collector. The emitter is connected to a first power supply port, the collector is connected to a power supply circuit, and the base is connected to the collector.

[0080] In some embodiments, the buffer circuit further includes at least one inductor, through which the base is connected to the collector.

[0081] In some embodiments, the buffer circuit further includes at least one inductor connected in series with an NPN transistor or a PNP transistor, the inductor being disposed between the NPN transistor or the PNP transistor and the power supply circuit; or...

[0082] The inductor is positioned between the NPN or PNP transistor and the photoelectric conversion chip.

[0083] In some embodiments, the RC time constant value of the buffer circuit is set within a preset range.

[0084] In some embodiments, the buffer circuit mitigates abrupt changes in the avalanche signal by reducing the overshoot amplitude of the avalanche signal and / or slowing down the rate of change of the avalanche signal abrupt change amplitude.

[0085] In some embodiments, the photoelectric conversion device is a single-photon avalanche diode, and the photoelectric conversion chip is a single-photon avalanche diode array chip.

[0086] Embodiments of this application provide a driving method for a photoelectric conversion chip, including the following steps:

[0087] A drive signal is provided to the photoelectric conversion chip; wherein the photoelectric conversion chip includes multiple photoelectric conversion devices, which are used to output a sudden avalanche signal in response to the avalanche effect of photons;

[0088] Before the driving signal is input to the photoelectric conversion chip, the driving signal is subjected to low-pass filtering to reduce the response of the driving signal to the avalanche signal.

[0089] In some embodiments, the photoelectric conversion chip includes a first power port and a second power port, the photoelectric conversion device includes a positive electrode and a negative electrode disposed opposite to each other, the positive electrodes of multiple photoelectric conversion devices are connected in parallel to the first power port, and the negative electrodes of multiple photoelectric conversion devices are connected in parallel to the second power port. The driving signal applies a lower first voltage to the first power port and a higher second voltage to the second power port to make the photoelectric conversion device operate in a reverse biased state. Low-pass filtering of the driving signal includes low-pass filtering of the driving signal before it is input to the first power port and / or low-pass filtering of the driving signal before it is input to the second power port.

[0090] In some embodiments, the drive signal is transmitted to the first power port after passing through at least one inductor.

[0091] In some embodiments, the drive signal is transmitted to the second power port after passing through at least one inductor.

[0092] In some embodiments, the drive signal is transmitted to the photoelectric conversion chip after passing through a diode, the positive terminal of the diode is connected to the first power port, and the negative terminal of the diode receives the drive signal.

[0093] In some embodiments, the drive signal is transmitted to the photoelectric conversion chip after passing through a diode, the negative terminal of the diode is connected to the second power supply port, and the positive terminal of the diode receives the drive signal.

[0094] In some embodiments, the drive signal first passes through an inductor connected in series with the diode before being transmitted to the diode; or,

[0095] The driving signal first passes through the diode and then through the inductor connected in series with the diode to be transmitted to the photoelectric conversion chip.

[0096] In some embodiments, the drive signal is transmitted to the photoelectric conversion chip via a switching device. The switching device includes a first connection terminal, a second connection terminal, and a control terminal for controlling the connection between the first connection terminal and the second connection terminal. The first connection terminal receives the drive signal, the second connection terminal is connected to the first power port, and the control terminal is connected to the second connection terminal.

[0097] In some embodiments, the control terminal is connected to the second connection terminal via at least one inductor.

[0098] In some embodiments, the drive signal is transmitted to the photoelectric conversion chip via a switching device. The switching device includes a first connection terminal, a second connection terminal, and a control terminal for controlling the connection between the first connection terminal and the second connection terminal. The first connection terminal receives the drive signal, the second connection terminal is connected to the second power port, and the control terminal is connected to the first connection terminal.

[0099] In some embodiments, the control terminal is connected to the first connection terminal via at least one inductor.

[0100] In some embodiments, the drive signal first passes through an inductor connected in series with the switching device before being transmitted to the switching device; or,

[0101] The drive signal first passes through the switching device and then through the inductor connected in series with the switching device to be transmitted to the photoelectric conversion chip.

[0102] In some embodiments, the switching device is a gallium nitride switch or a metal-oxide-semiconductor field-effect transistor switch.

[0103] In some embodiments, the drive signal is transmitted to the photoelectric conversion device via an NPN transistor, the NPN transistor including a base, an emitter, and a collector, the emitter receiving the drive signal, the collector connected to a first power supply port, and the base connected to the collector.

[0104] In some embodiments, the drive signal is transmitted to the photoelectric conversion device via an NPN transistor, the NPN transistor including a base, an emitter, and a collector, the emitter being connected to a second power supply port, the collector receiving the drive signal, and the base being connected to the collector.

[0105] In some embodiments, the drive signal is transmitted to the photoelectric conversion device via a PNP transistor, the PNP transistor including a base, an emitter, and a collector, the emitter receiving the drive signal, the collector being connected to a second power supply port, and the base being connected to the collector.

[0106] In some embodiments, the driving signal is transmitted to the photoelectric conversion device via a PNP transistor, the PNP transistor including a base, an emitter, and a collector, the emitter being connected to a first power supply port, the collector receiving the driving signal, and the base being connected to the collector.

[0107] In some embodiments, the base is connected to the collector via at least one inductor.

[0108] In some embodiments, the drive signal first passes through an inductor connected in series with the NPN transistor or PNP transistor before being transmitted to the switching device; or,

[0109] The drive signal first passes through the NPN transistor or PNP transistor and then through an inductor connected in series with the NPN transistor or PNP transistor to be transmitted to the photoelectric conversion chip.

[0110] In some embodiments, the photoelectric conversion device is a single-photon avalanche diode, and the photoelectric conversion chip is a single-photon avalanche diode array chip.

[0111] An embodiment of this application provides a receiving module for a lidar, including a driving circuit for a photoelectric conversion chip as described above. The receiving module obtains corresponding distance information based on the processing and analysis of the avalanche signal.

[0112] Embodiments of this application provide a lidar, including:

[0113] The transmitting module is used to transmit sensing light signals to a preset field of view according to a preset time sequence; and the receiving module as described above.

[0114] The distance information can be used in fields such as 3D modeling, identity recognition, autonomous driving, machine vision, monitoring, drone control, augmented reality (AR) / virtual reality (VR), simultaneous localization and mapping (SLAM), and object proximity determination, and this application does not limit it.

[0115] Embodiments of this application also provide an electronic device, including the lidar as described above. The electronic device can perform corresponding functions based on the distance information acquired by the lidar. Examples of the electronic device include: mobile phones, automobiles, robots, access control / monitoring systems, smart locks, unmanned mobile vehicles, and aircraft. Taking an autonomous driving vehicle as an example, installing a lidar in an autonomous driving vehicle can scan the surrounding environment by rapidly and repeatedly emitting sensing light pulses as beams to obtain point cloud data of the shape, position, and motion of objects within the field of view.

[0116] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0117] Figure 1 is a schematic diagram of the functional modules of the lidar provided in this application applied to an electronic device. Figure 2 is a schematic diagram of the functional modules of the lidar provided in this application.

[0118] As shown in Figure 1, in some embodiments, the electronic device 100 includes a processor 110, a memory 120, and a lidar 200. The lidar 200 and the memory 120 are respectively coupled to the processor 110. The processor 110 is used to control the lidar 200 to perform distance information sensing and to control the electronic device 100 to perform corresponding functions based on the sensed data.

[0119] The lidar 200 is used to sense distance information. The acquired distance information can be used for, for example, identity recognition, gesture recognition, posture or action recognition, autonomous driving, machine vision, building surveying, scene recognition and modeling, augmented reality (AR) / virtual reality (VR), ranging, proximity sensing, simultaneous localization and mapping (SLAM), or 3D mapping. The electronic device 100 can be a smartphone, tablet, computer, smart wearable device, smart door lock, motor vehicle, drone, medical device, aviation device, or other device or apparatus that requires three-dimensional (3D) information sensing capabilities.

[0120] The processor 110 may be, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an image processor (ISP), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, microprocessors, etc.

[0121] The memory 120 is used to store computer programs, such as random access memory (RAM), read-only memory (ROM), or other types of storage devices. Specifically, the memory 120 may include one or more computer-readable storage media, which may be non-transitory. In some embodiments, the non-transitory computer-readable storage media in the memory 120 are used to store at least one line of program code. The computer program stored in the memory 120 can be executed by the processor 110, thereby controlling the operation of the electronic device 100 and realizing related operations and functions.

[0122] Read-only memory (ROM) can be, for example, programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Random access memory (RAM), used as an external cache, can be, for example, static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DRRAM).

[0123] In some embodiments, the electronic device 100 may further include a peripheral device interface 130 and at least one peripheral device. The processor 110, memory 120, and peripheral device interface 130 are connected via a bus or signal line. Each peripheral device can be connected to the peripheral device interface 130 via a bus, signal line, or circuit board. For example, the peripheral device may include one or more of the following: a radio frequency (RF) circuit 140, a display screen 150, an audio circuit 160, and a power supply 170. The RF circuit 140 is used to receive and transmit radio frequency (RF) signals, or electromagnetic signals, and to communicate with communication networks and other communication devices. The display screen 150 is used to display a user interface (UI), which may include graphics, text, icons, video, and any combination thereof. The audio circuit 160 may include a microphone and a speaker. The microphone is used to collect sound information from the user and the environment, convert it into electrical signals, and transmit it to the processor 110 for processing, or to enable voice communication via the RF circuit 140. The power supply 170 is used to power the various components in the electronic device 100; the power supply 170 may be AC ​​power, DC power, a disposable battery, or a rechargeable battery.

[0124] Peripheral device interface 130 is used to connect at least one peripheral device to processor 110 and memory 120 via I / O (Input / Output). In some embodiments, processor 110, memory 120 and peripheral device interface 130 may be integrated on the same chip or circuit board. In other embodiments, any one or two of processor 110, memory 120 and peripheral device interface 130 may be implemented on separate chips or circuit boards, which is not limited in this embodiment.

[0125] The lidar 200 can be connected to the processor 110 and memory 120 via the peripheral device interface 130. Alternatively, the lidar 200 can also directly interact with the processor 110 and memory 120 via the internal bus of the electronic device 100.

[0126] As shown in Figure 2, the lidar 200 provided in this embodiment may include a transmitting module 210, a receiving module 220, and a processing circuit 230. The processing circuit 230 may be coupled to the processor 110, the transmitting module 210, and the receiving module 220.

[0127] The transmitting module 210 can be used to transmit sensing light signals into the field of view, a portion of which will be reflected back by external objects within the field of view and received by the receiving module 220. The transmitting module 210 is configured to transmit sensing light signals according to a preset time sequence, such as laser pulses with a preset frequency. Optionally, the sensing light signal can be visible light, infrared light, or near-infrared light, with wavelength ranges such as 390 nm-780 nm, 700 nm-1400 nm, and 800 nm-1000 nm.

[0128] In some embodiments, the lidar 200 senses distance information within the field of view based on the direct time of flight (dToF) principle. At least a portion of the sensing light signal emitted by the transmitting module 210 is reflected back by an external object within the field of view and then received and sensed by the receiving module 220. The time difference between the emission and reception times of the sensing light signal reflected back by the external object is called the flight time t of the sensing light signal. By calculating the distance traveled by the reflected sensing light signal sensed by the receiving module 220 within the flight time t, the distance information of the external object reflecting the sensing beam can be obtained: D = (c*t) / 2, where c is the speed of light. The flight time t of the sensing light signal can be obtained through statistical analysis of the time-count distribution of the photosensitive signal generated by the photons sensed by the receiving module 220.

[0129] In the embodiment shown in Figure 2, the transmitting module 210 and the receiving module 220 are arranged side-by-side as a paraxial light-receiving path. The light-emitting surface of the transmitting module 210 and the light-incident surface of the receiving module 220 both face the same side of the lidar 200. The distance between the transmitting module 210 and the receiving module 220, also known as the baseline length, can range from, for example, 2 mm to 20 mm. Since the transmitting module 210 and the receiving module 220 are relatively close, although the emission path of the sensed light signal from the transmitting module 210 to the external object and the return path from the external object to the receiving module 220 after reflection are not exactly equal, both are much greater than the distance between the transmitting module 210 and the receiving module 220, and can be considered approximately equal. Therefore, the distance information between the external object and the lidar 200 can be calculated based on the product of half the flight time t of the sensed light signal reflected back from the object and the speed of light c. In some other embodiments, the transmitting module 210 and the receiving module 220 may also form a coaxial receiving and transmitting path through a beam splitter (not shown). This application does not limit this.

[0130] The receiving module 220 includes a photoelectric conversion chip 221. Optionally, the photoelectric conversion chip 221 may include a single photosensitive pixel 223 or a pixel array formed by multiple photosensitive pixels 223. Of course, the multiple photosensitive pixels 223 may not be arranged in an array, for example, they may be arranged in an irregular manner. The photosensitive pixel 223 is used to sense light signals from the field of view and output corresponding light sensing signals. It should be understood that the light signals from the field of view include photons of ambient light and photons of the sensed light signals reflected back. The receiving module 220 may also include a receiving optics 222 for modulating, for example, collimating or converging, the light signals from the field of view and transmitting them to the corresponding photosensitive pixel 223.

[0131] In some embodiments, the photoelectric conversion chip 221 may include a data processing module (not shown) for processing and analyzing the generated photosensitive signal. For example, the data processing module may process and analyze the photosensitive signal based on time-correlated single photon counting (TCSPC) technology to construct a photon counting histogram; or, the data processing module may also process and analyze the photon counting histogram to determine the reception time of the sensed beam echo; or, the data processing module may further process and analyze the reception time of the sensed beam echo sequentially to obtain corresponding distance information.

[0132] The processing circuit 230 can be an integrated circuit chip with signal or data processing capabilities, used to process the data output by the photoelectric conversion chip 221. The processing circuit 230 may include, for example, a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an image processor (ISP), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. Of course, the processing circuit 230 can also be other types of circuits currently used for dToF sensing, control, and processing; this application does not limit this. The lidar 200 may also include a storage medium 240, which may be coupled to or integrated within the processing circuit 230 to provide storage support for the operation of the processing circuit 230. A detailed description of the storage medium 240 of the lidar 200 can be found in the description of the memory 120 of the electronic device 100, and will not be repeated here.

[0133] In some embodiments, referring to FIG3, the photosensitive pixel 223 includes at least one photoelectric conversion device 300. If a photosensitive pixel 223 includes multiple photoelectric conversion devices 300, the light-sensing signals generated by the multiple photoelectric conversion devices 300 during the operation of the photosensitive pixel 223 are all used as the output signals of the photosensitive pixel 223. Optionally, the photoelectric conversion device 300 may be, for example, an avalanche photodiode (APD), a single-photon avalanche diode (SPAD), a silicon photomultiplier (SiPM) with multiple SPADs connected in parallel, and / or other suitable photoelectric conversion devices 300.

[0134] In the embodiments of this application, a SPAD is used as the photoelectric conversion device 300 of the photosensitive pixel 223, and the photoelectric conversion chip 221 is an example of a single-photon avalanche diode array chip (SPAD array chip). When a working voltage exceeding the reverse breakdown voltage is applied across the SPAD, it is in a Geiger state. At this time, photons entering the SPAD have a certain probability of triggering an avalanche effect and outputting a multiplied avalanche signal as the photosensitive signal. After the SPAD avalanche, it needs to be quenched by a quenching circuit to avoid continuous avalanche and damage. After quenching, the SPAD cannot continuously sense photons and outputs an avalanche signal. It needs to be reset to gradually restore the voltage across the SPAD to a working voltage exceeding the reverse breakdown voltage so that the SPAD can return to the Geiger state and continue to sense photons. The duration of the above quenching and resetting process is the dead time when the SPAD cannot sense photons.

[0135] The receiving module 220 includes a driving circuit for the photoelectric conversion chip 221. The driving circuit includes the photoelectric conversion chip 221, a power supply circuit 224, and a buffer circuit 225. The power supply circuit 224 is connected to the photoelectric conversion chip 221 to supply power to it. The photoelectric conversion chip 221 includes a first power port and a second power port. Each photoelectric conversion device 300 includes a positive and a negative electrode arranged opposite to each other. The positive electrode of each of the plurality of photoelectric conversion devices 300 is connected to the first power port, and the negative electrode of each of the plurality of photoelectric conversion devices 300 is connected to the second power port. The power supply circuit 224 applies a lower first voltage to the first power port and a higher second voltage to the second power port to put the photoelectric conversion devices 300 in a reverse-biased operating state. The photoelectric conversion chip 221 includes a plurality of photoelectric conversion devices 300, which are used to output abrupt avalanche signals in response to the photon avalanche effect. When a high-power beam of light shines on the photoelectric conversion device 300, the avalanche signal output by the photoelectric conversion device 300 experiences abrupt changes, resulting in severe overshoot, which can damage other active circuits connected to the photoelectric conversion device 300. The buffer circuit 225 is disposed between the photoelectric conversion chip 221 and the power supply circuit 224 to mitigate the avalanche signal abrupt changes output by the photoelectric conversion device 300, thereby preventing damage to other connected active circuits caused by the avalanche signal overshoot.

[0136] As shown in Figure 3, in some embodiments, the buffer circuit 225 includes a first buffer circuit 2251 and a second buffer circuit 2252. The first buffer circuit 2251 is disposed between the power supply circuit 224 and the first power port of the photoelectric conversion chip 221, and the second buffer circuit 2252 is disposed between the power supply circuit 224 and the second power port of the photoelectric conversion chip 221. As shown in Figure 4, in some embodiments, the buffer circuit 225 is disposed only between the power supply circuit 224 and the first power port of the photoelectric conversion chip 221. As shown in Figure 5, in some embodiments, the buffer circuit 225 is disposed only between the power supply circuit 224 and the second power port of the photoelectric conversion chip 221.

[0137] As shown in Figure 6, taking the equivalent circuit of one SPAD as an example, the SPAD and the power supply circuit 224 constitute a drive loop. When the SPAD experiences an avalanche and outputs a sudden avalanche signal, the potential at each point in the drive loop also changes abruptly, causing fluctuations in the electrical signal within the drive loop. The buffer circuit 225 is used to perform low-pass filtering on the fluctuations in the electrical signal within the drive loop. By suppressing the high-frequency components of the electrical signal fluctuations caused by the avalanche signal abrupt change, the avalanche signal abrupt change is mitigated. As shown in Figure 7, the electrical signal in the drive loop includes, for example, the drive signal output from the power supply circuit 224 to the photoelectric conversion chip 221. When a sudden avalanche signal change occurs, the drive signal responds by changing to provide energy to sustain the avalanche signal abrupt change. The buffer circuit 225 can suppress changes in the response of the drive signal, making abrupt changes in the avalanche signal less sustainable. On one hand, it increases the time required for the entire avalanche signal abrupt change process; that is, the abrupt change time t1 with the buffer circuit 225 in Figure 7 is greater than the abrupt change time t2 without the buffer circuit 225. The change curve of the avalanche signal during the abrupt change process is smoother, and the slope of the change curve is smaller, allowing the circuit protection devices in the subsequent circuits connected to the SPAD to respond effectively and provide corresponding protection. On the other hand, it also reduces the maximum change amplitude of the avalanche signal during the abrupt change process, preventing the maximum change amplitude from exceeding the safety threshold of the subsequent circuits and causing damage. Therefore, the buffer circuit 225 mitigates avalanche signal abrupt changes by extending the time of the avalanche signal abrupt change process and / or reducing the maximum change amplitude during the avalanche signal abrupt change process.

[0138] The photoelectric conversion chip 221 includes an active circuit 310 corresponding to the SPAD. The active circuit 310 includes at least one active device, which is easily damaged by sudden input signal surges. The active circuit 310 is connected to the SPAD to achieve corresponding functions. For example, the active circuit 310 is the output circuit of the SPAD, used to output the avalanche signal generated by the SPAD; or, the active circuit 310 is the quenching circuit of the SPAD, used to quench and reset the avalanche-affected SPAD; or, the active circuit 310 is a switching circuit, used to select the connected SPAD to operate.

[0139] As shown in Figure 8, in some embodiments, the photoelectric conversion device 300 includes an active circuit 310 corresponding to the SPAD, and the active circuit 310 includes at least one active device. The active circuit 310 is connected to the negative terminal of the SPAD. The avalanche SPAD can converge the avalanche signal from the first branch connected to the second power port and the second branch connected to the active circuit 310. In this case, the buffer circuit 225 provided between the power circuit 224 and the second power port can only reduce the avalanche signal component on the first branch and has a small impact on the avalanche signal component on the second branch. The buffer circuit 225 provided between the power circuit 224 and the first power port can reduce the avalanche signal components on both the first and second branches simultaneously. Therefore, when the active circuit 310 is connected to the negative terminal of the SPAD, the buffer circuit 225 is set between the power supply circuit 224 and the first power port of the photoelectric conversion chip 221, while the buffer circuit 225 is not set between the power supply circuit 224 and the second power port of the photoelectric conversion chip 221. This allows for efficient mitigation of avalanche signals with fewer circuit components, resulting in a high cost-performance ratio.

[0140] As shown in Figure 9, in some embodiments, the photoelectric conversion device 300 includes an active circuit 310 corresponding to the SPAD, and the active circuit 310 includes at least one active device. The active circuit 310 is connected to the anode of the SPAD. The avalanche signal flowing through the SPAD can be shunted from a first branch connected to the first power port and a second branch connected to the active circuit 310. In this case, the buffer circuit 225 provided between the power circuit 224 and the first power port can only reduce the avalanche signal component on the first branch and has a small impact on the avalanche signal component on the second branch. Alternatively, the buffer circuit 225 provided between the power circuit 224 and the second power port can reduce the avalanche signal components on both the first and second branches simultaneously. Therefore, when the active circuit 310 is connected to the anode of the SPAD, the buffer circuit 225 is set between the power supply circuit 224 and the second power port of the photoelectric conversion chip 221, while the buffer circuit 225 is not set between the power supply circuit 224 and the first power port of the photoelectric conversion chip 221. This allows for efficient mitigation of avalanche signals with fewer circuit components, resulting in a high cost-performance ratio.

[0141] In some embodiments, the buffer circuit 225 includes at least one inductor 2251, one end of which is connected to the power supply circuit 224, and the other end of which is connected to the photoelectric conversion chip 221. As shown in FIG10, if the buffer circuit 225 is disposed between the power supply circuit 224 and the second power port of the photoelectric conversion chip 221, then the other end of the inductor 2251 is connected to the second power port. As shown in FIG11, if the buffer circuit 225 is disposed between the power supply circuit 224 and the first power port of the photoelectric conversion chip 221, then the other end of the inductor 2251 is connected to the first power port. If the buffer circuit 225 includes two or more inductors 2251, the inductors 2251 are connected in series to reduce the capacitance value of the generated parasitic capacitance. Since parasitic capacitance is more likely to transmit high-frequency signals, the equivalent parasitic capacitance can be reduced by connecting the inductors 2251 in series, thereby correspondingly reducing the high-frequency components of the avalanche signal transmitted through the parasitic capacitance, which is beneficial to maintaining a good mitigation effect on the avalanche signal.

[0142] In some embodiments, the buffer circuit 225 includes a diode 2252. As shown in FIG12, if the buffer circuit 225 is disposed between the power supply circuit 224 and the first power supply port, the anode of the diode 2252 is connected to the first power supply port, and the cathode of the diode 2252 is connected to the power supply circuit 224. As shown in FIG13, if the buffer circuit 225 is disposed between the power supply circuit 224 and the second power supply port, the cathode of the diode 2252 is connected to the second power supply port, and the anode of the diode 2252 is connected to the power supply circuit 224.

[0143] In some embodiments, the buffer circuit 225 further includes at least one inductor 2251 connected in series with the diode 2252, and the series connection order of the diode 2252 and the inductor 2251 can be interchanged. As shown in FIG14, if the buffer circuit 225 is disposed between the power supply circuit 224 and the first power supply port, the anode of the diode 2252 is connected to the first power supply port, the cathode of the diode 2252 is connected to the power supply circuit 224, and the inductor 2251 is connected in series between the diode 2252 and the power supply circuit 224. Optionally, in other embodiments, the inductor 2251 may also be connected in series between the diode 2252 and the first power supply port. As shown in FIG15, if the buffer circuit 225 is disposed between the power supply circuit 224 and the second power supply port, the cathode of the diode 2252 is connected to the second power supply port, the anode of the diode 2252 is connected to the power supply circuit 224, and the inductor 2251 is connected in series between the diode 2252 and the second power supply port. Alternatively, in other embodiments, the inductor 2251 may also be connected in series between the diode 2252 and the power supply circuit 224.

[0144] In some embodiments, the buffer circuit 225 includes a switching device 2253. The switching device 2253 may be, for example, a gallium nitride (GaN) switch or a metal-oxide-semiconductor field-effect transistor (MOSFET) switch, and includes a first connection terminal, a second connection terminal, and a control terminal for controlling the on / off state between the first connection terminal and the second connection terminal. Referring to FIG16, if the buffer circuit 225 is disposed between the power supply circuit 224 and the first power port, the first connection terminal of the switching device 2253 is connected to the power supply circuit 224, the second connection terminal of the switching device 2253 is connected to the first power port, and the control terminal is connected to the second connection terminal. Referring to FIG17, if the buffer circuit 225 is disposed between the power supply circuit 224 and the second power port, the first connection terminal is connected to the power supply circuit 224, the second connection terminal is connected to the second power port, and the control terminal is connected to the first connection terminal.

[0145] In some embodiments, the buffer circuit 225 further includes at least one inductor 2251 connected in series with the switching device 2253, and the series connection order of the switching device 2253 and the inductor 2251 can be interchanged. Referring to FIG18, if the buffer circuit 225 is disposed between the power supply circuit 224 and the first power port, the first connection terminal of the switching device 2253 is connected to the power supply circuit 224, the second connection terminal of the switching device 2253 is connected to the first power port, the control terminal is connected to the second connection terminal, and the inductor 2251 is connected in series between the switching device 2253 and the power supply circuit 224. Optionally, in other embodiments, the inductor 2251 may also be connected in series between the switching device 2253 and the first power port. Referring to FIG19, if the buffer circuit 225 is disposed between the power supply circuit 224 and the second power port, the first connection terminal is connected to the power supply circuit 224, the second connection terminal is connected to the second power port, the control terminal is connected to the first connection terminal, and the inductor 2251 is connected in series between the switching device 2253 and the second power port. Alternatively, in other embodiments, the inductor 2251 may also be connected in series between the diode 2252 and the power supply circuit 224.

[0146] In some embodiments, the buffer circuit 225 includes a switching device 2253 and at least one inductor 2251. Referring to FIG. 20, if the buffer circuit 225 is disposed between the power supply circuit 224 and the first power port, the first connection terminal of the switching device 2253 is connected to the power supply circuit 224, the second connection terminal of the switching device 2253 is connected to the first power port, and the control terminal is connected to the second connection terminal through the inductor 2251. Referring to FIG. 21, if the buffer circuit 225 is disposed between the power supply circuit 224 and the second power port, the first connection terminal is connected to the power supply circuit 224, the second connection terminal is connected to the second power port, and the control terminal is connected to the first connection terminal through the inductor 2251.

[0147] In some embodiments, the buffer circuit 225 includes a transistor 2254, which may be an NPN transistor or a PNP transistor, including a base, an emitter, and a collector. Referring to FIG22, if the transistor 2254 is an NPN transistor, the buffer circuit 225 is disposed between the power supply circuit 224 and the first power supply port. The emitter of the NPN transistor 2254 is connected to the power supply circuit 224, the collector is connected to the first power supply port, and the base is connected to the collector. Referring to FIG23, if the transistor 2254 is an NPN transistor, the buffer circuit 225 is disposed between the power supply circuit 224 and the second power supply port. The emitter is connected to the second power supply port, the collector is connected to the power supply circuit 224, and the base is connected to the collector. Referring to Figure 24, if the transistor 2254 is a PNP transistor, the buffer circuit 225 is disposed between the power supply circuit 224 and the first power supply port. The emitter is connected to the power supply circuit 224, the collector is connected to the power supply circuit 224, and the base is connected to the collector. Referring to Figure 25, if the transistor 2254 is a PNP transistor, the buffer circuit 225 is disposed between the power supply circuit 224 and the second power supply port. The emitter is connected to the power supply circuit 224, the collector is connected to the second power supply port, and the base is connected to the collector.

[0148] In some embodiments, the buffer circuit 225 further includes at least one inductor 2251 connected in series with the transistor 2254. The transistor 2254 can be an NPN transistor or a PNP transistor, and the series connection order of the transistor 2254 and the inductor 2251 can be interchanged.

[0149] Specifically, if the buffer circuit 225 is disposed between the power supply circuit 224 and the first power supply port, the transistor 2254 is an NPN transistor, as shown in FIG26, and the inductor 2251 is disposed between the emitter of the NPN transistor and the power supply circuit 224; or, as shown in FIG27, the inductor 2251 is disposed between the collector of the NPN transistor and the first power supply port.

[0150] If the buffer circuit 225 is disposed between the power supply circuit 224 and the first power supply port, and the transistor 2254 is a PNP transistor, as shown in Figure 28, the inductor 2251 is disposed between the collector of the PNP transistor 2254 and the power supply circuit 224; or, as shown in Figure 29, the inductor 2251 is disposed between the emitter of the PNP transistor 2254 and the first power supply port.

[0151] If the buffer circuit 225 is disposed between the power supply circuit 224 and the second power supply port, and the transistor 2254 is an NPN transistor, as shown in Figure 30, the inductor 2251 is disposed between the collector of the NPN transistor 2254 and the power supply circuit 224; or, as shown in Figure 31, the inductor 2251 is disposed between the emitter of the NPN transistor 2254 and the second power supply port.

[0152] If the buffer circuit 225 is located between the power supply circuit 224 and the second power supply port, and the transistor 2254 is a PNP transistor, as shown in Figure 32, the inductor 2251 is located between the emitter of the PNP transistor 2254 and the power supply circuit 224; or, as shown in Figure 33, the inductor 2251 is located between the collector of the PNP transistor 2254 and the second power supply port.

[0153] In some embodiments, the buffer circuit 225 includes a transistor 2254 and at least one inductor 2251, with the base of the transistor 2254 connected to the collector through the inductor 2251. Specifically, if the buffer circuit 225 is located between the power supply circuit 224 and the first power port, the transistor 2254 is an NPN transistor, as shown in FIG34. The emitter of the NPN transistor 2254 is connected to the power supply circuit 224, the collector is connected to the first power port, and the base is connected to the collector through the inductor 2251.

[0154] If the buffer circuit 225 is located between the power supply circuit 224 and the first power supply port, and the transistor 2254 is a PNP transistor, as shown in Figure 35, the emitter is connected to the power supply circuit 224, the emitter is connected to the first power supply port, the collector is connected to the power supply circuit 224, and the base is connected to the collector through the inductor 2251.

[0155] If the buffer circuit 225 is located between the power supply circuit 224 and the second power supply port, the transistor 2254 is an NPN transistor, as shown in Figure 36. The emitter is connected to the second power supply port, the collector is connected to the power supply circuit 224, and the base is connected to the collector through the inductor 2251.

[0156] If the buffer circuit 225 is located between the power supply circuit 224 and the second power supply port, the transistor 2254 is a PNP transistor, as shown in Figure 37. The emitter is connected to the power supply circuit 224, the collector is connected to the second power supply port, and the base is connected to the collector through the inductor 2251.

[0157] It should be understood that in the embodiments shown in Figures 3 and 6, the first buffer circuit 2251 can adopt any specific buffer circuit embodiment in Figures 10-38, and the second buffer circuit 2252 can adopt any specific buffer circuit embodiment in Figures 10-38. The first buffer circuit 2251 and the second buffer circuit 2252 can adopt the same buffer circuit embodiment, or they can each adopt different buffer circuit embodiments, and this application does not limit them in this regard.

[0158] In the above embodiments, the RC time constant of the buffer circuit 225 is set within a preset range. Since the RC time constant of the circuit is related to the circuit's frequency response to the signal, a smaller RC time constant allows the circuit to more easily suppress low-frequency signals while allowing high-frequency signals; a larger RC time constant allows the circuit to more easily suppress high-frequency signals while allowing low-frequency signals. Although the buffer circuit 225 in this application is configured to mitigate the avalanche signal abrupt changes output by the photoelectric conversion device 300, the avalanche signal still needs to maintain a certain degree of abrupt change to ensure it can still be sensed without damaging subsequent circuits. Therefore, the mitigation of the avalanche signal by the buffer circuit 225 must also be within a certain range; it cannot be mitigated too much or too little. In some embodiments, the degree of mitigation of the avalanche signal by the buffer circuit 225 can be adjusted by adjusting the RC time constant of the buffer circuit 225. Therefore, the RC time constant of the buffer circuit 225 is set within a preset range. Thus, the specific parameters of various circuit devices in any specific buffer circuit embodiment in Figures 10-38 can be set according to the range of the RC time constant of the buffer circuit 225.

[0159] The driving circuit of the photoelectric conversion chip 221 provided in this application embodiment provides a buffer circuit 225 between the photoelectric conversion chip 221 and the power supply circuit 224 for power supply. The buffer circuit 225 reduces the signal fluctuation caused by the avalanche signal of the avalanche output of the photoelectric conversion device 300 in the driving loop formed by the photoelectric conversion chip 221 and the power supply circuit 224. This can prevent excessively fast and violent signal fluctuations in the driving loop from damaging the active circuit 310 connected to the driving loop, thereby improving the reliability of the photoelectric conversion chip 221 and the entire lidar and electronic equipment.

[0160] This application embodiment also provides a driving method for a photoelectric conversion chip 221, the process of which is shown in Figure 38, including the following steps:

[0161] S101: Provide a driving signal to the photoelectric conversion chip 221; wherein, the photoelectric conversion chip 221 includes a plurality of photoelectric conversion devices 300, the photoelectric conversion devices 300 being used to output a sudden avalanche signal in response to the avalanche effect of photons;

[0162] S102: Before the driving signal reaches the photoelectric conversion chip, the driving signal is subjected to low-pass filtering to slow down the response change of the driving signal to the avalanche signal.

[0163] For specific embodiments of the low-pass filtering process, please refer to the detailed description of the buffer circuit diagrams 10-37 in the foregoing section, which will not be repeated here.

[0164] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A driving circuit for a photoelectric conversion chip, characterized in that, include: A photoelectric conversion chip includes multiple photoelectric conversion devices, which are used to output a sudden avalanche signal in response to the avalanche effect of photons. A power supply circuit is connected to the photoelectric conversion chip to supply power to the photoelectric conversion chip; and a buffer circuit is disposed between the photoelectric conversion chip and the power supply circuit. The buffer circuit is used to slow down the rate of change of the avalanche signal amplitude change to reduce the adverse effects on the circuit connected to the photoelectric conversion device. The photoelectric conversion device is a single-photon avalanche diode. The photoelectric conversion chip also includes an active circuit corresponding to the single-photon avalanche diode. The active circuit includes at least one active device. The photoelectric conversion chip includes a first power port and a second power port. The single-photon avalanche diode includes a positive electrode and a negative electrode arranged opposite to each other. The positive electrodes of multiple single-photon avalanche diodes are connected to the first power port, and the negative electrodes of multiple single-photon avalanche diodes are connected to the second power port. The power supply circuit applies a lower first voltage to the first power port and a higher second voltage to the second power port to make the single-photon avalanche diode in a reverse-biased Geiger state. When the active circuit is connected to the negative terminal of the corresponding single-photon avalanche diode, the buffer circuit is disposed between the power supply circuit and the first power supply port; when the active circuit is connected to the anode of the corresponding single-photon avalanche diode, the buffer circuit is disposed between the power supply circuit and the second power supply port.

2. The driving circuit of the photoelectric conversion chip as described in claim 1, characterized in that, The buffer circuit includes at least one inductor, one end of which is connected to the power supply circuit, and the other end of which is connected to the first power port or the second power port of the photoelectric conversion chip.

3. The driving circuit of the photoelectric conversion chip as described in claim 1, characterized in that, The buffer circuit includes a diode, the anode of which is connected to the first power supply port and the cathode of which is connected to the power supply circuit; or, the cathode of which is connected to the second power supply port and the anode of which is connected to the power supply circuit.

4. The driving circuit of the photoelectric conversion chip as described in claim 3, characterized in that, The buffer circuit also includes at least one inductor connected in series with the diode, and the inductor is disposed between the diode and the power supply circuit or the photoelectric conversion chip.

5. The driving circuit of the photoelectric conversion chip as described in claim 1, characterized in that, The buffer circuit includes a switching device, which includes a first connection terminal, a second connection terminal, and a control terminal for controlling the connection and disconnection between the first connection terminal and the second connection terminal. The first connection terminal is connected to a power supply circuit, the second connection terminal is connected to the first power supply port, and the control terminal is connected to the second connection terminal.

6. The driving circuit of the photoelectric conversion chip as described in claim 1, characterized in that, The buffer circuit includes a switching device, which includes a first connection terminal, a second connection terminal, and a control terminal for controlling the connection and disconnection between the first connection terminal and the second connection terminal. The first connection terminal is connected to a power supply circuit, the second connection terminal is connected to a second power supply port, and the control terminal is connected to the first connection terminal.

7. The driving circuit for the photoelectric conversion chip as described in claim 5 or 6, characterized in that, The buffer circuit further includes at least one inductor, and the control terminal is connected to the first connection terminal or the second connection terminal through the inductor.

8. The driving circuit for the photoelectric conversion device as described in claim 5 or 6, characterized in that, The buffer circuit also includes at least one inductor connected in series with the switching device, the inductor being disposed between the switching device and the power supply circuit or the photoelectric conversion chip.

9. The driving circuit for the photoelectric conversion chip as described in claim 5 or 6, characterized in that, The switching device is a gallium nitride switch or a metal-oxide-semiconductor field-effect transistor switch.

10. The driving circuit of the photoelectric conversion chip as described in claim 1, characterized in that, The buffer circuit includes an NPN transistor, which has a base, an emitter, and a collector. The emitter is connected to a power supply circuit, the collector is connected to a first power supply port, and the base is connected to the collector. Alternatively, the emitter is connected to a second power supply port, the collector is connected to a power supply circuit, and the base is connected to the collector.

11. The driving circuit of the photoelectric conversion chip as described in claim 1, characterized in that, The buffer circuit includes a PNP transistor, which has a base, an emitter, and a collector. The emitter is connected to a power supply circuit, the collector is connected to a second power supply port, and the base is connected to the collector. Alternatively, the emitter is connected to a first power supply port, the collector is connected to a power supply circuit, and the base is connected to the collector.

12. The driving circuit for the photoelectric conversion chip as described in claim 10 or 11, characterized in that, The buffer circuit further includes at least one inductor, through which the base is connected to the collector.

13. The driving circuit for the photoelectric conversion chip as described in claim 10 or 11, characterized in that, The buffer circuit further includes at least one inductor connected in series with the NPN transistor or PNP transistor, the inductor being disposed between the NPN transistor or PNP transistor and the power supply circuit; or, the inductor being disposed between the NPN transistor or PNP transistor and the photoelectric conversion chip.

14. A receiving module for a lidar, characterized in that, The receiving module includes a driving circuit for a photoelectric conversion chip as described in any one of claims 1-13, wherein the receiving module obtains corresponding distance information based on the processing and analysis of the avalanche signal.

15. A lidar, characterized in that, include: The transmitting module is used to transmit sensing light signals to a preset field of view according to a preset time sequence; And the receiving module as described in claim 14.

16. An electronic device, characterized in that, Including the lidar as described in claim 15.

17. A driving method for a photoelectric conversion chip, characterized in that, The method includes the following steps: providing a driving signal to a photoelectric conversion chip; wherein the photoelectric conversion chip includes a plurality of photoelectric conversion devices and an active circuit corresponding to the photoelectric conversion devices, the driving signal is used to drive the photoelectric conversion devices to output a sudden avalanche signal in response to the avalanche effect of photons; the driving signal is low-pass filtered before it reaches the photoelectric conversion chip to slow down the response of the driving signal to the avalanche signal, delay the rate of change of the avalanche signal amplitude, thereby reducing the adverse effects on the active circuit connected to the photoelectric conversion devices.

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