Method for reducing power consumption of ALU

Abstract

The invention relates to the field of computers, in particular to a method for reducing power consumption of an ALU. According to the method, inactive parts are temporarily closed through clock gating, unused modules are placed in a standby mode, clocks of operation blocks which do not participate in execution of selected operations at the current moment are forbidden, meanwhile, the structure of an ALU function assembly is set to be a composite structure, carry propagation and carry generation of a core adder are trimmed, and the core adder is made to be in a closed state. Circuits of the arithmetic operation instruction and the logic operation instruction are multiplexed, and a control signal is used for controlling the multiplexing circuit to execute related operation. And a truncation multiplier is used to reduce calculation complexity and hardware resource requirements, and a carry circuit and a result of a truncation part are compensated to realize error correction. Clock gating, one-hot coding and dormant transistor technologies are combined to ensure fewer switching activities and unique operation selection at the moment, and meanwhile, by adopting a composite structure and a cut-off multiplier, better power consumption and performance are realized.

Description

Technical Field

[0001] The invention relates to the field of computers, and in particular to a method for reducing ALU power consumption. Background Art

[0002] In recent years, applications such as IOT, mobile and wireless communications, image processing, and navigation involving signal processing have grown dramatically. At the same time, their strict requirements for low power consumption have brought tremendous pressure and challenges to researchers. ALU (arithmetic logic unit) is the main computing unit of almost all processors and controllers. Its main function is to perform arithmetic and logical operations. It is the core of the processor for processing data and executing instructions, and has a very high switching frequency. Therefore, reducing its power consumption without reducing performance has great benefits for the power consumption control of the entire smart device. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a method for reducing the power consumption of ALU, combining clock gating, one-hot encoding and sleep transistor technology to ensure less switching activities and a unique operation selection at that moment, while achieving better power consumption and performance by adopting a composite structure and a truncated multiplier.

[0004] In order to solve the technical problem, the technical solution adopted by the present invention is: a method for reducing the power consumption of ALU, which temporarily shuts down inactive components through clock gating, puts unused modules into standby mode, and disables the clocks of operation blocks that are not involved in executing the selected operation at the current moment. At the same time, the structure of the ALU functional components is set to a composite structure, the carry propagation and carry generation of the core adder are trimmed, the circuits of arithmetic operation instructions and logic operation instructions are multiplexed, and the multiplexed circuits are controlled by control signals to perform related operations.

[0005] Furthermore, the clock gating includes an AND gate and a D flip-flop, the input end of the AND gate is connected to the enable signal and clock signal of the active component, module, and operation block, the output end of the AND gate is connected to the clock input pin of the D flip-flop, the data input pin of the D flip-flop is connected to the data output end of the active component, module, and operation block, and the enable signal of the inactive component, unused module, and operation block that does not participate in executing the selected operation at the current moment is 0.

[0006] Furthermore, the enable signal is transmitted to the input of the AND gate after one-hot encoding.

[0007] Furthermore, a power switch is installed in the power supply part of the ALU and / or each module in the ALU. When the ALU is in the standby state, the power supply line is cut off by the power switch, so that the ALU is in the dormant state.

[0008] Furthermore, the power switch is two transistors, the gate of the upper PMOS tube is connected to the inverted sleep signal, the source is connected to the positive power supply voltage VDD, and the drain is connected to ALU; at the same time, the gate of the lower NMOS tube is connected to the sleep signal, the source is connected to the reference ground voltage VSS, and the drain is connected to ALU.

[0009] Furthermore, the methods of trimming carry propagation and carry generation of the core adder include: A. using a carry selector to calculate carry generation and carry propagation in advance to reduce the delay of the adder; B. using a hybrid adder.

[0010] Furthermore, the control signal includes an operation type selection signal, a carry control signal, a zero flag signal, and an overflow flag signal. The process of using the control signal to control the multiplexing circuit to perform related operations is as follows: S11, signal input, the control unit generates a control signal according to the type of instruction currently executed, and inputs it into the ALU through the control bus; S12, signal decoding, inside the ALU, there are one or more decoders for receiving control signals and decoding them into control signals for various components inside the ALU; S13, operation execution, the decoded control signal activates the corresponding components inside the ALU to perform the corresponding operation; S14, result output. After the operation is completed, the ALU outputs the operation result and related status flag signals to the data bus for use by other components.

[0011] Furthermore, the method uses a truncated multiplier to reduce computational complexity and hardware resource requirements, and compensates for the carry circuit and result of the truncated part to achieve error correction.

[0012] Furthermore, the truncated multiplier adopts a rounding truncation method, and the process of compensating the carry circuit and result of the truncated part is: S21, determining the magnitude and direction of the error by comparing the result of the truncated multiplier with the result of the exact multiplier; S22, predicting a bit that will generate a carry based on the characteristics of the multiplication operation and the characteristics of the input data; S23, statically segmenting the multiplier according to the actual operation result and the number of truncation bits, and generating a partial product array according to the redundancy detection result of each segment, and then using the truncation compensation technology in the partial product compression step to reduce the truncation error; S24) Compare and verify the results and make adjustments in real time.

[0013] Beneficial effects of the present invention: (1) Combining the above-mentioned clock gating and sleep transistor technologies, it reduces power consumption in the inactive state, provides fine-grained power management capabilities, and extends service life; (2) Using one-hot encoding technology, the circuit design is simplified, the complexity of transitions between states is reduced, the clock frequency is increased, the system throughput is improved, and the error probability is reduced; (3) The use of a composite structure and truncated multiplier achieves performance optimization, saves circuit area, improves integration, enhances flexibility and adaptability, speeds up calculations, reduces computational complexity and hardware resources, and significantly reduces power consumption.

[0014] (4) The integration of the above technologies and methods ensures the calculation accuracy and speed, effectively reduces the power consumption of the system, and reduces the resource usage of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 The schematic diagram of the circuit for clock gating is shown in FIG. Figure 2 Schematic diagram of a one-hot encoder; Figure 3 Schematic diagram of adding a sleep transistor to a power supply. DETAILED DESCRIPTION

[0016] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0017] Example 1 This embodiment discloses a method for reducing ALU power consumption, combining clock gating, one-hot encoding and sleep transistor technology to ensure less switching activities and unique selection of different operations at that moment, while achieving better power consumption and performance by adopting a composite structure and a truncated multiplier.

[0018] Clock gating technology can control cell-level exchanges by suppressing capacity cell information updates when the capacity cell output is not required for a given operation. That is, power consumption can be reduced by temporarily shutting down inactive components or placing unused modules in standby mode. Clock gating is applied throughout the distributed network to control subsystems.

[0019] One-hot encoding is also called one-bit effective encoding. It uses an N-bit state register to encode N states. Each state has its own independent register bit, and at any time, only one of them is valid. In the one-hot code value, only one bit is '1' for each code element value, and the other bits are '0', such as S0=3'b001, S1=3'b010, S2=3'b100.

[0020] The biggest advantage of one-hot encoding is that only one bit needs to be compared when comparing states, which simplifies the decoding logic to a certain extent. Although one-hot encoding takes up more bits, that is, consumes more triggers, when the same number of states needs to be represented, the state decoding is simple, the combinational logic can be reduced, and the speed is fast. This encoding method is also easy to modify. Adding states or changing state transition conditions can be easily implemented without affecting other parts of the state machine. In addition, its speed is independent of the number of states. In contrast, the speed of compressed state encoding will drop significantly when the number of states increases. The area occupied by these additional triggers can offset the area saved by the decoding circuit.

[0021] Therefore, one-hot code uses more triggers, but can reduce the number of combinational logic to implement the state machine, reduce complexity, and increase the speed of the system, that is, the operating clock frequency can be as high as possible.

[0022] At the same time, based on the above, dormant transistor technology can be used, such as Figure 3 As shown, a power switch is added to the power supply part of the ALU and / or each ALU module to cut off the power rail when the system is in standby mode to achieve a sleep state. Specifically, the power switch is two transistors, the gate of the upper PMOS tube is connected to the inverted sleep signal, the source is connected to the positive power supply voltage VDD, and the drain is connected to the ALU; at the same time, the gate of the lower NMOS tube is connected to the sleep signal, the source is connected to the reference ground voltage VSS, and the drain is connected to the ALU. The sleep signal is Figure 3 The SLEEP signal in controls the conduction of the ALU and / or each ALU module. When SLEEP is at a high level, the upper transistor is inactivated and turned on due to the inversion of SLEEP, and the lower transistor is grounded and turned on, and the ALU and / or each ALU module is in a dormant state; when SLEEP is at a low level, the upper transistor is activated and turned on due to the inversion of SLEEP, and the ALU and / or each ALU module is in a conducting working state.

[0023] Hence, since all the operations of the ALU are different operations, depending on the select input, the ALU can perform only one operation at a particular moment. Hence, there is an opportunity to reduce the switching activity by disabling the clocks of those operation blocks which are not involved in performing the selected operation at that moment. The operation module can be provided with a gated input enable to uniquely enable the operation module in a manner that ensures that only one input is high and the rest are low. The encoding is done using one-hot encoding technique. The above arrangement ensures low switching activity and hence less power is dissipated in the chip.

[0024] From the above description, we can see that clock gating can temporarily shut down inactive components, put unused modules into standby mode, and disable the clocks of operation blocks that are not involved in executing the selected operation at the current moment. These are all ways to reduce ALU power consumption, and there are certain differences in the specific operation objects and methods.

[0025] Temporarily shutting down inactive components means temporarily shutting down components in the system that do not need to be processed or operated at present, such as turning off the power supply, disabling the clock signal, reducing the voltage, etc. In clock gating technology, temporarily shutting down inactive components means stopping these components from working by disabling the clock signal.

[0026] Putting unused modules in standby mode means putting those modules that are not needed in the current operation cycle into a low-power standby state. In hardware design, putting unused modules in standby mode involves shutting down their clock signals and reducing the power supply voltage.

[0027] Disabling the clocks of those blocks that are not involved in executing the selected operation at that moment means reducing power consumption by turning off the clock signals of unnecessary blocks at a certain time. Only those blocks that are actually involved in the current operation will maintain the clock signal, thereby reducing unnecessary clock switching and dynamic power consumption.

[0028] In this embodiment, Figure 1 As shown, the clock gating includes an AND gate and a D flip-flop. The input end of the AND gate is connected to the enable signal and clock signal of the active component, module, and operation block. The output end of the AND gate is connected to the clock input pin of the D flip-flop. The data input pin of the D flip-flop is connected to the data output end of the active component, module, and operation block. The enable signal of the inactive component, the unused module, and the operation block that does not participate in executing the selected operation at the current moment is 0.

[0029] like Figure 2 As shown, the enable signal is one-hot encoded and passed to the input of the AND gate. The input of the one-hot encoder is the 4-bit select signal, which produces a 16-bit encoded output, denoted as enable. Suppose the processor wants to perform an addition operation on the ALU, then the chip select value is 0100, which is passed to a one-hot encoder and the enable value is 0000000000010000. Therefore, the addition is enabled and gets the clock, while the rest of the blocks are disabled at that moment. The above arrangement ensures low switching activity and therefore less power is dissipated in the chip.

[0030] According to the situation of multiplexing resources, the structure of the ALU functional component can be divided into: ① independent structure; ② tree structure; ③ chain structure; ④ composite structure. The composite structure combines multiple structures together and reasonably combines them to take into account both speed and power consumption. The present invention adopts a composite structure through comparison and trade-offs, and multiplexes the circuits of the instructions of arithmetic operations and logical operations by trimming the carry propagation and carry generation of the core adder, and uses several control signals to control the related operations performed by the circuit.

[0031] The adder is the core of the ALU operation. The carry propagation and carry generation modules are key modules used to ensure the correctness of the addition operation. The carry propagation module is responsible for passing the carry signal of the low bit to the high bit to perform multi-bit addition operations. The carry generation module refers to the generation of a carry by a certain bit. That is, whether the bit will generate a carry is independent of the previous carry. Specifically, the methods of trimming the carry propagation and carry generation of the core adder include: A. Using a carry selector to calculate the carry generation and carry propagation in advance to reduce the delay of the adder; B. Using a hybrid adder.

[0032] In this embodiment, the control signal includes an operation type selection signal (such as sel, used to select whether the ALU performs an arithmetic operation or a logical operation), a carry control signal (such as Carry in, used to indicate whether the carry of the previous bit needs to be added to the operation of the current bit), a zero flag signal (indicating whether the result is 0), and an overflow flag signal (used to determine whether to detect the overflow of the operation result and set the flag). The process of using the control signal to control the multiplexing circuit to perform related operations is as follows: S11, signal input, the control unit generates a control signal according to the type of instruction currently executed, and inputs it into the ALU through the control bus; S12, signal decoding, inside the ALU, there are one or more decoders for receiving control signals and decoding them into control signals for various components inside the ALU; S13, operation execution, the decoded control signal activates the corresponding components inside the ALU to perform the corresponding operation; S14, result output, after the operation is completed, the ALU outputs the operation result and related status flag signals to the data bus for use by other components; S15. Feedback mechanism: In some cases, the operation result of the ALU may need to be used as the input of the next operation. At this time, the output result of the ALU can be saved through a register or other storage component and used as the input of the next operation.

[0033] The multiplier is the most critical component in all operations. It is the core computing unit in the system and directly affects the speed of calculation and the complexity of hardware. Multipliers are widely used in digital signal processing, filtering, frequency control and convolution, which are essentially multiplexing of multiplication operations. Multipliers are used in daily life in image processing, encryption applications, telecommunications, audio and video processing and other technologies. Therefore, the performance of the multiplier has a decisive influence on improving the efficiency and accuracy of the entire system.

[0034] The low-power ALU unit of the present invention uses a truncated multiplier to reduce computational complexity and hardware resource requirements. The technology based on rounding is used to reduce computational complexity and reduce resource consumption of internal and external structures. Error correction is achieved by compensating the carry circuit and result of the truncated part. The specific rounding and compensation strategy can be selected according to the demand scenario, error analysis and simulation evaluation.

[0035] As the name implies, the truncated multiplier is a traditional multiplier that truncates the corresponding operation unit or multiplication result. It does not calculate the complete product result, but truncates the product according to the preset bit width (i.e. precision). Since the corresponding data or results are removed, this method will definitely reduce the overall amount of calculation; since some circuits and components used to process low-bit data are omitted, the hardware resource consumption and computational complexity of the multiplier can be significantly reduced, the critical path length can be reduced, and the processing speed can be improved.

[0036] This embodiment makes corresponding improvements to the traditional truncated multiplier, rather than simply and roughly truncating the width, and guarantees the accuracy as much as possible. The specific steps are as follows: S21, determining the magnitude and direction of the error by comparing the result of the truncated multiplier with the result of the exact multiplier; S22, based on the characteristics of the multiplication operation and the characteristics of the input data, predicting which bits may generate a carry; S23, statically segment the multiplier according to the actual operation result and the number of truncation bits, and generate a partial product array according to the redundancy detection results of each segment. Then, a truncation compensation technique is used in the partial product compression step to reduce the truncation error. The compensation value is dynamically adjusted to minimize the truncation error.

[0037] S24. Compare and verify the results and make adjustments in real time.

[0038] The composite structure is adopted to combine multiple structures together, reuse the circuits that execute arithmetic and logical operation instructions, and use several control signals to control the related operations performed by the circuit. The fixed-width truncated parallel multiplier is adopted, and the carry circuit of the truncated part is used for compensation, which effectively reduces the output error of the multiplier while ensuring the operation accuracy, improves the operation speed, and reduces the circuit area.

[0039] Verilog is used for coding, and relevant tests are performed on Xilinx ISE. The power consumption in the chip can be broadly defined as dynamic power consumption and static power consumption. Static power consumption usually includes leakage power consumption (power consumption caused by not closing tightly) generated by the chip when it is not flipped, power consumption generated by substrate current, power consumption caused by current effect caused by thermal electron effect, etc. Under normal circumstances, it is difficult to make some optimizations in the front-end design stage (power supply can be turned off). Instead, it is generally necessary to improve the process or process based on ME / BE to achieve better results. Dynamic power is an additional impact of signal, clock, logic and IO power. The power of the signal is related to the length and number of the signal exchange network. Clock control depends on the transmission method of the clock network, and the transmission method depends on the chip area. Therefore, total power consumption = static power consumption + dynamic power consumption, and dynamic power consumption = (signal + clock + logic + i / o) power. Analyzing the power consumption of this method and the conventional method, it can be seen that the power consumption can be reduced by 20-50% by using this method.

[0040] Clock gating technology: It controls the propagation of clock signals to reduce unnecessary register flips to reduce power consumption, so it reduces dynamic power consumption.

[0041] One-hot encoding technology: Compared with other encodings, one-hot encoding usually involves only one bit flipping during state transition, thereby reducing the number of signal flipping times and, in turn, reducing dynamic power consumption.

[0042] Sleep transistor technology: Sleep transistor technology controls the power connection of circuit modules when they are not needed by adding additional transistors (usually high threshold voltage transistors) to the circuit. When the circuit module enters the sleep state, the sleep transistor cuts off the power connection, thereby significantly reducing static power consumption (leakage current). At the same time, this technology may also indirectly reduce dynamic power consumption by reducing unnecessary circuit activity.

[0043] ALU composite structure: Its optimization measures mainly reduce the number of signal flips when the ALU performs operations, thereby reducing dynamic power consumption.

[0044] Truncated multiplier technology: is a method to reduce computational complexity and power consumption in multiplication operations. By truncating certain parts of the multiplication operation (such as low or high bits), the required calculation steps and register flip times can be reduced, thereby reducing dynamic power consumption.

[0045] Therefore, the present invention combines the above-mentioned clock gating and dormant transistor technology to reduce the power consumption in the inactive state, provide fine-grained power consumption management capabilities, and extend the service life; utilize unique hot encoding technology to simplify circuit design, reduce the complexity of transitions between states, increase clock frequency, improve system throughput, and reduce the probability of error; adopt composite structure and truncated multiplier to achieve performance optimization, save circuit area, improve integration, enhance flexibility and adaptability, speed up calculation speed, reduce calculation complexity and hardware resources, and significantly reduce power consumption; integrate the above-mentioned technologies and means to ensure calculation accuracy and speed, effectively reduce the power consumption of the system, and reduce the resource occupation of the system. This method can be used in fields that require calculations such as artificial intelligence and image processing, and can effectively reduce the power consumption of ALU arithmetic logic units, and has broad application prospects.

[0046] The above description is only the basic principle and preferred embodiments of the present invention. Improvements and substitutions made by those skilled in the art based on the present invention belong to the protection scope of the present invention.

Claims

1. A method for reducing ALU power consumption, Features: The method temporarily shuts down inactive components, places unused modules in standby mode, and disables clocks of operation blocks that are not involved in executing selected operations at the current moment through clock gating. At the same time, the structure of the ALU functional component is set to a composite structure, the carry propagation and carry generation of the core adder are trimmed, the circuits of arithmetic operation instructions and logic operation instructions are multiplexed, and the multiplexed circuits are controlled by control signals to execute related operations.

2. The method for reducing ALU power consumption according to claim 1, Features: Clock gating includes an AND gate and a D flip-flop. The input end of the AND gate is connected to the enable signal and clock signal of the active component, module, and operation block. The output end of the AND gate is connected to the clock input pin of the D flip-flop. The data input pin of the D flip-flop is connected to the data output end of the active component, module, and operation block. The enable signal of the inactive component, the unused module, and the operation block that does not participate in executing the selected operation at the current moment is 0.

3. The method for reducing ALU power consumption according to claim 2, Features: The enable signal is one-hot encoded and transmitted to the input of the AND gate.

4. The method for reducing ALU power consumption according to claim 1, Features: A power switch is added to the power supply part of the ALU and / or each module in the ALU. When the ALU is in the standby state, the power supply line is cut off by the power switch, so that the ALU is in the dormant state.

5. The method for reducing ALU power consumption according to claim 4, Features: The power switch is two transistors, the gate of the upper PMOS tube is connected to the inverted sleep signal, the source is connected to the positive power supply voltage VDD, and the drain is connected to the ALU; at the same time, the gate of the lower NMOS tube is connected to the sleep signal, the source is connected to the reference ground voltage VSS, and the drain is connected to the ALU.

6. The method for reducing ALU power consumption according to claim 1, Features: Ways to trim the carry propagation and carry generation of the core adder include: A. using a carry selector to calculate carry generation and carry propagation in advance to reduce the delay of the adder; B. using a hybrid adder.

7. The method for reducing ALU power consumption according to claim 1, Features: The control signal includes an operation type selection signal, a carry control signal, a zero flag signal, and an overflow flag signal. The process of using the control signal to control the multiplexing circuit to perform related operations is as follows: S11, signal input, the control unit generates a control signal according to the type of instruction currently executed, and inputs it into the ALU through the control bus; S12, signal decoding, inside the ALU, there are one or more decoders for receiving control signals and decoding them into control signals for various components inside the ALU; S13, operation execution, the decoded control signal activates the corresponding components inside the ALU to perform the corresponding operation; S14, result output. After the operation is completed, the ALU outputs the operation result and related status flag signals to the data bus for use by other components.

8. The method for reducing ALU power consumption according to claim 1, Features: The method uses a truncated multiplier to reduce computational complexity and hardware resource requirements, and compensates for the carry circuit and result of the truncated part to achieve error correction.

9. The method for reducing ALU power consumption according to claim 7, Features: The truncated multiplier uses a rounding method to compensate for the carry circuit and result of the truncated part as follows: S21, determining the magnitude and direction of the error by comparing the result of the truncated multiplier with the result of the exact multiplier; S22, predicting a bit that will generate a carry based on the characteristics of the multiplication operation and the characteristics of the input data; S23, statically segmenting the multiplier according to the actual operation result and the number of truncation bits, and generating a partial product array according to the redundancy detection result of each segment, and then using the truncation compensation technology in the partial product compression step to reduce the truncation error; S24) Compare and verify the results and make adjustments in real time.

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