Vehicle-mounted chip system, method, equipment and medium based on ARM architecture

Abstract

The invention relates to a vehicle-mounted chip system, method, equipment and medium based on an ARM architecture, a system kernel accesses a storage module through an I / D TCM, and the system performance is obviously improved; dynamic distribution of I / D TCM storage capacity is achieved in the storage module, different development environments are adapted, access of a kernel and other hosts is not stored through CACHE in the system, the problem of maintaining data consistency does not exist, and great convenience is brought to software. Compared with the prior art, by optimizing the storage architecture, the performance of the vehicle-mounted chip can be greatly improved, development of system software is more concise, and applicable use scenes can be more diversified.

Description

Technical Field

[0001] The present invention belongs to the technical field of vehicle-mounted computer memory access, and relates to a vehicle-mounted chip system, method, device and medium based on ARM architecture. Background Art

[0002] In recent years, the trend of automobile electrification, networking and intelligence has accelerated, and the proportion of various electronic devices using semiconductor chips in automobiles has gradually increased. For example, the number of on-board chips in new energy vehicles and self-driving cars is greater than that in traditional fuel vehicles, and the technical requirements for on-board chips are also higher. With the popularization of new energy vehicles and the maturity of self-driving technology, the demand for on-board chips in automobiles has also increased rapidly. At present, there are more and more chips based on ARM as the core in on-board chips, and users have higher and higher requirements for storage and system performance. Simple on-board chips developed based on the ARM architecture can no longer meet the current needs of on-board applications, and there are technical problems of insufficient system performance. Summary of the invention

[0003] In response to the problems existing in the above-mentioned traditional methods, the present invention proposes a vehicle-mounted chip system based on the ARM architecture, a vehicle-mounted chip storage management method based on the ARM architecture, a computer device and a computer-readable storage medium, which can effectively improve system performance.

[0004] In order to achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0005] On the one hand, an ARM architecture-based vehicle chip system is provided, comprising a core, a storage module and a bus, wherein the bus is respectively connected to the core and the storage module, and the bus is used to connect to other hosts;

[0006] The core is connected to the storage module through the TCM bus, which includes an ITCM interface and a DTCM interface. In the storage module, the core and other hosts access the storage module after arbitration.

[0007] In one of the embodiments, the storage module dynamically allocates the storage capacity of the ITCM and the storage capacity of the DTCM according to the input storage configuration.

[0008] In one embodiment, the storage module includes a FLASH memory and a SRAM memory.

[0009] On the other hand, a vehicle-mounted chip storage management method based on ARM architecture is also provided, which is applied to a vehicle-mounted chip system based on ARM architecture, wherein the vehicle-mounted chip system comprises a core, a storage module and a bus, wherein the bus is connected to the core and the storage module respectively, and the bus is used to connect to other hosts; the core is connected to the storage module via a TCM bus, and the TCM bus comprises an ITCM interface and a DTCM interface, and within the storage module, the core and other hosts perform storage access to the storage module after arbitration;

[0010] The vehicle-mounted chip storage management method comprises the following steps:

[0011] Get storage access requests initiated by the kernel and other hosts for data exchange;

[0012] After arbitrating each received storage access request in the storage module, the storage access corresponding to the storage access request is processed according to the arbitration result.

[0013] In one embodiment, the above-mentioned vehicle-mounted chip storage management method based on ARM architecture further includes the steps of:

[0014] The storage capacity of ITCM and the storage capacity of DTCM in the storage module are dynamically allocated according to the input storage configuration.

[0015] In one embodiment, the storage module includes a FLASH memory and a SRAM memory.

[0016] On the other hand, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above-mentioned vehicle-mounted chip storage management method based on the ARM architecture when executing the computer program.

[0017] On the other hand, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned vehicle-mounted chip storage management method based on the ARM architecture are implemented.

[0018] One of the above technical solutions has the following advantages and beneficial effects:

[0019] In the above-mentioned ARM-based on-board chip system, method, device and medium, the system kernel accesses the storage module through I / DTCM, and the system performance is significantly improved; the dynamic allocation of I / DTCM storage capacity is realized in the storage module to adapt to different development environments. The kernel and other hosts do not access the system's internal CACHE storage, so there is no problem of maintaining data consistency, which brings great convenience to the software. Compared with traditional technologies, by optimizing the storage architecture, the performance of on-board chips can be greatly improved, and the development of system software is more concise, and the applicable usage scenarios can be more diversified. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 This is a schematic diagram of the storage architecture of a traditional vehicle-mounted chip;

[0022] Figure 2 A schematic diagram of the storage architecture of an ARM-based on-board chip system in one embodiment;

[0023] Figure 3 The figure is a flowchart of a vehicle chip storage management method based on the ARM architecture in an embodiment. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0025] It should be noted that the reference to "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase at various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be appreciated by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification of the present invention and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0026] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.

[0027] The storage architecture of traditional automotive chips can be Figure 1 As shown, it improves performance through built-in cache (CACHE, a mechanism for temporarily storing data in a computer system to increase the speed of data reading), which brings about the problem of software maintaining data consistency. In computer architecture, ICACHE (Instruction Tightly Coupled Memory) and DCACHE (Data Tightly Coupled Memory) are two types of caches used to improve CPU performance. They store instructions and data respectively to reduce the time the CPU accesses the main memory. ITCM (Instruction Tightly Coupled Memory) and DTCM (Data Tightly Coupled Memory) are special memory types used in ARM processors to further optimize performance. Unlike ICACHE and DCACHE, they provide direct memory access paths and avoid cache-related complexity and delays. ICTM (Instruction Cacheable Tightly Coupled Memory) and DCTM (Data Cacheable Tightly Coupled Memory) are memory types related to the ITCM and DTCM concepts, but they have different characteristics. ICTM is used to store the instruction code of the processor, and DCTM is used to store data that the processor needs to access quickly. CTM memory combines the advantages of cache and tightly coupled memory, providing a hybrid storage solution.

[0028] In the storage architecture of traditional automotive chips, the kernel accesses the system storage through an external bus. There will be performance loss from the kernel to the bus part, and in general, to compensate for this performance loss, an I / D CACHE is added on the path from the kernel to the bus to reduce performance loss. When adding CACHE, it will bring data consistency issues, that is, if the kernel does not maintain data consistency for data written by other hosts, the kernel will always fetch old data from the CACHE, resulting in the inability to fetch the latest data updated by other hosts. Maintaining data consistency also brings many inconveniences to the software; and the storage capacity of its I / D TCM is fixed, and its size cannot be dynamically adjusted according to the user's scenario.

[0029] The present invention is developed based on the ARM architecture, and moves the storage module of the vehicle chip system (including but not limited to FLASH memory and SRAM memory) from the AXI BUS (Advanced eXtensible Interface BUS, an on-chip bus for high performance, high bandwidth, and low latency) to the TCM BUS bus, thereby greatly improving the processing performance of the kernel's instruction and data fetching. By studying and optimizing the storage architecture of the vehicle chip system, the performance of the vehicle chip can be greatly improved, and the software development is more concise, and the usage scenarios can be more diverse.

[0030] In one embodiment, Figure 2 As shown, a vehicle-mounted chip system 100 based on the ARM architecture is provided, which may include a kernel, a storage module and a bus. The bus connects the kernel and the storage module respectively, and the bus is used to connect other hosts. The kernel is connected to the storage module via a TCM bus, and the TCM bus includes an ITCM interface and a DTCM interface. In the storage module, the kernel and other hosts perform storage access to the storage module after arbitration.

[0031] It can be understood that the explanation of the components such as the core, bus and other hosts can be understood in the same way as the similar components in the storage architecture of the traditional vehicle-mounted chip in the field, and will not be elaborated in this specification. In this embodiment, the memory moved from the AXI BUS bus to the TCM BUS bus can be but not limited to FLASH memory and SRAM memory, such as DRAM (dynamic random access memory) and FRAM (ferroelectric random access memory), as long as it can be used to improve the instruction and data fetching performance of the core.

[0032] The key point of improvement in this embodiment is that the kernel of the processor of the vehicle chip accesses the internal storage module of the system through the TCM bus, without the need for the system's CACHE storage, to ensure the performance of the kernel accessing the storage. As for the data interaction between the kernel and other hosts, in the storage module, the kernel and other hosts arbitrate the access before accessing the storage. This can solve the problem of data interaction, and such an architecture avoids the involvement of CACHE, so that developers no longer need to maintain data consistency, reducing the complexity of the developer's development program.

[0033] In a computer system, multiple components (such as CPU cores and other host devices) may need to access shared storage resources (such as memory, cache, or external storage devices) at the same time. In order to ensure the orderliness of these access operations and the consistency of data, a mechanism is needed to coordinate these access requests, which is the arbitration mechanism. The arbitration mechanism is a method of controlling and managing multiple access requests to ensure that each request can access shared resources in an orderly manner according to certain rules. The main goals of the arbitration mechanism include preventing conflicts, avoiding multiple devices from accessing the same storage location at the same time, resulting in data errors or system crashes; fairness, ensuring that all requesters have the opportunity to access resources and will not be blocked for a long time due to the high priority of some devices; priority processing, according to predefined priority rules, decide which request can access resources first. In the storage module, the kernel (usually refers to the processor core) and other hosts (such as DMA controller, peripheral device controller, etc.) may need to access shared storage resources. The general steps of the arbitration process may include: the kernel and other host devices send storage access requests to the arbitrator; the arbitrator evaluates all requests according to predefined rules (such as priority, request time, etc.); the arbitrator decides which request can have priority access to the storage resource; the arbitrator grants access to the priority requester and notifies other requesters to wait; the device that obtains access performs data read and write operations with the storage module; after the access is completed, the arbitrator processes the next request and repeats the above process.

[0034] In multi-core processors and multi-device systems, storage access arbitration between the core and other host devices is particularly important. Specific implementation methods include: time slicing, which divides storage access rights in time and allows different devices to access storage in different time slices; priority scheduling, which determines the order of storage access based on the priority of the device. For example, the priority of real-time tasks is usually higher than that of non-real-time tasks; round-robin scheduling, which allocates storage access rights to each requester in turn in a round-robin manner to ensure fairness. Through the arbitration mechanism, the system can effectively manage and coordinate multiple access requests to ensure system stability and performance.

[0035] In the above-mentioned ARM-based on-board chip system 100, the system kernel accesses the storage module through the I / D TCM, and the system performance is significantly improved; the dynamic allocation of the I / D TCM storage capacity is realized in the storage module to adapt to different development environments. The kernel and other hosts do not access the system's internal CACHE storage, so there is no problem of maintaining data consistency, which brings great convenience to the software. Compared with traditional technologies, by optimizing the storage architecture, the performance of the on-board chip can be greatly improved, and the development of the system software is more concise, and the applicable usage scenarios can be more diversified.

[0036] It should be noted that the AXI BUS is part of the AMBA (Advanced Microcontroller Bus Architecture), supports high-performance, high-bandwidth data transmission, has the characteristics of supporting multi-master and multi-slave architecture, high throughput and low latency, and supports burst transfer. The TCM BUS provides deterministic, low-latency memory access and is usually used in real-time systems and performance-critical applications. It has deterministic latency, is suitable for real-time applications, has a simple bus protocol, is easy to integrate and use, and is usually tightly coupled with a specific processor core.

[0037] The specific implementation process of moving the storage module from the AXI BUS bus to the TCM BUS bus can be seen as follows: First, analyze and determine whether the storage module requires deterministic access, low latency and high throughput, and study and understand which applications need to be migrated to the TCM bus, such as real-time data processing and high-priority tasks, and then reconnect the storage module to be used from the interface connected to the AXIBUS bus to the TCM BUS bus interface. If the on-chip interconnect structure is used in the system, the interconnection needs to be reconfigured to support the connection between the storage module and the TCM BUS bus. Then, to ensure that the processor core supports access to the TCM BUS bus, it is necessary to check the processor manual and configuration options to ensure that the TCM BUS bus is enabled and accessible; update the system's memory map so that the address range of the migrated storage module is mapped to the TCM BUS bus address space. Then, the startup code can be modified to ensure that the kernel and other hosts can correctly initialize and access the storage module on the TCM BUS bus when the system starts. If the storage module uses a specific driver, its driver also needs to be modified to support TCM BUS bus access. Finally, existing hardware verification tools and methods (such as FPGA prototype verification and simulation) can be used to verify the modified hardware design to ensure that the storage module works properly on the TCM BUS, and run the system software to verify that all functions related to the storage module are normal and ensure that there are no access conflicts or performance issues.

[0038] In one embodiment, the storage module dynamically allocates the storage capacity of the ITCM and the storage capacity of the DTCM according to the input storage configuration.

[0039] It can be understood that in this embodiment, the above-mentioned ARM architecture-based vehicle chip system 100 has another advantage: the storage module will dynamically allocate the storage size of TCM according to the storage configuration input by the developer. For example, if the developer's instruction program is large, the storage configuration input by the developer can instruct the system's storage module to configure the storage capacity of ITCM to be larger, so as to fully meet the access requirements of high-speed instructions in the current application scenario. If there is more data, the storage configuration input by the developer can instruct the system's storage module to configure the capacity of DTCM to be larger, so as to fully meet the access requirements of high-speed data in the current application scenario, thereby achieving the adaptation effect of various different development scenarios.

[0040] In one embodiment, the storage module includes a FLASH memory and an SRAM memory. It can be understood that in this embodiment, the memory moved from the AXI BUS bus to the TCM BUS bus can be a FLASH memory and an SRAM memory, thereby further reducing the difficulty and workload of system development while just meeting the system requirements.

[0041] Each module in the above-mentioned vehicle-mounted chip system 100 based on the ARM architecture can be fully or partially implemented by software, hardware and their combination. The above-mentioned modules can be embedded in or independent of a device with data processing functions in the form of hardware, or can be stored in the memory of the aforementioned device in the form of software, so that the processor can call and execute the operations corresponding to the above-mentioned modules. The aforementioned device can be, but is not limited to, various types of vehicle-mounted computer devices already available in the art.

[0042] The above-mentioned ARM-based on-board chip system 100 has been fully tested and a prototype has been developed, and the effect is relatively ideal and consistent with the design expectations.

[0043] In one embodiment, Figure 3 As shown, a vehicle-mounted chip storage management method based on ARM architecture is also provided, which is applied to a vehicle-mounted chip system based on ARM architecture. The vehicle-mounted chip system includes a core, a storage module and a bus, the bus is connected to the core and the storage module respectively, and the bus is used to connect other hosts; the core is connected to the storage module through a TCM bus, and the TCM bus includes an ITCM interface and a DTCM interface. In the storage module, the access of the core and other hosts is arbitrated before the storage module is accessed;

[0044] The above-mentioned vehicle-mounted chip storage management method may include the following processing steps S10 to S12:

[0045] S10, obtaining a storage access request initiated by the kernel and other hosts for data interaction;

[0046] S12, after arbitrating each received storage access request in the storage module, processing the storage access corresponding to the storage access request according to the arbitration result.

[0047] It can be understood that for the specific interpretation and limitation of the vehicle-mounted chip system based on the ARM architecture in this embodiment, please refer to the corresponding interpretation and limitation of the vehicle-mounted chip system 100 based on the ARM architecture above, and no further details will be given here.

[0048] In the above-mentioned ARM-based vehicle chip storage management method, the system kernel accesses the storage module through the I / D TCM, and the system performance is significantly improved; the dynamic allocation of the I / D TCM storage capacity is realized in the storage module to adapt to different development environments. The kernel and other hosts do not access the system's internal CACHE storage, so there is no problem of maintaining data consistency, which brings great convenience to the software. Compared with traditional technologies, by optimizing the storage architecture, the performance of vehicle chips can be greatly improved, and the development of system software is simpler, and the applicable usage scenarios can be more diverse.

[0049] In one embodiment, the above-mentioned vehicle-mounted chip storage management method based on ARM architecture further includes the steps of:

[0050] The storage capacity of ITCM and the storage capacity of DTCM in the storage module are dynamically allocated according to the input storage configuration.

[0051] In one embodiment, the storage module includes a FLASH memory and a SRAM memory.

[0052] For the specific interpretation and limitation of the vehicle-mounted chip storage management method based on the ARM architecture, please refer to the corresponding interpretation and limitation of the vehicle-mounted chip system 100 based on the ARM architecture above, and no further details will be given here.

[0053] It should be understood that although Figure 3 The steps in the method are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps can be executed in other orders. Figure 3At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequentially, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0054] In one embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the following processing steps when executing the computer program: obtaining a storage access request initiated by a kernel and other hosts for data interaction; arbitrating each received storage access request in a storage module, and processing the storage access corresponding to the storage access request according to the arbitration result.

[0055] In one embodiment, when the processor executes the computer program, it can also implement the steps or sub-steps added in each embodiment of the above-mentioned vehicle-mounted chip storage management method based on the ARM architecture.

[0056] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following processing steps are implemented: obtaining a storage access request initiated by a kernel and other hosts for data interaction; arbitrating each received storage access request in a storage module, and processing the storage access corresponding to the storage access request according to the arbitration result.

[0057] In one embodiment, when the computer program is executed by a processor, it can also implement the steps or sub-steps added in each embodiment of the above-mentioned vehicle-mounted chip storage management method based on the ARM architecture.

[0058] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus dynamic random access memory (RambusDRAM, referred to as RDRAM) and interface dynamic random access memory (DRDRAM).

[0059] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0060] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of protection of the invention. It should be pointed out that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the attached claims.

Claims

1. An ARM-based on-board chip system, characterized in that: It includes a kernel, a storage module and a bus, wherein the bus is connected to the kernel and the storage module respectively, and the bus is used to connect to other hosts; The core is connected to the storage module via a TCM bus, and the TCM bus includes an ITCM interface and a DTCM interface. In the storage module, the core and the other hosts perform storage access to the storage module after arbitration.

2. The vehicle-mounted chip system based on ARM architecture according to claim 1, characterized in that: The storage module dynamically allocates the storage capacity of the ITCM and the storage capacity of the DTCM according to the input storage configuration.

3. The vehicle-mounted chip system based on ARM architecture according to claim 1 or 2, characterized in that: The storage module includes a FLASH memory and a SRAM memory.

4. A vehicle-mounted chip storage management method based on ARM architecture, characterized in that: The invention is applied to an in-vehicle chip system based on ARM architecture, the in-vehicle chip system comprises a kernel, a storage module and a bus, the bus respectively connects the kernel and the storage module, and the bus is used to connect other hosts; the kernel is connected to the storage module via a TCM bus, the TCM bus comprises an ITCM interface and a DTCM interface, and in the storage module, the kernel and the other hosts perform storage access to the storage module after arbitration; The vehicle-mounted chip storage management method comprises the steps of: Acquire a storage access request initiated by the kernel and the other host for data interaction; After arbitrating each of the received storage access requests in the storage module, the storage access corresponding to the storage access request is processed according to the arbitration result.

5. The vehicle-mounted chip storage management method based on ARM architecture according to claim 4 is characterized in that: Also includes the steps: The storage capacity of the ITCM and the storage capacity of the DTCM in the storage module are dynamically allocated according to the input storage configuration.

6. The vehicle-mounted chip storage management method based on ARM architecture according to claim 4 or 5, characterized in that: The storage module includes a FLASH memory and a SRAM memory.

7. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, the steps of the vehicle-mounted chip storage management method based on the ARM architecture as described in any one of claims 4 to 6 are implemented.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the vehicle-mounted chip storage management method based on the ARM architecture as described in any one of claims 4 to 6 are implemented.

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