A method for simulating IP module K library based on mode

Abstract

The purpose of the present invention is to provide a method based on the mode analog IP module K library, the method comprising: determining the type of timing arc in the analog IP module to be detected; selecting a measurement mode according to the type of the timing arc; and detecting the analog IP module according to the measurement mode. The present invention divides a complex IP analog module into multiple submodules according to the test mode, then runs each submodule in parallel to obtain intermediate parameters, and then calculates the final timing lib file based on the intermediate parameters, which can avoid the complexity and uncertainty brought by the k library tool and improve the efficiency of generating the timing lib file.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a method for simulating an IP module K library based on mode. Background Art

[0002] The essence of K library (library feature parameter extraction) is to generate Timing lib (timing library) files, which accurately characterize the electrical characteristics of the circuit in the form of library files (.lib). The specific implementation method is to generate a database file of the timing information of the circuit under various PVT (process, voltage, temperature) working conditions through spice simulation. These timing information include circuit delay, setup time, hold time, etc. Timing lib is a prerequisite for any digital design process. The information stored in the timing library file will be used throughout the implementation process of digital design, from logic synthesis, through design optimization, to the final signoff verification. Accurately creating timing lib is crucial to ensure a high degree of consistency between design intent and the final silicon chip.

[0003] Analog IP modules refer to IC design modules that have been verified and can be reused in IC design and have a certain exact function. Analog IP modules can improve the efficiency and reusability of IC design. By using pre-verified IP cores, designers can focus on realizing the differentiated functions of the product instead of designing each functional module from scratch. The application of analog IP modules not only speeds up the chip design process, but also improves the reliability and quality of the design. In IC design, analog IP modules can cover everything from simple logic units to complex system-level functions such as processors, memory controllers, etc. These analog IP modules can be purchased from third-party suppliers or developed by the designers themselves, but in either case, they must be rigorously verified and tested to ensure that their functions and performance meet the design requirements. The reusability of analog IP modules is one of the reasons why they are so important in the semiconductor industry. It allows designers to utilize the same analog IP modules in different projects, saving a lot of design and verification time.

[0004] For larger and more complex analog IP modules, it has always been a challenging task to quickly and accurately generate timing libs for analog IP. Existing k-library tools have the following disadvantages: advanced nodes and increased circuit scale have led to a significant increase in simulation time, and more and more working conditions also mean an increase in k-library time. Although complex analog modules can use tools to cut circuits to retain timing-related parts and reduce circuit size to quickly obtain simulation results, there may also be situations where incorrect cutting leads to unreasonable results. When there is a problem with the k-library process or simulation results, it is difficult to debug the cause and find the root cause. The repeated iteration process leads to an increase in k-library time, which affects the project progress. Summary of the invention

[0005] The purpose of the present invention is to provide a method based on the mode simulation IP module K library, which divides the complex IP simulation module into multiple sub-modules according to the test mode, then runs each sub-module in parallel to obtain intermediate parameters, and then calculates the final timing lib file according to the intermediate parameters. The method can avoid the complexity and uncertainty brought by the k library tool and improve the efficiency of generating timing lib files.

[0006] A method for simulating an IP module K library based on mode, comprising:

[0007] Determine the type of timing arc in the analog IP module to be tested;

[0008] Selecting a measurement mode according to the type of the timing arc;

[0009] Detecting the analog IP module according to the measurement mode;

[0010] Generate a timing lib file based on the detection results.

[0011] Preferably, the selecting a measurement mode according to the type of the timing arc comprises:

[0012] A first mode is used to measure a setup / hold timing arc;

[0013] Get the delay from the analog module input data to the trigger D terminal;

[0014] Get the delay from the input clock to the flip-flop ck terminal.

[0015] Preferably, the selecting a measurement mode according to the type of the timing arc comprises:

[0016] The second mode is used to measure the delays caused by the combined timing arcs and flip-flops;

[0017] Get the delay from the internal clock to the trigger output Q;

[0018] Get the delay from the trigger output Q to the analog module output;

[0019] Gets the delay from the internal clock to the output of the analog block.

[0020] Preferably, the selecting a measurement mode according to the type of the timing arc comprises:

[0021] The third mode is used to measure the delay of the combined timing arc and the delay of the setup / hold timing arc;

[0022] Get the delay from the analog module input to the trigger ck terminal;

[0023] Get the delay from the internal clock to the trigger ck end;

[0024] Gets the delay from the internal clock to the output of the analog block.

[0025] Preferably, determining the type of timing arc in the analog IP module to be detected includes:

[0026] Get the process / voltage / temperature parameters of the timing arc;

[0027] The temporal arc recognition model is trained based on prior knowledge;

[0028] The trained timing arc recognition model is used to identify the type of the timing arc according to the process / voltage / temperature parameters of the timing arc.

[0029] Preferably, the adopting the first mode to measure the setup / hold timing arc comprises:

[0030] The analog module of the first mode includes: a first combinational logic module, a second combinational logic module and a first trigger;

[0031] The input end of the first combinational logic module is connected to the first input data, and the output end is connected to the D end of the first trigger;

[0032] The input end of the second combinational logic module is connected to the input clock, and the output end is connected to the ck end of the first trigger;

[0033] Acquire signals of an input terminal and an output terminal of a first combinational logic module;

[0034] The signals of the input terminal and the output terminal of the second combinational logic module are obtained.

[0035] Preferably, the step of measuring the delay caused by the combined timing arc and the trigger using the second mode comprises:

[0036] The analog module of the second mode includes: a first internal clock module, a third combinational logic module, a fourth combinational logic module, a second trigger and a fifth combinational logic module;

[0037] The first internal clock module is connected to the input ends of the third combinational logic module and the fourth combinational logic module;

[0038] The output end of the third combinational logic module is connected to the ck end of the second trigger;

[0039] The output end of the fourth combinational logic module is connected to the first clock output;

[0040] The input end of the fifth combinational logic module is connected to the Q end of the second flip-flop, and the output end is connected to the output of the analog module of the second mode;

[0041] Preferably, obtaining a signal output by a first internal clock;

[0042] Acquire signals of the input and output terminals of the fifth combinational logic module;

[0043] Get the signal output by the first clock.

[0044] Preferably, the adopting the third mode to measure the delay of the combined timing arc and the delay of the setup / hold timing arc comprises:

[0045] The analog module of the third mode includes: a sixth combinational logic module, a seventh combinational logic module, an eighth combinational logic module, a second internal clock module and a third trigger;

[0046] The input end of the sixth combinational logic module is connected to the second input data, and the output end is connected to the D end of the trigger;

[0047] The input end of the seventh combinational logic module is connected to the internal clock module, and the output end is connected to the ck end of the trigger;

[0048] The input end of the eighth combinational logic module is connected to the internal clock module, and the output end is connected to the second clock output;

[0049] Acquiring signals from an input terminal and an output terminal of a sixth combinational logic module;

[0050] Acquiring signals from an input terminal and an output terminal of a seventh combinational logic module;

[0051] The signals of the input terminal and the output terminal of the eighth combinational logic module are obtained.

[0052] A system based on mode simulation IP module K library, comprising:

[0053] A judgment module, used for judging the type of timing arc in the analog IP module to be detected;

[0054] A selection module, used for selecting a measurement mode according to the type of the timing arc;

[0055] A detection module, used for detecting the analog IP module according to the measurement mode;

[0056] The generation module is used to generate the timing lib file based on the detection results.

[0057] An electronic device comprises: a processor and a memory, wherein the memory is used to store computer program codes, the computer program codes comprise computer instructions, and when the processor executes the computer instructions, the electronic device executes a method based on a mode simulation IP module K library.

[0058] The beneficial effect of the present application is that the present application divides all the timing arcs of a large analog module into different types according to the test mode, selects different test modes according to the type of the timing arc, and simulates the circuit in parallel to obtain different types of circuit intermediate parameters. Then, after filling in the Excel form, the script automatically calculates the final circuit parameters according to the circuit intermediate parameters according to the test mode to generate the timing lib. The present application can avoid the complexity and uncertainty brought by the K library tool, obtain the intermediate circuit parameters through spice simulation and measurement, and then automatically generate the timing lib according to the algorithm, thereby generating the timing lib file faster. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0060] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0061] Figure 1 A flow chart of a method for simulating IP module K library based on mode of the present invention;

[0062] Figure 2 This is a schematic diagram of the first mode test structure of the present invention;

[0063] Figure 3 It is a schematic diagram of the second mode test structure of the present invention;

[0064] Figure 4 This is a schematic diagram of the third mode test structure of the present invention;

[0065] Figure 5 The figure is a schematic diagram of the hardware structure of an electronic device of the present invention. DETAILED DESCRIPTION

[0066] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0067] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0068] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0069] For larger and more complex analog IP modules, it has always been a challenging task to quickly and accurately generate timing libs for analog IP. Existing k-library tools have the following disadvantages: advanced nodes and increased circuit scale have led to a significant increase in simulation time, and more and more working conditions also mean an increase in k-library time. Although complex analog modules can use tools to cut circuits to retain timing-related parts and reduce circuit size to quickly obtain simulation results, there may also be situations where incorrect cutting leads to unreasonable results. When there is a problem with the k-library process or simulation results, it is difficult to debug the cause and find the root cause. The repeated iteration process leads to an increase in k-library time, which affects the project progress.

[0070] This application divides all the timing arcs of a large analog module into different types according to the test mode, selects different test modes according to the type of timing arc, and simulates the circuit in parallel to obtain different types of circuit intermediate parameters. Then, after filling in the Excel table, the script automatically calculates the final circuit parameters according to the test mode and the circuit intermediate parameters to generate the timing lib. This application can avoid the complexity and uncertainty brought by the K library tool, obtain the intermediate circuit parameters through spice simulation and measurement, and then automatically generate the timing lib according to the algorithm, so as to generate the timing lib file faster.

[0071] Example 1

[0072] A method based on mode simulation IP module K library, reference Figure 1 ,include:

[0073] S100, determining the type of timing arc in the analog IP module to be detected;

[0074] A timing arc is a path required to track signal transmission in static timing analysis. Each timing arc has a starting point and an end point, and the timing arc contains the timing information between the two points. Timing arcs are usually divided into the delay of the connection and the delay of the unit. The delay of the connection refers to the delay information between the output port of the unit and the fan-out network load. The delay of the unit refers to the delay information from the input port of the unit to the output port of the unit. When the signal is flipped, you need to pay attention to the position of the time point card. The setup time refers to the time before the rising edge of the clock that the data must remain stable. The maximum delay cannot exceed the limit of the setup time, otherwise it will cause the trigger to be metastable; the hold time refers to the period of time after the rising edge of the clock that the data remains unchanged. If it changes within the hold time, the trigger cannot obtain stable data.

[0075] As an important concept to describe the timing relationship of digital logic circuits, the timing arc can help circuit designers perform timing analysis, fault detection, timing optimization and other tasks on the circuit. The timing arc is also the basis for electronic design automation software to implement functions such as logic synthesis, layout and routing, and timing simulation, and plays an important role in improving the efficiency and reliability of digital circuit design. The timing arc is widely used in various digital circuit design fields, such as processors, memories, FPGAs, etc. In terms of timing analysis, the timing arc can help designers evaluate the propagation delay and peak moment of the signal in the circuit in order to design a more accurate circuit. In terms of timing optimization, the timing arc can help designers identify potential timing problems in the circuit and try to optimize the circuit structure and timing characteristics to improve the performance and stability of the circuit.

[0076] S200, selecting a measurement mode according to the type of the timing arc;

[0077] According to the actual situation, three modes are summarized and statistically applied to the actual timing requirements of existing analog IP modules. Selecting the corresponding detection mode according to the different types of timing arcs to be detected can greatly improve the efficiency of analog IP module detection and reduce the error rate of analog IP module detection.

[0078] S300, detecting the analog IP module according to the measurement mode;

[0079] Timing lib is a prerequisite for any digital design process. The information stored in the timing library file will be used throughout the implementation process of the digital design, from logic synthesis, through design optimization, to the final signoff verification. Accurately creating a timing lib is critical to ensuring a high degree of consistency between the design intent and the final silicon chip. The basic parameters of the timing arc include: Start level: the level state at the starting point of the timing arc. End level: the level state at the end point of the timing arc. Timing check type: defines the relationship between the clock edge and the data edge. Delay time: defines the propagation time of the signal on the timing arc. Voltage domain: describes the timing behavior of the signal at different voltages.

[0080] S400: Generate a timing lib file according to the detection result.

[0081] Timing arcs are data used to describe the delay information of two nodes. The information of timing arcs is generally divided into wire delay and unit delay. Wire delay is the delay information between the unit output port and the fan-out network load. Unit delay is the delay information between the unit input port and the output port. Therefore, the timing information calculation of a complete path consists of wire delay and unit delay. Wire delay has no functional attributes, so there is no difference in the classification of delay information. The timing arcs in unit delay are divided into basic timing arcs and constrained timing arcs. Among them, the constrained timing arc is used to represent the information of the timing constraint Q between the input ports. Basic timing arcs include combinational timing arcs, edge timing arcs, reset and clear timing arcs, tri-state enable timing arcs, etc. Constrained timing arcs include setup timing arcs, hold timing arcs, recovery timing arcs, removal timing arcs, and pulse width timing arcs.

[0082] The accurate creation of the timing library can help designers perform timing analysis, fault detection, timing optimization and other tasks on the circuit. The timing library is also the basis for electronic design automation software to implement functions such as logic synthesis, layout and routing, and timing simulation, and plays an important role in improving the efficiency and reliability of digital circuit design. Timing libraries are widely used in various digital circuit design fields, such as processors, memories, FPGAs, etc. In terms of timing analysis, the timing library can help designers evaluate the propagation delay and peak moment of the signal in the circuit in order to design a more accurate circuit. In terms of timing optimization, the timing library can help designers identify potential timing problems in the circuit, and try to optimize the circuit structure and timing characteristics to improve the performance and stability of the circuit.

[0083] Preferably, reference Figure 2 , S200, select the measurement mode according to the type of timing arc, including:

[0084] S210A, measuring a setup / hold timing arc using a first mode;

[0085] The establishment of timing arcs is used to indicate the constraint information required by the timing unit to obtain the correct data signal, that is, the time information that the data input signal remains valid before the clock edge is valid. The time information that the signal must be valid before the high level effective edge of the timing unit clock is indicated by the establishment of timing arcs.

[0086] The hold timing arc is used to indicate the constraint information required by the timing unit to obtain the correct signal, that is, the data input signal continues to maintain valid time information after the clock edge is valid. The hold timing arc is divided into two types: rising edge valid and falling edge valid.

[0087] Get the delay from the analog module input data to the trigger D terminal;

[0088] A trigger is a special stored procedure that is different from a regular stored procedure and is executed mainly by triggering an event. When inserting, modifying, and deleting operations are performed on the specified data table, the trigger will be automatically executed to ensure that the processing of the data complies with the predefined rules. Triggers provide an effective monitoring and processing mechanism for the database, ensuring the integrity of data and business. They are mainly used to implement complex referential integrity and data consistency, strengthen constraints, track changes, cascade operations, and call stored procedures. A trigger or latch is a circuit with two stable states that can be used to store state information. This circuit can change state by applying a signal to one or more control inputs and will have one or two outputs. It is a basic storage element in sequential logic and is widely used in computers, communications, and many other types of systems.

[0089] Get the delay from the input clock to the flip-flop ck terminal.

[0090] The present application sets up multiple detection points in the simulation module. By obtaining the delay of the detection points, the correct parameter information of the timing library can be deduced, so that the timing library can be automatically calculated and generated through a script, which can greatly improve the efficiency and accuracy of the timing library generation.

[0091] Preferably, reference Figure 3 , S200, select the measurement mode according to the type of timing arc, including:

[0092] S210B, measuring the delay caused by the combined timing arc and the trigger using the second mode;

[0093] The combinational timing arc is the most basic unit delay information timing arc, which is mainly used to represent the delay information of the combinational logic unit. The combinational timing arc is divided into the following three delay arcs in different logic states according to the different unit functional logics: same-direction timing arc, reverse timing arc and indeterminate timing arc. The same-direction timing arc indicates that the input signal change direction is consistent with the output signal change direction. The reverse timing arc indicates that the input signal change direction is opposite to the output signal change direction. The indeterminate timing arc indicates that there is no fixed relationship between the input signal change direction and the output signal change direction.

[0094] Get the delay from the internal clock to the trigger output Q;

[0095] Get the delay from the trigger output Q to the analog module output;

[0096] Gets the delay from the internal clock to the output of the analog block.

[0097] In the present application, the D flip-flop is used to provide a state in which peripheral data is ready and has a memory function. The D flip-flop has two stable states, namely "0" and "1". Under the action of a certain external signal, the D flip-flop can flip from one stable state to another stable state. This characteristic makes the D flip-flop widely used in digital systems and computers. It can not only be used to register digital signals, but also can be used for various functions such as shift register, frequency division and waveform generator. The operation of the D flip-flop depends on the edge trigger of the clock pulse CP. When CP changes from a low level to a high level, the output state of the D flip-flop will depend on the state of the input D terminal, that is, the next state = D. This characteristic enables the D flip-flop to receive the input signal before the rising edge of the clock signal and trigger the flip at the rising edge, thereby ensuring that the input signal is blocked after the rising edge, realizing the edge triggering function. This design allows the input signal to be added at the moment before the CP trigger edge arrives, thereby greatly shortening the time when the input terminal is interfered with and reducing the possibility of interference. In addition, the D flip-flop also has two functions of setting 0 and setting 1. The state of the D flip-flop can be forced to "0" or "1" through appropriate control signals (such as SD and RD), which is very useful when building more complex digital circuits. For example, in a counter circuit, when the counter reaches its maximum value, the Reset input of the RD flip-flop can be used to force the counter value to 0 to achieve the reset function; while the SD flip-flop can set the initial value of the counter to a non-zero value through the Set input, thereby achieving the setting operation of the counter.

[0098] Preferably, reference Figure 4 , S200, select the measurement mode according to the type of timing arc, including:

[0099] S210C, measuring the delay of the combined timing arc and the delay of the setup / hold timing arc using the third mode;

[0100] Get the delay from the analog module input to the trigger ck terminal;

[0101] Get the delay from the internal clock to the trigger ck end;

[0102] Gets the delay from the internal clock to the output of the analog block.

[0103] After dividing all the timing arcs of the analog module into three modes, the relevant circuits are simulated in parallel to obtain the values ​​of t1 / t2 / t3, and the corresponding mode is selected by filling in the Excel table according to certain format specifications. The algorithms of different modes and different timing arcs are analyzed through scripts to automatically generate the correct timing lib file. The calculation method of mode is shown in the following table, where dff_setup / dff_hold are the setup and hold values ​​of the trigger itself.

[0104] Table 1: Mode calculation method table

[0105]

[0106] Fill in the pin information of the circuit and the simulated t1 / t2 / t3 values, and run the script to automatically calculate and generate timinglib.

[0107] Table 2: Timing lib generation table

[0108]

[0109] Preferably, determining the type of timing arc in the analog IP module to be detected includes:

[0110] Get the process / voltage / temperature parameters of the timing arc;

[0111] Static timing analysis is usually performed under specific working conditions, which are defined as a combination of process, voltage and temperature, referred to as PVT. The logic unit delay is obtained by searching the lib library file. Process: Semiconductor foundries provide three processing process models for digital design: slow process model, typical process model and fast process model; the faster, the smaller the delay Voltage: logic unit operating voltage; the higher the voltage, the smaller the delay Temperature: logic unit operating temperature; usually, the higher the temperature, the smaller the delay, but as the process becomes more advanced and the channel length becomes smaller, a temperature reversal effect may occur, that is, the lower the temperature, the smaller the delay: logic unit operating voltage; the higher the voltage, the smaller the delay Temperature: logic unit operating temperature; usually, the higher the temperature, the smaller the delay, but as the process becomes more advanced and the channel length becomes smaller, a temperature reversal effect may occur, that is, the lower the temperature, the smaller the delay: logic unit operating voltage; the higher the voltage, the smaller the delay Temperature: logic unit operating temperature; usually, the higher the temperature, the smaller the delay, but as the process becomes more advanced and the channel length becomes smaller, a temperature reversal effect may occur, that is, the lower the temperature, the smaller the delay.

[0112] The temporal arc recognition model is trained based on prior knowledge;

[0113] Prior knowledge includes the type of timing library generated under the existing PVT working conditions and timing information, and the timing information includes circuit delay, setup time, hold time, etc. In the next step of cognitive activities such as the timing arc recognition model processing information and making decisions, prior knowledge can guide and assist the timing arc recognition model, helping the timing arc recognition model to quickly process information and make decisions, and obtain the timing arc type results.

[0114] The training of the temporal arc recognition model adjusts the parameters of the model through a large amount of prior data, so that the temporal arc recognition model can make accurate predictions on unseen data or perform specific tasks. The temporal arc recognition model learns task-related features and representations through training. During the training process, the temporal arc recognition model automatically learns how to extract useful features from the input data by adjusting weights and parameters. These features are crucial for the successful execution of the task. Training enables the temporal arc recognition model to have the ability to generalize, that is, to make good predictions when faced with unseen data. By learning from a large amount of training data, the temporal arc recognition model can capture common patterns in the data instead of just remembering specific samples in the training set. The temporal arc recognition model usually contains a large number of parameters, which can be adjusted through training to minimize the prediction error of the model on the training data. The optimization algorithm adjusts the parameters by minimizing the loss function so that the output of the temporal arc recognition model is closer to the true label. The temporal arc recognition model learns the hierarchical representation and abstraction of data through multi-level neural networks, so that it can understand complex relationships and patterns. This hierarchical representation helps improve the model's ability to understand the input data. The temporal arc recognition model can adapt to different data distributions and patterns during the training process. By repeatedly adjusting the model parameters, the temporal arc recognition model can adapt to various input conditions, which enhances the flexibility of the temporal arc recognition model.

[0115] The trained timing arc recognition model is used to identify the type of timing arc according to the process / voltage / temperature parameters of the timing arc.

[0116] The K-means clustering model is used as the main framework of the time series arc recognition model. The K-means clustering model is used to group data points into clusters with similar properties. The algorithm iteratively optimizes the objective function of the sum of squared errors, assigns data points to the nearest cluster center, and recalculates the location of the cluster center until the cluster center no longer changes or changes very little. The advantages of the K-means clustering model include simplicity and ease of implementation, fast processing speed, and suitability for processing large-scale data sets. The basic steps of the K-means clustering model include: randomly selecting K objects as the initial cluster centers. Assigning other data points to the cluster where the nearest cluster center is located. Recalculating the center point of each cluster. Repeating the steps until the cluster center no longer changes or changes very little. When implementing the K-means clustering model, the elbow method can be used to determine the optimal number of clusters K, that is, selecting a suitable K value by observing the trend of the sum of squared errors (SSE) as the K value increases. In addition, the silhouette coefficient is also a method to evaluate the clustering effect. The larger the value, the better the clustering effect. As for the principle of the K-means clustering model, it assigns data points to the nearest cluster center based on a distance metric (such as Euclidean distance) and optimizes the clustering results by minimizing the sum of the squares of the distances from all data points to their cluster centers.

[0117] The advantages of the K-means clustering model include simplicity, speed, ease of implementation, and good data representation. However, it also has some limitations, such as the need to pre-set the number of clusters k, sensitivity to outliers, possible convergence to local minima, and high algorithm complexity for large clustering problems, which may lead to slow operation. Despite these limitations, the K-means clustering model has been widely used in various fields due to its simple principle, strong interpretability, easy implementation, and fast convergence speed.

[0118] The timing arc recognition model can determine the type of the generated timing arc according to the process / voltage / temperature parameters when the timing arc is generated, and can improve the accuracy of the measurement of the timing arc in the next step.

[0119] Preferably, measuring the setup / hold timing arc using the first mode includes:

[0120] The analog module of the first mode includes: a first combinational logic module, a second combinational logic module and a first trigger;

[0121] The input terminal of the first combinational logic module is connected to the first input data, and the output terminal is connected to the D terminal of the first trigger;

[0122] The input end of the second combinational logic module is connected to the input clock, and the output end is connected to the ck end of the first trigger;

[0123] Acquire signals of an input terminal and an output terminal of a first combinational logic module;

[0124] The signals of the input terminal and the output terminal of the second combinational logic module are obtained.

[0125] like Figure 2 As shown, the first mode mode1 corresponds to the measurement of the setup / hold arc, in which t1 is the delay from the analog module input data pin to the trigger D terminal, and t2 is the delay from the input clock pin to the trigger ck terminal.

[0126] Preferably, using the second mode to measure the delay caused by the combined timing arc and the trigger comprises:

[0127] The analog module of the second mode includes: a first internal clock module, a third combinational logic module, a fourth combinational logic module, a second trigger and a fifth combinational logic module;

[0128] The first internal clock module is connected to the input terminals of the third combinational logic module and the fourth combinational logic module;

[0129] The output terminal of the third combinational logic module is connected to the ck terminal of the second flip-flop;

[0130] The output terminal of the fourth combinational logic module is connected to the first clock output;

[0131] The input terminal of the fifth combinational logic module is connected to the Q terminal of the second flip-flop, and the output terminal is connected to the output of the analog module of the second mode;

[0132] Preferably, obtaining a signal output by a first internal clock;

[0133] Acquire signals of the input and output terminals of the fifth combinational logic module;

[0134] Get the signal output by the first clock.

[0135] like Figure 3 As shown, the second mode mode2 corresponds to two types of measured timing arcs: the combinatinal arc and the delay from the trigger to the clock (ck2q). In the figure, t1 is the delay from the internal clock to the trigger output Q, t2 is the delay from the trigger output Q to the analog module output pin, and t3 is the delay from the internal clock to the analog module output clock pin.

[0136] Preferably, measuring the delay of the combined timing arc and the delay of the setup / hold timing arc using the third mode includes:

[0137] The analog module of the third mode includes: a sixth combinational logic module, a seventh combinational logic module, an eighth combinational logic module, a second internal clock module and a third trigger;

[0138] The input terminal of the sixth combinational logic module is connected to the second input data, and the output terminal is connected to the D terminal of the trigger;

[0139] The input end of the seventh combinational logic module is connected to the internal clock module, and the output end is connected to the ck end of the trigger;

[0140] The input end of the eighth combinational logic module is connected to the internal clock module, and the output end is connected to the second clock output;

[0141] Acquiring signals from an input terminal and an output terminal of a sixth combinational logic module;

[0142] Acquiring signals from an input terminal and an output terminal of a seventh combinational logic module;

[0143] The signals of the input terminal and the output terminal of the eighth combinational logic module are obtained.

[0144] like Figure 4As shown, the third mode mode3 also has two types of measured arcs: the combinatorial arc and the setup / hold arc delay. In the figure, t1 is the delay from the analog module input pin data to the trigger ck, t2 is the delay from the internal clock to the trigger ck, and t3 is the delay from the internal clock to the analog module output pin.

[0145] Example 2

[0146] A system based on mode simulation IP module K library, comprising:

[0147] A judgment module, used for judging the type of timing arc in the analog IP module to be detected;

[0148] A selection module for selecting a measurement mode according to the type of timing arc;

[0149] A detection module, used for detecting the analog IP module according to the measurement mode;

[0150] The generation module is used to generate the timing lib file based on the detection results.

[0151] Example 3

[0152] An electronic device comprises: a processor and a memory, wherein the memory is used to store computer program codes, and the computer program codes include computer instructions. When the processor executes the computer instructions, the electronic device executes a method based on a mode simulation IP module K library.

[0153] refer to Figure 5 , the electronic device 2 includes a processor 21, a memory 22, an input device 23, and an output device 24. The processor 21, the memory 22, the input device 23, and the output device 24 are coupled via a connector, and the connector includes various interfaces, transmission lines, or buses, etc., which are not limited in the embodiments of the present invention. It should be understood that in various embodiments of the present invention, coupling refers to mutual connection in a specific manner, including direct connection or indirect connection through other devices, for example, through various interfaces, transmission lines, buses, etc.

[0154] The processor 21 may be one or more graphics processing units (GPUs). When the processor 21 is a GPU, the GPU may be a single-core GPU or a multi-core GPU. Optionally, the processor 21 may be a processor group consisting of multiple GPUs, and the multiple processors are coupled to each other via one or more buses. Optionally, the processor may also be other types of processors, etc., which are not limited in the embodiments of the present invention.

[0155] The memory 22 can be used to store computer program instructions and various computer program codes including program codes for executing the scheme of the present invention. Optionally, the memory includes but is not limited to random access memory (RAM), read-only memory (ROM), erasable programmable read only memory (EPROM), or portable read only memory (CD-ROM), which is used for related instructions and data.

[0156] The input device 23 is used to input data and / or signals, and the output device 24 is used to output data and / or signals. The output device 24 and the input device 23 may be independent devices or an integrated device.

[0157] This application divides all the timing arcs of a large analog module into different types according to the test mode, selects different test modes according to the type of timing arc, and simulates the circuit in parallel to obtain different types of circuit intermediate parameters. Then, after filling in the Excel table, the script automatically calculates the final circuit parameters according to the test mode and the circuit intermediate parameters to generate the timing lib. This application can avoid the complexity and uncertainty brought by the K library tool, obtain the intermediate circuit parameters through spice simulation and measurement, and then automatically generate the timing lib according to the algorithm, so as to generate the timing lib file faster.

[0158] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for simulating IP module K library based on mode, characterized in that: include: Determine the type of timing arc in the analog IP module to be tested; Selecting a measurement mode according to the type of the timing arc; Detecting the analog IP module according to the measurement mode; Generate timing lib file based on the detection results; The selecting of the measurement mode according to the type of the timing arc comprises: A first mode is used to measure a setup / hold timing arc; Get the delay from the analog module input data to the trigger D terminal; Get the delay from the input clock to the trigger ck end; The selecting of the measurement mode according to the type of the timing arc comprises: The second mode is used to measure the delays caused by the combined timing arcs and flip-flops; Get the delay from the internal clock to the trigger output Q; Get the delay from the trigger output Q to the analog module output; Get the delay from the internal clock to the analog module output; The selecting of the measurement mode according to the type of the timing arc comprises: The third mode is used to measure the delay of the combined timing arc and the delay of the setup / hold timing arc; Get the delay from the analog module input to the trigger ck terminal; Get the delay from the internal clock to the trigger ck end; Gets the delay from the internal clock to the output of the analog block.

2. A method based on mode simulation IP module K library according to claim 1, characterized in that: Determining the type of timing arc in the analog IP module to be detected includes: Get the process / voltage / temperature parameters of the timing arc; The temporal arc recognition model is trained based on prior knowledge; The trained timing arc recognition model is used to identify the type of the timing arc according to the process / voltage / temperature parameters of the timing arc.

3. A method based on mode simulation IP module K library according to claim 2, characterized in that: The adopting the first mode to measure the setup / hold timing arc comprises: The analog module of the first mode includes: a first combinational logic module, a second combinational logic module and a first trigger; The input end of the first combinational logic module is connected to the first input data, and the output end is connected to the D end of the first trigger; The input end of the second combinational logic module is connected to the input clock, and the output end is connected to the ck end of the first trigger; Acquire signals of an input terminal and an output terminal of a first combinational logic module; The signals of the input terminal and the output terminal of the second combinational logic module are obtained.

4. A method based on mode simulation IP module K library according to claim 3, characterized in that: The method of using the second mode to measure the delay caused by the combined timing arc and the trigger includes: The analog module of the second mode includes: a first internal clock module, a third combinational logic module, a fourth combinational logic module, a second trigger and a fifth combinational logic module; The first internal clock module is connected to the input ends of the third combinational logic module and the fourth combinational logic module; The output end of the third combinational logic module is connected to the ck end of the second trigger; The output end of the fourth combinational logic module is connected to the first clock output; The input end of the fifth combinational logic module is connected to the Q end of the second flip-flop, and the output end is connected to the output of the analog module of the second mode; Obtaining a signal output by a first internal clock; Acquire signals of the input and output terminals of the fifth combinational logic module; Get the signal output by the first clock.

5. A method based on mode simulation IP module K library according to claim 4, characterized in that: The method of measuring the delay of the combined timing arc and the delay of the setup / hold timing arc by using the third mode includes: The analog module of the third mode includes: a sixth combinational logic module, a seventh combinational logic module, an eighth combinational logic module, a second internal clock module and a third trigger; The input end of the sixth combinational logic module is connected to the second input data, and the output end is connected to the D end of the trigger; The input end of the seventh combinational logic module is connected to the internal clock module, and the output end is connected to the ck end of the trigger; The input end of the eighth combinational logic module is connected to the internal clock module, and the output end is connected to the second clock output; Acquiring signals from an input terminal and an output terminal of a sixth combinational logic module; Acquiring signals from an input terminal and an output terminal of a seventh combinational logic module; The signals of the input terminal and the output terminal of the eighth combinational logic module are obtained.

6. A system based on mode simulation IP module K library, characterized in that: include: A judgment module, used for judging the type of timing arc in the analog IP module to be detected; A selection module, used for selecting a measurement mode according to the type of the timing arc; A detection module, used for detecting the analog IP module according to the measurement mode; Generation module, used to generate timing lib files according to the detection results; The selecting of the measurement mode according to the type of the timing arc comprises: A first mode is used to measure a setup / hold timing arc; Get the delay from the analog module input data to the trigger D terminal; Get the delay from the input clock to the trigger ck end; The selecting of the measurement mode according to the type of the timing arc comprises: The second mode is used to measure the delays caused by the combined timing arcs and flip-flops; Get the delay from the internal clock to the trigger output Q; Get the delay from the trigger output Q to the analog module output; Get the delay from the internal clock to the analog module output; The selecting of the measurement mode according to the type of the timing arc comprises: The third mode is used to measure the delay of the combined timing arc and the delay of the setup / hold timing arc; Get the delay from the analog module input to the trigger ck terminal; Get the delay from the internal clock to the trigger ck end; Gets the delay from the internal clock to the output of the analog block.

7. An electronic device, characterized in that: include: A processor and a memory, wherein the memory is used to store computer program code, wherein the computer program code includes computer instructions. When the processor executes the computer instructions, the electronic device executes a method based on a mode simulation IP module K library as described in any one of claims 1 to 5.

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