10T-SRAM cell, dual-channel read and content-addressed logic circuit and chip

Abstract

The present invention belongs to the field of integrated circuit technology, and specifically relates to a 10T-SRAM cell, a dual-channel read and content-addressed logic circuit, and a chip thereof. The 10T-SRAM cell is composed of P1 to P2 and N1 to N8. P1, P2, N1 to N4 constitute a 6T memory cell, and the remaining devices constitute a configuration circuit. The gates of N5 and N6 are respectively connected to the storage nodes Q and QB in the 6T memory cell; the gates of N7 and N8 are respectively connected to the control signals SL and SR; the drain of N5 is connected to the source of N7; the source of N8 is connected to the drain of N6; the sources of N5 and N6 are connected to the transfer signal line TL, and the drains of N7 and N8 are connected to the mark signal line ML. Arranging multiple 10T-SRAM arrays and connecting the TL and ML of adjacent cells in the same row constitutes a dual-channel read and content-addressed logic circuit. The circuit of the present invention simultaneously has data storage, dual-channel data reading, and content-addressing functions; the circuit is simple yet powerful, and can overcome the efficiency and power consumption shortcomings of existing circuits.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a 10T-SRAM unit, a dual-channel read and content-addressed logic circuit designed based on the 10T-SRAM unit, and a corresponding CIM chip. Background Art

[0002] The rapid development of technologies such as artificial intelligence, edge computing, and neural networks has placed higher demands on the speed and energy efficiency of processors. Traditional processors are designed based on the von Neumann architecture. The computing unit and the storage unit are separated. The calculation is performed in the arithmetic unit, and the instructions and data are stored in the memory. When performing calculations, the computer needs to read data from the memory. After the calculation is completed, the computer needs to write the results back to the memory, which causes a large amount of data to be transmitted back and forth between the computer and the memory. This data operation method will bring the following problems: (1) Data transmission requires higher and higher bandwidth for communication between the processor and the memory, but there are obvious limitations on the bandwidth that can be achieved in terms of physical bandwidth. (2) With the continuous development of semiconductor technology, the speed of the arithmetic unit has far exceeded the read and write speed of the storage unit, resulting in the "storage wall" problem. (3) The transmission of data between the arithmetic unit and the storage unit generates a lot of power consumption. With the continuous advancement of technology, the power consumption problem has become more prominent, resulting in the "power wall" problem.

[0003] To overcome the storage and power consumption bottlenecks of the traditional von Neumann architecture, researchers have developed a new computing architecture and solution. Compute in Memory (CIM) directly utilizes memory cells for computation, integrating data and computing. This architecturally eliminates memory access operations, potentially breaking through computing power and power consumption bottlenecks. It is particularly well-suited for areas with intensive algorithmic access and rule-based operations, such as artificial intelligence and graph computing.

[0004] Currently, in-memory arithmetic circuits can be used to perform logical operations such as multiplication and MAC in data processing tasks such as artificial intelligence, edge computing, and neural networks. They can also be used for content addressing. Content addressing is an operation that can match input targets with stored content in a single search cycle. It has great applications in efficient machine learning models such as feature retrieval and distance-based in-memory computing. However, the content addressing unit design in traditional CIM circuits occupies a large area, has a single function, and has a small application range, which limits its storage density for mapping computationally intensive algorithms. Summary of the Invention

[0005] To address the common shortcomings of existing CIM circuits supporting content addressing functions, such as complex circuits, large area occupation, and high power consumption, the present invention provides a 10T-SRAM cell, a dual-channel read and content addressing logic circuit designed based on the 10T-SRAM cell, and a corresponding CIM chip.

[0006] The technical solution provided by the present invention is:

[0007] A 10T-SRAM cell with dual-channel data read and content addressing capabilities consists of two PMOS transistors P1-P2 and eight NMOS transistors N1-N8. P1, P2, and N1-N4 form a 6T storage cell, supporting data storage functions including read, write, and retain. The remaining transistors N5-N8 form a configuration circuit, which is used to query the data stored in the 6T storage cell and provide an alternative data read channel.

[0008] Among them, the circuit connection relationship of the configuration circuit is as follows:

[0009] The gates of N5 and N6 are connected to the storage nodes Q and QB in the 6T memory cell respectively; the gates of N7 and N8 are connected to the control signals SL and SR respectively; the drain of N5 is connected to the source of N7; the source of N8 is connected to the drain of N6; the sources of N5 and N6 are connected to the transfer signal line TL, and the drains of N7 and N8 are connected to the mark signal line ML.

[0010] In the solution of the present invention, the circuit connection relationship of the 6T memory cell is as follows:

[0011] The sources of P1 and P2 are connected to VDD; the gates of P2 and N2 are connected to the drains of P1 and N1 and serve as the storage node Q; the gates of P1 and N1 are connected to the drains of P2 and N2 and serve as the storage node QB; the sources of N1 and N2 are grounded; N3 serves as a transmission tube between the storage node Q and the bit line BL; N4 serves as a transmission tube between the storage node QB and the bit line BLB; the gates of N3 and N4 are connected to the word line WL.

[0012] As a further improvement of the present invention, the operation strategy of configuring the circuit to implement content addressing is as follows:

[0013] (1) Pre-store the content to be searched in the 6T storage unit:

[0014] When Q is high and QB is low, it means the stored data is "1". When Q is low and QB is high, it means the stored data is "0".

[0015] (2) Set SL and SR to high level, and then precharge the transfer signal line TL and the mark signal line ML to high level.

[0016] (3) After TL and ML are precharged, the coded query number is input through the control signals SL and SR:

[0017] When SL is high and SR is low, it indicates that the query number is "1". When SL is low and SR is high, it indicates that the query number is "0".

[0018] (4) The transfer signal line TL is grounded, and the result of content addressing is determined according to the level change of the mark signal line ML:

[0019] If ML drops to a low level, the query number is the same as the stored data. If ML remains high, the query number is different from the stored data.

[0020] As a further improvement of the present invention, the 6T memory cell includes a channel 1 for reading data using the bit lines BL and BL, and the configuration circuit includes a channel 2 for reading data using the transfer signal line TL and the mark signal line ML;

[0021] The 10T-SRAM cell provided by the present invention allows data stored in the 6T memory cell to be read through channel 1 when performing a content addressing operation.

[0022] As a further improvement of the present invention, there are two strategies for implementing data reading in channel 1, one of which is as follows:

[0023] Precharge the bit lines BL and BLB to a high level, and then turn on the word line WL; the stored data is reflected in the level states of the bit lines BL and BLB:

[0024] If BL remains high and BLB drops to low, it means the stored data is "1". If BL drops to low and BLB remains high, it means the stored data is "0".

[0025] As a further improvement of the present invention, the strategy for implementing data reading in channel 2 is as follows:

[0026] After SL and SR are set to high level, the transfer signal line TL and the mark signal line ML are precharged to high level.

[0027] After the precharge is completed, SL is set to a high level and SR is set to a low level.

[0028] When the transfer signal line TL is discharged to a low level, the stored data is reflected in the voltage state of the mark signal line ML:

[0029] If ML remains high, it means the stored data is "0"; if ML drops to a low level, it means the stored data is "1".

[0030] In the present invention, another strategy for implementing data reading in channel 2 is as follows:

[0031] After SL and SR are set to high level, the transfer signal line TL and the mark signal line ML are precharged to high level.

[0032] After the precharge is completed, SL is set to low level and SR is set to high level.

[0033] When the transfer signal line TL is discharged to a low level, the stored data is reflected in the voltage state of the mark signal line ML:

[0034] If ML remains high, it means the stored data is "1"; if ML drops to a low level, it means the stored data is "0".

[0035] The present invention also includes a dual-channel read and content-addressed logic circuit, which is formed by arranging a plurality of 10T-SRAM cell arrays as described above.

[0036] Each 10T-SRAM cell in a row shares the same word line WL. The ML end of each 10T-SRAM cell in each row is connected to the TL end of the adjacent 10T-SRAM cell on the right. The transfer signal line TL of the leftmost 10T-SRAM cell serves as an independent port, while the flag signal line ML of the rightmost 10T-SRAM cell serves as an independent port.

[0037] The 10T-SRAM cells in the same column share the same set of bit lines BL, BLB and signal lines corresponding to control signals SL and SR.

[0038] N 10T-SRAM units in the same row of the dual-channel read and content-addressed logic circuit provided by the present invention together constitute a basic unit for implementing N-bit data content addressing.

[0039] As a further improvement of the present invention, the operation strategy of the dual-channel read and content addressing logic circuit to implement multi-bit content addressing is as follows:

[0040] (1) The multi-bit number to be searched is pre-stored bit by bit in each 10T-SRAM cell in the same row through the bit lines BL and BLB.

[0041] (2) The SL and SR corresponding to each 10T-SRAM cell are set to a high level, and then the transfer signal line TL and the mark signal line ML are precharged to a high level.

[0042] (3) After TL and ML precharge is completed, the query number is input bit by bit into each 10T-SRAM unit in the same row through the control signals SL and SR.

[0043] (4) The transfer signal line TL is grounded, and the result of content addressing is determined according to the level change of the mark signal line ML:

[0044] If ML drops to a low level, it indicates that the query number is the same as the stored data; if ML remains at a high level, it indicates that the query number is different from the stored data.

[0045] The present invention also includes a CIM chip, which includes an SRAM array and peripheral circuits that cooperate with the SRAM array to implement data storage and content addressing functions. The SRAM array uses the aforementioned dual-channel read and content addressing logic circuit.

[0046] The technical solution provided by the present invention has the following beneficial effects:

[0047] The present invention designs a novel 10T-SRAM cell and, based on it, designs an in-memory arithmetic circuit capable of dual-channel data reading and content addressing operations. The CIM circuit provided by the present invention not only implements basic read and write functions but also has two channels for reading data that do not interfere with each other. The data reading path provided by the configuration circuit can effectively overcome the problem of read corruption.

[0048] The circuit structure of the present invention is simple, but can realize complex multi-bit content addressing functions, and can achieve matching of multiple multi-bit data within one cycle, with high query efficiency and can significantly reduce the dynamic power consumption of the circuit.

[0049] The circuit provided by the present invention provides dual functions, which can not only realize the read and write operations of the storage unit, but also realize the addressing function of the storage unit content. Moreover, while performing content addressing, the storage content can be read using channel 1, so the application scenarios are more extensive.

[0050] The circuit design of the present invention simplifies the calculation process, can effectively improve the operation efficiency and speed, reduce the energy consumed in the transmission process, and optimize the area of ​​the circuit and chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 This is a circuit diagram of the 10T-SRAM unit provided in Example 1 of the present invention.

[0052] Figure 2 Schematic diagram of the circuit that performs the task of matching the query number "1" with the stored data "1" for a 10T-SRAM cell.

[0053] Figure 3 Schematic diagram of the circuit that performs the task of matching the query number "1" with the stored data "0" for a 10T-SRAM cell.

[0054] Figure 4Schematic diagram of the circuit that performs the task of matching the query number "0" with the stored data "1" for a 10T-SRAM cell.

[0055] Figure 5 Schematic diagram of the circuit that performs the task of matching the query number "0" with the stored data "0" for a 10T-SRAM cell.

[0056] Figure 6 This is a circuit diagram of a dual-channel read and content-addressed logic circuit provided in embodiment 2 of the present invention.

[0057] Figure 7 Schematic diagram of the dual-channel read and content-addressable logic circuit performing the content-addressing task of a 5-bit number.

[0058] Figure 8 This is a schematic diagram of the principle structure of the CIM circuit provided in Example 3 of the present invention. DETAILED DESCRIPTION

[0059] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0060] Example 1

[0061] This embodiment provides a 10T-SRAM cell, which has dual-channel data reading and content addressing functions, such as Figure 1 As shown, the 10T-SRAM cell consists of two PMOS transistors P1-P2 and eight NMOS transistors N1-N8. P1, P2, and N1-N4 form a 6T storage cell, supporting data storage functions including read, write, and retain. The remaining transistors N5-N8 form the configuration circuit, which is used to query the data stored in the 6T storage cell and provide an alternative data read channel.

[0062] The circuit connection relationship of the 6T memory cell is as follows:

[0063] The sources of P1 and P2 are connected to VDD; the gates of P2 and N2 are connected to the drains of P1 and N1 and serve as the storage node Q; the gates of P1 and N1 are connected to the drains of P2 and N2 and serve as the storage node QB; the sources of N1 and N2 are grounded; N3 serves as a transmission tube between the storage node Q and the bit line BL; N4 serves as a transmission tube between the storage node QB and the bit line BLB; the gates of N3 and N4 are connected to the word line WL.

[0064] The circuit connection relationship of the configuration circuit is as follows:

[0065] The gates of N5 and N6 are connected to the storage nodes Q and QB in the 6T memory cell respectively; the gates of N7 and N8 are connected to the control signals SL and SR respectively; the drain of N5 is connected to the source of N7; the source of N8 is connected to the drain of N6; the sources of N5 and N6 are connected to the transfer signal line TL, and the drains of N7 and N8 are connected to the mark signal line ML.

[0066] In the solution of this embodiment, the strategy for implementing data writing in the 6T storage unit is:

[0067] In the initial state, WL is at a low level; at this time, the bit lines BL and BLB are set according to the data to be written: when the data to be written is "1", BL is set to a high level and BLB is set to a low level; when the data to be written is "0", BL is set to a low level and BLB is set to a high level.

[0068] Next, WL is set to a high level, turning on pass transistors N3 and N4. At this point, charge is shared between the storage node and the corresponding bit line. When the data to be written is "1", the bit line BL pair charges the storage node Q, pulling Q to a high level. The storage node QB is discharged through the bit line BLB, pulling QB to a low level, thereby implementing the write operation of the data "1". When the data to be written is "0", the bit line BLB pair charges the storage node QB, pulling QB to a high level. The storage node Q is discharged through the bit line BL, pulling Q to a low level, thereby implementing the write operation of the data "0".

[0069] After the data is written, WL is set to a low level, and the transmission tubes N3 and N4 are turned off. At this time, the circuit is in a holding state, and the latch structure composed of P1, P2, N1, and N2 can stably hold the written data.

[0070] In the solution of this embodiment, the 6T memory cell includes a channel 1 for reading data using the bit lines BL and BL. The strategy for the 6T memory cell to implement data reading using the channel 1 is:

[0071] Precharge the bit lines BL and BLB to a high level, and then turn on the word line WL; the stored data is reflected in the level states of the bit lines BL and BLB:

[0072] Specifically, when the data stored in the 6T memory cell is "1", Q is at a high level and QB is at a low level; at this time, the storage node Q has the same potential as the directly connected bit line BL, and BL still maintains a high level; while the potential of the storage node QB is lower than that of the bit line BLB, so the charge sharing between the two causes the bit line BLB to drop to a low level.

[0073] On the contrary, when the data stored in the 6T memory cell is "0", Q is at a low level and QB is at a high level; at this time, the potential of the storage node QB is the same as that of the directly connected bit line BLB, and BLB still maintains a high level; and the potential of the storage node Q is lower than that of the bit line BL, so the charge sharing between the two causes the bit line BL to drop to a low level.

[0074] In summary: During the data reading phase, if BL remains high and BLB drops to a low level, it indicates that the stored data is "1". If BL drops to a low level and BLB remains high, it indicates that the stored data is "0".

[0075] In the 10T-SRAM cell provided in this embodiment, content addressing can be implemented by configuring the circuit portion, that is, querying whether the data stored in the storage cell is the same as the specified data. Specifically, the operation strategy for implementing content addressing in the 10T-SRAM cell of this embodiment is as follows:

[0076] (1) Based on the data storage function of the 6T storage unit, the content to be searched is pre-stored in the 6T storage unit:

[0077] In each 6T memory cell, when Q is high and QB is low, it indicates that the stored data is "1". When Q is low and QB is high, it indicates that the stored data is "0".

[0078] (2) Set SL and SR to high level, and then precharge the transfer signal line TL and the mark signal line ML to high level.

[0079] (3) After TL and ML are precharged, the coded query number is input through the control signals SL and SR:

[0080] When SL is high and SR is low, it indicates that the query number input is "1". When SL is low and SR is high, it indicates that the query number input is "0".

[0081] (4) The transfer signal line TL is grounded, and the result of content addressing is determined according to the level change of the mark signal line ML:

[0082] If ML drops to a low level, the query number is the same as the stored data. If ML remains high, the query number is different from the stored data.

[0083] The following describes in detail the process and principle of implementing content addressing in the 10T-SRAM cell provided in this embodiment, with respect to different query numbers and storage data situations:

[0084] Specifically, such as Figure 2As shown in the figure, when the query number is "1" and the stored data is "1", Q in the 6T memory cell is high and QB is low; SL in the configuration circuit is high and SR is low. At this point, N5 is on, N6 is off, N7 is on, and N8 is off. In this state, a discharge path is formed between TL and ML through N5 and N7, and ML eventually drops to a low level, indicating that the query number and stored data successfully match.

[0085] like Figure 3 As shown in the figure, when the query number is "1" and the target number is "0," Q in the 6T memory cell is high and QB is low. SL in the configuration circuit is low and SR is high. At this point, N5 is on, N6 is off, N7 is off, and N8 is on. In this state, no discharge path can be formed between TL and ML, and ML remains high, indicating a mismatch between the query number and the stored data.

[0086] like Figure 4 As shown in the figure, when the query number is "0" and the target number is "1," Q in the 6T memory cell is low and QB is high. SL in the configuration circuit is high and SR is low. At this point, N5 is off, N6 is on, N7 is on, and N8 is off. In this state, no discharge path can be formed between TL and ML, and ML remains high, indicating a mismatch between the query number and the stored data.

[0087] like Figure 5 As shown in the figure, when the query number is "0" and the target number is "0," Q in the 6T memory cell is low and QB is high. SL in the configuration circuit is low and SR is high. At this point, N5 is off, N6 is on, N7 is off, and N8 is on. In this state, a discharge path is formed between TL and ML through N6 and N8, and ML eventually drops to a low level, indicating a successful match between the query number and the stored data.

[0088] The truth table corresponding to the above data matching process is shown in the following table:

[0089] Table 1: Truth table for content-addressed operations in a 10T-SRAM cell

[0090]

[0091] In summary, in the configuration circuit of the 10T-SRAM cell designed in this embodiment, if the query number and stored data are the same, ML and TL will be directly connected, forming a discharge path. If the query number and stored data are different, ML and TL will be disconnected, and thus no discharge path will be formed. The existence of a connected path ultimately affects the final level state of ML. Therefore, the change in the ML level state can be used to determine whether the query number and stored data match successfully, thereby completing the content addressing task.

[0092] It should be noted that in the 10T-SRAM cell of this embodiment, data reading and content addressing operations are performed by different objects, and the operation of the configuration circuit does not affect the data stored in the 6T memory cell. Therefore, the circuit supports reading data stored in the 6T memory cell through channel 1 while performing content addressing operations. This helps improve the circuit's operational efficiency in certain computing tasks.

[0093] In addition, technicians can also use the configuration circuit in the 10-SRAM of this embodiment to implement data reading. The principle of this circuit performing such data reading operations is: in the data reading stage, the query number is fixed to "1" or "0", and then the matching result of the stored data and the query number is quantized, and the quantized result is used as the result of the data reading. For example, when the query number is fixed to "1", if the stored data successfully matches the query number, it means that the stored data read is "1", and if the stored data fails to match the query number, it means that the stored data read is "0". Conversely, when the query number is fixed to "0", if the stored data successfully matches the query number, it means that the stored data read is "0", and if the stored data fails to match the query number, it means that the stored data read is "1". That is, the configuration circuit in the 10-SRAM provides a second channel for implementing a read operation on the data stored in the 6T memory cell.

[0094] In detail, the data reading strategy of channel 2 in this embodiment is as follows:

[0095] After SL and SR are set to high level, the transfer signal line TL and the mark signal line ML are precharged to high level.

[0096] After the precharge is completed, SL is set to a high level and SR is set to a low level.

[0097] When the transfer signal line TL is discharged to a low level, the stored data is reflected in the voltage state of the mark signal line ML:

[0098] If ML remains high, it means the stored data is "0"; if ML drops to a low level, it means the stored data is "1".

[0099] Alternatively, the data reading strategy for channel 2 is as follows:

[0100] After SL and SR are set to high level, the transfer signal line TL and the mark signal line ML are precharged to high level.

[0101] After the precharge is completed, SL is set to low level and SR is set to high level.

[0102] When the transfer signal line TL is discharged to a low level, the stored data is reflected in the voltage state of the mark signal line ML:

[0103] If ML remains high, it means the stored data is "1"; if ML drops to a low level, it means the stored data is "0".

[0104] Of the two strategies described above for performing data read operations using channel two, the quantization logic of the first strategy is identical to that of channel one, and thus can be implemented using the same ADC circuit. Therefore, this quantization logic is relatively superior. Considering that the configuration circuit does not affect the data stored in the storage unit, the data read operations of channel two and channel one provided in this embodiment do not conflict with each other and can be performed in parallel.

[0105] Example 2

[0106] Based on the solution of Example 1, this embodiment further provides a dual-channel read and content-addressed logic circuit, which is composed of a plurality of 10T-SRAM cell arrays as in Example 1.

[0107] Among them, such as Figure 6 As shown, each 10T-SRAM cell in the same row shares the same word line WL. The ML end of each 10T-SRAM cell in each row is connected to the TL end of the adjacent 10T-SRAM cell on the right. The transfer signal line TL of the leftmost 10T-SRAM cell serves as an independent port, and the flag signal line ML of the rightmost 10T-SRAM cell serves as an independent port.

[0108] The 10T-SRAM cells in the same column share the same set of bit lines BL, BLB and signal lines corresponding to control signals SL and SR.

[0109] In combination with the solution of Example 1, it can be seen that each 10T-SRAM unit can achieve a numerical match between a single-bit query number and a single-bit stored data. If the match is successful, TL and ML are connected; if the match fails, TL and ML cannot be connected. Figure 6 With this circuit design, after the ML and TL of adjacent 10T-SRAM cells in the same row are directly connected, if the corresponding two single-bit numbers in each 10T-SRAM cell in the same row are successfully matched, the TL end of the first 10T-SRAM cell in the row can be connected to the ML end of the last 10T-SRAM cell. If the corresponding two single-bit numbers in any 10T-SRAM cell in the same row fail to match, the TL end of the first 10T-SRAM cell in the row cannot be connected to the ML end of the last 10T-SRAM cell.

[0110] Based on the above circuit characteristics, the N 10T-SRAM cells in the same row of the dual-channel read and content-addressed logic circuit provided in this embodiment together constitute a basic unit for implementing N-bit data content addressing.

[0111] When the circuit implements multi-bit content addressing operations, it only needs to input the storage data bit by bit into the 6T storage cell part of each 10T-SRAM unit in the same row, and then input the query number bit by bit into the configuration circuit of each 10T-SRAM unit;

[0112] In detail, the dual-channel read and content addressing logic circuit provided in this embodiment implements the following operation strategy for multi-bit content addressing:

[0113] (1) The multi-bit number to be searched is pre-stored bit by bit in each 10T-SRAM cell in the same row through the bit lines BL and BLB.

[0114] For example, if the pre-stored data in the four 10T-SRAM cells in a row are A1, A2, A3, and A4, respectively, they can be used to represent a 4-bit number. Assuming the stored data is input in order from high to low bits, the pre-stored 4-bit number is "A1A2A3A4".

[0115] (2) The SL and SR corresponding to each 10T-SRAM cell are set to a high level, and then the transfer signal line TL and the mark signal line ML are precharged to a high level.

[0116] (3) After TL and ML precharge is completed, the query number is input bit by bit into each 10T-SRAM unit in the same row through the control signals SL and SR.

[0117] Assuming a 4-bit query number is "B1B2B3B4," it should be decomposed bit by bit into B1, B2, B3, and B4. These four single-bit numbers are then input into the 10T-SRAM cells in the corresponding row in order of bit weight. Specifically, B1 is input into the 10T-SRAM cell corresponding to A1, B2 into the 10T-SRAM cell corresponding to A2, and so on.

[0118] (4) The transfer signal line TL is grounded, and the result of content addressing is determined based on the level change of the mark signal line ML.

[0119] According to the aforementioned circuit principle, if the query number and the stored result are exactly the same, the TL and ML terminals of all 10T-SRAM cells will be connected, forming a discharge path. The ML level will drop, indicating that the two multi-bit numbers match successfully. However, if any bit in the query number and the target number differs, the 10T-SRAM cell at the corresponding bit will fail to match and become disconnected. This will cause the TL and ML terminals to lose connectivity, preventing the discharge path from forming. The ML terminal will remain high, indicating that the two multi-bit numbers have failed to match.

[0120] That is, if ML drops to a low level, it indicates that the query number is the same as the stored data; if ML remains at a high level, it indicates that the query number is different from the stored data.

[0121] Specifically, Figure 7 The figure shows a typical 5-bit content addressing process. The content addressing query number is "11011" from MSB to LSB. The first row of the array stores "11010" and the second row stores "11011".

[0122] Before the content addressing operation, the transmission tubes between the cell columns are first turned on, that is, SL1~SL5 and SR1~SR5 in the configuration circuit are all set to VDD; then ML1 and ML2 in the configuration circuit are precharged to VDD, and TL1 and TL2 are also precharged to VDD.

[0123] When a content-addressed operation begins, the signal lines for each column in the configuration block are set as follows:

[0124] SL1=1, SR1=0, SL2=1, SR2=0, SL3=0, SR3=1, SL4=1, SR4=0, SL5=1, SR5=0;

[0125] Then, TL1 and TL2 in the configuration circuit are discharged to VSS. At this point, in the first row of cells, the stored contents of the cells in columns 1 through 4 match the target value, so the transfer signal TL5 of the cells in column 5 is discharged to VSS. However, because the stored data in the cells in column 5 do not match the query number, no discharge path can be formed. Therefore, the result of flag signal ML1 remains at VDD, indicating a data match failure. In the second row of cells, the stored data in columns 1 through 5 all match the query number, and flag signal ML2 is discharged to VSS through columns 1 through 5, indicating a successful data match.

[0126] Example 3

[0127] Based on the solution of embodiment 2, this embodiment further provides a CIM chip, such as Figure 8As shown, it includes an SRAM array and peripheral circuits that cooperate with the SRAM array to implement data storage functions and content addressing functions. The SRAM array adopts the dual-channel read and content addressing logic circuit as in Example 2. Each SRAM cell in the CIM of this embodiment can implement complete data read, write, and hold operations, and the CIM circuit provides two independent data read channels for each SRAM cell. In addition, the CIM circuit can also implement single-bit or multi-bit content addressing; wherein, each SRAM cell serves as the execution object of the single-bit content addressing operation, and multiple SRAM cells in the SRAM array together constitute the execution object of the multi-bit content addressing operation.

[0128] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0129] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A 10T-SRAM cell having dual-channel data reading and content addressing functions, characterized in that: It consists of two PMOS transistors P1-P2 and eight NMOS transistors N1-N8. Among them, P1, P2, and N1-N4 form a 6T storage unit and support data storage functions including data reading, writing, and retention. The remaining N5-N8 form a configuration circuit, which is used to query the content of the data stored in the 6T storage unit and provide another data reading channel. The circuit connection relationship of the configuration circuit is as follows: The gates of N5 and N6 are connected to the storage nodes Q and QB in the 6T memory cell respectively; the gates of N7 and N8 are connected to the control signals SL and SR respectively; the drain of N5 is connected to the source of N7; the source of N8 is connected to the drain of N6; the sources of N5 and N6 are connected to the transfer signal line TL, and the drains of N7 and N8 are connected to the mark signal line ML.

2. The 10T-SRAM cell according to claim 1, wherein: The circuit connection relationship of the 6T memory cell is as follows: The sources of P1 and P2 are connected to VDD; the gates of P2 and N2 are connected to the drains of P1 and N1 and serve as the storage node Q; the gates of P1 and N1 are connected to the drains of P2 and N2 and serve as the storage node QB; the sources of N1 and N2 are grounded; N3 serves as a transmission tube between the storage node Q and the bit line BL; N4 serves as a transmission tube between the storage node QB and the bit line BLB; the gates of N3 and N4 are connected to the word line WL.

3. The 10T-SRAM cell according to claim 2, wherein: The configuration circuit implements the content addressing operation strategy as follows: (1) Pre-store the content to be searched in the 6T storage unit; When Q is high and QB is low, it means the stored data is "1"; when Q is low and QB is high, it means the stored data is "0"; (2) Set SL and SR to high level, and then precharge the transfer signal line TL and the mark signal line ML to high level; (3) After TL and ML are precharged, the coded query number is input through the control signals SL and SR: When SL is high and SR is low, it means the query number is "1"; when SL is low and SR is high, it means the query number is "0"; (4) The transfer signal line TL is grounded, and the result of content addressing is determined according to the level change of the mark signal line ML: If ML drops to a low level, it indicates that the query number is the same as the stored data; if ML remains at a high level, it indicates that the query number is different from the stored data.

4. The 10T-SRAM cell according to claim 3, wherein: The 6T memory cell includes a channel 1 for reading data using the bit lines BL and BL, and the configuration circuit includes a channel 2 for reading data using the transfer signal line TL and the mark signal line ML; The 10T-SRAM cell allows data stored in the 6T memory cell to be read through channel one when performing a content addressing operation.

5. The 10T-SRAM cell according to claim 4, wherein: The data reading strategy for channel 1 is as follows: Precharge the bit lines BL and BLB to a high level, and then turn on the word line WL; the stored data is reflected in the level states of the bit lines BL and BLB: If BL remains at a high level and BLB drops to a low level, it means that the stored data is "1"; if BL drops to a low level and BLB remains at a high level, it means that the stored data is "0".

6. The 10T-SRAM cell according to claim 4, wherein: The data reading strategy for channel 2 is as follows: After SL and SR are set to high level, the transfer signal line TL and the mark signal line ML are precharged to high level; After the precharge is completed, SL is set to high level and SR is set to low level; When the transfer signal line TL is discharged to a low level, the stored data is reflected in the voltage state of the mark signal line ML: If ML remains high, it means the stored data is "0"; if ML drops to a low level, it means the stored data is "1".

7. The 10T-SRAM cell according to claim 4, wherein: The data reading strategy for channel 2 is as follows: After setting SL and SR to high level, both the transfer signal line TL and the mark signal line ML are precharged to high level; After the precharge is completed, SL is set to low level and SR is set to high level; When the transfer signal line TL is discharged to a low level, the stored data is reflected in the voltage state of the mark signal line ML: If ML remains high, it means the stored data is "1"; if ML drops to low, it means the stored data is "0".

8. A dual-channel read and content-addressed logic circuit, characterized in that: It is composed of a plurality of 10T-SRAM cell arrays as described in any one of claims 1 to 7; Among them, each 10T-SRAM cell in the same row shares the same word line WL; the ML end of each 10T-SRAM cell in each row is connected to the TL end of the adjacent 10T-SRAM cell on the right; and the transfer signal line TL of the leftmost 10T-SRAM cell serves as an independent port, and the flag signal line ML of the rightmost 10T-SRAM cell serves as an independent port; Each 10T-SRAM cell in the same column shares the same set of bit lines BL, BLB and control signals SL and SR; The N 10T-SRAM cells in the same row of the dual-channel read and content-addressed logic circuit together constitute a basic unit for implementing N-bit data content addressing.

9. The dual-channel read and content-addressed logic circuit according to claim 8, wherein: The dual-channel read and content addressing logic circuit implements the following operation strategy for multi-bit content addressing: (1) The multi-bit number to be searched is pre-stored bit by bit in each 10T-SRAM cell in the same row through the bit lines BL and BLB; (2) Set the SL and SR corresponding to each 10T-SRAM cell to a high level, and then precharge the transfer signal line TL and the mark signal line ML to a high level; (3) After TL and ML precharge is completed, the query number is input bit by bit into each 10T-SRAM cell in the same row through the control signals SL and SR; (4) The transfer signal line TL is grounded, and the result of content addressing is determined according to the level change of the mark signal line ML: If ML drops to a low level, it indicates that the query number is the same as the stored data; if ML remains at a high level, it indicates that the query number is different from the stored data.

10. A CIM chip, characterized in that: It includes an SRAM array and a peripheral circuit that cooperates with the SRAM array to realize data storage function and content addressing function; the SRAM array adopts the dual-channel reading and content addressing logic circuit as described in claim 8 or 9.

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