Power module with three-level circuit topological structure

Abstract

The invention relates to the technical field of semiconductors, in particular to a power module with a three-level circuit topological structure, which comprises an insulating plate, a metal layer, metal pins and a power chip, according to the design that the three-level circuit topology main power loop is folded in half and arranged next to each other, the parasitic inductance of the module power main loop is greatly reduced; when the power module adopting the silicon-based chip and the silicon carbide-based chip in a mixed mode is used in cooperation with a matched control strategy, the working efficiency of the power module can be greatly improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power module with a three-level circuit topology structure. Background Art

[0002] High power, high frequency and high speed switching are an important development trend of power modules. Compared with two-level circuit topology, the power chip in three-level circuit topology has advantages such as low voltage stress, small voltage change rate and higher output power. The use of multi-level circuit topology is one of the effective means for power modules to achieve high efficiency and high power performance advantages.

[0003] The commonly used multi-level circuit topology is mainly the three-level circuit topology, which includes T-type three-level and I-type three-level circuit topologies, among which the I-type three-level circuit topology includes the diode neutral point clamped topology (NPC, Neutral Point Clamped) and the active neutral point clamped topology (ANPC, Active Neutral Point Clamped). The NPC three-level topology uses multiple capacitors on the neutral point to achieve multiple output voltage levels by using passive diodes to clamp the neutral point at a predefined voltage level. Since the device voltage stress is low, the switching loss is small; since no high-voltage power chip is required, its cost is relatively low; however, compared with the ANPC topology module, the NPC three-level module has higher conduction loss, the clamping diode is subjected to reverse recovery voltage, there is reverse recovery loss, and the DC bus capacitor charging and discharging is unbalanced. Usually an additional DC power supply is required to maintain the neutral point voltage.

[0004] The ANPC three-level topology uses active switches to clamp the neutral point voltage instead of relying on capacitors or passive diodes. The ANPC topology can also achieve multiple output voltage levels by dynamically adjusting the neutral point voltage, thereby improving the flexibility of the level output and optimizing the control performance. Due to the use of additional switches to control or clamp the neutral point voltage, the ANPC circuit topology power module usually has higher switching losses and better dynamic response.

[0005] Compared with silicon IGBT chips, silicon carbide MOSFET chips have high switching frequency and low switching loss. However, if the ANPC three-level topology power module adopts silicon carbide chips, the module cost will increase significantly. How to build a low-cost, high-efficiency, high-power module is the main technical problem that must be faced. Summary of the invention

[0006] In view of this, the purpose of the present invention is to propose a power module with a three-level circuit topology structure to solve the technical problem of building a low-cost, high-efficiency, and high-power module.

[0007] Based on the above objectives, the present invention provides a power module with a three-level circuit topology structure, comprising: An insulating plate, comprising a first insulating plate and a second insulating plate, wherein the second insulating plate and the first insulating plate are arranged side by side on the same plane along the X direction; A metal layer, located on the upper surface of the insulating plate, including a patterned metal layer area, for realizing the circuit topology of the power module, wherein the metal layers on the first insulating plate and the second insulating plate are electrically connected via a metal layer connecting bridge; Metal pins, including a "DC+" pin for inputting a positive DC bus, a "DC-" pin for inputting a negative DC bus, an "AC" pin for outputting an alternating current, and an "M" pin for midpoint potential clamping, wherein the metal pins are arranged on the metal layer; A power chip, wherein the power chip is arranged on the metal layer and electrically connected to the metal layer; The insulating plate, the metal layer, the metal pins and the power chip are connected to form a circuit topology structure of the power module. The circuit topology structure is a three-level topology structure with active neutral point clamping. The three-level topology structure includes a main bridge arm and a clamping bridge arm. The main bridge arm includes a first group, a second group, a third group and a fourth group of power chips connected in series in sequence. The four groups of power chips all include a silicon IGBT chip and a freewheeling diode chip connected in anti-parallel therewith. The clamping bridge arm includes a fifth group of power chips and a sixth group of power chips connected in series therewith. The fifth group of power chips and the sixth group of power chips all include silicon carbide MOSFET chips connected in parallel. The drain of the silicon carbide MOSFET chip in the fifth group of power chips is connected to the emitter of the silicon IGBT chip in the first group of power chips and the collector of the silicon IGBT chip in the second group of power chips. The source of the silicon carbide MOSFET chip in the sixth group of power chips is connected to the emitter of the silicon IGBT chip in the third group of power chips and the collector of the silicon IGBT chip in the fourth group of power chips.

[0008] Preferably, the "DC+" pin and the "DC-" pin of the main bridge arm are arranged on the metal layer area on the right edge of the first insulating board along the Y direction, the "M" pin for neutral point clamping of the clamping bridge arm is arranged on the metal layer area on the left edge of the second insulating board, a part of the "AC" pin for the main bridge arm outputting alternating current is arranged on the metal layer area on the left edge of the first insulating board and the other part is arranged on the metal layer area on the right edge of the second insulating board, and the two parts of the "AC" pin are symmetrically distributed on both sides of the center line of the module parallel to the Y direction.

[0009] Preferably, the "DC+" pin, the "DC-" pin, the first group of power chips, the fourth group of power chips, the freewheeling diode chips in the second group of power chips, the freewheeling diode chips in the third group of power chips and a part of the "AC" pins are arranged on the metal layer on the upper surface of the first insulating board, and the fifth group of power chips, the sixth group of power chips and the silicon IGBT chips in the second group of power chips, the silicon IGBT chips in the third group of power chips, the "M" pin and another part of the "AC" pins are arranged on the metal layer on the upper surface of the second insulating board.

[0010] Preferably, the metal layer area of ​​the silicon IGBT chips in the second group of power chips and the metal layer area of ​​the freewheeling diode chips in the second group of power chips are electrically connected through the metal layer connecting bridge, and the metal layer area of ​​the silicon IGBT chips in the third group of power chips and the metal layer area of ​​the freewheeling diode chips in the third group of power chips are also electrically connected through the metal layer connecting bridge.

[0011] Preferably, the metal layer area for layout of the first group of power chips and the metal layer area for layout of the fourth group of power chips are located on the upper surface of the right half area of ​​the first insulating plate, and are separated by the metal layer area for layout of the "DC-" pin, the metal layer area for layout of the freewheeling diode chips in the second group of power chips and the metal layer area for layout of the freewheeling diode chips in the third group of power chips are located on the upper surface of the left half area of ​​the first insulating plate and are adjacent to each other, and the gate bar metal layer area and the emitter bar metal layer area corresponding to the gate and emitter of the fourth group of power chips are arranged along the X direction and are arranged on the left side of the metal layer area for layout of the "DC-" pin.

[0012] Preferably, the metal layer area for layout of the fifth group of power chips and the metal layer area for layout of the silicon IGBT chips in the second group of power chips are a single connected area and are located on the upper surface of the upper half area of ​​the second insulating plate, the metal layer area for layout of the silicon IGBT chips in the third group of power chips and the metal layer area for layout of the sixth group of power chips are arranged in a direction opposite to the X direction and are located in the lower half area of ​​the second insulating plate, the metal layer area corresponding to the source of the silicon carbide MOSFET chip in the sixth group of power chips and the metal layer area corresponding to the emitter of the silicon IGBT chip in the third group of power chips are a first single connected area, and the pattern of the first single connected area is "L" shaped and is nested between the metal layer area for layout of the silicon IGBT chips in the third group of power chips and the metal layer area for layout of the sixth group of power chips.

[0013] Preferably, the metal layer area corresponding to the anode of the freewheeling diode in the third group of power chips and the metal layer area where the fourth group of power chips are arranged are the second single connected area, and the second single connected area is "L"-shaped and is arranged along the Y direction next to the metal layer area where the freewheeling diode chips in the third group of power chips are arranged; the first single connected area and the second single connected area are symmetrically distributed on both sides of the module center line parallel to the Y direction, and are electrically connected to each other through the metal layer connecting bridge.

[0014] Preferably, the metal layer area for layout of the sixth group of power chips, the metal layer area for layout of the "M" pins, and the metal layer area corresponding to the source of the silicon carbide MOSFET chip in the fifth group of power chips are the third single connected area, and the third single connected area is "T" shaped and is located on the left half area of ​​the second insulating plate.

[0015] Preferably, the gate strip metal layer region corresponding to the gate of the silicon carbide MOSFET chip in the fifth group of power chips and the source strip metal layer region corresponding to the source are both parallel to the X direction of the power module and located in the upper side region of the second insulating plate, and the gate strip metal layer region corresponding to the gate of the silicon carbide MOSFET chip in the sixth group of power chips and the source strip metal layer region corresponding to the source are both parallel to the Y direction of the power module and located in the lower left side region of the second insulating plate.

[0016] Preferably, the emitter strip metal layer area and the gate strip metal layer area corresponding to the emitter and gate of the silicon IGBT chip in the first group of power chips are located in the upper side area of ​​the first insulating plate, the emitter strip metal layer area and the gate strip metal layer area corresponding to the emitter and gate of the silicon IGBT chip in the second group of power chips are located in the upper side area of ​​the second insulating plate, and the thermistor is located on the upper side area of ​​the first insulating plate between the two upper side areas.

[0017] The beneficial effects of the present invention are as follows: in order to address the problems of excessively high voltage spikes caused by large parasitic inductance of the module during module switching, which affect the working safety of the inverter, and large losses and low working efficiency of the all-silicon IGBT power module during operation, the voltage spikes are reduced and the working efficiency of the inverter is improved by folding the main power circuit of the power module in half and laying them out closely, and by mixing silicon-based and silicon carbide-based power chips. The power module can be used in high-speed switching and high-frequency fields, and has significant practical value in high-power applications such as new energy and industrial frequency conversion that have high power density requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only for the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 is a schematic diagram of the overall structure of a power module according to an embodiment of the present invention; Figure 2 A schematic diagram of a circuit topology structure of a power module according to an embodiment of the present invention; Figure 3 Schematic diagram of the projection structure of the power module of an embodiment of the present invention on the XY plane; Figure 4 FIG. 4 is a schematic diagram of a design of a patterned metal layer of a power module according to an embodiment of the present invention. DETAILED DESCRIPTION

[0020] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments.

[0021] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and understandable, the specific implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the embodiments of the present disclosure. However, the embodiments of the present disclosure can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the embodiments of the present disclosure, so the embodiments of the present disclosure are not limited by the specific examples of the embodiments disclosed below.

[0022] In the description of the embodiments of the present disclosure, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "perpendicular", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present disclosure and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the embodiments of the present disclosure.

[0023] In the embodiments of the present disclosure, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0024] In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. Exemplarily, the first silicon carbide MOSFET chip may be referred to as the second silicon carbide MOSFET chip, and the second silicon carbide MOSFET chip may also be referred to as the first silicon carbide MOSFET chip. In the description of the embodiments of the present disclosure, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0025] In the embodiments of the present disclosure, unless otherwise clearly specified and limited, the terms "connected", "connected", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integrated connection; it can be a flexible connection, or a rigid connection along at least one direction; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or directly connected with the presence of an intermediate medium, or it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly limited. The terms "installed", "set", "fixed", etc. can be broadly understood as connection. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0026] As used herein, the terms "layer" and "region" refer to a portion of a material including a region having a certain thickness. A layer can extend horizontally, vertically and / or along a tapered surface. A layer can be a region of a uniform or non-uniform continuous structure, and its thickness perpendicular to the extension direction may not be greater than the thickness of the continuous structure. A layer can include multiple layers. The shapes of various regions, zones, and layers in the accompanying drawings and their relative sizes and positional relationships are only exemplary, and may actually deviate due to manufacturing tolerances or technical limitations, and the design can be adjusted according to actual needs.

[0027] like Figure 1As shown, an embodiment of the present specification provides a power module with a three-level circuit topology structure, including: a first insulating plate 1, a second insulating plate 2, a metal layer connecting bridge 3, an input DC positive electrode "DC+" pin 4, an input DC negative electrode "DC-" pin 5, an output AC electrode "AC" pin 6, a midpoint potential clamping electrode "M" pin 7 and a metal lead 9.

[0028] like Figure 2 As shown, the port "DC+" and the port "DC-" are the positive electrode and negative electrode of the DC bus, respectively. The port "DC+" corresponds to Figure 1 The "DC+" pin 4 in the port corresponds to the "DC-" pin Figure 1 The "DC-" pin 5 in the port "AC" is mainly used to output the alternating current signal "AC", corresponding to Figure 1 The "AC electrode 6; port "M" corresponds to Figure 1 The midpoint clamping electrode "M" pin 7 in the circuit; the IGBT1 chip 10 and the D1 freewheeling diode chip 11 connected in anti-parallel thereto constitute the first group of power chips; the IGBT1 chip 20 and the D2 freewheeling diode chip 21 connected in anti-parallel thereto constitute the second group of power chips; the IGBT3 chip 30 and the D3 freewheeling diode chip 31 connected in anti-parallel thereto constitute the third group of power chips; the IGBT4 chip and the D4 freewheeling diode chip 41 connected in anti-parallel thereto constitute the fourth group of power chips; the silicon carbide MOS5 chip 50 connected in parallel is the fifth group of power chips, and the silicon carbide MOS6 chip 60 connected in parallel is the sixth group of power chips.

[0029] The circuit topology of the main power circuit formed by the first to fourth groups of power chips is connected in series, and the circuit topology of the clamping circuit formed by the fifth and sixth groups of power chips is also connected in series, wherein the drain of MOS5 in the fifth group of power chips is connected to the emitter of IGBT1 in the first group of power chips and the collector of IGBT2 in the second group of power chips, and the source of MOS6 in the sixth group of power chips is connected to the emitter of silicon IGBT3 in the third group of power chips and the collector of IGBT4 in the fourth group of power chips.

[0030] like Figure 3The figure shows a schematic diagram of the structural projection of a power module in an XY plane according to an embodiment of the present invention, which includes: a first insulating layer 1, a second insulating layer 2, a metal layer connecting bridge 3, a "DC+" pin 4, a "DC-" pin 5, an "AC" pin 6, a midpoint clamping pin 7, a freewheeling diode chip 11 in the first group of power chips, a silicon IGBT chip 20 and a freewheeling diode chip 21 in the second group of power chips, a silicon IGBT chip 30 in the third group of power chips, a silicon IGBT chip 40 and its freewheeling diode chip 41 in the fourth group of power chips, a silicon carbide MOSFET chip 50 connected in parallel in the fifth group of power chips, and a silicon carbide MOSFET chip 60 connected in parallel in the sixth group of power chips.

[0031] like Figure 4 This is a schematic diagram of a power mode patterned metal layer design according to an embodiment of the present invention, comprising: a first insulating plate 1; a second insulating plate 2; The metal layer area located on the upper surface of the first insulating plate 1 includes: a single connected area 100 composed of a metal layer area 105 for arranging the "DC+" pin 4 and a metal layer area 110 for arranging the first group of power chips, an emitter strip metal layer area 112 corresponding to the emitter of the IGBT1 chip in the first group of power chips, and a gate strip metal layer area 111 corresponding to the gate; The metal layer area 220 for the freewheeling diode chip in the second group of power chips is arranged, and the metal layer area 10 for the temperature-sensitive resistor is arranged; The metal layer area 320 for the flyback diode chip 31 in the third group of power chips is arranged, the metal layer area 325 for a part of the "AC" pin is arranged, the metal layer area 324 corresponding to the anode of the flyback diode chip 31 is arranged, the metal layer area 410 for the fourth group of power chips is arranged, and the second single connected area 400 composed of the metal layer area 324 and the metal layer area 410; the gate bar metal layer area 411 corresponding to the gate of the fourth group of power chips and the emitter bar metal layer area 412 corresponding to the emitter bar; the metal layer area 405 for the "DC-" pin is arranged; and the metal layer area 406 for the "DC-" pin is arranged on the upper surface of the second insulating plate 2. The metal layer region of the surface includes: a metal layer region 210 for arranging the silicon IGBT chip (IGBT2) in the second group of power chips, a gate strip metal layer region 211 corresponding to the gate of the IGBT2 chip, a source strip metal layer region 212 corresponding to the source of the IGBT2 chip, a metal layer region 510 for arranging the silicon carbide MOSFET chip (MOS5) in the fifth group of power chips; a gate strip metal layer region 511 and a source strip metal layer region 512 corresponding to the gate and source of the MOS5 chip; and a single connected region 500 composed of the metal layer region 510 and the metal layer region 210; The metal layer area 310 of the silicon IGBT chip (IGBT3) in the third group of power chips, the gate bar metal layer area 311 corresponding to the gate of the IGBT3 chip, the source bar metal layer area 312 corresponding to the source, and the metal layer area 314 corresponding to the source are laid out; the metal layer areas 313 and 323 of the metal layer connection bridge 3 are laid out; and the metal layer area 315 of another part of the "AC" pins is laid out; The metal layer area 610 of the silicon carbide MOSFET chip (MOS6) in the sixth group of power chips is arranged, the metal layer area 605 of the midpoint clamping electrode "M" pin 7 is arranged, and the third single connected metal layer area 600 is composed of the metal layer area 605 of the midpoint clamping electrode "M" pin 7 and the area 610 of the sixth group of power chips and the metal layer area 514 corresponding to the source of the fifth group of power chips; the gate strip metal layer area 611 corresponding to the gate of the MOS6 chip, the source strip metal layer area 612 corresponding to the source of the MOS6 chip, and the metal layer area 614 corresponding to the source of the MOS6 chip; the first single connected area 630 is composed of the metal layer area 614 corresponding to the source of MOS6 and the metal layer area 314 corresponding to the emitter of IGBT3, and the area 630 is "L" shaped as a whole.

[0032] A power module and its structural design according to an embodiment of the present invention include: an insulating plate, including a first insulating plate 1 and a second insulating plate 2, wherein the second insulating plate 2 and the first insulating plate 1 are arranged in parallel on the same plane along the X direction; a metal layer, including various patterned metal layer areas with uniform thickness but different shapes, the metal layer is used to realize the circuit topology of the power module, and the metal layer is located on the upper surface of the insulating plate; a power chip, the power chip is arranged on the metal layer; metal pins, including a "DC+" pin 4 for inputting a positive DC bus, a "DC-" pin 5 for inputting a negative DC bus, an "AC" pin 6 for outputting an alternating current, and an "M" pin 7 for midpoint potential clamping, and the metal pins are also arranged on the metal layer; a metal layer connecting bridge 3, used to realize electrical connection between patterned metal layer areas, and the metal layer connecting bridge is also arranged on the metal layer; a metal lead 9, used to realize electrical connection between the power chip and the patterned metal layer areas. The electrical connection between the metal layer areas; and the circuit topology structure of the power module in which the insulating board, the metal layer, the power chip, the metal pins, the metal layer connecting bridge and the metal lead are overlapped. The circuit topology structure of the power module is a three-level topology structure with active neutral point clamping. The "DC+" pin 4 and the "DC-" pin 5 of the main bridge arm of the three-level circuit topology are arranged on the metal layer area on the right edge of the first insulating board along the Y direction, and the neutral point clamping "M" pin 7 of the clamping bridge arm of the three-level circuit topology is arranged on the metal layer area 605 on the left edge of the second insulating board. A part of the "AC" pin 6 of the main bridge arm of the three-level circuit topology outputs the alternating current is arranged on the metal layer area 325 on the left edge of the first insulating board and the other part is arranged on the metal layer area 315 on the right edge of the second insulating board, and the two parts of the pins are symmetrically distributed on both sides of the module center line parallel to the Y direction.

[0033] In some embodiments, the three-level topology structure includes a main bridge arm and a clamping bridge arm, the main bridge arm is formed by connecting the first group, the second group, the third group and the fourth group of power chips in series in sequence, the first group, the second group, the third group and the fourth group of power chips all include silicon IGBT chips and freewheeling diode chips connected in anti-parallel thereto, the clamping bridge arm is formed by connecting the fifth group of power chips and the sixth group of power chips in series, the fifth group and the sixth group of power chips all include silicon carbide MOSFET chips connected in parallel, the drain of the silicon carbide MOSFET chip 50 in the fifth group of power chips is connected to the emitter of the silicon IGBT chip 10 in the first group of power chips and the collector of the silicon IGBT chip 20 in the second group of power chips, and the source of the silicon carbide MOSFET chip 60 in the sixth group of power chips is connected to the emitter of the silicon IGBT chip 30 in the third group of power chips and the collector of the silicon IGBT chip 40 in the fourth group of power chips.

[0034] In some embodiments, the "DC+" pin 4, the "DC-" pin 6, the first group of power chips 10 and 11, the fourth group of power chips 40 and 41, the freewheeling diode chip 21 in the second group of power chips, the freewheeling diode chip 31 in the third group of power chips, and a portion of the "AC" pins are arranged on the metal layer on the upper surface of the first insulating board 1, and the fifth group of power chips, the sixth group of power chips, and the silicon IGBT chip 20 in the second group of power chips, the silicon IGBT chip 30 in the third group of power chips, the "M" pin 7, and another portion of the "AC" pins are arranged on the metal layer on the upper surface of the second insulating board 2; In some embodiments, the metal layer region 210 of the silicon IGBT chip 20 in the second group of power chips and the metal layer region 220 of the freewheeling diode chip 21 in the second group of power chips are electrically connected via a metal layer connecting bridge 3, and the metal layer region 310 of the silicon IGBT chip 30 in the third group of power chips and the metal layer region 320 of the freewheeling diode chip 31 in the third group of power chips are also electrically connected via a metal layer connecting bridge 3.

[0035] In some embodiments, the metal layer area on the upper surface of the first insulating plate 1, the metal layer area 110 for arranging the first group of power chips and the metal layer area 410 for arranging the fourth group of power chips are located on the upper surface of the right half area of ​​the first insulating plate 1, and the two are separated by the metal layer area 405 for arranging the "DC-" pin, the metal layer area 220 for arranging the freewheeling diode chip 21 in the second group of power chips and the metal layer area 320 for arranging the freewheeling diode chip 31 in the third group of power chips are located on the upper surface of the left half area of ​​the first insulating plate 1 and are adjacent to each other, and the gate bar metal layer area 411 and the emitter bar metal layer area 412 corresponding to the gate and emitter of the fourth group of power chips are arranged along the X direction and are arranged to the left of the metal layer area 405 for arranging the "DC-" pin.

[0036] In some embodiments, the metal layer area on the upper surface of the second insulating plate 2, the metal layer area 510 for the layout of the fifth group of power chips and the metal layer area 210 for the layout of the silicon IGBT chip 20 in the second group of power chips are a single connected area 500 and are located on the upper surface of the upper half area of ​​the second insulating plate, the metal layer area 310 for the layout of the silicon IGBT chip 30 in the third group of power chips and the metal layer area 610 for the layout of the sixth group of power chips are arranged in a direction opposite to the X direction and are located in the lower half area of ​​the second insulating plate 2, the metal layer area 614 corresponding to the source of the silicon carbide MOSFET chip 60 in the sixth group of power chips and the metal layer area 314 corresponding to the emitter of the silicon IGBT chip 30 in the third group of power chips are a first single connected area 630, and the pattern of the first single connected area 630 is "L" shaped and is nested between the metal layer area 310 for the layout of the silicon IGBT chip in the third group of power chips and the third single connected area 600 for the layout of the sixth group of power chips.

[0037] In some embodiments, the metal layer region 610 for arranging the sixth group of power chips, the metal layer region 605 for arranging the "M" pins, and the metal layer region 514 corresponding to the source of the silicon carbide MOSFET chip in the fifth group of power chips are the third single connected region 600, and the third single connected region is "T"-shaped and is located on the left half of the second insulating plate 2; In some embodiments, the gate strip metal layer region 511 corresponding to the gate of the silicon carbide MOSFET chip in the fifth group of power chips and the source strip metal layer region 512 corresponding to the source are both parallel to the X direction of the power module and located in the upper side region of the second insulating plate, and the gate strip metal layer region 611 corresponding to the gate of the silicon carbide MOSFET chip in the sixth group of power chips and the source strip metal layer region 612 corresponding to the source are both parallel to the Y direction of the power module and located in the lower left side region of the second insulating plate 2; In some embodiments, the emitter strip metal layer region 112 and the gate strip metal layer region 111 corresponding to the emitter and the gate of the silicon IGBT chip in the first group of power chips are located in the upper side region of the first insulating plate 1, the emitter strip metal layer region 212 and the gate strip metal layer region 211 corresponding to the emitter and the gate of the silicon IGBT chip in the second group of power chips are located in the upper side region of the second insulating plate 2, and the temperature sensitive resistor is located on the upper side region 10 of the first insulating plate between the two upper side regions; In some embodiments, the metal layer region 324 corresponding to the anode of the freewheeling diode in the third group of power chips and the metal layer region 410 for the layout of the fourth group of power chips are the second single connected region 400. The second single connected region 400 is "L"-shaped and is arranged along the Y direction next to the metal layer region 320 for the layout of the freewheeling diode chip in the third group of power chips; the two "L"-shaped metal layer regions 630 and 400 are symmetrically distributed on both sides of the module center line parallel to the Y direction, and are electrically connected to each other through the metal layer connecting bridge 3.

[0038] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present invention is limited to these examples. Under the concept of the present invention, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the present invention as described above, which are not provided in detail for the sake of simplicity.

[0039] The present invention is intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A power module with a three-level circuit topology, characterized in that: include: An insulating plate, comprising a first insulating plate and a second insulating plate, wherein the second insulating plate and the first insulating plate are arranged side by side on the same plane along the X direction; A metal layer, located on the upper surface of the insulating plate, including a patterned metal layer area, for realizing the circuit topology of the power module, wherein the metal layers on the first insulating plate and the second insulating plate are electrically connected via a metal layer connecting bridge; Metal pins, including a "DC+" pin for inputting a positive DC bus, a "DC-" pin for inputting a negative DC bus, an "AC" pin for outputting an alternating current, and an "M" pin for midpoint potential clamping, wherein the metal pins are arranged on the metal layer; A power chip, wherein the power chip is arranged on the metal layer and electrically connected to the metal layer; The insulating plate, the metal layer, the metal pins and the power chip are connected to form a circuit topology structure of the power module. The circuit topology structure is a three-level topology structure with active neutral point clamping. The three-level topology structure includes a main bridge arm and a clamping bridge arm. The main bridge arm includes a first group, a second group, a third group and a fourth group of power chips connected in series in sequence. The four groups of power chips all include a silicon IGBT chip and a freewheeling diode chip connected in anti-parallel therewith. The clamping bridge arm includes a fifth group of power chips and a sixth group of power chips connected in series therewith. The fifth group of power chips and the sixth group of power chips all include silicon carbide MOSFET chips connected in parallel. The drain of the silicon carbide MOSFET chip in the fifth group of power chips is connected to the emitter of the silicon IGBT chip in the first group of power chips and the collector of the silicon IGBT chip in the second group of power chips. The source of the silicon carbide MOSFET chip in the sixth group of power chips is connected to the emitter of the silicon IGBT chip in the third group of power chips and the collector of the silicon IGBT chip in the fourth group of power chips.

2. The power module with a three-level circuit topology structure according to claim 1, characterized in that: The "DC+" pin and the "DC-" pin of the main bridge arm are arranged on the metal layer area at the right edge of the first insulating board along the Y direction, the "M" pin of the neutral point clamp of the clamping bridge arm is arranged on the metal layer area at the left edge of the second insulating board, and a part of the "AC" pin of the main bridge arm outputting alternating current is arranged on the metal layer area at the left edge of the first insulating board and the other part is arranged on the metal layer area at the right edge of the second insulating board, and the two parts of the "AC" pin are symmetrically distributed on both sides of the center line of the module parallel to the Y direction.

3. The power module with a three-level circuit topology structure according to claim 1, characterized in that: The "DC+" pin, the "DC-" pin, the first group of power chips, the fourth group of power chips, the freewheeling diode chips in the second group of power chips, the freewheeling diode chips in the third group of power chips and a part of the "AC" pins are arranged on the metal layer on the upper surface of the first insulating board, and the fifth group of power chips, the sixth group of power chips and the silicon IGBT chips in the second group of power chips, the silicon IGBT chips in the third group of power chips, the "M" pin and another part of the "AC" pins are arranged on the metal layer on the upper surface of the second insulating board.

4. The power module with a three-level circuit topology structure according to claim 1, characterized in that: The metal layer area of ​​the silicon IGBT chips in the second group of power chips and the metal layer area of ​​the freewheeling diode chips in the second group of power chips are electrically connected through the metal layer connecting bridge, and the metal layer area of ​​the silicon IGBT chips in the third group of power chips and the metal layer area of ​​the freewheeling diode chips in the third group of power chips are also electrically connected through the metal layer connecting bridge.

5. The power module with a three-level circuit topology structure according to claim 1, characterized in that: The metal layer area for layout of the first group of power chips and the metal layer area for layout of the fourth group of power chips are located on the upper surface of the right half area of ​​the first insulating plate, and are separated by the metal layer area for layout of the "DC-" pin. The metal layer area for layout of the freewheeling diode chips in the second group of power chips and the metal layer area for layout of the freewheeling diode chips in the third group of power chips are located on the upper surface of the left half area of ​​the first insulating plate and are adjacent to each other. The gate bar metal layer area and the emitter bar metal layer area corresponding to the gate and emitter of the fourth group of power chips are arranged along the X direction and are arranged on the left side of the metal layer area for layout of the "DC-" pin.

6. The power module with a three-level circuit topology structure according to claim 1, characterized in that: The metal layer area for layout of the fifth group of power chips and the metal layer area for layout of the silicon IGBT chips in the second group of power chips are a single connected area and are located on the upper surface of the upper half area of ​​the second insulating plate. The metal layer area for layout of the silicon IGBT chips in the third group of power chips and the metal layer area for layout of the sixth group of power chips are arranged in a direction opposite to the X direction and are located in the lower half area of ​​the second insulating plate. The metal layer area corresponding to the source of the silicon carbide MOSFET chip in the sixth group of power chips and the metal layer area corresponding to the emitter of the silicon IGBT chip in the third group of power chips are the first single connected area. The pattern of the first single connected area is "L" shaped and is nested between the metal layer area for layout of the silicon IGBT chips in the third group of power chips and the metal layer area for layout of the sixth group of power chips.

7. The power module with a three-level circuit topology structure according to claim 6, characterized in that: The metal layer area corresponding to the anode of the freewheeling diode in the third group of power chips and the metal layer area where the fourth group of power chips are arranged are the second single connected area. The second single connected area is "L" shaped and is arranged along the Y direction next to the metal layer area where the freewheeling diode chips in the third group of power chips are arranged; the first single connected area and the second single connected area are symmetrically distributed on both sides of the module center line parallel to the Y direction, and are electrically connected to each other through the metal layer connecting bridge.

8. The power module with a three-level circuit topology structure according to claim 1, characterized in that: The metal layer area for laying out the sixth group of power chips, the metal layer area for laying out the "M" pins, and the metal layer area corresponding to the source of the silicon carbide MOSFET chip in the fifth group of power chips are the third single connected area, and the third single connected area is "T" shaped and is located on the left half of the second insulating plate.

9. The power module with a three-level circuit topology structure according to claim 1, characterized in that: The gate strip metal layer region corresponding to the gate of the silicon carbide MOSFET chip in the fifth group of power chips and the source strip metal layer region corresponding to the source are both parallel to the X direction of the power module and located in the upper side region of the second insulating plate. The gate strip metal layer region corresponding to the gate of the silicon carbide MOSFET chip in the sixth group of power chips and the source strip metal layer region corresponding to the source are both parallel to the Y direction of the power module and located in the lower left side region of the second insulating plate.

10. The power module with a three-level circuit topology structure according to claim 1, characterized in that: The emitter strip metal layer area and the gate strip metal layer area corresponding to the emitter and gate of the silicon IGBT chip in the first group of power chips are located in the upper side area of ​​the first insulating plate, the emitter strip metal layer area and the gate strip metal layer area corresponding to the emitter and gate of the silicon IGBT chip in the second group of power chips are located in the upper side area of ​​the second insulating plate, and the thermistor is located on the upper side area of ​​the first insulating plate between the two upper side areas.

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