A successive approximation flash analog-to-digital converter and an operation method thereof

Abstract

The application discloses a successive approximation flash analog-digital converter and an operation method thereof, and belongs to the technical field of in-memory computing in semiconductor CMOS ultra-large scale integrated circuits.The successive approximation flash analog-digital converter completes rough quantization of N1 bits in one operation, rough quantization and fine quantization are performed on an input signal VIN through N2 steps, the quantization step is gradually shortened, the output precision of each quantization is N1 bits, and the quantization of N (N=N1*N2) bits is completed until the offset voltage limit of a sensitive amplifier is reached.The digital control logic is simple, the use of a binary capacitor array is avoided, and the area and power consumption are smaller than those of a Flash ADC and a SAR ADC with the same precision.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of compute-in-memory in semiconductor and CMOS ultra large scale integrated circuit (ULSI), and particularly relates to an analog-to-digital conversion circuit (ADC) used in vector matrix multiplication (VMM) based on a memory array. BACKGROUND

[0002] With the continuous progress of artificial intelligence and deep learning technology, artificial neural networks have been widely used in natural language processing, image recognition, autonomous driving, graph neural networks and other fields. However, the expansion of network size leads to a large amount of energy consumption in data transmission between memory and traditional computing devices (such as CPU and GPU), which is known as the von Neumann bottleneck. In artificial neural network algorithms, the most important computing task is vector matrix multiplication. Compute-in-memory avoids the frequent transmission of data between memory and computing units by storing weights in memory cells and performing vector matrix multiplication in arrays, and is considered an effective method to solve the von Neumann bottleneck.

[0003] As shown in Figure 1 , compute-in-memory usually adopts a digital-analog hybrid computing method. The memory cell can be a volatile memory such as SRAM or DRAM, or a non-volatile memory such as Flash, RRAM, PCRAM, or MRAM. The weights of vector matrix multiplication are stored in the memory, the input is realized through a digital-to-analog converter (DAC) or a buffer (Buffer), and the calculation result is represented as current or voltage on the bit line (BL). The calculation result needs to be read through an analog-to-digital converter (ADC), and the ADC structure commonly used in compute-in-memory includes a successive approximation ADC (SAR-ADC) and a flash ADC (Flash-ADC).

[0004] In order to realize high-precision vector matrix multiplication, a high-precision ADC is needed for analog-to-digital conversion reading. The structures of traditional SAR-ADC and Flash-ADC are as shown in Figure 2As shown in the figure, the area and power consumption of the SAR-ADC's capacitor array increase exponentially with increasing readout accuracy. Similarly, the number of sense amplifiers (SAs) and total power consumption required by the Flash-ADC also increase exponentially with increasing readout accuracy. Because hybrid in-memory computing requires parallel readings from a large number of ADCs, the increased area and power consumption of a single ADC significantly increases the overall system area and power consumption, creating a bottleneck for improving the area and energy efficiency of hybrid in-memory computing. Summary of the Invention

[0005] In view of the above problems, the present invention proposes a successive approximation flash analog-to-digital converter, which first performs coarse quantization on the input signal, then performs multiple fine quantizations, and finally realizes the conversion of the signal.

[0006] The technical solutions of the present invention are as follows:

[0007] A successive approximation flash analog-to-digital converter, characterized in that it comprises a V REF Producing unit, A successive approximation flash memory analog-to-digital module, a digital control module, the successive approximation flash memory module consists of a sense amplifier, a boost capacitor and a 2 N1 -1 select 1 multiplexer, the positive terminal of the sense amplifier is connected to the input voltage, the reference voltage V REF Connect directly to the negative terminal of the sense amplifier through a switch, or connect to the left side of the boost capacitor through a switch, 2 N1 The -1 select 1 multiplexer connects the voltage to be boosted to the right side of the Boost capacitor to charge the Boost capacitor. In the comparison phase, the connection with the Boost capacitor is cut off. The right side of the Boost capacitor is connected to the negative terminal of the sensitive amplifier. The sensitive amplifier is used to compare the two voltages and output the comparison result. If the voltage to be measured is greater than the current V REF [i] is greater, then the output is high level "1". If the voltage to be measured is greater than the current V REF [i] is small, then the output is low level "0"; 2 N1 The -1 select 1 multiplexer selects the appropriate next step quantization basic voltage based on the comparison of OUT[N1:1], stores this voltage in the Boost capacitor, and raises the reference voltage V of the sense amplifier in the next comparison. REF , A successive approximation flash memory analog-to-digital module is compared once Thermometer code ( "0" or "1"); the digital control module includes a thermometer decoder and a bit splicing module. The thermometer decoder converts the output of a single operation into The thermometer code is converted into binary code OUT[N1:1], and the bit splicing module integrates the binary codes obtained through N2 steps to obtain the final N (N=N1×N2) bit output.

[0008] Further, an operation method of the successive approximation flash analog-to-digital converter is provided, one operation completes N1-bit coarse quantization, and N-bit fine quantization is completed through N2 steps, wherein N=N1×N2, and the steps include:

[0009] 1) Accumulation of the CIM array IN The direct input is connected to a successive approximation flash module, the input signal is connected to the positive end of the sensitive amplifier, the negative end of the sensitive amplifier is connected to V REF _1 st [1], which is uniformly distributed within the entire reference voltage V REF , the output precision of the single comparison of the successive approximation flash module is N1, the thermometer decoder obtains a thermometer code through one comparison, which is converted into binary code OUT_1 st [N1:1];

[0010] 2) The 2 N1 -1 select-1 multiplexer determines the quantization reference voltage of the next step according to the binary code result OUT_1 st [N1:1]; The entire quantization size is The left end of each Boost capacitor is connected to VSS, and the right end is connected to V REF _2 nd , and the quantization reference voltage of this conversion is stored;

[0011] 3) The left end of the Boost capacitor is connected to a voltage level that is uniformly distributed between 0 and V REF / N1, the right end of the Boost capacitor is disconnected from V REF _2 nd , and is directly connected to the input end of the sensitive amplifier, and the reference voltage is sequentially raised to V REF _2 nd [i]+V REF _2 nd , the thermometer decoder compares the input signal with the reference voltage to obtain a thermometer code and convert it into binary code OUT_2 nd [N1:1];

[0012] 4) Repeat step 2) - step 3), change the voltage value of the Boost storage in turn, so that its voltage value gradually approaches the input voltage V IN , until the last step output OUT_N2 th [N1:1].

[0013] The beneficial effects of the present application are as follows:

[0014] The Multi-Step N bit SAR-Flash-ADC of the present application performs coarse quantization and then fine quantization on the input signal V IN through multi-step (N2) quantization, gradually shortens the quantization step, and the output precision of each quantization is N1 bits, until the offset voltage limit of the sensitive amplifier is reached, that is, N (N=N1xN2) bit quantization is completed. Compared with the N-bit Flash ADC, the number of sensitive amplifiers is reduced from 2 N -1 to Taking N=16 and N1=4 as an example, the number of sensitive amplifiers is reduced from 65535 to 15; compared with the N-bit SAR ADC, the digital control logic is simpler, and the use of binary capacitor array is avoided, and the area and power consumption are smaller than the same accuracy of Flash ADC and SAR ADC. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 It is a vector matrix multiplication diagram based on digital-analog hybrid memory calculation;

[0016] Figure 2 It is a SAR-ADC and Flash-ADC structure diagram;

[0017] Figure 3 It is a Multi-Step N bit SAR-Flash-ADC structure diagram of the present application;

[0018] Figure 4 It is a first step coarse quantization (step 1) connection diagram of the present application;

[0019] Figure 5 It is a storage quantization basic voltage (step 2) connection diagram of the present application;

[0020] Figure 6 It is a second step fine quantization (step 3) connection diagram of the present application;

[0021] Figure 7 It is a V REF relationship diagram of the multi-step quantization process of the present application; DETAILED EMBODIMENT

[0022] The invention provides a successive approximation flash analog-to-digital converter (Multi-Step N-bit SAR-Flash-ADC), such as Figure 3 As shown, it contains a V REF Generate unit, A successive approximation flash analog-to-digital module, a digital control module consisting of a thermometer decoder and a bit splicing module, V REF The generation unit can be shared in the ADC of CIM. The thermometer decoder converts the single output thermometer code into binary code OUT[N1:1]. The bit splicing module integrates the multi-step (N2) binary code to obtain the final N (N=N1×N2) bit output. The successive approximation flash memory module consists of a sense amplifier, a boost capacitor and a 2 N1 -1 select 1 multiplexer. The sensitive amplifier is used to compare the two voltages and output the comparison result. If the voltage to be measured is greater than the current V REF [i] is greater, then the output is high level "1". If the voltage to be measured is greater than the current V REF [i] is small, the output is low level "0". N1 -1 selects 1 multiplexer according to the OUT[2 N1 -1:1] Select the appropriate quantization basic voltage for the next step, store this voltage in the Boost capacitor, and raise the reference voltage V of the sense amplifier in the next comparison step RFF . V REF The generating unit can be shared among the ADCs of the CIM.

[0023] The calculation method of the successive approximation flash memory analog-to-digital converter of the present invention comprises the following steps:

[0024] 1) Cumulative signal V of CIM array IN Direct input connection to 2 N1 -1 successive approximation flash memory module, the input signal is connected to the positive terminal of the sense amplifier, and the negative terminal of the sense amplifier is directly connected to V REF _1 st [2 N1 -1:1], V REF _1 st [2 N1 -1:1] over the entire reference voltage V REF The output accuracy of a single comparison of the flash memory module is N1, and the thermometer decoder obtains 2 by one comparison. N1 -1 thermometer code, convert the thermometer code into binary code OUT_1 st [N1:1], complete the first step of coarse quantization, such as Figure 4 As shown;

[0025] 2) according to the coarse quantization result OUT_1 st [N1:1] determine the quantization basic voltage V REF _2 nd of the second step REF _2 nd , which takes a value in the range of , connect the left end of each Boost capacitor to VSS, connect the right end to V REF _2 nd , and store the quantization basic voltage converted this time, as shown in Figure 5 ;

[0026] 3) connect the left end of 2 N1 -1 Boost capacitors to the levels of , which are uniformly distributed between 0 and V REF / N1, disconnect the right end of 2 N1 -1 Boost capacitors from V REF _2 nd , and directly connect the input end of the sensitive amplifier, sequentially raise the reference voltage to V REF _2 nd [i]+V REF _2 nd , and the thermometer decoder compares the input signal with the reference voltage to obtain 2 N1 -1 thermometer codes and convert them into binary codes OUT_2 nd [N1:1], complete the fine quantization of the second step, as shown in Figure 6 ;

[0027] 4) repeat steps 2) to 3), i.e., according to the fine quantization result OUT_2 nd [N1:1], determine the quantization basic voltage V REF _3 rd , V REF _3 rd takes a value in the range of V REF _2 nd [i]+V REF _2 nd , connect the left end of each Boost capacitor to VSS, connect the right end to V REF _3 rd , and store the quantization basic voltage converted this time;

[0028] 5) connect the reference voltage at the left end of 2 N1 -1 Boost capacitors to V REF _3 rd [2 N1 -1:1], V REF _3 rd [2 N1-1:1] are uniformly distributed between 0 and V REF / N1 2 between 2 N1 -1 Boost capacitor is disconnected from V REF _3 rd , the input of the sensitive amplifier is directly connected, and the reference voltage is sequentially raised to V REF _3 rd [i]+V REF _3 rd , the thermometer decoder compares the input signal with the reference voltage to obtain 2 N1 -1 thermometer codes and convert them into binary codes OUT_3 rd [N1:1], completing the fine quantization of the third step;

[0029] 6) Repeat steps 2)-step 3), sequentially change the voltage value of the Boost storage, so that the voltage value gradually approaches the input voltage VIN, on this basis, finer quantization levels are divided, until the final step output OUT_N2 th [N1:1] is obtained. Ideally, as Figure 7 shown, the input voltage V IN can be infinitely approximated by an infinite number of operation steps, then the actual structure is limited by the offset voltage of the sensitive amplifier, so it is necessary to ensure that the minimum quantization step LSB(V REF / 2 N ) is greater than the offset voltage of the sensitive amplifier.

[0030] The above embodiments are only used to illustrate the technical solutions of the present application and not to limit them, and those skilled in the art can modify or equivalently replace the technical solutions of the present application without departing from the spirit and scope of the present application, the protection scope of the present application should be subject to the claims.

Claims

1. A successive approximation flash analog-to-digital converter, comprising: Contains a Producing unit, A successive approximation flash memory analog-to-digital module and a digital control module. The successive approximation flash memory analog-to-digital converter is used for an in-memory calculation circuit for performing vector-matrix multiplication calculation based on a memory array. Each successive approximation flash memory module consists of a sense amplifier, a Boost capacitor and a 2 N1 -1 to 1 multiplexer, the positive terminal of the sense amplifier is connected to the input voltage, the reference voltage Directly connect to the negative terminal of the sense amplifier through a switch, or connect the Boost capacitor through a switch and then connect to the negative terminal of the sense amplifier, 2 N1 -1 select 1 multiplexer connects the voltage to be boosted to the Boost capacitor to charge the Boost capacitor, and cuts off the connection with the Boost capacitor when the sense amplifier compares the two voltages. The sense amplifier is used to compare the two voltages and output the comparison result. If the voltage to be measured is greater than the current If the voltage to be measured is greater than the current Small, then output low level "0"; 2 N1 -1 select 1 multiplexer according to the comparison of OUT[ :1], and select the appropriate quantization basic voltage for the next step, store this voltage in the Boost capacitor, and raise the reference voltage of the sense amplifier in the next comparison step , A successive approximation flash memory analog-to-digital module is compared once Thermometer code ( "0" or "1"); the digital control module includes a thermometer decoder and a bit splicing module. The thermometer decoder converts the output of a single operation into Convert thermometer code to binary code , the bit splicing module will The binary codes obtained by the step operation are integrated to obtain the final ( ) bit output, through multi-step quantization, where the multi-step is N2, the input signal V IN Perform coarse quantization and then fine quantization, gradually shortening the quantization step size, and the output accuracy of each quantization is N1 bits until the offset voltage limit of the sense amplifier is reached.

2. The successive approximation flash analog-to-digital converter of claim 1, wherein, The The generating unit is arranged in the ADC of the CIM.

3. The method of claim 1, wherein one operation is completed. coarse quantization of the bits by the operation of the step is completed fine quantization of the bits, wherein the steps comprising: 1) the cumulative signal V of the CIM array IN directly input connected to the positive end of the input signal of the sensitive amplifier, the negative end of the sensitive amplifier is connected to to , uniformly distributed within the entire reference voltage , the output precision of the single comparison of the successive approximation flash module is , the thermometer decoder obtains thermometer code through one comparison, and converts it into binary code ; 2) 2 N1 -1 select 1 multiplexer according to the binary encoding result Determine the next quantization reference voltage , The entire quantization size is Connect the left end of each Boost capacitor to VSS and the right end to Store the quantization basic voltage of this conversion; 3) the left end of the Boost capacitor is connected in turn , , , the level of the Boost capacitor is uniformly distributed between 0 and V REF / N1, , the right end of the Boost capacitor is disconnected from , and is directly connected to the input end of the sensitive amplifier, and in turn the reference voltage is raised to V REF _2 nd [i]+ V REF _2 nd , the thermometer decoder compares the input signal with this reference voltage to obtain thermometer code and convert it to binary code OUT_2 nd [N1:1]; 4) Repeat Step 2) - Step 3) with the voltage value of the Boost storage changed in turn, so that the voltage value of the Boost storage gradually approaches the input voltage V IN , until the output of the last step is obtained .

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