A data encryption processing method and device

Abstract

The embodiment of the present application provides a data encryption processing method and device, the method is applied to a microprocessor, the microprocessor is connected with n encryption calculation units, n is a positive integer, and the method comprises the following steps: obtaining to-be-processed data and a key, generating first target data composed of m operators according to the to-be-processed data and the key, sending the first operator in the m operators to a target encryption calculation unit for calculation, saving the calculation result returned by the target encryption calculation unit as the first first result, sending the i-th operator and the (i-1)-th first result to the target encryption calculation unit for calculation, and saving the calculation result returned by the target encryption calculation unit as the i-th first result, wherein i=2,...,m. The embodiment of the present application can solve the problem that the hardware implementation of the encryption algorithm with a fixed input data length in the related art cannot be reused and reconstructed, improve the reusability of the encryption calculation unit, save hardware resources, and also run faster.

Description

Technical Field

[0001] This application relates to the field of communications, and more specifically, to a data encryption processing method and apparatus. Background Technology

[0002] SHA-2 (Secure Hash Algorithm 2) is a one-way hash algorithm published in 2002. It can map messages of arbitrary length into message digests of fixed length. Depending on the length of the output message digest, it can be divided into SHA-224, SHA-256, SHA-384, and SHA-512. It can be applied to digital signatures, HMAC (Hash-based Message Authentication Code) authentication, password protection, data integrity verification, and network security protocols. SHA-256 can convert input messages of any finite length (less than 2^64 bits) into a 256-bit message digest. The processing steps can be divided into three parts: data preprocessing, data augmentation, and data compression. HMAC, on the other hand, is an algorithm based on SHA and a key, and is widely used in many security protocols for providing authentication services. The implementation of HMAC-SHA can be seen as an integration of multiple SHA operations. In practical applications, the SHA operation is called separately according to the key and the message to achieve the effect of the HMAC-SHA algorithm. HMAC-SHA-256 is calculated based on the SHA-256 algorithm in the SHA algorithm.

[0003] SHA-2 can be implemented in software on general-purpose devices or in hardware on dedicated devices. Software implementations offer advantages such as low resource consumption, ease of use, and portability. However, with the development of communication technology, the amount of data that encryption algorithms need to process has exploded. In many applications, simple software implementations of SHA-2 are gradually failing to meet system speed requirements. To improve system efficiency, many systems are beginning to adopt dedicated hardware devices for SHA-2.

[0004] Currently, the hardware implementation of the SHA algorithm mainly uses a pipelined structure, with computation designed based on a fixed length of input data. However, if the data is very long, the computation path will be very long, consuming more resources and meaning higher costs and power consumption. Related technologies optimize the hardware implementation method for each type of input data, but optimization schemes introduce complex control units and have problems such as incompatibility with other optimization schemes or high process requirements. More importantly, these schemes can only perform algorithm calculations on fixed-length input data, lacking reusability, and the difficulty of optimization increases with the data length.

[0005] In summary, there is still no good solution to the problem that the hardware implementation of encryption algorithms with fixed input data length cannot be reused and reconstructed in related technologies. Summary of the Invention

[0006] This application provides a data encryption processing method and apparatus to at least solve the problem that the hardware implementation of encryption algorithms with fixed input data length in related technologies cannot be reused and reconstructed.

[0007] According to one embodiment of this application, a data encryption processing method is provided, applied to a microprocessor, the microprocessor being connected to n encryption computing units, where n is a positive integer. The method includes: acquiring data to be processed and a key; generating first target data based on the data to be processed and the key, wherein the first target data consists of m operators, each operator corresponding to data of a first preset length, where m is an integer greater than 1; sending the first operator among the m operators to a target encryption computing unit for calculation, and saving the calculation result returned by the target encryption computing unit as the first first result, wherein the target encryption computing unit is any one of the n encryption computing units; for each operator from the 2nd to the mth operator among the m operators, sending the i-th operator and the (i-1)-th first result to the target encryption computing unit for calculation, and saving the calculation result returned by the target encryption computing unit as the i-th first result, where i=2,...,m, and the (i-1)-th first result is the calculation result of the target encryption computing unit performing the calculation on the (i-1)-th operator.

[0008] According to another embodiment of this application, a data encryption processing apparatus is provided, comprising: a microprocessor and n encryption computing units, where n is a positive integer; the microprocessor is configured to acquire data to be processed and a key, generate first target data based on the data to be processed and the key, wherein the first target data consists of m operators, each operator corresponding to data of a first preset length, where m is an integer greater than 1; send the first operator of the m operators to the target encryption computing unit for calculation, and save the calculation result returned by the target encryption computing unit as the first first result, wherein the target encryption computing unit is one of the n encryption computing units. Any one of the m operators; for each of the 2nd to mth operators, send the i-th operator and the (i-1)th first result to the target encryption computing unit for calculation, and save the calculation result returned by the target encryption computing unit as the i-th first result, where i=2,...,m, and the (i-1)th first result is the calculation result of the target encryption computing unit on the (i-1)th operator; the encryption computing unit is used to receive each of the 1st to mth operators and the 1st to (m-1)th first results sent by the microprocessor, perform encryption calculation on each operator respectively, and send the calculation result to the microprocessor.

[0009] According to yet another embodiment of this application, a computer-readable storage medium is also provided, which stores a computer program, wherein the computer program is executed by a processor to perform the steps in any of the above method embodiments.

[0010] According to yet another embodiment of this application, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0011] In this embodiment, the microprocessor preprocesses the data to be processed and the key to generate first target data consisting of multiple fixed-length operators. Each operator is then sent to the encryption computing unit for multiple data interactions and iterative calculations. This solves the problem that the hardware implementation of encryption algorithms with fixed input data lengths cannot be reused and reconstructed in related technologies. It not only improves the reusability of the encryption computing unit and saves hardware resources, but also has the advantage of faster hardware algorithm calculation and operation speed. Attached Figure Description

[0012] Figure 1 This is a hardware structure block diagram of the data encryption processing method according to an embodiment of this application;

[0013] Figure 2 This is a hardware structure block diagram of a SHA-2 computing unit according to an embodiment of this application;

[0014] Figure 3 This is a schematic diagram of the processing flow of a SHA-256 computing unit according to an embodiment of this application;

[0015] Figure 4 This is a flowchart of a data encryption processing method according to an embodiment of this application;

[0016] Figure 5 This is a flowchart illustrating data encryption processing based on the HMAC-SHA-2 algorithm according to an embodiment of this application;

[0017] Figure 6 This is a flowchart illustrating a data encryption method based on SHA-256 according to an embodiment of this application.

[0018] Figure 7 This is a structural block diagram (a) of a data encryption processing device according to an embodiment of this application;

[0019] Figure 8 This is a structural block diagram (II) of a data encryption processing device according to an embodiment of this application;

[0020] Figure 9 This is a structural block diagram of a microprocessor for data encryption processing according to an embodiment of this application. Detailed Implementation

[0021] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0022] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0023] The methods and embodiments provided in this application can be executed on a mobile terminal, a computer terminal, or a similar computing device. Taking running on a computer terminal as an example, Figure 1 This is a hardware structure block diagram of the data encryption processing method according to an embodiment of this application, such as... Figure 1 As shown, a hardware board may include one or more ( Figure 1 Only one is shown in the diagram. A processor 12 (which may include, but is not limited to, a microprocessor MCU or programmable logic device, etc.) and a memory 14 for storing data are also shown. The mobile terminal may further include a transmission device 16 for communication functions and an input / output device 18. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the mobile terminal described above. For example, the mobile terminal may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1The different configurations shown.

[0024] The memory 14 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the data encryption processing method in this embodiment. The processor 12 executes various functional applications and the data encryption processing method by running the computer program stored in the memory 14, thus implementing the aforementioned method. The memory 14 may include high-speed random access memory and non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 14 may further include memory remotely located relative to the processor 12, and these remote memories can be connected to the mobile terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0025] The transmission device 16 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a telecommunications provider. In one example, the transmission device 16 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 16 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0026] According to one embodiment of this application, a data encryption processing method is provided, applied to a microprocessor, wherein the microprocessor is connected to n encryption computing units, where n is a positive integer. The encryption computing units are implemented through a hardware structure.

[0027] In one exemplary embodiment, the encryption computing unit is a hardware implementation of an encryption algorithm that can only process input data of a fixed length, specifically a SHA-2 computing unit.

[0028] Figure 2 This is a hardware structure block diagram of a SHA-2 computing unit according to an embodiment of this application, such as... Figure 2 As shown, taking the SHA-256 computation unit as an example, it can include the following structure:

[0029] Counting unit 21, data expansion unit 22, data compression unit 23, constant selection unit 24, data preprocessing unit 25, data output unit 26.

[0030] In this embodiment, the counting unit 21 is used to count the current number of calculation rounds so that other units can select calculation data based on the current number of calculation rounds. Furthermore, for each operator sent by the microprocessor to the SHA-256 calculation unit, the SHA-256 calculation unit needs to perform 64 rounds of iterative calculation.

[0031] In this embodiment, the data expansion unit 22 is used to expand the input 512-bit operator into 64 32-bit data, and select the data to participate in the calculation according to the number of calculation rounds in the counting unit 21.

[0032] In this embodiment, the constant selection unit 24 is used to select 64 K constants according to the number of calculation rounds to participate in the calculation.

[0033] In one exemplary embodiment, the 64 K constants (i.e., K0-K63) sequentially include: 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5, 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5, 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3, 0x72be5d74, 0x80deb1fe , 0x9bdc06a7, 0xc19bf174, 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc, 0x2de92c6f, 0x4a7484aa, 0x5 cb0a9dc, 0x76f988da, 0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7, 0xc6e00bf3, 0xd5a79147, 0x06ca6 351, 0x14292967, 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13, 0x650a7354, 0x766a0abb, 0x81c2c92e , 0x92722c85, 0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3, 0xd192e819, 0xd6990624, 0xf40e3585, 0x1 06aa070, 0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5, 0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6 ff3, 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208, 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2.

[0034] In one embodiment of this application, the data preprocessing unit 25 is used to select the hash value for iterative calculation. If it is the initial iterative calculation, the hash constant is selected; otherwise, the result obtained from the previous round of calculation is selected as the hash value. Furthermore, in this embodiment of the application, the hash constant is used only when calculating the first operator, and the calculation result of the SHA-256 of the previous operator is used when calculating other operators.

[0035] In one exemplary embodiment, the hash constants sequentially include: 0x6a09e667, 0xbb67ae85, 0x3c6ef372, 0xa54ff53a, 0x510e527f, 0x9b05688c, 0x1f83d9ab, and 0x5be0cd19.

[0036] In this embodiment, the data compression unit 23 performs 64 rounds of iterative calculations based on the data selected from the above-mentioned units.

[0037] In an exemplary embodiment, each round of iterative calculation in the data compression unit 23 may include the following calculation steps:

[0038] sum0 = a_reg>>>2 ^ a_reg>>>13 ^ a_reg>>>22

[0039] sum1 = e_reg>>>6 ^ e_reg>>>11 ^ e_reg>>>25

[0040] ch = (e_reg & f_reg) ^ (~e_reg & f_reg)

[0041] maj = (a_reg & b_reg) ^ (a_reg & c_reg) ^ (b_reg & c_reg)

[0042] t1 = h_reg + sum1 + ch + tmp_w + tem_k

[0043] t2 = sum0 + maj

[0044] a_reg = t1 +t2

[0045] b_reg = a_reg

[0046] c_reg = b_reg

[0047] d_reg = c_reg

[0048] e_reg = d_reg + t1

[0049] f_reg = e_reg

[0050] g_reg = f_reg

[0051] h_reg = g_reg

[0052] Where >>> is a circular right shift, >> is a logical right shift, the initial a_reg to h_reg are the eight hash values ​​selected by the data preprocessing unit 25, tmp_w is the data selected by the data expansion unit 21 in each round, and tem_k is the data selected by the constant selection unit 23 in each round.

[0053] In this embodiment, the data output unit 26 is only valid after the data compression unit 23 has performed 64 rounds of calculation. It is used to perform the final calculation on the calculation results of the last round of the data compression unit 23 (the final a_reg to h_reg) and the initial hash value (hash constant or iterative calculation result of the previous operator) in the data preprocessing unit 25, and output the final calculation result.

[0054] The SHA-2 calculation unit in this embodiment is implemented in hardware and can only process input data of fixed length. However, this embodiment can use a microprocessor to split input data of any finite length (length less than 2^64 bits) into multiple operators of fixed length, and then use the SHA-2 calculation unit to iteratively calculate multiple operators, thereby realizing the SHA-2 calculation of input data of any length in hardware.

[0055] This application does not impose any restrictions on the hardware structure of the SHA-2 computing unit, and the SHA-2 computing unit can also adopt other hardware implementation methods.

[0056] Figure 3 This is a schematic diagram of the processing flow of a SHA-256 computing unit according to an embodiment of this application, as shown below. Figure 3 As shown, taking the SHA-256 calculation unit as an example, the process includes: expanding the input data (data_in) into w0 to w63; selecting one 32-bit data from w0 to w63 and one constant from k0 to k63 in sequence according to the calculation round, and performing 64 rounds of iterative calculation on the hash value (a to h); summing the calculation result of the 64th round with the initial hash value to obtain the final SHA-256 calculation result.

[0057] The embodiments of this application demonstrate that the SHA-2 algorithm can be implemented in hardware, improving computational efficiency. This application is not limited to the SHA-256 algorithm; the SHA-2 computation unit can also be a dedicated hardware device for other SHA-2 algorithms.

[0058] Furthermore, the encryption calculation unit in this application embodiment can also be replaced with other hardware encryption calculation units with fixed input lengths.

[0059] Figure 4 This is a flowchart of a data encryption processing method according to an embodiment of this application, such as... Figure 4 As shown, the process includes the following steps:

[0060] Step S402: Obtain the data to be processed and the key;

[0061] Step S404: Generate first target data based on the data to be processed and the key, wherein the first target data consists of m operators, each operator corresponding to data of a first preset length, and m is an integer greater than 1;

[0062] Step S406: Send the first operator among the m operators to the target encryption computing unit for calculation, and save the calculation result returned by the target encryption computing unit as the first first result, wherein the target encryption computing unit is any one of the n encryption computing units;

[0063] Step S408: For each of the 2nd to mth operators among the m operators, send the i-th operator and the (i-1)th first result to the target encryption calculation unit for calculation, and save the calculation result returned by the target encryption calculation unit as the i-th first result, where i=2,...,m, and the (i-1)th first result is the calculation result of the target encryption calculation unit on the (i-1)th operator.

[0064] In this embodiment, the microprocessor is connected to n encrypted computing units, where n is a positive integer.

[0065] In this embodiment of the application, by using the above steps S402 to S410, the problem that the hardware implementation of encryption algorithms with fixed input data length cannot be reused and reconstructed in the related art can be solved. By using the microprocessor to interact with the encryption computing unit, the reusability of the encryption computing unit is improved, hardware resources are saved, and the hardware algorithm has the advantage of faster calculation and running speed.

[0066] In one exemplary embodiment, the data to be processed can be the input data to be encrypted, and the key is a first key, which is an internal padding key of a second preset length generated based on the input initial key.

[0067] In another exemplary embodiment, the data to be processed may be the encryption result calculated by a secure hash algorithm on the input data to be encrypted and the first key, and the key may be a second key. The first key and the second key are respectively an inner padding key and an outer padding key of a second preset length generated based on the input initial key.

[0068] Furthermore, the method further includes: generating second target data based on the m-th first result and the second key, wherein the second target data consists of l operators, each operator corresponding to data of a first preset length, where l is an integer greater than 1; sending the first operator among the l operators to the target encryption computing unit for calculation, and saving the calculation result returned by the target encryption computing unit as the first second result; for each operator among the 2nd to the l-th operators, sending the j-th operator and the (j-1)-th second result to the target encryption computing unit for calculation, and saving the calculation result returned by the target encryption computing unit as the j-th second result, where j=2,...,l, and the (j-1)-th second result is the calculation result of the target encryption computing unit performing the calculation on the (j-1)-th operator.

[0069] The data encryption method used in this application combines HMAC (Keyed-Hashing for Message Authentication) with a fixed-input-length encryption algorithm, such as SHA-2 (Secure Hash Algorithm 2). The HMAC-SHA-2 algorithm requires first performing SHA-2 calculation on the input data and the internal padding key, and then performing SHA-2 calculation on the result and the external padding key. That is, it corresponds to the method in the above embodiment that first performs encryption operation on the first key and the data to be encrypted (first target data), and then performs encryption operation on the encryption result and the external padding key (second target data).

[0070] In this embodiment, the microprocessor can extract the data to be processed and the key into operators, and then send the operators to the SHA-2 computing unit implemented in hardware. This eliminates the need for additional design of the SHA-2 computing unit, improving its reusability. Furthermore, this embodiment overcomes the limitation of the SHA-2 computing unit, which can only perform algorithmic calculations on input data of a fixed length. Even when processing very long input data, it can save significant hardware resources.

[0071] In an exemplary embodiment, step S404 may include the following steps:

[0072] Step S4042: Concatenate the data to be processed and the key to obtain the first concatenated data;

[0073] Step S4044: Fill the first spliced ​​data with data to obtain the first target data.

[0074] In one exemplary embodiment, the first key can be obtained by the following method:

[0075] If the length of the initial key is greater than the second preset length, the initial key is sent to one of the n encryption calculation units for calculation to obtain an intermediate key of the second preset length.

[0076] The first key is obtained by performing an XOR operation between the intermediate key and a preset internal padding sequence.

[0077] In another exemplary embodiment, the first key and the second key can be obtained by the following method:

[0078] If the length of the initial key is greater than the second preset length, the initial key is sent to one of the n encryption computing units for calculation to obtain the intermediate key of the second preset length.

[0079] The first key is obtained by performing an XOR operation between the intermediate key and a preset internal padding sequence.

[0080] The intermediate key is XORed with a preset external padding sequence to obtain the second key.

[0081] In one exemplary embodiment, the inner pad (ipad) is a fixed-length byte sequence filled with 0x36 (hexadecimal), that is, 0x36 is repeated multiple times until a first preset length is reached. The outer pad (opad) is similar to the inner pad, filled with 0x5C (hexadecimal), that is, 0x5C is repeated multiple times until the first preset length is reached.

[0082] In one exemplary embodiment, the encryption calculation unit may be a secure hash algorithm SHA-2 calculation unit.

[0083] Furthermore, when the SHA-2 calculation unit calculates the first operator among the m operators, a preset initial hash constant is used as the initial hash value of the secure hash algorithm; when the SHA-2 calculation unit calculates the ith operator among the m operators, the (i-1)th first result is used as the initial hash value of the secure hash algorithm.

[0084] In an exemplary embodiment, step S4044 may include: converting the total length of the first spliced ​​data into first length information of a third preset length; adding a suffix identifier, multiple preset padding characters, and the first length information sequentially after the first spliced ​​data to fill the data, thereby obtaining the first target data, wherein the length of the first target data is m times the first preset length.

[0085] In an exemplary embodiment, when the SHA-2 computation unit is an SHA-256 computation unit, the first preset length is 256 bits, the second preset length is 512 bits, the third preset length is 64 bits, the bit end identifier is 1, and the preset padding character is 0. The first target data consists of input data (length less than 2^64 bits), an internal padding key (256 bits), a 1 (bit end identifier), multiple 0s (preset padding characters), and 64 bits of first length information.

[0086] In an exemplary embodiment, the specific steps for generating the second target data based on the m-th first result and the second key are similar to the steps for generating the first target data in the above embodiment. It is also obtained by splicing and data filling, except that the data to be encrypted is replaced with the m-th first result obtained by iterative processing of the first target data.

[0087] Figure 5 This is a flowchart illustrating data encryption processing based on the HMAC-SHA-2 algorithm according to an embodiment of this application, applied to a microprocessor, such as... Figure 5 As shown, the specific steps may include:

[0088] Step S502: Obtain input data and initial key, and process the initial key into an internal padding key and an external padding key of a second preset length;

[0089] Step S504: Concatenate the input data and the internal padding key to obtain the first concatenated data, and pad the first concatenated data to obtain the first target data including multiple operators, wherein each operator corresponds to data of a first preset length;

[0090] Step S506: Send the first target data to the SHA-2 secure hash algorithm calculation unit, and receive the encryption result obtained by the SHA-2 calculation unit through iterative SHA-2 calculation of the first target data;

[0091] Step S508: Concatenate the encryption result and the external padding key to obtain the second concatenated data, and pad the second concatenated data to obtain the second target data containing multiple operators;

[0092] Step S510: Send the second target data to the SHA-2 calculation unit and receive the output data obtained by the SHA-2 calculation unit through iterative SHA-2 calculation of the second target data.

[0093] In this embodiment of the application, by using the above steps S502 to S510, the problem that the hardware implementation of encryption algorithms with fixed input data length cannot be reused and reconstructed in the related technology can be solved. By using the microprocessor to interact with the SHA-2 computing unit, the SHA-2 computing unit can be reused multiple times, which saves hardware resources and has the advantage of faster hardware algorithm calculation speed.

[0094] In this embodiment, the encryption result in step S506 is equivalent to the m-th first result in the above embodiment, processed by m iterations of the SHA-2 algorithm. The output data in step S510 is equivalent to the l-th second result in the above embodiment, processed by l iterations. m and l are the number of fixed-length operators.

[0095] The data encryption processing method used in this application combines HMAC (Keyed-Hashing for Message Authentication) and SHA-2 (Secure Hash Algorithm 2). The microprocessor extracts the input data and key into operators, and then sends the operators to the SHA-2 calculation unit implemented in hardware. No additional design is required for the SHA-2 calculation unit, which improves the reusability of the SHA-2 calculation unit.

[0096] In related technologies, the hardware implementation of the SHA-2 algorithm only processes data with a fixed input length (i.e., the first preset length). The method in this application embodiment can overcome the shortcoming that the SHA-2 computing unit can only perform algorithm calculations on input data of a fixed length. Even if very long input data needs to be processed, a lot of hardware resources can be saved.

[0097] In this embodiment, the SHA-2 algorithm can convert an input message of any finite length (less than 2^64 bits) into a fixed-length message digest. The SHA-2 algorithm is further divided into four types based on the length of the output message digest: SHA-224, SHA-256, SHA-384, and SHA-512. The second preset length in step S402 is the length of the message digest output by the SHA-2 calculation unit.

[0098] In one exemplary embodiment, the SHA-2 calculation unit is an SHA-256 calculation unit, and the length of the output data is 256 bits, that is, the second preset length is 256 bits.

[0099] In another exemplary embodiment, in a hardware implementation method of the SHA-256 computing unit, the first preset length is 512 bits, meaning the microprocessor can only perform encryption operations on input data of length 512 bits at a time. Through the microprocessor's preprocessing of the input data, it is possible to split data of arbitrary length into operators of fixed length, and then send the operators into the SHA-256 computing unit.

[0100] In an exemplary embodiment, step S502, which processes the initial key into an inner padding key and an outer padding key of a second preset length, may include the following steps:

[0101] Step S5022: Process the initial key into an intermediate key of the second preset length;

[0102] Step S5024: Perform an XOR operation between the intermediate key and the preset internal padding sequence to obtain the internal padding key;

[0103] Step S5026: Perform an XOR operation between the intermediate key and a preset external padding sequence to obtain the external padding key.

[0104] In this embodiment, the inner padding sequence in step S5024 and the outer padding sequence in step S5026 are of a second preset length.

[0105] In one exemplary embodiment, the inner pad (ipad) is a fixed-length byte sequence filled with 0x36 (hexadecimal), that is, 0x36 is repeated multiple times until a second preset length is reached. The outer pad (opad) is similar to the inner pad sequence, filled with 0x5C (hexadecimal), that is, 0x5C is repeated multiple times until a second preset length is reached.

[0106] In one exemplary embodiment, step S5022 may include any of the following:

[0107] If the length of the initial key is less than the second preset length, the initial key is padded to the second preset length using multiple preset padding characters to obtain the intermediate key;

[0108] If the length of the initial key is greater than the second preset length, the initial key is sent to the SHA-2 calculation unit for calculation, and the intermediate key obtained by the SHA-2 calculation unit on the initial key is received.

[0109] If the length of the initial key is equal to the second preset length, the initial key is directly used as the intermediate key.

[0110] In one exemplary embodiment, the preset padding character can be 0, and the initial key, which is shorter than the second preset length, is padded to the second preset length by adding 0 after the initial key.

[0111] In an exemplary embodiment, step S504, which involves filling the first spliced ​​data to obtain first target data including multiple operators, may include the following steps:

[0112] Step S5042: Convert the total length of the first spliced ​​data into first length information of a third preset length;

[0113] Step S5044: After the first concatenated data, add a suffix identifier, multiple preset padding characters and the first length information in sequence to fill the data to obtain the first target data, wherein the length of the first target data is an integer multiple of the second preset length.

[0114] In an exemplary embodiment, when the SHA-2 computation unit is an SHA-256 computation unit, the second preset length is 256 bits, the second preset length is 512 bits, the third preset length is 64 bits, the bit end identifier is 1, and the preset padding character is 0. The first target data consists of input data (length less than 2^64 bits), an internal padding key (256 bits), a 1 (bit end identifier), multiple 0s (preset padding characters), and 64 bits of first length information.

[0115] Furthermore, step S5044 fills the data to an integer multiple of 512 bits by padding multiple zeros between the bit end identifier and the first length information, thus obtaining the first target data.

[0116] In an exemplary embodiment, a microprocessor can perform data padding processing in steps S5042 to S5044 on input data of arbitrary length to obtain multiple operators of fixed length. These multiple operators are then sequentially fed into the SHA-2 computing unit for iterative calculation, thereby solving the problem in the related art that the SHA-2 computing unit can only process data of fixed length.

[0117] In an exemplary embodiment, step S406 may include the following steps:

[0118] Step S5062: Divide the first target data into multiple operators;

[0119] Step S5064: Send the first operator in the first target data and the preset initial hash constant to the SHA-2 calculation unit, and receive the calculation result obtained by the SHA-2 calculation unit on the first operator in the first target data, wherein the calculation result is the second preset length;

[0120] Step S5066: The calculation result of the previous round of SHA-2 calculation is used as the hash constant for the new round of SHA-2 calculation. The next operator in the first target data and the hash constant are sent to the SHA-2 calculation unit for the new round of SHA-2 calculation. This continues until the last operator in the first target data is sent to the SHA-2 calculation unit. The encryption result obtained by the SHA-2 calculation unit on the last operator in the first target data is received.

[0121] In an exemplary embodiment, the input data length (i.e., the first preset length) of the SHA-2 computing unit is 512 bits, and the microprocessor can send a 512-bit operator into the SHA-256 computing unit for calculation at a time.

[0122] In an exemplary embodiment, in the SHA-256 calculation unit, the preset initial hash constant is eight 32-bit constants, including: 0x6a09e667, 0xbb67ae85, 0x3c6ef372, 0xa54ff53a, 0x510e527f, 0x9b05688c, 0x1f83d9ab, and 0x5be0cd19.

[0123] Furthermore, the 256-bit result from the previous SHA-256 calculation can be divided into eight 32-bit data sets and used as the hash constant for the next round of SHA-256 calculations, thus enabling iterative processing of multiple operators. N operators require N rounds of SHA-256 calculations.

[0124] In an exemplary embodiment, step S508, which involves filling the second spliced ​​data to obtain second target data containing multiple operators, may include the following steps:

[0125] Step S5082: Convert the total length of the second spliced ​​data into second length information of a third preset length;

[0126] Step S5084: After the second concatenation data, add a suffix identifier, multiple preset padding characters and the second length information in sequence to fill the data to obtain the second target data, wherein the length of the second target data is an integer multiple of the first preset length.

[0127] In an exemplary embodiment, step S510 may include the following steps:

[0128] Step S5102: The second target data is split into multiple operators;

[0129] Step S5104: Send the first operator in the second target data and the preset initial hash constant to the SHA-2 calculation unit, and receive the calculation result obtained by the SHA-2 calculation unit on the first operator in the third target data, wherein the calculation result is the second preset length;

[0130] Step S5106: The calculation result of the previous round of SHA-2 calculation is used as the hash constant for the new round of SHA-2 calculation, and the next operator in the second target data and the hash constant are sent to the SHA-2 calculation unit to perform a new round of SHA-2 calculation until the last operator in the second target data is sent to the SHA-2 calculation unit, and the output data obtained by the SHA-2 calculation unit on the last operator in the second target data is received.

[0131] In this embodiment, the specific implementation methods of steps S504 and S508 are basically the same, and the specific implementation methods of steps S506 and S510 are basically the same.

[0132] In this embodiment of the application, the interaction between the microprocessor and the SHA-2 computing unit can improve the reusability of the SHA-2 computing unit. Only one SHA-2 computing unit is needed to realize the entire data encryption process of the HMAC-SHA2 algorithm, which not only ensures the hardware implementation of the HMAC-SHA2 algorithm, but also reduces resource consumption.

[0133] Figure 6 This is a flowchart illustrating a data encryption method based on SHA-256 according to an embodiment of this application. Figure 6 As shown, embodiments of this application can convert input messages of any finite length (length less than 2^64 bits) into message digests of 256 bits in length.

[0134] In this embodiment, the input message first needs to be padded with data to a length that is an integer multiple of 512 bits.

[0135] Specifically, you can add a 1 to the end of the input message, and the last 64 bits of the data block represent the total length of the original data. Then, pad the data block with multiple 0s between the added 1 and the 64-bit total length, making the data block a multiple of 512 bits. Alternatively, you can first add a 1 to the end of the input message, then add several 0s until the message length is a remainder of 448 when divided by 512. Then, add the remaining 64 bits of the original data length to the end, thus making the data block a multiple of 512 bits.

[0136] In this embodiment, the padded data block also needs to be split into n operators, each operator being 512 bits. However, this application is not limited to this; the length of the operators can be adjusted according to the requirements of the input data length in the algorithm hardware implementation.

[0137] In this embodiment, SHA-256 calculation needs to be performed sequentially on each group of 512-bit data (operators).

[0138] Specifically, when performing SHA-256 calculation on the first operator M1, the first operator M1 and H0 (hash constant) need to be input into the SHA-256 calculation unit to obtain the calculation result H1. When performing SHA-256 calculation on the second operator M2, the second operator M2 and the calculation result H1 from the previous round need to be input into the SHA-256 calculation unit to obtain the calculation result H2. This process is repeated multiple times until the last operator Mn and the calculation result Hn-1 from the previous round are input into the SHA-256 calculation unit to obtain the final result Hn.

[0139] In this embodiment, the data padding process and data interaction with the SHA-256 calculation unit are both implemented by a microprocessor. This embodiment allows for SHA-256 calculation of data of arbitrary length, but it is not limited to the SHA-256 algorithm; it can also be applied to algorithms such as SHA-224, SHA-384, and SHA-512.

[0140] According to another aspect of the embodiments of this application, a data encryption processing apparatus is also provided.

[0141] Figure 7 This is a structural block diagram (a) of a data encryption processing device according to an embodiment of this application, as shown below. Figure 7 As shown, the device includes:

[0142] The system includes a microprocessor 72 and n encrypted computing units 74. n is a positive integer.

[0143] In an exemplary embodiment, a microprocessor 72 is configured to acquire data to be processed and a key, and generate first target data based on the data to be processed and the key, wherein the first target data consists of m operators, each operator corresponding to data of a first preset length, and m is an integer greater than 1; send the first operator of the m operators to a target encryption computing unit for calculation, and save the calculation result returned by the target encryption computing unit as the first first result, wherein the target encryption computing unit is any one of the n encryption computing units; for each operator from the second to the mth operator of the m operators, send the i-th operator and the (i-1)-th first result to the target encryption computing unit for calculation, and save the calculation result returned by the target encryption computing unit as the i-th first result, wherein i=2,...,m, and the (i-1)-th first result is the calculation result of the target encryption computing unit on the (i-1)-th operator;

[0144] In an exemplary embodiment, the encryption calculation unit 74 is configured to receive each of the first to m-th operators and the first to m-1-th first results sent by the microprocessor, perform encryption calculations on each operator respectively, and send the calculation results to the microprocessor.

[0145] In one exemplary embodiment, the encryption calculation unit is a hardware structure with a fixed input data length, such as a SHA-2 calculation unit.

[0146] Furthermore, the SHA-2 algorithm is further divided into four types based on the length of the output message digest: SHA-224, SHA-256, SHA-384, and SHA-512. The second preset length is the length of the message digest output by the SHA-2 computation unit. Taking the SHA-256 computation unit as an example, the length of the output data is 256 bits, that is, the second preset length is 256 bits.

[0147] In an exemplary embodiment, the microprocessor 72 is further configured to process the initial key into an intermediate key of the second preset length; perform an XOR operation on the intermediate key and a preset internal padding sequence to obtain the internal padding key; and perform an XOR operation on the intermediate key and a preset external padding sequence to obtain the external padding key, wherein the internal padding sequence and the external padding sequence are of the second preset length.

[0148] In one exemplary embodiment, the inner pad (ipad) is a fixed-length byte sequence filled with 0x36 (hexadecimal), that is, 0x36 is repeated multiple times until a second preset length is reached. The outer pad (opad) is similar to the inner pad sequence, filled with 0x5C (hexadecimal), that is, 0x5C is repeated multiple times until a second preset length is reached.

[0149] In an exemplary embodiment, the microprocessor 72 is further configured to: when the length of the initial key is less than the second preset length, fill the initial key to the second preset length with a plurality of preset padding characters to obtain the intermediate key; when the length of the initial key is greater than the second preset length, send the initial key to the encryption calculation unit for calculation, and receive the intermediate key obtained by the encryption calculation unit through encryption calculation of the initial key; and when the length of the initial key is equal to the second preset length, directly use the initial key as the intermediate key.

[0150] Furthermore, the preset padding character can be 0, which is used to pad the initial key (which is shorter than the second preset length) to the second preset length by adding 0 after the initial key.

[0151] In an exemplary embodiment, the microprocessor 72 is further configured to convert the total length of the first spliced ​​data into first length information of a third preset length; and to add a suffix identifier, a plurality of preset padding characters and the first length information sequentially after the first spliced ​​data to fill the data, thereby obtaining the first target data, wherein the length of the first target data is an integer multiple of the first preset length.

[0152] In an exemplary embodiment, the microprocessor 72 is further configured to: split the first target data into multiple operators; send the first operator in the first target data and a preset initial hash constant to the encryption calculation unit, and receive the calculation result obtained by the encryption calculation unit performing encryption calculation on the first operator in the first target data, wherein the calculation result is the second preset length; use the calculation result of the previous round of encryption calculation as the hash constant for the new round of encryption calculation, and send the next operator in the first target data and the hash constant to the encryption calculation unit for the new round of encryption calculation, until the last operator in the first target data is sent to the encryption calculation unit, and receive the encryption result obtained by the encryption calculation unit performing encryption calculation on the last operator in the first target data.

[0153] In an exemplary embodiment, the microprocessor 72 is further configured to convert the total length of the second spliced ​​data into second length information of a third preset length; and to add a suffix identifier, a plurality of preset padding characters and the second length information sequentially after the second spliced ​​data to fill the data, thereby obtaining the second target data, wherein the length of the second target data is an integer multiple of the first preset length.

[0154] In an exemplary embodiment, the microprocessor 72 is further configured to: split the second target data into multiple operators; send the first operator in the second target data and a preset initial hash constant to the encryption calculation unit; and receive the calculation result obtained by the encryption calculation unit performing encryption calculation on the first operator in the third target data, wherein the calculation result is the second preset length; use the calculation result of the previous round of encryption calculation as the hash constant for the new round of encryption calculation; and send the next operator in the second target data and the hash constant to the encryption calculation unit for the new round of encryption calculation, until the last operator in the second target data is sent to the encryption calculation unit, and receive the output data obtained by the encryption calculation unit performing encryption calculation on the last operator in the second target data.

[0155] In this embodiment of the application, the interaction between the microprocessor and the encryption computing unit can improve the reusability of the encryption computing unit. Taking the HMAC-SHA2 algorithm as an example, only one SHA-2 computing unit is needed to realize the entire data encryption process of the HMAC-SHA2 algorithm, which not only ensures the hardware implementation of the HMAC-SHA2 algorithm, but also reduces resource consumption.

[0156] Figure 8 This is a structural block diagram (II) of a data encryption processing device according to an embodiment of this application, as shown below. Figure 8 As shown, the device includes:

[0157] The system includes a microprocessor 72, n encrypted computing units 74, and a scheduling module 86. n is a positive integer.

[0158] The scheduling module 86 is located between the microprocessor 72 and the n encrypted computing units 74.

[0159] In one exemplary embodiment, the scheduling module is configured to schedule multiple encrypted computing units for parallel processing when the microprocessor simultaneously acquires multiple pieces of data to be processed, wherein each piece of data to be processed corresponds to one encrypted computing unit.

[0160] Furthermore, if a microprocessor needs to perform HMAC-SHA2 calculations on multiple messages simultaneously and has requirements for computation speed, the computation speed can be improved by cascading multiple SHA-2 computation units and using a scheduling module to schedule these units for parallel processing. Each SHA-2 computation unit can only perform encryption calculations on one message at a time, and multiple operators split from the same message are iteratively calculated within the same SHA-2 computation unit.

[0161] Figure 9 This is a structural block diagram of a microprocessor for data encryption processing according to an embodiment of this application, such as... Figure 9 As shown, a microprocessor may include:

[0162] The instruction unit 92, the computing unit 94, and the data storage unit 96.

[0163] In one exemplary embodiment, the instruction unit 92 is used to issue control instructions, such as storage instructions and calculation instructions, to the computing unit 94 and the data storage unit 96. The instruction unit 92 can decompose the microprocessor processing steps in any of the above embodiments and control the computing unit 94 and the data storage unit 96 to jointly complete the data encryption processing flow in the form of instructions.

[0164] In an exemplary embodiment, the computing unit 94 is configured to generate the first target data based on the data to be processed and the key under the control of the computing instruction.

[0165] In one exemplary embodiment, the computing unit 94 is further configured to perform computational tasks required by the microprocessor under the control of the instruction unit 92. These tasks may include key processing, data padding, and operator splitting.

[0166] In an exemplary embodiment, the data storage unit 96 is configured to read and write the data to be processed, the key, the first target data, and the calculation results returned by the target encryption calculation unit under the control of the read / write instruction, wherein the calculation results include the first to the mth first results.

[0167] In an exemplary embodiment, the data storage unit 96 is further used to store data that participates in or is generated during the data encryption process. The data storage unit 96 can be divided into three parts: a key, a response, and a message.

[0168] Furthermore, the key is used to store the initial key, the internal padding key, the external padding key, and the intermediate key; the response is used to store the calculation results returned by the encryption calculation unit after performing encryption calculations on each operator, such as H1 to Hn; and the message is used to store the input data, the first concatenation data, the second concatenation data, and multiple operators.

[0169] In one exemplary embodiment, taking the SHA-256 algorithm as an example, the input data message is temporarily stored in the microprocessor, and the key can be stored in the microprocessor either directly input or as a command. The microprocessor determines whether to perform SHA-256 calculation based on the length of the key. If not, it padded the key with 0s to 256 bits to generate a new key; if so, it sends the key to the interactive SHA-256 calculation unit, and upon receiving the calculation result, replaces the original key with the new key.

[0170] In an exemplary embodiment, the microprocessor performs an XOR operation on the new key with 256'h3636...36 and 256'h5C5C...5C respectively to obtain the internal padding key ipadkey and the external padding key opadkey, and temporarily stores the calculation results in the microprocessor.

[0171] In one exemplary embodiment, the microprocessor concatenates the message and iPad key, stores them again, and performs SHA-256 data padding on the concatenated data. This involves adding a 1 bit to the end of the data bits, with the last 64 bits of the data block representing the total length of the original data. Then, zeros are used to pad the data between the added 1 and the total length of the 64 bits, ensuring the data length is a multiple of 512 bits. Each 512 bits is called an operator and is stored in the microprocessor.

[0172] In an exemplary embodiment, the microprocessor sequentially performs the following steps: First, it sends the first operator to the SHA-256 calculation unit for computation. The hash constant H0 corresponding to the first computation is the initial hash constant, and the calculated result H1 is returned to the microprocessor as a response (rsp) for storage. In the second computation, the microprocessor uses the previous round's response rsp as the initial hash value for this round, along with the second operator, and sends it to the SHA-256 calculation unit for computation. The result is then returned and stored in the microprocessor. In the third computation, the microprocessor uses the previous round's response rsp as the initial hash value, along with the third operator, and sends it to the SHA-256 calculation unit for computation. This process iterates until the original input data (message and iPad key) are computed using SHA-256, and the result is stored as a new message.

[0173] In one exemplary embodiment, the microprocessor also needs to concatenate the new message with the opadkey and perform the SHA-256 iterative calculation process described above again to obtain the final output data (result) and output it.

[0174] In one exemplary embodiment, when multiple messages need to be processed, the microprocessor needs to allocate corresponding space for each message and associate and identify each data and space through the thread number in the microprocessor. When processing data from multiple threads, each thread can issue a SHA-2 computation request. At this time, the scheduling module sends these computation requests and thread numbers together to the corresponding SHA-2 computation unit. When returning the computation result (rsp), the thread number previously sent to the computation unit is also returned. The scheduling module then identifies the returned thread number and stores it in the rsp space corresponding to that thread number.

[0175] Through the embodiments of this application, HMAC-SHA2 algorithm calculations can be performed simultaneously on multiple sets of data, improving the calculation speed. This application also allows for the selection of the number of cascaded SHA-2 calculation units according to specific computational needs, exhibiting strong reconfigurability.

[0176] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is executed by a processor to perform the steps in any of the above method embodiments.

[0177] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0178] Embodiments of this application also provide an electronic device including a memory and a processor, the memory storing a computer program and the processor being configured to run the computer program to perform the steps in any of the above method embodiments.

[0179] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0180] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0181] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0182] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A data encryption processing method, characterized in that, Applied to a microprocessor, wherein the microprocessor is connected to n encrypted computing units, where n is a positive integer, the method includes: Obtain the data to be processed and the key; First target data is generated based on the data to be processed and the key, wherein the first target data consists of m operators, each operator corresponds to data of a first preset length, and m is an integer greater than 1; The first operator among the m operators is sent to the target encryption computing unit for calculation, and the calculation result returned by the target encryption computing unit is saved as the first first result, wherein the target encryption computing unit is any one of the n encryption computing units; For each of the 2nd to the mth operators among the m operators, the i-th operator and the (i-1)th first result are sent to the target encryption calculation unit for calculation, and the calculation result returned by the target encryption calculation unit is saved as the i-th first result, where i = 2,...,m, and the (i-1)th first result is the calculation result of the target encryption calculation unit on the (i-1)th operator.

2. The method according to claim 1, characterized in that, The data to be processed is the input data to be encrypted, and the key is a first key, which is an internal padding key of a second preset length generated based on the input initial key.

3. The method according to claim 1, characterized in that, The data to be processed is the encryption result calculated by using a secure hash algorithm on the input data to be encrypted and the first key. The key is a second key, wherein the first key and the second key are respectively an inner padding key and an outer padding key of a second preset length generated based on the input initial key.

4. The method according to claim 2, characterized in that, The method further includes: The second target data is generated based on the m-th first result and the second key, wherein the second target data consists of l operators, each operator corresponding to data of a first preset length, and l is an integer greater than 1; The first operator among the l operators is sent to the target encryption calculation unit for calculation, and the calculation result returned by the target encryption calculation unit is saved as the first second result; For each of the 2nd to 1st operators among the l operators, the jth operator and the (j-1)th second result are sent to the target encryption calculation unit for calculation, and the calculation result returned by the target encryption calculation unit is saved as the jth second result, where j = 2,...,l, and the (j-1)th second result is the calculation result of the target encryption calculation unit on the (j-1)th operator.

5. The method according to claim 1, characterized in that, Generate first target data based on the data to be processed and the key, including: The data to be processed and the key are concatenated to obtain the first concatenated data; The first spliced ​​data is filled with data to obtain the first target data.

6. The method according to claim 2, characterized in that, The method further includes: If the length of the initial key is greater than the second preset length, the initial key is sent to one of the n encryption calculation units for calculation to obtain an intermediate key of the second preset length. The first key is obtained by performing an XOR operation between the intermediate key and a preset internal padding sequence.

7. The method according to claim 3, characterized in that, The method further includes: If the length of the initial key is greater than the second preset length, the initial key is sent to one of the n encryption calculation units for calculation to obtain an intermediate key of the second preset length. The first key is obtained by performing an XOR operation between the intermediate key and a preset internal padding sequence. The intermediate key is XORed with a preset external padding sequence to obtain the second key.

8. The method according to claim 1, characterized in that, The method further includes: The encryption calculation unit is a secure hash algorithm SHA-2 calculation unit; When the SHA-2 calculation unit calculates the first operator among the m operators, the preset initial hash constant is used as the initial hash value of the secure hash algorithm; When the SHA-2 calculation unit calculates the i-th operator among the m operators, the (i-1)-th first result is used as the initial hash value of the secure hash algorithm.

9. The method according to claim 5, characterized in that, The first spliced ​​data is filled with data to obtain the first target data, including: The total length of the first spliced ​​data is converted into first length information of a third preset length; After the first concatenated data, a tail identifier, multiple preset padding characters, and the first length information are added sequentially to fill the data, thereby obtaining the first target data, wherein the length of the first target data is m times the first preset length.

10. A data encryption processing device, characterized in that, The device includes: A microprocessor and n encrypted computing units, where n is a positive integer; The microprocessor is configured to acquire data to be processed and a key, and generate first target data based on the data to be processed and the key. The first target data consists of m operators, each corresponding to data of a first preset length, where m is an integer greater than 1. The microprocessor sends the first operator among the m operators to a target encryption computing unit for calculation, and saves the calculation result returned by the target encryption computing unit as the first first result. The target encryption computing unit is any one of the n encryption computing units. For each operator from the 2nd to the mth operator among the m operators, the microprocessor sends the ith operator and the (i-1)th first result to the target encryption computing unit for calculation, and saves the calculation result returned by the target encryption computing unit as the ith first result. Here, i = 2,...,m, and the (i-1)th first result is the calculation result of the target encryption computing unit on the (i-1)th operator. The encryption calculation unit is used to receive each of the first to m-th operators and the first to m-1 first results sent by the microprocessor, perform encryption calculations on each operator respectively, and send the calculation results to the microprocessor.

11. The apparatus according to claim 10, characterized in that, The device further includes: The scheduling module is used to schedule multiple encrypted computing units for parallel processing when the microprocessor simultaneously acquires multiple pieces of data to be processed, wherein each piece of data to be processed corresponds to one encrypted computing unit.

12. The apparatus according to claim 10, characterized in that, The microprocessor includes: The instruction unit is used to issue control instructions to the computing unit and the data storage unit, wherein the control instructions include computing instructions and read / write instructions; A computing unit is configured to generate the first target data based on the data to be processed and the key under the control of the computing instructions. The data storage unit is used to read and write the data to be processed, the key, the first target data, and the calculation results returned by the target encryption calculation unit under the control of the read and write instructions, wherein the calculation results include the first to the mth first results.

13. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, wherein the computer program is executed by a processor to perform the method described in any one of claims 1 to 9.

14. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to run the computer program to perform the method of any one of claims 1 to 9.

Images