Reference voltage circuit and semiconductor device

Abstract

A reference voltage circuit and a semiconductor device. The reference voltage circuit includes a depletion-mode transistor as a current source and an enhancement-mode transistor as a load, and includes a plurality of transistors. The plurality of transistors include the depletion-mode transistor configured by connecting at least one depletion-mode transistor including a first depletion-mode transistor, and the enhancement-mode transistor configured by connecting at least one enhancement-mode transistor including a first enhancement-mode transistor connected in series with the first depletion-mode transistor. The plurality of transistors in which the depletion-mode transistors and the enhancement-mode transistors are mixed are arranged so as to share a common center of mass. The common center of mass is a common center of gravity.

Description

[0001] This application is a divisional application of an invention patent application with an application date of May 30, 2018, application number 201810535941.3, and invention name “Reference voltage circuit and semiconductor device”. Technical Field

[0002] The present invention relates to a reference voltage circuit and a semiconductor device. Background Art

[0003] As a reference voltage circuit, it is known that Figure 7 The reference voltage circuit 700 shown is a combination of a depletion-mode transistor and an enhancement-mode transistor (see, for example, Japanese Unexamined Patent Application Publication No. 2012-531825).

[0004] The reference voltage circuit 700 includes a depletion-mode transistor 710 , an enhancement-mode transistor 720 , and a terminal 730 for outputting a reference voltage VREF.

[0005] Reference Figure 8 , the operation of the reference voltage circuit 700 is described. When the threshold voltage of the transistor 710 is VTND, the relationship between the voltage and the current of the transistor 710 is represented by the characteristic 801. When the threshold voltage of the transistor 720 is VTNE, the relationship between the voltage and the current of the transistor 720 is represented by the characteristic 802. The voltage generated by the current equal to the intercept value of the characteristic 801 flowing into the enhancement transistor 720 is output to the terminal 730 as the reference voltage VREF.

[0006] Patent Document 1: Japanese Patent Application No. 2012-531825 Summary of the invention

[0007] Generally speaking, it is known that semiconductor devices have characteristics that vary due to the influence of stress generated by resin sealing (packaging).

[0008] For example, when a semiconductor device in which transistors 710 and 720 are arranged in the x-axis direction is sealed with resin, stress is applied in the x-axis direction, and the characteristics of transistors 710 and 720 may deviate. That is, characteristics 801 and 802 may deviate from desired characteristics.

[0009] The present invention is made in order to avoid the influence of characteristic variation caused by stress such as resin sealing of a semiconductor device, and to provide a semiconductor device having a reference voltage circuit with little product variation.

[0010] Means for solving problems

[0011] The reference voltage circuit of the present invention is characterized in that the depletion-type transistor and / or the enhancement-type transistor is composed of a plurality of transistors, and the depletion-type transistor and the enhancement-type transistor are arranged in a common centroid manner, and the common centroid is a common center of gravity.

[0012] Effects of the Invention

[0013] According to the reference voltage circuit of the present invention, it is possible to provide a semiconductor device including the reference voltage circuit which is free from the influence of characteristic variation due to stress such as resin sealing of a conductor device and has little product variation. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is an explanatory diagram showing a reference voltage circuit according to the first embodiment of the present invention.

[0015] Figure 2 It is an explanatory diagram showing another example of the reference voltage circuit according to the first embodiment.

[0016] Figure 3 It is an explanatory diagram showing another example of the reference voltage circuit according to the first embodiment.

[0017] Figure 4 It is an explanatory diagram showing another example of the reference voltage circuit according to the first embodiment.

[0018] Figure 5 It is an explanatory diagram showing another example of the reference voltage circuit according to the first embodiment.

[0019] Figure 6 It is an explanatory diagram showing a reference voltage circuit according to a second embodiment of the present invention.

[0020] Figure 7 : is a circuit diagram showing a general reference voltage circuit.

[0021] Figure 8 yes Figure 7 Schematic diagram illustrating the operation of the reference voltage circuit.

[0022] Description of symbols

[0023] 110, 210, 410, 610: depletion-mode transistors; 120, 220, 420, 620: enhancement-mode transistors; 640, 650: transistors; 130: terminal. DETAILED DESCRIPTION

[0024] Figure 1 It is an explanatory diagram showing a reference voltage circuit according to the first embodiment of the present invention.

[0025] The reference voltage circuit 100 includes a depletion-mode transistor 110 , an enhancement-mode transistor 120 , and a terminal 130 for outputting a reference voltage VREF.

[0026] The transistor 110 is formed by connecting two depletion-mode transistors 111 and 112 in series. The transistor 120 is formed by connecting two enhancement-mode transistors 121 and 122 in series.

[0027] The reference voltage circuit 100 operates in the same manner as a general reference voltage circuit including a depletion-mode transistor 110 and an enhancement-mode transistor 120 , and outputs a reference voltage VREF to a terminal 130 .

[0028] Here, the transistor 111 and the transistor 112 of the reference voltage circuit 100 have the same size (W length and L length), and the transistor 121 and the transistor 122 have the same size (W length and L length). Figure 1 As shown, the transistors 111, 112, 121, and 122 are arranged to have a substantially common centroid (a common center of gravity) on the semiconductor device.

[0029] That is, the transistors 111, 112, 121, and 122 are arranged in point symmetry to achieve a common center of mass (common center of gravity).

[0030] In the reference voltage circuit 100 configured as described above, even if the characteristics of the transistors change in the x-axis direction or the y-axis direction due to stress from resin sealing or the like, the transistors 110 and 120 are affected in the same manner. Therefore, the transistors 110 and 120 can produce the same characteristic changes, thereby having an effect of reducing the deviation of the characteristics after the change from the desired voltage-current characteristics.

[0031] As described above, in the reference voltage circuit 100, the transistor 110 and the transistor 120 are arranged in a manner that has a substantially common centroid on the semiconductor device, thereby providing a semiconductor device having a reference voltage circuit that avoids the influence of characteristic changes caused by stress such as resin sealing of the semiconductor device and has little product variation.

[0032] Figure 2 It is an explanatory diagram showing another example of the reference voltage circuit according to the first embodiment.

[0033] In the reference voltage circuit 200 , the depletion mode transistor 210 and the enhancement mode transistor 220 are each constituted by three transistors.

[0034] The transistor 210 is formed by connecting three depletion-mode transistors 211, 212, and 213 in series. The transistor 220 is formed by connecting three transistors 221, 222, and 223 in series.

[0035] Here, each transistor is configured similarly to the reference voltage circuit 100. Figure 2 As shown in the figure, the reference voltage circuit 200 is arranged so as to have a substantially common center of mass (a common center of gravity) on the semiconductor device. The reference voltage circuit 200 configured in this way can also obtain the same effect.

[0036] In addition, the reference voltage circuit 200 may also be Figure 3 As shown, the transistors 211, 212, and 223 are arranged to have a common center of mass (common center of gravity) on the semiconductor device. That is, the transistors 211, 212, and 223 are arranged to be line-symmetrical with the transistors 213, 221, and 222 to achieve a common center of mass (common center of gravity).

[0037] Figure 4 It is an explanatory diagram showing another example of the reference voltage circuit according to the first embodiment.

[0038] In the reference voltage circuit 400 , a depletion mode transistor 410 and an enhancement mode transistor 420 are each constituted by two transistors.

[0039] The transistor 410 is formed by connecting two depletion-mode transistors 411 and 412 in parallel. The transistor 420 is formed by connecting two enhancement-mode transistors 421 and 422 in parallel.

[0040] The reference voltage circuit 400 and Figure 1 The reference voltage circuit 100 is similarly arranged on the semiconductor device so as to have a substantially common center of mass (a common center of gravity). The reference voltage circuit 400 configured in this way can also obtain the same effect.

[0041] In the reference voltage circuit 400 , each transistor is formed by connecting two transistors in parallel, but two or more transistors may be connected in parallel and arranged so as to have a substantially common centroid (a common center of gravity) on the semiconductor device.

[0042] Figure 5 It is an explanatory diagram showing another example of the reference voltage circuit according to the first embodiment.

[0043] The reference voltage circuit 500 includes a depletion transistor 110, an enhancement transistor 120, and a terminal 130 for outputting a reference voltage VREF. The transistor 120 is formed by connecting two enhancement transistors 121 and 122 in series.

[0044] exist Figure 1 In the reference voltage circuit 100, the depletion transistor 110 is formed by connecting two depletion transistors 111 and 112 in series. Figure 5 As shown, even if it is composed of a single transistor, it can be arranged in a manner that substantially shares a common center of mass (a common center of gravity) on the semiconductor device.

[0045] In addition, Figure 5 In the reference voltage circuit 500 , an example in which the depletion-mode transistor 110 is formed of one transistor is described, but the enhancement-mode transistor 120 may be formed of one transistor.

[0046] The reference voltage circuit of the first embodiment described above includes one to three transistors as each transistor, but three or more transistors may be connected in series or in parallel and arranged to have a substantially common center of mass (a common center of gravity) on the semiconductor device.

[0047] Figure 6 It is an explanatory diagram showing a reference voltage circuit according to a second embodiment of the present invention.

[0048] The reference voltage circuit 600 includes a depletion-type transistor 610, an enhancement-type transistor 620, and transistors 640 and 650 constituting a current mirror circuit. The reference voltage circuit 600 is formed by combining the transistor 610 and the transistor 620 through a current mirror circuit, and its basic operation is the same as that of the reference voltage circuit of the first embodiment. The reference voltage circuit 600 is formed by a plurality of transistors, similarly to the reference voltage circuit of the first embodiment.

[0049] The transistor 610 is formed by connecting two depletion-type transistors 611 and 612 in series. The transistor 620 is formed by connecting two transistors 621 and 622 in series. The transistor 640 is formed by connecting two transistors 641 and 642 in series. The transistor 650 is formed by connecting two transistors 651 and 652 in series.

[0050] Each transistor is configured similarly to the reference voltage circuit of the first embodiment. Also, for example, transistor 610 and transistor 620 are configured to have a common center of mass (common center of gravity) on the semiconductor device, and transistor 640 and transistor 650 are configured to have a common center of mass (common center of gravity) on the semiconductor device, similarly to the reference voltage circuit 100. The reference voltage circuit 600 configured in this way can also obtain the same effect.

[0051] In the reference voltage circuit 600 of the second embodiment, each transistor is composed of two transistors, but two or more transistors may be connected in series or in parallel as in the first embodiment and arranged so as to have a substantially common center of mass (common center of gravity) on the semiconductor device.

Claims

1. A reference voltage circuit, comprising a depletion-mode transistor as a current source and an enhancement-mode transistor as a load, wherein: The reference voltage circuit is composed of a plurality of transistors, the plurality of transistors including the depletion-mode transistor formed by connecting at least one depletion-mode transistor including a first depletion-mode transistor, and the enhancement-mode transistor formed by connecting at least one enhancement-mode transistor including a first enhancement-mode transistor connected in series with the first depletion-mode transistor. The plurality of transistors in which the depletion-mode transistors and the enhancement-mode transistors are mixed are arranged in a manner of sharing a common centroid, which is a common center of gravity.

2. The reference voltage circuit according to claim 1, wherein: The depletion-mode transistor and the enhancement-mode transistor are arranged in point symmetry.

3. The reference voltage circuit according to claim 1, wherein: The depletion-mode transistor and the enhancement-mode transistor are arranged in line symmetry.

4. The reference voltage circuit according to claim 1, characterized in that: The depletion-mode transistor and the enhancement-mode transistor are connected via a current mirror circuit.

5. The reference voltage circuit according to claim 4, characterized in that: The transistors constituting the current mirror circuit are composed of a plurality of transistors. The plurality of transistors are arranged in a centroidal manner, which is a common center of gravity. 6 . A semiconductor device comprising the reference voltage circuit according to claim 1 .

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