A method to effectively improve the LDO power supply rejection ratio through cascode compensation

Abstract

A method for effectively improving the power supply rejection ratio (PSRR) of an LDO (Low-Power-Dependent Oscillator) (LDO) using cascode compensation is disclosed. The method includes a high-PSRR LDO circuit with cascode compensation. The circuit comprises a bandgap reference circuit VREF, an error amplifier EA, a PMOS power transistor, and resistor feedback networks R5 and R6. The bandgap reference circuit of the present invention does not have an op amp structure and generates a PTAT current via a current mirror, reducing the influence of the power supply voltage on the output reference voltage. The present invention improves the error amplifier EA and employs cascode compensation to eliminate the right-half-plane zero problem caused by Miller compensation, thereby improving the power supply rejection ratio (PSRR) of the LDO circuit output. By designing an EA module and feeding back the output LDO voltage to the current compensation circuit, current compensation is achieved for each branch in the circuit, thereby stabilizing the LDO output voltage and significantly improving the power supply rejection ratio (PSRR).

Description

Technical Field

[0001] The present invention relates to a method for improving a power supply rejection ratio (PSR), and in particular to a method for effectively improving an LDO (Low-Drain Voltage Drain) PSR through cascode compensation. Background Art

[0002] With the rapid development of electronic chips, portable devices have become an indispensable part of people's lives. To ensure the stable and efficient operation of these electronic devices, power supply design is crucial. Low-dropout linear regulators (LDOs) are a key type of power management IC. They offer advantages such as simplicity, cost, ease of integration, and good line and load regulation. However, their PSRR and accuracy are not ideal. Consequently, significant efforts have been made to improve the accuracy and PSRR of LDOs.

[0003] A lot of efforts have been made to improve the PSRR of LDOs. A high PSRR can be obtained by improving the structure of the Wilson current source and the op amp, or by designing a multi-stage buffer, but this will result in poor loop stability. The power supply rejection ratio can also be improved by improving the structure of the error amplifier. The most common way to improve the internal structure of the error amplifier is to add Miller compensation. However, for a two-stage op amp with Miller compensation, the presence of a feedforward path will introduce a zero point in the right half plane, thereby deteriorating the frequency response stability. This can be solved by adding a zeroing resistor. In addition, this invention proposes that the defects of Miller compensation can be eliminated through cascode compensation, thereby improving the power supply rejection ratio. Summary of the Invention

[0004] The purpose of the present invention is to propose a method for effectively improving the power supply rejection ratio of an LDO by cascode compensation. The method uses a high power supply rejection ratio LDO circuit compensated by cascode to stabilize the LDO output voltage and significantly improve the power supply rejection ratio (PSRR).

[0005] To achieve the above object, the technical solution of the present invention is as follows:

[0006] A method for effectively improving the power supply rejection ratio (PSR) of an LDO (Low-Drain Voltage Regulator) by cascode compensation. The method includes an LDO circuit with a high power supply rejection ratio (PSR) and cascode compensation, wherein the circuit is configured as follows:

[0007] A bandgap reference circuit module, wherein an output terminal VREF of the bandgap reference circuit is connected to a negative input terminal of the error amplifier EA, so as to provide a reference voltage VREF for the error amplifier;

[0008] An error amplifier EA includes a folded cascode amplifier and a cascode compensation circuit. The voltage VFB collected by the feedback network is fed to the positive input of the error amplifier EA, compared with the reference voltage VREF at the negative input, and then amplified to obtain the required voltage.

[0009] A PMOS power tube, wherein the gate of the PMOS power tube is connected to the output end of the error amplifier;

[0010] A resistor feedback network generates a feedback voltage VFB and outputs it to the positive input terminal of the error amplifier.

[0011] In the above-mentioned method for effectively improving the power supply rejection ratio of an LDO by cascode compensation, a high power supply rejection ratio LDO circuit with cascode compensation is provided, wherein the bandgap reference circuit includes transistors Q1-Q4, resistors R1-R4, capacitor C1, and MOS transistors M1-M27;

[0012] The power supply is connected to the source of the MOS transistor M1, the source of the MOS transistor M7, the source of the MOS transistor M2, the source of the MOS transistor M3, the source of the MOS transistor M4, the source of the MOS transistor M11, the source of the MOS transistor M5, the source of the MOS transistor M6, the source of the MOS transistor M20, the drain of the MOS transistor M24, the source of the MOS transistor M26, and the positive end of the resistor R4.The drain of MOS transistor M1 is connected to the gate of MOS transistor M15, the gate and source of MOS transistor M16, the drain of MOS transistor M8, and the gate end of MOS transistor M17. The gate of MOS transistor M1 is connected to the drain of MOS transistor M26 and the drain of MOS transistor M27. The gate of MOS transistor M2 is connected to the gate of MOS transistor M3, the gate of MOS transistor M4, the drain of MOS transistor M9, the gate of MOS transistor M11, the gate of MOS transistor M12, the gate of MOS transistor M13, and the source of MOS transistor M17. The drain of MOS transistor M2 is connected to the source of MOS transistor M8, the drain of MOS transistor M3 is connected to the source of MOS transistor M9, and the drain of MOS transistor M4 is connected to the gate of MOS transistor M1. The source of MOS transistor M0 is connected to the drain of MOS transistor M11, the drain of MOS transistor M12, the drain of MOS transistor M13, the drain of MOS transistor M19, the gate of MOS transistor M20, the gate of MOS transistor M21, the gate of MOS transistor M22, and the gate of MOS transistor M23. The drain of MOS transistor M5 is connected to the source of MOS transistor M12, the drain of MOS transistor M6 is connected to the source of MOS transistor M13, the gate of MOS transistor M5 and the gate of MOS transistor M6 are connected to external opposite signals A and B, the gate of MOS transistor M7 is connected to the gate and drain of MOS transistor M14, the source of MOS transistor M15, the gate of MOS transistor M8, the gate of MOS transistor M9, and the gate of MOS transistor M10. The drain of MOS tube M7 is connected to the source of MOS tube M14, the drain of MOS tube M15 is connected to the emitter of transistor Q1, the drain of MOS tube M16 is connected to the emitter of transistor Q2, the drain of MOS tube M17 is connected to the positive end of resistor R1, the negative end of resistor R1 is connected to the emitter of transistor Q3, the drain of MOS tube M10 is connected to the positive end of resistor R2 and the output end VREF of the bandgap reference circuit, the negative end of resistor R2 is connected to the positive end of resistor R3, the negative end of resistor R3 is connected to the emitter of transistor Q4, the negative end of resistor R4 is connected to the gate and drain of MOS tube M18, the gate of MOS tube M19, and the positive end of capacitor C1, and ground is connected to the positive end of transistor Q1. The base and collector, the base and collector of transistor Q2, the base and collector of transistor Q3, the base and collector of transistor Q4, the source of MOS transistor M18, the source of MOS transistor M19, the negative terminal of capacitor C1, the source of MOS transistor M23, the drain of MOS transistor M25, and the source of MOS transistor M27 are connected. The drain of MOS transistor M20 is connected to the source of MOS transistor M21 and the source of MOS transistor M24. The drain of MOS transistor M21 is connected to the drain of MOS transistor M22, the gate of MOS transistor M24, the gate of MOS transistor M25, the gate of MOS transistor M26, and the gate of MOS transistor M27. The source of MOS transistor M22 is connected to the drain of MOS transistor M23.

[0013] In the above-mentioned method for effectively improving the LDO power supply rejection ratio through cascode compensation, there is an LDO circuit with a high power supply rejection ratio with cascode compensation, wherein the error amplifier EA includes MOS tubes M28-M41, resistors R5-R6 and a compensation capacitor Cc;.

[0014] Among them, the gate of the MOS transistor M28 is connected to the reference voltage VREF of the bandgap reference, the gate of the MOS transistor M29 and the gate of the MOS transistor M30 are connected to the feedback voltage VFB, the negative end of the resistor R5, and the positive end of the resistor R6, the source of the MOS transistor M28 is connected to the source of the MOS transistor M29 and the drain of the MOS transistor M31, the drain of the MOS transistor M28 is connected to the drain of the MOS transistor M34 and the drain of the MOS transistor M36, the drain of the MOS transistor M29 is connected to the drain of the MOS transistor M38, the drain of the MOS transistor M39, and the positive end of the compensation capacitor Cc, the drain of the MOS transistor M32 is connected to the source of the MOS transistor M30, the gates of the MOS transistor M31 and the gates of the MOS transistor M32 are connected to the external voltage terminal VB1 to form a current source, the drain of the MOS transistor M30 is connected to the gate and drain of the MOS transistor M35, the gate of the MOS transistor M36, and the gate of the MOS transistor M39, and the gate and drain of the MOS transistor M33 are connected to the gate and drain of the MOS transistor M34. The gate of the MOS transistor M7 is connected to the source of the MOS transistor M34. The gate of the MOS transistor M34 and the gate of the MOS transistor M38 are connected to the external voltage terminal VB2 to form a current source. The drain of the MOS transistor M37 is connected to the source of the MOS transistor M38 and the gate of the MOS transistor M40. The power supply is connected to the source of the MOS transistor M31, the source of the MOS transistor M32, the source of the MOS transistor M33, the source of the MOS transistor M37, the source of the MOS transistor M40, and the source of the MOS transistor M41. The drain of the MOS transistor M40 is connected to the gate of the MOS transistor M41, the negative terminal of the compensation capacitor Cc, and the drain of the MOS transistor M42. The gate of the MOS transistor M42 is connected to the external voltage terminal VB3 to form a current source. The ground is connected to the source of the MOS transistor M35, the source of the MOS transistor M36, the source of the MOS transistor M39, the source of the MOS transistor M42, and the negative terminal of the resistor R6. The drain of the MOS transistor M41 is connected to the positive terminal of the resistor R5 and the LDO output voltage terminal VOUT.

[0015] In the above-mentioned method for effectively improving the LDO power supply rejection ratio through cascode compensation, a high power supply rejection ratio LDO circuit with cascode compensation is provided. The error amplifier EA includes a folded cascode amplifier and a cascode compensation part. The folded cascode amplifier can output a large output voltage swing while ensuring the LDO loop gain. PMOS transistors M28 and M29 are used to form an input pair of transistors. MOS transistors M31 and M32 provide appropriate bias for the input pair of transistors, compare the reference voltage VREF and the feedback voltage VFB, and operate in the saturation region through M34 and M35 to adjust the startup voltage of the LDO circuit.

[0016] In the above-mentioned method for effectively improving the LDO power supply rejection ratio through cascode compensation, a high power supply rejection ratio LDO circuit with cascode compensation is provided. The cascode compensation circuit includes a MOS transistor M40, a MOS transistor M42, a MOS transistor M38, and a compensation capacitor Cc; the drain of the MOS transistor M40 is connected to the drain of the MOS transistor M42 and the negative end of the compensation capacitor Cc, the output VO of the folded cascode amplifier is connected to the positive end of the compensation capacitor Cc, the drain of the MOS transistor M38, and the drain of the MOS transistor M39, the source of the MOS transistor M40 is connected to the power supply, and the source of the MOS transistor M42 is connected to the ground.

[0017] In the above-mentioned method of effectively improving the LDO power supply rejection ratio through cascode compensation, a LDO circuit with a high power supply rejection ratio with cascode compensation is provided, wherein the resistor feedback network includes a resistor R5 and a resistor R6, the negative end of the resistor R5 and the positive end of the resistor R6 are connected to the negative input terminal VFB of the error amplifier EA, the positive end of the resistor R5 is connected to the output terminal VOUT of the LDO, and the negative end of the resistor R6 is connected to the ground.

[0018] The advantages and effects of the present invention are:

[0019] 1. The present invention includes a bandgap reference circuit VREF, an error amplifier EA, a PMOS power transistor, and resistor feedback networks R5 and R6. The bandgap reference circuit lacks an op amp structure and generates a PTAT current via a current mirror, reducing the influence of the power supply voltage on the output reference voltage. By improving the error amplifier EA and employing cascode compensation to eliminate the right-half-plane zero problem caused by Miller compensation, the present invention improves the power supply rejection ratio (PSRR) of the LDO circuit output. By designing the EA module and feeding the output LDO voltage back to the current compensation circuit, the present invention achieves current compensation for each branch in the circuit, thereby stabilizing the LDO output voltage and significantly improving the power supply rejection ratio (PSRR).

[0020] 2. The bandgap reference circuit of the present invention is used to generate the reference voltage required by the LDO. Compared with the traditional bandgap reference circuit, the structure does not adopt an op amp structure, but only generates PTAT current through a current mirror, reducing the influence of the power supply voltage on the output reference voltage.

[0021] 3. The error amplifier of the present invention includes a folded cascode amplifier and a cascode compensation portion. In the folded cascode amplifier, a MOS transistor M30 is added as one end of a differential pair. The gate of the MOS transistor M30 is connected to the gate of the MOS transistor M29, and both serve as the positive input end of the error amplifier. A common-mode feedback network is added to stabilize the common-mode level and static operating point of the circuit. At the same time, cascode compensation is added to the error amplifier to eliminate the right-half-plane zero problem of the Maitreya effect, making the circuit more stable and improving the power supply rejection ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Schematic diagram of the overall LDO with high power supply rejection ratio and cascode compensation of the present invention;

[0023] Figure 2 Schematic diagram of the bandgap reference circuit of the present invention;

[0024] Figure 3 Schematic diagram of the error amplifier EA of the present invention;

[0025] Figure 4 This is the Cascode compensation circuit diagram of the present invention;

[0026] Figure 5 This is a PSRR performance curve diagram of the circuit of the present invention. DETAILED DESCRIPTION

[0027] In order to clearly and completely describe the objectives and technical solutions of the present invention and to make the advantages more clearly understood, the embodiments of the present invention are further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only some embodiments of the present invention, not all embodiments, and are only used to explain the embodiments of the present invention, not to limit the embodiments of the present invention. All other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0028] To address the problem of non-ideal PSRR in LDO circuits, cascode compensation is added to the output of the error amplifier to make the LDO output more stable and greatly improve the power supply rejection ratio.

[0029] LDO circuit with high power supply rejection ratio with cascode compensation, such as Figure 1As shown, it includes: a bandgap reference circuit, an error amplifier EA, a PMOS power tube, and a resistor feedback network R5-R6;

[0030] Among them, the output terminal VREF of the bandgap reference circuit is connected to the negative input terminal of the error amplifier EA, aiming to provide a reference voltage VREF for the error amplifier; the error amplifier EA includes a folded common-source common-gate amplifier and a cascode compensation circuit; the voltage VFB collected by the feedback network is input to the positive input terminal of the error amplifier EA, compared with the reference voltage VREF at the negative input terminal, and then amplified to obtain the required voltage; the gate of the PMOS power tube is connected to the output terminal of the error amplifier; the feedback voltage VFB generated by the resistor feedback network is output to the positive input terminal of the error amplifier.

[0031] like Figure 2 As shown, the bandgap reference circuit includes transistors Q1-Q4, resistors R1-R4, capacitor C1, MOS tubes M1-M27;

[0032] The power supply is connected to the source of the MOS transistor M1, the source of the MOS transistor M7, the source of the MOS transistor M2, the source of the MOS transistor M3, the source of the MOS transistor M4, the source of the MOS transistor M11, the source of the MOS transistor M5, the source of the MOS transistor M6, the source of the MOS transistor M20, the drain of the MOS transistor M24, the source of the MOS transistor M26, and the positive end of the resistor R4.The drain of MOS transistor M1 is connected to the gate of MOS transistor M15, the gate and source of MOS transistor M16, the drain of MOS transistor M8, and the gate end of MOS transistor M17. The gate of MOS transistor M1 is connected to the drain of MOS transistor M26 and the drain of MOS transistor M27. The gate of MOS transistor M2 is connected to the gate of MOS transistor M3, the gate of MOS transistor M4, the drain of MOS transistor M9, the gate of MOS transistor M11, the gate of MOS transistor M12, the gate of MOS transistor M13, and the source of MOS transistor M17. The drain of MOS transistor M2 is connected to the source of MOS transistor M8, the drain of MOS transistor M3 is connected to the source of MOS transistor M9, and the drain of MOS transistor M4 is connected to the gate of MOS transistor M1. The source of MOS transistor M0 is connected to the drain of MOS transistor M11, the drain of MOS transistor M12, the drain of MOS transistor M13, the drain of MOS transistor M19, the gate of MOS transistor M20, the gate of MOS transistor M21, the gate of MOS transistor M22, and the gate of MOS transistor M23. The drain of MOS transistor M5 is connected to the source of MOS transistor M12, the drain of MOS transistor M6 is connected to the source of MOS transistor M13, the gate of MOS transistor M5 and the gate of MOS transistor M6 are connected to external opposite signals A and B, the gate of MOS transistor M7 is connected to the gate and drain of MOS transistor M14, the source of MOS transistor M15, the gate of MOS transistor M8, the gate of MOS transistor M9, and the gate of MOS transistor M10. The drain of MOS tube M7 is connected to the source of MOS tube M14, the drain of MOS tube M15 is connected to the emitter of transistor Q1, the drain of MOS tube M16 is connected to the emitter of transistor Q2, the drain of MOS tube M17 is connected to the positive end of resistor R1, the negative end of resistor R1 is connected to the emitter of transistor Q3, the drain of MOS tube M10 is connected to the positive end of resistor R2 and the output end VREF of the bandgap reference circuit, the negative end of resistor R2 is connected to the positive end of resistor R3, the negative end of resistor R3 is connected to the emitter of transistor Q4, the negative end of resistor R4 is connected to the gate and drain of MOS tube M18, the gate of MOS tube M19, and the positive end of capacitor C1, and ground is connected to the positive end of transistor Q1. The base and collector, the base and collector of transistor Q2, the base and collector of transistor Q3, the base and collector of transistor Q4, the source of MOS transistor M18, the source of MOS transistor M19, the negative terminal of capacitor C1, the source of MOS transistor M23, the drain of MOS transistor M25, and the source of MOS transistor M27 are connected. The drain of MOS transistor M20 is connected to the source of MOS transistor M21 and the source of MOS transistor M24. The drain of MOS transistor M21 is connected to the drain of MOS transistor M22, the gate of MOS transistor M24, the gate of MOS transistor M25, the gate of MOS transistor M26, and the gate of MOS transistor M27. The source of MOS transistor M22 is connected to the drain of MOS transistor M23.

[0033] This bandgap reference circuit, devoid of an op amp, generates a PTAT current solely through a current mirror, minimizing the impact of the power supply voltage on the output reference voltage. MOS transistors M16 and M17 form a current mirror structure. The drain voltage of MOS transistors M16 and M17 is equal. The base-emitter voltage VBE2 of transistor Q2 is equal to the sum of the base-emitter voltage VBE3 of transistor Q3 and the voltage of resistor R1. The voltage difference between the base-emitter voltages VBE2 and VBE3 of transistor Q2 divided by resistor R1 yields the PTAT current. This current is replicated by the current mirror to resistors R2 and R3, resulting in a positive temperature coefficient voltage. The base-emitter voltage VBE4 of transistor Q4 has a negative temperature coefficient. The sum of these two voltages yields the zero temperature coefficient voltage VREF.

[0034] like Figure 3 As shown, the error amplifier EA includes MOS tubes M28-M41, resistors R5-R6 and a compensation capacitor Cc;.

[0035] Among them, the gate of the MOS transistor M28 is connected to the reference voltage VREF of the bandgap reference, the gate of the MOS transistor M29 and the gate of the MOS transistor M30 are connected to the feedback voltage VFB, the negative end of the resistor R5, and the positive end of the resistor R6, the source of the MOS transistor M28 is connected to the source of the MOS transistor M29 and the drain of the MOS transistor M31, the drain of the MOS transistor M28 is connected to the drain of the MOS transistor M34 and the drain of the MOS transistor M36, the drain of the MOS transistor M29 is connected to the drain of the MOS transistor M38, the drain of the MOS transistor M39, and the positive end of the compensation capacitor Cc, the drain of the MOS transistor M32 is connected to the source of the MOS transistor M30, the gates of the MOS transistor M31 and the gates of the MOS transistor M32 are connected to the external voltage terminal VB1 to form a current source, the drain of the MOS transistor M30 is connected to the gate and drain of the MOS transistor M35, the gate of the MOS transistor M36, and the gate of the MOS transistor M39, and the gate and drain of the MOS transistor M33 are connected to the gate and drain of the MOS transistor M34. The gate of the MOS transistor M7 is connected to the source of the MOS transistor M34. The gate of the MOS transistor M34 and the gate of the MOS transistor M38 are connected to the external voltage terminal VB2 to form a current source. The drain of the MOS transistor M37 is connected to the source of the MOS transistor M38 and the gate of the MOS transistor M40. The power supply is connected to the source of the MOS transistor M31, the source of the MOS transistor M32, the source of the MOS transistor M33, the source of the MOS transistor M37, the source of the MOS transistor M40, and the source of the MOS transistor M41. The drain of the MOS transistor M40 is connected to the gate of the MOS transistor M41, the negative terminal of the compensation capacitor Cc, and the drain of the MOS transistor M42. The gate of the MOS transistor M42 is connected to the external voltage terminal VB3 to form a current source. The ground is connected to the source of the MOS transistor M35, the source of the MOS transistor M36, the source of the MOS transistor M39, the source of the MOS transistor M42, and the negative terminal of the resistor R6. The drain of the MOS transistor M41 is connected to the positive terminal of the resistor R5 and the LDO output voltage terminal VOUT.

[0036] The error amplifier EA includes a folded cascode amplifier and a cascode compensation part. The folded cascode amplifier can output a large output voltage swing while ensuring the LDO loop gain. PMOS transistors M28 and M29 are used to form an input pair of transistors. MOS transistors M31 and M32 provide appropriate bias for the input pair of transistors, compare the reference voltage VREF and the feedback voltage VFB, and operate in the saturation region through M34 and M35 to adjust the startup voltage of the LDO circuit.

[0037] like Figure 4As shown, the cascode compensation circuit includes a MOS transistor M40, a MOS transistor M42, a MOS transistor M38, and a compensation capacitor Cc; the drain of the MOS transistor M40 is connected to the drain of the MOS transistor M42 and the negative end of the compensation capacitor Cc, the output VO of the folded cascode amplifier is connected to the positive end of the compensation capacitor Cc, the drain of the MOS transistor M38, and the drain of the MOS transistor M39, the source of the MOS transistor M40 is connected to the power supply, and the source of the MOS transistor M42 is connected to the ground.

[0038] The cascode compensation circuit uses the MOS transistor M38 as a current buffer and moves one end of the compensation capacitor Cc from point X to point Y, changing the compensation from conventional Miller compensation to cascode compensation. The cascode is used to cut off the feedforward path from point X through the capacitor Cc to the output, pushing the right-half-plane zero to a very high frequency, greatly improving the power supply rejection ratio.

[0039] The power supply rejection ratio PSRR performance curve is as follows Figure 5 As shown, the horizontal axis is frequency in Hz, and the vertical axis is PSRR in dB. It can be seen from the figure that the PSRR at low frequency gradually decreases as the frequency increases. It can be seen that the PSRR is as high as 97dB at 1kHz.

[0040] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been demonstrated above with a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with this patent can make some changes or modifications to equivalent embodiments using the above-mentioned technical content without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiment based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the solution of the present invention.

Claims

1. A method for effectively improving the LDO power supply rejection ratio through cascode compensation, characterized in that: The method includes an LDO circuit with high power supply rejection ratio and cascode compensation, wherein the circuit is configured with: The bandgap reference circuit module has an output terminal VREF of the bandgap reference circuit connected to the negative input terminal of the error amplifier EA, so as to provide a reference voltage VREF for the error amplifier; The error amplifier EA includes a folded cascode amplifier and a cascode compensation circuit; The voltage VFB collected by the feedback network is input to the positive input terminal of the error amplifier EA, compared with the reference voltage VREF at the negative input terminal, and then amplified to obtain the required voltage; A PMOS power tube, wherein the gate of the PMOS power tube is connected to the output end of the error amplifier; A resistor feedback network generates a feedback voltage VFB and outputs it to the positive input of the error amplifier; The bandgap reference circuit includes transistors Q1-Q4, resistors R1-R4, capacitor C1, and MOS tubes M1-M27; The power supply is connected to the source of the MOS transistor M1, the source of the MOS transistor M7, the source of the MOS transistor M2, the source of the MOS transistor M3, the source of the MOS transistor M4, the source of the MOS transistor M11, the source of the MOS transistor M5, the source of the MOS transistor M6, the source of the MOS transistor M20, the drain of the MOS transistor M24, the source of the MOS transistor M26, and the positive end of the resistor R4.The drain of MOS transistor M1 is connected to the gate of MOS transistor M15, the gate and source of MOS transistor M16, the drain of MOS transistor M8, and the gate end of MOS transistor M17. The gate of MOS transistor M1 is connected to the drain of MOS transistor M26 and the drain of MOS transistor M27. The gate of MOS transistor M2 is connected to the gate of MOS transistor M3, the gate of MOS transistor M4, the drain of MOS transistor M9, the gate of MOS transistor M11, the gate of MOS transistor M12, the gate of MOS transistor M13, and the source of MOS transistor M17. The drain of MOS transistor M2 is connected to the source of MOS transistor M8, the drain of MOS transistor M3 is connected to the source of MOS transistor M9, and the drain of MOS transistor M4 is connected to the gate of MOS transistor M1. The source of MOS transistor M0 is connected to the drain of MOS transistor M11, the drain of MOS transistor M12, the drain of MOS transistor M13, the drain of MOS transistor M19, the gate of MOS transistor M20, the gate of MOS transistor M21, the gate of MOS transistor M22, and the gate of MOS transistor M23. The drain of MOS transistor M5 is connected to the source of MOS transistor M12, the drain of MOS transistor M6 is connected to the source of MOS transistor M13, the gate of MOS transistor M5 and the gate of MOS transistor M6 are connected to external opposite signals A and B, the gate of MOS transistor M7 is connected to the gate and drain of MOS transistor M14, the source of MOS transistor M15, the gate of MOS transistor M8, the gate of MOS transistor M9, and the gate of MOS transistor M10. The drain of MOS tube M7 is connected to the source of MOS tube M14, the drain of MOS tube M15 is connected to the emitter of transistor Q1, the drain of MOS tube M16 is connected to the emitter of transistor Q2, the drain of MOS tube M17 is connected to the positive end of resistor R1, the negative end of resistor R1 is connected to the emitter of transistor Q3, the drain of MOS tube M10 is connected to the positive end of resistor R2 and the output end VREF of the bandgap reference circuit, the negative end of resistor R2 is connected to the positive end of resistor R3, the negative end of resistor R3 is connected to the emitter of transistor Q4, the negative end of resistor R4 is connected to the gate and drain of MOS tube M18, the gate of MOS tube M19, and the positive end of capacitor C1, and ground is connected to the positive end of transistor Q1. The base and collector, the base and collector of transistor Q2, the base and collector of transistor Q3, the base and collector of transistor Q4, the source of MOS transistor M18, the source of MOS transistor M19, the negative terminal of capacitor C1, the source of MOS transistor M23, the drain of MOS transistor M25, and the source of MOS transistor M27 are connected. The drain of MOS transistor M20 is connected to the source of MOS transistor M21 and the source of MOS transistor M24. The drain of MOS transistor M21 is connected to the drain of MOS transistor M22, the gate of MOS transistor M24, the gate of MOS transistor M25, the gate of MOS transistor M26, and the gate of MOS transistor M27. The source of MOS transistor M22 is connected to the drain of MOS transistor M23.

2. The method for effectively improving the LDO power supply rejection ratio by cascode compensation according to claim 1, characterized in that: The error amplifier EA includes MOS tubes M28-M41 and a compensation capacitor Cc; Among them, the gate of the MOS transistor M28 is connected to the reference voltage VREF of the bandgap reference, the gate of the MOS transistor M29 and the gate of the MOS transistor M30 are connected to the feedback voltage VFB, the negative end of the resistor R5, and the positive end of the resistor R6, the source of the MOS transistor M28 is connected to the source of the MOS transistor M29 and the drain of the MOS transistor M31, the drain of the MOS transistor M28 is connected to the drain of the MOS transistor M34 and the drain of the MOS transistor M36, the drain of the MOS transistor M29 is connected to the drain of the MOS transistor M38, the drain of the MOS transistor M39, and the positive end of the compensation capacitor Cc, the drain of the MOS transistor M32 is connected to the source of the MOS transistor M30, the gates of the MOS transistor M31 and the gates of the MOS transistor M32 are connected to the external voltage terminal VB1 to form a current source, the drain of the MOS transistor M30 is connected to the gate and drain of the MOS transistor M35, the gate of the MOS transistor M36, and the gate of the MOS transistor M39, and the gate and drain of the MOS transistor M33 are connected to the gate and drain of the MOS transistor M34. The gate of the MOS transistor M7 is connected to the source of the MOS transistor M34. The gate of the MOS transistor M34 and the gate of the MOS transistor M38 are connected to the external voltage terminal VB2 to form a current source. The drain of the MOS transistor M37 is connected to the source of the MOS transistor M38 and the gate of the MOS transistor M40. The power supply is connected to the source of the MOS transistor M31, the source of the MOS transistor M32, the source of the MOS transistor M33, the source of the MOS transistor M37, the source of the MOS transistor M40, and the source of the MOS transistor M41. The drain of the MOS transistor M40 is connected to the gate of the MOS transistor M41, the negative terminal of the compensation capacitor Cc, and the drain of the MOS transistor M42. The gate of the MOS transistor M42 is connected to the external voltage terminal VB3 to form a current source. The ground is connected to the source of the MOS transistor M35, the source of the MOS transistor M36, the source of the MOS transistor M39, the source of the MOS transistor M42, and the negative terminal of the resistor R6. The drain of the MOS transistor M41 is connected to the positive terminal of the resistor R5 and the LDO output voltage terminal VOUT.

3. The method for effectively improving the LDO power supply rejection ratio by cascode compensation according to claim 2, characterized in that: The error amplifier EA includes a folded cascode amplifier and a cascode compensation part. The folded cascode amplifier can output a large output voltage swing while ensuring the LDO loop gain. PMOS transistors M28 and M29 are used to form an input pair of transistors. MOS transistors M31 and M32 provide appropriate bias for the input pair of transistors, compare the reference voltage VREF and the feedback voltage VFB, and operate in the saturation region through M34 and M35 to adjust the startup voltage of the LDO circuit.

4. The method for effectively improving the LDO power supply rejection ratio by cascode compensation according to claim 3, characterized in that: The cascode compensation circuit includes a MOS transistor M40, a MOS transistor M42, and a MOS transistor M38, and a compensation capacitor Cc. The drain of the MOS transistor M40 is connected to the drain of the MOS transistor M42 and the negative end of the compensation capacitor Cc. The output VO of the folded cascode amplifier is connected to the positive end of the compensation capacitor Cc, the drain of the MOS transistor M38, and the drain of the MOS transistor M39. The source of the MOS transistor M40 is connected to the power supply, and the source of the MOS transistor M42 is connected to the ground.

5. The method for effectively improving the LDO power supply rejection ratio by cascode compensation according to claim 1, characterized in that: The resistor feedback network includes a resistor R5 and a resistor R6, the negative end of the resistor R5 and the positive end of the resistor R6 are connected to the negative input terminal VFB of the error amplifier EA, the positive end of the resistor R5 is connected to the output terminal VOUT of the LDO, and the negative end of the resistor R6 is connected to the ground.

Images