Reference circuit

Abstract

The embodiment of the invention provides a reference circuit. The circuit comprises a starting module, a current source module and a band-gap module, the starting module can start the current source module after a power supply is powered on, the current source module can generate nA-magnitude reference current after starting is completed and control the starting module to stop working, and the band-gap module can generate band-gap reference voltage with a zero temperature coefficient according to the reference current. After the circuit is started, the current source module can generate nA-magnitude reference current, so that the power consumption of the circuit can be reduced, the starting module stops working after the circuit is started, and the power consumption of the circuit can be further reduced.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular, to a reference circuit. Background Art

[0002] Reference source modules are widely used in analog and mixed circuits. The reference signal they output is stable and has nothing to do with power supply voltage, temperature, and process changes. Many modules of system-level chips require reference sources to provide stable voltage or current, so the circuit design of the reference source has become the key to the entire chip design.

[0003] In the prior art, a reference source needs to generate a reference current of the order of 100 nanoamperes, and a reference voltage is generated based on the reference current. However, since the generated reference current is relatively large, the circuit power consumption is relatively large. Summary of the invention

[0004] The embodiments of the present disclosure provide a reference circuit capable of generating a reference current of nanoampere order, thereby reducing circuit power consumption.

[0005] In a first aspect, the present disclosure provides a reference circuit, including: a startup module, a current source module and a bandgap module.

[0006] The output end of the startup module is connected to the input end of the current source module, the output end of the current source module is connected to the input end of the bandgap module and the input end of the startup module, the output end of the bandgap module is connected to the output end of the reference circuit, and the power supply end of the startup module, the power supply end of the current source module and the power supply end of the bandgap module are connected to a power supply.

[0007] The startup module is configured to start the current source module after the power supply is powered on. The current source module is configured to generate a reference current of the order of nA after the startup is completed, and control the startup module to stop working. The bandgap module is configured to generate a bandgap reference voltage with a zero temperature coefficient according to the reference current.

[0008] In some embodiments of the present disclosure, the current source module includes a first current mirror unit, a second current mirror unit, a first transistor, and a second transistor.

[0009] The input end of the first current mirror unit is connected to the power supply, the first output end of the first current mirror unit is connected to the first input end of the second current mirror unit, the control end of the second current mirror unit and the output end of the startup module, the second output end of the first current mirror unit is connected to the second input end of the second current mirror unit, and the third output end of the first current mirror unit is connected to the second end of the first transistor, the control end of the first transistor and the control end of the second transistor.

[0010] A first output terminal of the second current mirror unit is grounded, a second output terminal of the second current mirror unit is connected to a second terminal of the second transistor, and a first terminal of the second transistor and a first terminal of the first transistor are grounded.

[0011] In some embodiments of the present disclosure, the first current mirror unit includes a third transistor, a fourth transistor, and a fifth transistor.

[0012] The first end of the third transistor, the first end of the fourth transistor and the first end of the fifth transistor are connected to the power supply, the control end of the third transistor is connected to the control end of the fourth transistor, the second end of the fourth transistor, the control end of the fifth transistor, the second input end of the second current mirror unit, the input end of the startup module and the input end of the bandgap module, the second end of the third transistor is connected to the second end of the first transistor, the control end of the first transistor and the control end of the second transistor, and the second end of the fifth transistor is connected to the first input end of the second current mirror unit, the control end of the second current mirror unit and the output end of the startup module.

[0013] In some embodiments of the present disclosure, the second current mirror unit includes a sixth transistor and a seventh transistor.

[0014] The first end of the sixth transistor is connected to the second end of the second transistor, the second end of the sixth transistor is connected to the second output end of the first mirror unit, the control end of the sixth transistor is connected to the control end of the seventh transistor, the second end of the seventh transistor, the first output end of the first mirror unit and the output end of the startup module, and the first end of the seventh transistor is grounded.

[0015] In some embodiments of the present disclosure, the first transistor operates in a saturation region, the second transistor operates in a linear region, and the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor operate in a subthreshold region.

[0016] In some embodiments of the present disclosure, the reference current is expressed as:

[0017]

[0018] Wherein, i is the reference current, n c is the process coefficient, V t is the thermal voltage, μ nM2 is the electron mobility of the second transistor, C OXM2 is the capacitance per unit area of ​​the gate oxide layer of the second transistor, W M2 / L M2is the width-to-length ratio of the second transistor, S2 is expressed as:

[0019]

[0020] Among them, W M1 / L M1 is the width-to-length ratio of the first transistor, W M3 / L M3 is the width-to-length ratio of the third transistor, W M4 / L M4 is the width-to-length ratio of the fourth transistor, μ nM1 is the electron mobility of the first transistor, C OXM1 is the capacitance per unit area of ​​the gate oxide layer of the first transistor;

[0021] S1 is expressed as:

[0022]

[0023] Among them, W M6 / L M6 is the width-to-length ratio of the sixth transistor, W M7 / L M7 is the width-to-length ratio of the seventh transistor, W M5 / L M5 is the width-to-length ratio of the fifth transistor.

[0024] In some embodiments of the present disclosure, the startup module includes an eighth transistor, a ninth transistor, and a transistor assembly.

[0025] The first end of the eighth transistor and the first end of the ninth transistor are connected to the power supply, the second end of the eighth transistor is connected to the control end of the ninth transistor and the input end of the transistor component, the control end of the eighth transistor is connected to the output end of the current source module, the second end of the ninth transistor is connected to the input end of the current source module, and the output end of the transistor component is grounded.

[0026] The transistor component is configured to, after the current source module is started up, pull up the control voltage of the ninth transistor to control the ninth transistor to be turned off.

[0027] In some embodiments of the present disclosure, the transistor component includes a plurality of diode-connected transistors connected in series.

[0028] In some embodiments of the present disclosure, the startup module further includes a capacitor.

[0029] The first plate of the capacitor is connected to the second end of the eighth transistor, the control end of the ninth transistor and the input end of the transistor component, and the second plate of the capacitor is grounded.

[0030] In a second aspect, the present disclosure provides a chip, comprising any reference circuit provided in the first aspect.

[0031] In the technical solution of the embodiment of the present disclosure, the reference circuit includes a startup module, a current source module and a bandgap module. The startup module can start the current source module after the power supply is powered on. The current source module can generate a reference current of the order of nA after the startup is completed, and control the startup module to stop working. The bandgap module can generate a bandgap reference voltage with a zero temperature coefficient according to the reference current. In this way, after the startup is completed, the current source module can generate a reference current of the order of nA, thereby reducing the power consumption of the circuit. After the startup is completed, the startup module stops working, which can further reduce the power consumption of the circuit.

[0032] The above description is only an overview of the technical solution of the embodiment of the present application. In order to more clearly understand the technical means of the embodiment of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiment of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, a brief introduction will be given below to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 A circuit diagram of a reference source provided by the prior art.

[0035] Figure 2 A schematic diagram of the structure of a reference circuit provided in an embodiment of the present disclosure.

[0036] Figure 3 A circuit diagram of a reference circuit provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0038] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the disclosed subject matter belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" together shall mean that the parts are joined together directly or through one or more intermediate components.

[0039] Reference to "embodiments" in this disclosure means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiments" in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in this disclosure may be combined with other embodiments.

[0040] In addition, the terms "first", "second", etc. in the specification and claims of the present disclosure or the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0041] The term "and / or" in this disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0042] In the description of the present disclosure, unless otherwise specified, "plurality" and "at least two" mean more than two (including two), and similarly, "multiple groups" and "at least two groups" mean more than two groups (including two).

[0043] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0044] Figure 1 A circuit diagram of a reference source provided by the prior art, such as Figure 1 As shown, the reference source includes a first current source Idc1, a second current source Idc2, a third current source Idc3, a first field effect transistor N1, a second field effect transistor N2, a third field effect transistor N3, a fourth field effect transistor N4, a fifth field effect transistor N5 and a sixth field effect transistor P.

[0045] Among them, the input end of the first current source Idc1, the input end of the second current source Idc2, the input end of the third current source Idc3 and the second end of the fifth field effect transistor N5 are connected to the power supply, the output end of the first current source Idc1 is connected to the second end of the third field effect transistor N3, the control end of the third field effect transistor N3 and the control end of the fourth field effect transistor N4, the output end of the second current source Idc2 is connected to the control end of the sixth field effect transistor P, the second end of the first field effect transistor N1, the control end of the first field effect transistor N1 and the control end of the second field effect transistor N2, and the output end of the third current source Idc3 is connected to the first end of the sixth field effect transistor P and the control end of the fifth field effect transistor N5.

[0046] The first end of the fifth field effect transistor N5 is connected to the second end of the second field effect transistor N2, the first end of the second field effect transistor N2 is connected to the second end of the fourth field effect transistor N4 and the output end of the reference source, the first end of the first field effect transistor N1, the first end of the third field effect transistor N3, the first end of the fourth field effect transistor N4 and the second end of the sixth field effect transistor P are grounded.

[0047] Exemplarily, the output currents of the first current source Idc1 , the second current source Idc2 , and the third current source Idc3 are all in the order of hundreds of nanoamperes, for example, 100 nA.

[0048] The first field effect transistor N1, the second field effect transistor N2, the third field effect transistor N3, the fourth field effect transistor N4 and the fifth field effect transistor N5 are N-type metal oxide semiconductor field effect transistors (NMOS), and the sixth field effect transistor P is a PMOS.

[0049] The source of the first field effect transistor N1, the source of the third field effect transistor N3, the source of the fourth field effect transistor N4 and the drain of the sixth field effect transistor P are grounded, the gate of the first field effect transistor N1 is connected to the drain of the first field effect transistor N1, the gate of the second field effect transistor N2, the gate of the sixth field effect transistor P and the output end of the second current source Idc2, and the gate of the third field effect transistor N3 is connected to the drain of the third field effect transistor N3, the gate of the fourth field effect transistor N4 and the output end of the first current source Idc1.

[0050] The gate of the fifth field effect transistor N5 is connected to the source of the sixth field effect transistor P and the output end of the third current source Idc3, the drain of the fifth field effect transistor N5 is connected to the power supply, the source of the fifth field effect transistor N5 is connected to the drain of the second field effect transistor N2, and the source of the second field effect transistor N2 is connected to the drain of the fourth field effect transistor N4 and the output end of the reference source.

[0051] The bandgap reference voltage Vbg output by the reference source is Vgs1-Vgs2, where Vgs1 is the gate-source voltage of the first field effect transistor N1, and Vgs2 is the gate-source voltage of the second field effect transistor N2. In this way, the reference current generated inside the reference source is large, resulting in large circuit power consumption.

[0052] In order to solve the above problems, the embodiment of the present disclosure provides a reference circuit, including a startup module, a current source module and a bandgap module. The startup module can start the current source module after the power supply is powered on. The current source module can generate a reference current of the order of nA after the startup is completed, and control the startup module to stop working. The bandgap module can generate a bandgap reference voltage with a zero temperature coefficient according to the reference current. In this way, after the startup is completed, the current source module can generate a reference current of the order of nA, thereby reducing the power consumption of the circuit. After the startup is completed, the startup module stops working, which can further reduce the power consumption of the circuit.

[0053] Figure 2 A schematic diagram of a reference circuit provided in an embodiment of the present disclosure is shown in FIG. Figure 2 As shown, the reference circuit 100 includes a startup module 110 , a current source module 120 and a bandgap module 130 .

[0054] Among them, the output end of the startup module 110 is connected to the input end of the current source module 120, the output end of the current source module 120 is connected to the input end of the bandgap module 130 and the input end of the startup module 110, the output end of the bandgap module 130 is connected to the output end of the reference circuit 100, and the power supply end of the startup module 110, the power supply end of the current source module 120 and the power supply end of the bandgap module 130 are connected to the power supply.

[0055] The startup module 110 is configured to start the current source module 120 after the power supply is powered on. The current source module 120 is configured to generate a reference current i of the order of nA after the startup is completed, and control the startup module 110 to stop working. The bandgap module 130 is configured to generate a bandgap reference voltage Vbg with a zero temperature coefficient according to the reference current i.

[0056] For example, Figure 3 A circuit diagram of a reference circuit provided by an embodiment of the present disclosure is shown in FIG. Figure 3 As shown, the current source module 120 includes a first current mirror unit 121 , a second current mirror unit 122 , a first transistor M1 , and a second transistor M2 .

[0057] The input end of the first current mirror unit 121 is connected to a power supply, the first output end of the first current mirror unit 121 is connected to the first input end of the second current mirror unit 122, the control end of the second current mirror unit 122 and the output end of the start-up module 110, the second output end of the first current mirror unit 121 is connected to the second input end of the second current mirror unit 122, the third output end of the first current mirror unit 121 is connected to the second end of the first transistor M1, the control end of the first transistor M1 and the control end of the second transistor M2. The first output end of the second current mirror unit 122 is grounded, the second output end of the second current mirror unit 122 is connected to the second end of the second transistor M2, and the first end of the second transistor M2 and the first end of the first transistor M1 are grounded.

[0058] Specifically, the first transistor M1 and the second transistor M2 are NMOS. The drain of the first transistor M1 is connected to the gate of the first transistor M1, the gate of the second transistor M2 and the third output terminal of the first current mirror unit 121, the drain of the second transistor M2 is connected to the second output terminal of the second current mirror unit 122, and the source of the second transistor M2 and the source of the first transistor M1 are grounded.

[0059] Continue to see Figure 3 , the first current mirror unit 121 includes a third transistor M3, a fourth transistor M4 and a fifth transistor M5. The first end of the third transistor M3, the first end of the fourth transistor M4 and the first end of the fifth transistor M5 are connected to the power supply, the control end of the third transistor M3 is connected to the control end of the fourth transistor M4, the second end of the fourth transistor M4, the control end of the fifth transistor M5, the second input end of the second current mirror unit 122, the input end of the startup module 110 and the input end of the bandgap module 130, the second end of the third transistor M3 is connected to the second end of the first transistor M1, the control end of the first transistor M1 and the control end of the second transistor M2, and the second end of the fifth transistor M5 is connected to the first input end of the second current mirror unit 122, the control end of the second current mirror unit 122 and the output end of the startup module 110.

[0060] Specifically, the third transistor M3, the fourth transistor M4 and the fifth transistor M5 are PMOS. The source of the third transistor M3, the source of the fourth transistor M4 and the source of the fifth transistor M5 are connected to the power supply, the gate of the third transistor M3 is connected to the gate of the fourth transistor M4, the drain of the fourth transistor M4, the gate of the fifth transistor M5, the second input end of the second current mirror unit 122, the input end of the startup module 110 and the input end of the bandgap module 130, the drain of the third transistor M3 is connected to the drain of the first transistor M1, the gate of the first transistor M1 and the gate of the second transistor M2, and the drain of the fifth transistor M5 is connected to the first input end of the second current mirror unit 122, the control end of the second current mirror unit 122 and the output end of the startup module 110.

[0061] Continue to see Figure 3 The second current mirror unit 122 includes a sixth transistor M6 and a seventh transistor M7. The first end of the sixth transistor M6 is connected to the second end of the second transistor M2, the second end of the sixth transistor M6 is connected to the second output end of the first mirror unit 121, the control end of the sixth transistor M6 is connected to the control end of the seventh transistor M7, the second end of the seventh transistor M7, the first output end of the first mirror unit 121 and the output end of the start-up module 110, and the first end of the seventh transistor M7 is grounded.

[0062] Specifically, the sixth transistor M6 and the seventh transistor M7 are NMOS. The source of the sixth transistor M6 is connected to the drain of the second transistor M2, the drain of the sixth transistor M6 is connected to the drain of the fourth transistor M4, the gate of the fourth transistor, the gate of the fifth transistor M5, the gate of the third transistor M3, the input end of the startup module 110 and the input end of the bandgap module 130, the gate of the sixth transistor M6 is connected to the gate of the seventh transistor M7, the drain of the seventh transistor M7, the drain of the fifth transistor M5 and the output end of the startup module 110, and the source of the seventh transistor M7 is grounded.

[0063] The power supply provides a power supply voltage Vcc, and after the power supply is powered on, the startup module 110 provides the output startup voltage to the current source module 120 to start the current source module 120. During the startup process of the current source module 120, the gate of the sixth transistor M6 receives the startup voltage, and the gate voltage of the sixth transistor M6 gradually increases. When the gate-source voltage of the sixth transistor M6 increases to exceed the threshold voltage of the sixth transistor M6, the sixth transistor M6 is turned on, which can pull down the drain voltage of the fourth transistor M4, thereby pulling down the gate voltage of the third transistor M3, the gate voltage of the fourth transistor M4, and the gate voltage of the fifth transistor M5, and then the third transistor M3, the fourth transistor M4, and the fifth transistor M5 are all turned on.

[0064] After the third transistor M3, the fourth transistor M4 and the fifth transistor M5 are turned on, the current source module 120 is a negative feedback loop, and the feedback coefficient is less than 1. At this time, the current source module 120 is started up, and the negative feedback loop is stable. After the current source module 120 is started up, a reference current i of the order of nA can be output, and the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 work in the subthreshold region under the condition of small current.

[0065] After the current mirror module 120 is started, since the fourth transistor M4 operates in the subthreshold region, the gate voltage of the fourth transistor M4 is a low-level signal, that is, the current mirror module 120 outputs a low-level signal to the start-up module 110 to control the start-up module 110 to stop working, thereby reducing the power consumption of the start-up module 110, that is, reducing the power consumption of the reference circuit 100.

[0066] After the current mirror module 120 is started, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 operate in the subthreshold region, and the source voltage Vs M6 It can be expressed as:

[0067]

[0068] Among them, n c is the process coefficient, V t is the thermal voltage, W M6 / L M6 is the width-to-length ratio of the sixth transistor M6, W M7 / L M7 is the width-to-length ratio of the seventh transistor M7, W M5 / L M5 is the width-to-length ratio of the fifth transistor M5, W M4 / L M4 is the width-to-length ratio of the fourth transistor M4.

[0069] After the current mirror module 120 is started, the third transistor M3 operates in the subthreshold region, and the first transistor M1 operates in the saturation region. Then, the current i flowing through the third transistor M3 is M3 It can be expressed as:

[0070]

[0071] Among them, μ nM1 is the electron mobility of the first transistor M1, C OXM1 is the capacitance per unit area of ​​the gate oxide layer of the first transistor M1, Vth M1 is the threshold voltage of the first transistor M1, W M1 / L M1is the width-to-length ratio of the first transistor M1, Vg M1 is the gate voltage of the first transistor M1.

[0072] In addition, after the current mirror module 120 is started, the second transistor M2 operates in the linear region, and the reference current i can be expressed as:

[0073]

[0074] Among them, W M2 / L M2 is the width-to-length ratio of the second transistor M2, Vth M2 is the threshold voltage of the second transistor M2, μ nM2 is the electron mobility of the second transistor M2, C OXM2 is the capacitance per unit area of ​​the gate oxide layer of the second transistor M2.

[0075] make

[0076] Among them, W M3 / L M3 is the width-to-length ratio of the third transistor M3, and Vth M1 =Vth M2 , according to formula (1), formula (2) and formula (3), we can get the following formula:

[0077]

[0078] According to formula (4), the value of the reference current i depends on the width-to-length ratio W of the second transistor M2. M2 / L M2 .

[0079] In this way, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 operate in the subthreshold region, and can generate a small reference current i. In addition, by selecting the second transistor M2 with a small width-to-length ratio, the current source module 120 can generate a reference current i of the nA order of magnitude, for example, a reference current of 6nA can be generated.

[0080] Continue to see Figure 3 The start-up module 110 includes an eighth transistor M8, a ninth transistor M9 and a transistor assembly 111. The first end of the eighth transistor M8 and the first end of the ninth transistor M9 are connected to the power supply, the second end of the eighth transistor M8 is connected to the control end of the ninth transistor M9 and the input end of the transistor assembly 111, the control end of the eighth transistor M8 is connected to the output end of the current source module 120, the second end of the ninth transistor M9 is connected to the input end of the current source module 120, and the output end of the transistor assembly 111 is grounded.

[0081] Specifically, the eighth transistor M8 and the ninth transistor M9 are PMOS. The source of the eighth transistor M8 and the source of the ninth transistor M9 are connected to the power supply, the gate of the eighth transistor M8 is connected to the gate of the third transistor M3, the gate of the fourth transistor M4, the drain of the fourth transistor M4, the gate of the fifth transistor M5, the drain of the sixth transistor M6 and the input end of the bandgap module 130, the drain of the eighth transistor M8 is connected to the gate of the ninth transistor M9 and the input end of the transistor assembly 111, and the drain of the ninth transistor M9 is connected to the gate of the sixth transistor M6, the gate of the seventh transistor M7, the drain of the seventh transistor M7 and the drain of the fifth transistor M5.

[0082] During the power-on process, the voltage provided by the power supply gradually rises from 0 to the power supply voltage Vcc and stabilizes at the power supply voltage Vcc. After the power supply is powered on, the gate voltage of the ninth transistor M9 is initially 0, and the ninth transistor M9 is turned on. The ninth transistor M9 can use the voltage provided by the power supply as a starting voltage and provide it to the gate of the sixth transistor M6 and the gate of the seventh transistor M7.

[0083] As the voltage provided by the power supply gradually increases, the startup voltage gradually increases, and the gate voltage of the sixth transistor M6 and the gate voltage of the seventh transistor M7 also gradually increase. When the gate-source voltage of the sixth transistor M6 increases to exceed the threshold voltage of the sixth transistor M6, the current source module 120 starts to start.

[0084] After the current source module 120 is started, the gate voltage of the fourth transistor M4 is a low-level signal, the gate voltage of the eighth transistor M8 is a low-level signal, the eighth transistor M8 is turned on, the eighth transistor M8 and the fourth transistor M4 form a mirror structure, and the eighth transistor M8 can mirror the reference current i to the transistor component 111, and flow into the ground through the transistor component 111. After the current mirrored by the eighth transistor M8 flows through the transistor component 111, a voltage drop is generated between the input terminal and the output terminal of the transistor component 111, which can pull up the input terminal voltage of the transistor component 111, that is, pull up the gate voltage of the ninth transistor M9, so as to control the ninth transistor M9 to turn off, and then the start-up module 110 stops working.

[0085] In this way, after the current source module 120 is started up, the transistor component 111 can pull up the control voltage of the ninth transistor M9 to control the ninth transistor M9 to be turned off.

[0086] Continue to see Figure 3The bandgap module 130 includes a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12. The first end of the tenth transistor M10 is connected to the power supply, the control end of the tenth transistor M10 is connected to the input end of the start-up module 110 and the output end of the current source module 120, the second end of the tenth transistor M10 is connected to the second end of the eleventh transistor M11, the control end of the eleventh transistor M11, and the control end of the twelfth transistor M12, the first end of the eleventh transistor M11 is connected to the second end of the twelfth transistor M12 and the output end of the reference circuit 100, and the first end of the twelfth transistor M12 is grounded.

[0087] Specifically, the tenth transistor M10 is a PMOS, the eleventh transistor M11 is a Flipped Gate Doped (FGD) NMOS, the twelfth transistor M12 is a Normal Gate Doped (NGD) NMOS, and the eleventh transistor M11 and the twelfth transistor M12 operate in a subthreshold region.

[0088] The gate of the tenth transistor M10 is connected to the gate of the third transistor M3, the gate of the fourth transistor M4, the gate of the fifth transistor M5, the gate of the eighth transistor M8, the drain of the fourth transistor M4 and the drain of the sixth transistor M6, the drain of the tenth transistor M10 is connected to the drain of the eleventh transistor M11, the gate of the eleventh transistor M11 and the gate of the twelfth transistor M12, the source of the eleventh transistor M11 is connected to the drain of the twelfth transistor M12, and the source of the twelfth transistor M12 is grounded.

[0089] After the current source module 120 is started, the tenth transistor M10 and the fifth transistor M5 form a mirror structure, and the tenth transistor M10 can mirror the reference current i and output it. Since the reference current i is a current of nA order of magnitude, the current mirrored by the tenth transistor M10 is also a current of nA order of magnitude.

[0090] The bandgap reference voltage Vbg can be expressed as:

[0091] Vbg=Vgs M12 -Vgs M11 (5)

[0092] Among them, Vgs M12 is the gate-source voltage of the twelfth transistor M12, Vgs M11 is the gate-source voltage of the eleventh transistor M11.

[0093] The eleventh transistor M11 and the twelfth transistor M12 operate in the subthreshold region. Based on formula (5), the bandgap reference voltage Vbg can be further expressed as:

[0094]

[0095] Among them, Vth M12 is the threshold voltage of the twelfth transistor M12, Vth M11 is the threshold voltage of the eleventh transistor M11, W M11 / L M11 is the width-to-length ratio of the eleventh transistor M11, W M12 / L M12 is the width-to-length ratio of the twelfth transistor M12.

[0096] Since the eleventh transistor M11 is a FGD NMOS and the twelfth transistor M12 is a NGD NMOS, Vth M12 -Vth M11 is a negative temperature coefficient voltage. In addition, V t It is a positive temperature coefficient voltage, so by adjusting the width-to-length ratio of the eleventh transistor M11 and the width-to-length ratio of the twelfth transistor M12, a bandgap reference voltage Vbg with a zero temperature coefficient can be obtained.

[0097] In summary, the current source module can generate a reference current of nA level after startup is completed, thereby reducing the power consumption of the reference circuit. The current source module can also control the startup module to stop working after startup is completed, further reducing the power consumption of the reference circuit.

[0098] In some embodiments, see Figure 3 The transistor component 111 includes a plurality of diode-connected transistors connected in series.

[0099] For example, Figure 3 As shown, the transistor component 111 includes a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, and a seventeenth transistor M17.

[0100] Among them, the second end of the thirteenth transistor M13 is connected to the control end of the thirteenth transistor M13, the second end of the eighth transistor M8 and the control end of the ninth transistor M9, the first end of the thirteenth transistor M13 is connected to the second end of the fourteenth transistor M14 and the control end of the fourteenth transistor M14, the first end of the fourteenth transistor M14 is connected to the second end of the fifteenth transistor M15 and the control end of the fifteenth transistor M15, the first end of the fifteenth transistor M15 is connected to the second end of the sixteenth transistor M16 and the control end of the sixteenth transistor M16, the first end of the sixteenth transistor M16 is connected to the second end of the seventeenth transistor M17 and the control end of the seventeenth transistor M17, and the first end of the seventeenth transistor M17 is grounded.

[0101] Specifically, the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16 and the seventeenth transistor M17 are NMOS. The drain of the thirteenth transistor M13 is connected to the gate of the thirteenth transistor M13, the drain of the eighth transistor M8 and the gate of the ninth transistor M9, the source of the thirteenth transistor M13 is connected to the drain of the fourteenth transistor M14 and the gate of the fourteenth transistor M14, the source of the fourteenth transistor M14 is connected to the drain of the fifteenth transistor M15 and the gate of the fifteenth transistor M15, the source of the fifteenth transistor M15 is connected to the drain of the sixteenth transistor M16 and the gate of the sixteenth transistor M16, the source of the sixteenth transistor M16 is connected to the drain of the seventeenth transistor M17 and the gate of the seventeenth transistor M17, and the source of the seventeenth transistor M17 is grounded.

[0102] After the current source module 120 is started, the current mirrored by the eighth transistor M8 flows into the ground through the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16 and the seventeenth transistor M17 in sequence. At this time, the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16 and the seventeenth transistor M17 can be understood as impedance devices, so a high-level signal is generated at the drain of the thirteenth transistor M13, thereby pulling up the gate voltage of the ninth transistor M9 to control the ninth transistor M9 to turn off.

[0103] Since the reference current i is a current of the order of nA, the current mirrored by the eighth transistor M8 is also a current of the order of nA, and the power supply voltage Vcc provided by the power supply is generally a voltage of the order of V, so an impedance of the order of GΩ is required. An impedance of the order of GΩ can be achieved by using a plurality of transistors connected in series with diodes, which has a smaller size than a resistor, and is conducive to miniaturization of the circuit.

[0104] It should be noted that the embodiment of the present disclosure only takes five diode-connected transistors in series as an example to exemplify the transistor component 111. In practical applications, the transistor component 111 may also include two, three, four or more diode-connected transistors in series.

[0105] In some embodiments, see Figure 3 The startup module 110 further includes a capacitor C. A first plate of the capacitor C is connected to the second end of the eighth transistor M8, the control end of the ninth transistor M9 and the input end of the transistor assembly 111, and a second plate of the capacitor C is grounded.

[0106] Exemplarily, after the power supply is turned on, the parasitic capacitance in the reference circuit 100 may increase the gate voltage of the ninth transistor M9 , thereby increasing the startup time of the reference circuit 100 .

[0107] In the embodiment of the present disclosure, a capacitor C is connected between the gate of the ninth transistor M9 and the ground. During the startup process, the capacitor C can pull the gate voltage of the ninth transistor M9 down to the ground, providing a large startup voltage to the current source module 120 as much as possible, thereby shortening the startup time of the reference circuit 100.

[0108] An embodiment of the present disclosure further provides a chip, comprising the reference circuit 100 provided in any of the above embodiments.

[0109] The chip provided by the embodiment of the present disclosure includes the reference circuit 100 provided by any of the above embodiments, and has the same functional modules and beneficial effects as the reference circuit 100, which will not be described in detail here.

[0110] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0111] Further aspects and scopes of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended for purposes of illustration only and are not intended to limit the scope of the present application.

[0112] Several embodiments of the present disclosure are described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the attached claims.

Claims

1. A reference circuit, characterized in that: include: Start-up module, current source module and bandgap module; The output end of the startup module is connected to the input end of the current source module, the output end of the current source module is connected to the input end of the bandgap module and the input end of the startup module, the output end of the bandgap module is connected to the output end of the reference circuit, and the power supply end of the startup module, the power supply end of the current source module and the power supply end of the bandgap module are connected to a power supply; The startup module is configured to start the current source module after the power supply is powered on; The current source module is configured to generate a reference current of the nanoampere level after the startup is completed, and control the startup module to stop working; The bandgap module is configured to generate a bandgap reference voltage with a zero temperature coefficient according to the reference current.

2. The reference circuit according to claim 1, characterized in that: The current source module includes a first current mirror unit, a second current mirror unit, a first transistor and a second transistor; The input end of the first current mirror unit is connected to the power supply, the first output end of the first current mirror unit is connected to the first input end of the second current mirror unit, the control end of the second current mirror unit and the output end of the startup module, the second output end of the first current mirror unit is connected to the second input end of the second current mirror unit, and the third output end of the first current mirror unit is connected to the second end of the first transistor, the control end of the first transistor and the control end of the second transistor; A first output terminal of the second current mirror unit is grounded, a second output terminal of the second current mirror unit is connected to a second terminal of the second transistor, and a first terminal of the second transistor and a first terminal of the first transistor are grounded.

3. The reference circuit according to claim 2, characterized in that: The first current mirror unit includes a third transistor, a fourth transistor and a fifth transistor; The first end of the third transistor, the first end of the fourth transistor and the first end of the fifth transistor are connected to the power supply, the control end of the third transistor is connected to the control end of the fourth transistor, the second end of the fourth transistor, the control end of the fifth transistor, the second input end of the second current mirror unit, the input end of the startup module and the input end of the bandgap module, the second end of the third transistor is connected to the second end of the first transistor, the control end of the first transistor and the control end of the second transistor, and the second end of the fifth transistor is connected to the first input end of the second current mirror unit, the control end of the second current mirror unit and the output end of the startup module.

4. The reference circuit according to claim 3, characterized in that: The second current mirror unit includes a sixth transistor and a seventh transistor; The first end of the sixth transistor is connected to the second end of the second transistor, the second end of the sixth transistor is connected to the second output end of the first mirror unit, the control end of the sixth transistor is connected to the control end of the seventh transistor, the second end of the seventh transistor, the first output end of the first mirror unit and the output end of the startup module, and the first end of the seventh transistor is grounded.

5. The reference circuit according to claim 4, characterized in that: The first transistor operates in a saturation region, the second transistor operates in a linear region, and the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor operate in a subthreshold region.

6. The reference circuit according to claim 5, characterized in that: The reference current is expressed as: Wherein, i is the reference current, n c is the process coefficient, V t is the thermal voltage, μ nM2 is the electron mobility of the second transistor, C OXM2 is the capacitance per unit area of ​​the gate oxide layer of the second transistor, W M2 / L M2 is the width-to-length ratio of the second transistor, S2 is expressed as: Among them, W M1 / L M1 is the width-to-length ratio of the first transistor, W M3 / L M3 is the width-to-length ratio of the third transistor, W M4 / L M4 is the width-to-length ratio of the fourth transistor, μ nM1 is the electron mobility of the first transistor, C OXM1 is the capacitance per unit area of ​​the gate oxide layer of the first transistor; S1 is expressed as: Among them, W M6 / L M6 is the width-to-length ratio of the sixth transistor, W M7 / L M7 is the width-to-length ratio of the seventh transistor, W M5 / L M5 is the width-to-length ratio of the fifth transistor.

7. The reference circuit according to claim 1, characterized in that: The startup module includes an eighth transistor, a ninth transistor and a transistor assembly; The first end of the eighth transistor and the first end of the ninth transistor are connected to the power supply, the second end of the eighth transistor is connected to the control end of the ninth transistor and the input end of the transistor component, the control end of the eighth transistor is connected to the output end of the current source module, the second end of the ninth transistor is connected to the input end of the current source module, and the output end of the transistor component is grounded; The transistor component is configured to, after the current source module is started up, pull up the control voltage of the ninth transistor to control the ninth transistor to be turned off.

8. The reference circuit according to claim 7, characterized in that: The transistor assembly includes a plurality of diode-connected transistors connected in series.

9. The reference circuit according to claim 7, characterized in that: The startup module also includes a capacitor; The first plate of the capacitor is connected to the second end of the eighth transistor, the control end of the ninth transistor and the input end of the transistor component, and the second plate of the capacitor is grounded.

10. The reference circuit according to any one of claims 1 to 9, characterized in that: The bandgap module includes a tenth transistor, an eleventh transistor and a twelfth transistor; The first end of the tenth transistor is connected to the power supply, the control end of the tenth transistor is connected to the input end of the startup module and the output end of the current source module, the second end of the tenth transistor is connected to the second end of the eleventh transistor, the control end of the eleventh transistor and the control end of the twelfth transistor, the first end of the eleventh transistor is connected to the second end of the twelfth transistor and the output end of the reference circuit, and the first end of the twelfth transistor is grounded; The eleventh transistor and the twelfth transistor operate in a subthreshold region, the eleventh transistor is a gate reverse-doped N-type metal oxide semiconductor field effect transistor FGD NMOS, and the twelfth transistor is a normal gate NGDNMOS.

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