Power switch circuit, chip, terminal and control method of power switch circuit

Abstract

The invention provides a power switch circuit, a chip, a terminal and a control method of the power switch circuit, and belongs to the technical field of circuit design. The power switch circuit comprises a first buffer and a plurality of voltage drop layers. The plurality of voltage drop layers are sequentially connected in series, and the head ends of the plurality of voltage drop layers are electrically connected with the output end of the first buffer and a power supply respectively; the tail ends of the plurality of voltage drop layers are electrically connected with a mature design IP (Internet Protocol) of a circuit module with an independent function in a controlled chip; the first buffer is used for receiving a standby signal and transmitting the standby signal to the plurality of voltage drop layers; and the plurality of voltage drop layers are used for reducing the voltage transmitted to the IP by the power supply in response to the standby signal. The power consumption saving effect can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of circuit design, and in particular to a power switch circuit, a chip, a terminal, and a control method for the power switch circuit. Background Art

[0002] In order to save the power consumption of the terminal, a mature design of a circuit module with independent functions (Intellectual Property inside chip, IP) is set in the chip of the terminal. The IP is powered separately by the power switch circuit corresponding to the IP. Therefore, when the IP is in sleep or standby state, the power switch circuit of the IP is controlled to reduce the overall power consumption of the terminal.

[0003] In the related art, when the IP is in sleep or standby mode, the overall power consumption of the terminal is reduced by turning off the clock corresponding to the IP. However, simply turning off the clock has no effect on saving the leakage current of the IP, so this method has very limited effect on saving power consumption, that is, the effect of saving power consumption is poor. Summary of the invention

[0004] The embodiment of the present application provides a power switch circuit, a chip, a terminal and a control method of the power switch circuit, which can improve the power saving effect. The technical solution is as follows:

[0005] In one aspect, a power switch circuit is provided, the power switch circuit comprising:

[0006] a first buffer and a plurality of pressure drop layers;

[0007] The plurality of voltage drop layers are sequentially connected in series, and a first voltage drop layer of the plurality of voltage drop layers is electrically connected to an output end of the first buffer and a power source respectively;

[0008] The last voltage drop layer of the plurality of voltage drop layers is electrically connected to a mature design IP of a circuit module with independent functions in the controlled chip;

[0009] The first buffer is used to receive a standby signal and transmit the standby signal to the plurality of voltage drop layers;

[0010] The plurality of voltage drop layers are used to reduce the voltage delivered from the power supply to the IP in response to the standby signal.

[0011] On the other hand, a chip is provided, wherein the chip includes the above-mentioned power switch circuit.

[0012] On the other hand, a terminal is provided, comprising the above chip.

[0013] On the other hand, a control method is provided, which is applied to the power switch circuit described in the above aspect, and the method includes:

[0014] When it is determined that the IP is in a standby state, sending a standby signal to the first buffer so that the first buffer transmits the standby signal to the plurality of voltage drop layers;

[0015] In response to the standby signal, a voltage delivered by the power supply to the IP is reduced through the plurality of voltage drop layers.

[0016] In the embodiment of the present application, multiple voltage drop layers are added to the power switch circuit of the IP, so that the voltage transmitted from the power supply to the IP can be reduced through the multiple voltage drop layers; and because there are multiple voltage drop layers, more voltage can be reduced, so that the voltage transmitted to the IP will be relatively small, thereby reducing the vulnerability power consumption of the IP, that is, the power consumption saving effect can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A block diagram of a power switch circuit shown in an exemplary embodiment of the present application is shown;

[0018] Figure 2 A block diagram of a power switch circuit shown in an exemplary embodiment of the present application is shown;

[0019] Figure 3 A block diagram of a power switch circuit shown in an exemplary embodiment of the present application is shown;

[0020] Figure 4 A block diagram of a power switch circuit shown in an exemplary embodiment of the present application is shown;

[0021] Figure 5 A block diagram of a power switch circuit shown in an exemplary embodiment of the present application is shown;

[0022] Figure 6 A block diagram of a power switch circuit shown in an exemplary embodiment of the present application is shown;

[0023] Figure 7 A flow chart showing a method for controlling a power switch circuit according to an exemplary embodiment of the present application is shown;

[0024] Figure 8 A flow chart showing a method for controlling a power switch circuit according to an exemplary embodiment of the present application is shown;

[0025] Fig. 9 A flow chart showing a method for controlling a power switch circuit according to an exemplary embodiment of the present application is shown;

[0026] Fig.10 A schematic diagram of a control method for a power switch circuit according to an exemplary embodiment of the present application is shown.

[0027] 10First Buffer

[0028] 20 Pressure drop layer

[0029] 201Power Header

[0030] 202 voltage drop control unit

[0031] 203 Second Buffer

[0032] 2011 Transistor

[0033] 2012Power Switch DETAILED DESCRIPTION

[0034] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0035] The term "multiple" as used herein refers to two or more than two. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.

[0036] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions. For example, the standby signals and wake-up signals involved in this application are all obtained with full authorization.

[0037] Please refer to Figure 1 , which shows a block diagram of a power switch circuit shown in an exemplary embodiment of the present application. The power switch circuit includes: a first buffer 10 and multiple voltage drop layers 20; the multiple voltage drop layers 20 are connected in series in sequence, and the first voltage drop layers of the multiple voltage drop layers 20 are electrically connected to the output end of the first buffer 10 and the power supply (Vdd) respectively; the last voltage drop layer of the multiple voltage drop layers 20 is electrically connected to the mature design IP of the circuit module with independent functions in the controlled chip. The output of the last voltage drop layer is the output end (Vdd_out), so it is electrically connected to the IP through Vdd_out.

[0038] The first buffer 10 is used to receive a standby signal and transmit the standby signal to a plurality of voltage drop layers 20; in some embodiments, the input end of the first buffer 10 is electrically connected to the first controller, and the first controller is used to input a standby signal to the first buffer 10 when the IP enters the standby state. The type of the standby signal may be a nsleep_in signal, which is used to control whether the power switch circuit enters the standby state, that is, when the IP is in the standby state, the nsleep_in signal is used to control the power switch circuit to enter the standby state, thereby saving power consumption of the terminal; and when the IP is in the working state, the nsleep_in signal is used to control the power switch circuit to exit the standby state, thereby controlling the power supply to supply power to the IP through the power switch circuit to ensure the normal operation of the IP.

[0039] Multiple voltage drop layers 20 are used to reduce the voltage delivered from the power supply to the IP in response to the standby signal. In some embodiments, after the IP enters the standby state, multiple voltage drop layers 20 can be connected in series between the power supply and the IP, so that the multiple voltage drop layers 20 can consume some voltage, so that the voltage delivered from the power supply to the IP will be reduced, so as to reduce the voltage delivered from the power supply to the IP through multiple voltage drop layers 20. In some embodiments, multiple voltage drop layers 20 are equivalent to multi-layer stacking, and one voltage drop layer 20 is equivalent to one layer of stacking, that is, the embodiment of the present application is to reduce the voltage delivered from the power supply to the IP through multi-layer stacking, thereby reducing the leakage circuit of the IP, thereby saving the power consumption of the terminal.

[0040] In some embodiments, IP is any module with independent functions in the terminal; for example, IP can be a voice wake-up module or a camera module in the terminal, etc. In the embodiment of the present application, IP is not specifically limited. In the embodiment of the present application, the power consumption of the terminal can be saved by powering the IP through a power switch circuit. In addition, the number of voltage drop layers 20 can be set and changed as needed; for example, the number of voltage drop layers 20 can be 2, 3 or 4, etc. In the embodiment of the present application, the number of voltage drop layers 20 is 3 for illustration, that is, the embodiment of the present application is a low-power standby solution that responds quickly through a 3-layer stack.

[0041] In the embodiment of the present application, multiple voltage drop layers 20 are added to the power switch circuit of the IP, and the voltage transmitted from the power supply to the IP can be reduced through the multiple voltage drop layers 20; and because there are multiple voltage drop layers 20, more voltage can be reduced, so that the voltage transmitted to the IP will be relatively small, thereby reducing the vulnerability power consumption of the IP, that is, the power consumption saving effect can be improved.

[0042] Moreover, in the embodiment of the present application, the power supply (Power Rail) is not turned off. Instead, the voltage of the power supply delivered to the IP is reduced. Therefore, compared with the solution of turning off the Power Rail, the clock cycle required to enter and exit the standby state can be greatly shortened to one tenth of the clock cycle required to turn off the Power Rail. Moreover, since the Power Rail is not turned off, the power supply provides sufficient voltage and leakage current so that the registers in the IP retain the original data without losing it.

[0043] Please refer to Figure 2 , which shows a block diagram of a power switch circuit shown in an exemplary embodiment of the present application. The voltage drop layer 20 includes a voltage drop control unit 201 and multiple power switch elements (Power Header 201). The multiple Power Headers 201 are connected in sequence. The input end of the first Power Header 201 in the multiple Power Headers 201 is electrically connected to the output end of the voltage drop control unit 201; the input ends of the multiple Power Headers 201 are electrically connected to the output end of the first buffer 10 and the power supply respectively; the output ends of the multiple Power Headers 201 are electrically connected to the IP. Figure 2 In the description, the voltage drop layer 20 includes two Power Headers 201 as an example.

[0044] For the first voltage drop layer 20, the input ends of the multiple Power Headers 201 included in the first voltage drop layer 20 are directly electrically connected to the output end and the power supply of the first buffer 10, and for other voltage drop layers 20, the input ends of the multiple Power Headers 201 included in other voltage drop layers 20 are indirectly electrically connected to the output end and the power supply of the first buffer 10, that is, the input ends of the multiple Power Headers 201 included in other voltage drop layers 20 are electrically connected to the output ends of the multiple Power Headers 201 included in the previous voltage drop layer 20, and the input ends of the multiple Power Headers 201 included in the previous voltage drop layer 20 are electrically connected to the output ends of the multiple Power Headers 201 included in the previous voltage drop layer 20, and so on, until the input ends of the multiple Power Headers 201 included in the first voltage drop layer 20 are electrically connected to the output end and the power supply of the first buffer 10.

[0045] For the last voltage drop layer 20, the output ends of the multiple Power Headers 201 included in the last voltage drop layer 20 are directly electrically connected to the IP, and for other voltage drop layers 20, the output ends of the multiple Power Headers 201 included in other voltage drop layers 20 are indirectly electrically connected to the IP, that is, the output ends of the multiple Power Headers 201 included in other voltage drop layers 20 are electrically connected to the input ends of the multiple Power Headers 201 included in the next voltage drop layer 20, and the output ends of the multiple Power Headers 201 included in the next voltage drop layer 20 are electrically connected to the input ends of the multiple Power Headers 201 included in the next voltage drop layer 20, and so on, until the output ends of the multiple Power Headers 201 included in the last voltage drop layer 20 are electrically connected to the IP.

[0046] The voltage drop control unit 202 is used to control the switches of multiple Power Headers 201; in some embodiments, the input end of the voltage drop control unit 202 is electrically connected to the output end of the second controller, so that the second controller controls the voltage drop control unit 202 through a control signal, so that the voltage drop control unit 202 controls the switch of the Power Header 201. For example, when it is necessary to start the Power Header 201, the voltage drop control unit 202 controls the switch of the Power Header 201 to be in an on state; when it is not necessary to start the Power Header 201, the voltage drop control unit 202 controls the switch of the Power Header 201 to be in a closed state. In addition, the first controller and the second controller can be the same controller or different controllers. In the embodiment of the present application, the first controller and the second controller are taken as the same controller as an example for explanation.

[0047] Power Header 201 is used to reduce the voltage delivered from the power supply to the IP when in the on state. In some embodiments, when Power Header 201 is in the on state, Power Header 201 is connected in series between the power supply and the IP, and Power Header 201 is equivalent to a diode, which consumes some voltage, so that the voltage delivered from the power supply to the IP is reduced. When Power Header 201 is in the off state, Power Header 201 is not connected in series between the power supply and the IP, so that Power Header 201 does not consume voltage and does not reduce the voltage delivered from the power supply to the IP.

[0048] In some embodiments, when the voltage reduction layer 20 includes a plurality of power headers 20 , the number of the first buffers 10 may also be multiple, that is, one first buffer is electrically connected to one power header 20 .

[0049] Please refer to Figure 3 , which shows a block diagram of a power switch circuit shown in an exemplary embodiment of the present application. Power Header 201 includes a transistor 2011 and a power switch Power Switch 2012;

[0050] The base of transistor 2011 and one end of Power Switch 2012 are electrically connected to the output end of the first buffer 10 and the power supply respectively, the collector of transistor 2011 and the other end of Power Switch 2012 are electrically connected to IP respectively, and the emitter of transistor 2011 is electrically connected to the output end of the voltage drop control unit 202.

[0051] In some embodiments, the voltage drop layer 20 further includes a second buffer 203, the input end of the second buffer 203 is electrically connected to the collector of the transistor 2011 and the other end of the Power Switch 2012, respectively, and the output end of the second buffer 203 is electrically connected to the emitter of the transistor 2011 included in the next Power Header 201.

[0052] The second buffer 203 is used to transmit the control signal output by the previous voltage drop control unit 202 to the next Power Header 201. For example, if the voltage drop control unit 202 outputs a high level signal, the voltage drop control unit 202 transmits the high level signal to the first Power Header 201, the first Power Header 201 transmits the high level signal to the second buffer 203 electrically connected thereto, the second buffer 203 transmits the high level signal to the second Power Header 201, and so on, until the high level signal is transmitted to the last Power Header 201.

[0053] For the first Power Header 201, the emitter of the transistor 2011 included in the Power Header 201 is directly electrically connected to the output end of the voltage drop control unit 202, while the emitters of the transistors 2011 included in other Power Headers 201 are indirectly electrically connected to the output end of the voltage drop control unit 202, that is, the emitters of the transistors 2011 included in other Power Headers 201 are electrically connected to the output end of the second buffer 203 included in the previous Power Header 201, and the emitter of the transistor 2011 included in the previous Power Header 201 is electrically connected to the output end of the second buffer 203 included in the previous Power Header 201, and so on, until the emitter of the transistor 2011 included in the first Power Header 201 is directly electrically connected to the output end of the voltage drop control unit 202.

[0054] In some embodiments, the transistor 2011 may be a P-metal-oxide-semiconductor (PMOS).

[0055] In some embodiments, the voltage drop control unit 202 includes: an OR gate and an inverter; the input end of the OR gate is electrically connected to the second controller, the output end of the OR gate is electrically connected to the input end of the inverter, and the output end of the inverter is electrically connected to the input end of the Power Header 201. The output end of the inverter is electrically connected to the input end of the first Power Header 201, and the input ends of other Power Headers 201 are electrically connected to the output ends of the previous Power Header 201.

[0056] In some embodiments, the second controller sends a first control signal (bypass) and a second control signal (nlv_stby) to the OR gate, and the first control signal and the second control signal can both be high-level signals, or both be low-level signals, or one high-level signal and one low-level signal. The high-level signal can be 1, and the low-level signal can be 0.

[0057] The OR gate is used to perform OR processing on the first control signal and the second control signal, and transmit the control signal obtained by the OR processing to the inverter; the inverter is used to invert the control signal obtained by the OR processing, and output the inverted control signal to the first Power Header 201 (or the transistor 2011 included therein), and the first Power Header 201 outputs the inverted control signal to the next Power Header 201, and the next Power Header 201 outputs the inverted control signal to the next Power Header 201, and so on, until the inverted control signal is output to the last Power Header 201.

[0058] In the embodiment of the present application, a diode (Switch Cell) is connected in parallel at both ends of the transistor 2011 of each layer to form a Switch Cell, and a control signal nlv_stby and a control signal bypass are added to be connected to the Switch Cell of each layer, so that these two control signals are used to control whether the diode is connected to the power switch circuit, so as to control whether the voltage transmitted from the power supply to the IP is reduced through the diode.

[0059] In some embodiments, when the IP is in working state, the input of at least one of the first control signal and the second control signal is a high level signal. Figure 4 shown. Figure 4 The description is made by taking one cell as an example, and the structures of other cells are the same as this cell, which will not be described in detail. One cell includes a first buffer 10 , a Power Header 201 and a second buffer 203 .

[0060] from Figure 4 It can be seen that when at least one of the first control signal and the second control signal is input as a high-level signal, the control signal obtained by the first control signal and the second control signal after being processed by the OR gate is a high-level signal, and the control signal obtained by the high-level signal after being inverted by the inverter is a low-level signal. The low-level signal causes the current output from the power supply to pass through the transistor 2011 instead of the diode, that is, the Switch Cell is the same as the Power Switch 2012 in the related art, so that the embodiment of the present application can ensure the compatibility of the power switch circuit and the ordinary PowerSwitch 2012. The normal nsleep_in signal can normally control the output voltage of the Power Header 201.

[0061] The embodiment of the present application ensures compatibility with the original Power Switch 2012, and does not introduce a very high voltage drop IR Drop. The final Power Switch 2012 will be composed of a small amount (<5%) of the power switch circuit plus a large amount of ordinary Power Switch 2012. In normal use, the small amount of IR Drop of the power switch circuit will be mitigated by a large amount of ordinary Power Switch 2012. When the power switch circuit is enabled in the standby state, IR Drop does not need to be paid special attention to, because the IP does not have a clock inversion at this time.

[0062] In some embodiments, when the IP is in the standby state, the first control signal and the second control signal are both low level signals, and the plurality of voltage drop layers 20 are in the standby state, and the IP powered by the power switch circuit is in the clock-off state, so the nsleep_in signal fails to control the power switch circuit. At this time, the power switch circuit is Figure 5 As shown, Figure 5 This is explained using a cell as an example. Figure 5 It can be seen that the voltage transmitted from the power supply to IP is the voltage output by the power supply minus the voltage drop of three diodes, thus achieving the effect of reducing the voltage and suppressing the leakage power consumption.

[0063] In some embodiments, when the IP is in the standby state, it is only necessary to allow the power switch circuit to control the leakage current of the register in the power supply IP to maintain the data stored therein, and the other Power Switches 2012 connected in series can completely enter the off state. In addition, when the IP is changed from the standby state to the working state, that is, when the IP exits the standby state, it is only necessary to change any one of the first control signal and the second control signal from a low level signal to a high level signal to quickly restore the power supply to the IP.

[0064] In some embodiments, multiple voltage drop layers 20 may all be in a working state, so that multiple voltage drop layers 20 are all used to reduce the voltage delivered from the power supply to the IP; or, some of the voltage drop layers 20 in the multiple voltage drop layers 20 are in a working state, and some of the voltage drop layers 20 are in an idle state, so that some of the voltage drop layers 20 are used to reduce the voltage delivered from the power supply to the IP. In the embodiment of the present application, the output voltage Vdd_out can be effectively reduced by flexibly configuring the number of voltage drop layers 20 converted into voltage drop layers 20 providing voltage drop in the multiple voltage drop layers 20 of the power switch circuit. Therefore, the embodiment of the present application provides a wider adjustment range and a more flexible adjustment method.

[0065] In some embodiments, when the first control signal nlv_stby is at a low level, the second control signal bypass of each voltage drop layer can be at a high level or at a low level, depending on how many layers the control logic wants to convert at most to use the voltage drop of the diode to reduce the output voltage Vdd_out. For example, please refer to Figure 6 ,same Figure 5 Taking a cell as an example, the two stacks (two voltage drop layers) in the power switch circuit are put into standby mode, and the top stack is still in a normal power supply state. At this time, the IP powered by this power switch circuit should be in a clock-off state. At this time, the nsleep_in signal fails to control the power switch circuit. At this time, the final output voltage Vdd_out is the voltage of the power supply minus the voltage drop of two diodes. In this way, the effect of lowering the voltage and suppressing leakage power consumption is achieved. At the same time, when the power switch circuit is in different voltage configurations, the output voltage Vdd_out can be effectively reduced by flexibly configuring the number of layers of diodes that provide voltage drops in the multi-layer stack unit of the power switch circuit.

[0066] Since the power supply will not be turned off, the embodiment of the present application can greatly reduce the leakage power consumption of the IP in the sleep state without completely turning off the voltage. In the circuit simulation, the power switch circuit provided by the embodiment of the present application is used, and the leakage current of the IP in the sleep state is reduced by 50% to 90%. Moreover, the lower the temperature and the closer the temperature is to room temperature, in the scenario of advanced process, the leakage current will be much lower than that at high temperature, and the power saving effect of the power switch circuit at this time is better.

[0067] In some embodiments, a chip is further provided, which includes the power switch circuit of the above embodiment.

[0068] In some embodiments, a terminal is also provided, the terminal including the above chip. The terminal may be a mobile phone, a tablet computer, a vehicle-mounted terminal, or a wearable device.

[0069] Please refer to Figure 7 , which shows a flow chart of a control method of a power switch circuit shown in an exemplary embodiment of the present application. The execution subject of the method may be a controller, or a terminal including a controller; in the embodiment of the present application, the execution subject of the method is taken as an example of a controller. The method includes:

[0070] Step 701: When it is determined that the IP is in a standby state, a standby signal is sent to a first buffer, so that the first buffer transmits the standby signal to a plurality of voltage drop layers.

[0071] The controller sends a standby signal to the first buffer, and the first buffer receives the standby signal and transmits the standby signal to a plurality of voltage drop layers.

[0072] Step 702: In response to a standby signal, reduce the voltage delivered by the power supply to the IP through a plurality of voltage drop layers.

[0073] For any voltage drop layer, the voltage drop layer receives standby and consumes the voltage delivered to the IP by the power supply, thereby reducing the voltage delivered to the IP.

[0074] In an embodiment of the present application, when the IP is in standby mode, the voltage transmitted from the power supply to the IP can be reduced through multiple voltage drop layers; and because there are multiple voltage drop layers, more voltage can be reduced, so that the voltage transmitted to the IP will be relatively small, thereby reducing the vulnerability power consumption of the IP, that is, the power consumption saving effect can be improved.

[0075] Please refer to Figure 8 , which shows a flow chart of a control method of a power switch circuit shown in an exemplary embodiment of the present application. The method includes:

[0076] Step 801: When it is determined that the IP is in a standby state, the controller sends a standby signal to the first buffer, so that the first buffer transmits the standby signal to a plurality of voltage drop layers.

[0077] In some embodiments, this step is the same as step 701 and will not be repeated here.

[0078] In some embodiments, when it is determined that the IP is in a standby state, the controller sends a standby signal to the first buffer; in some embodiments, when it is determined that the IP is in a standby state, the controller estimates the standby time of the IP, and when the standby time is less than a third preset time, the controller sends a standby signal to the first buffer, so that when the IP exits the standby state, it can be quickly restored; when the standby time is not less than the third preset time, the controller turns off the power supply to save power consumption.

[0079] In some embodiments, the controller may reduce the voltage delivered from the power supply to the IP through multiple voltage drop layers; or may reduce the voltage delivered from the power supply to the IP through some of the multiple voltage drop layers. When the controller reduces the voltage delivered from the power supply to the IP through some of the multiple voltage drop layers, after executing step 801, step 802 is executed.

[0080] In some embodiments, when it is determined that the IP is in a standby state, the controller may first determine a target voltage drop layer, and the controller sends a standby signal to the first buffer so that the first buffer transmits the standby signal to the target voltage drop layer.

[0081] Step 802: In response to the standby signal, the controller determines a first number of pressure drop layers currently required.

[0082] In some embodiments, the controller determines the first number of voltage drop layers currently required based on the minimum voltage required by the IP; accordingly, the step of the controller determining the first number of voltage drop layers currently required may be: the controller determines the minimum voltage of the IP, the minimum voltage being the minimum voltage required for the IP to maintain the data in the registers it includes; based on the voltage provided by the power supply and the minimum voltage, determines the voltage that needs to be reduced; based on the voltage reduced by each voltage drop layer in the multiple voltage drop layers and the voltage that needs to be reduced, determines the first number of voltage drop layers currently required.

[0083] The controller determines the difference between the voltage provided by the voltage and the minimum voltage to obtain the voltage that needs to be reduced; determines the ratio of the voltage that needs to be reduced to the voltage reduced by each voltage drop layer to obtain the first number of voltage drop layers currently required. When the ratio is an integer, the ratio is the first number of voltage drop layers currently required; when the ratio is a non-integer, the controller rounds down the ratio to obtain the first number of voltage drop layers currently required.

[0084] In some embodiments, the controller determines the first number of voltage drop layers currently required based on the standby state of the IP; accordingly, the step for the controller to determine the first number of voltage drop layers currently required can be: the controller determines the standby state of the IP, different standby states require different voltages so that the IP maintains the data in the registers it includes; and obtains the first number of layers that matches the standby state.

[0085] Standby state one corresponds to one pressure drop layer; standby state two corresponds to two pressure drop layers; standby state three corresponds to three pressure drop layers.

[0086] In the embodiment of the present application, the voltage is reduced while ensuring that the data of the register in the IP will not be lost, and there is no need to introduce an additional retention unit (Retention Flip-Flop, Retention FF); because in this dormant state, the clock has been turned off without any inversion. A small amount of current provided by the power switch circuit and a voltage not lower than the minimum voltage of the register to maintain data are sufficient to enable the register to still retain the data before entering the dormant state when the working voltage and working state are restored.

[0087] Step 803: The controller determines a first number of target pressure drop layers among the multiple pressure drop layers.

[0088] The controller randomly selects the first several target voltage drop layers from multiple voltage drop layers; or, the controller selects the first several target voltage drop layers closest to the power supply from multiple voltage drop layers; or, the controller selects the first several target voltage drop layers with the lowest usage frequency from multiple voltage drop layers.

[0089] In steps 802-803, the example in which the voltage reduced by each of the multiple voltage drop layers is the same is used for explanation; in the embodiment of the present application, the voltage reduced by each of the multiple voltage drop layers may be different; in the case in which the voltage reduced by each of the multiple voltage drop layers is different, steps 802-803 may be replaced as follows: in response to the standby signal, the controller determines the lowest voltage of the IP, the lowest voltage being the lowest voltage required for the IP to maintain the data in the registers included therein; based on the voltage provided by the power supply and the lowest voltage, the voltage to be reduced is determined, and based on the voltage reduced by each of the multiple voltage drop layers and the voltage to be reduced, at least one target voltage drop layer is determined, and the voltage reduced by at least one target voltage drop layer is equal to or less than the voltage to be reduced.

[0090] Step 804: The controller reduces the voltage delivered by the power supply to the IP through the target voltage drop layer.

[0091] This step can be achieved by following the steps (1) and (2), including:

[0092] (1) For any target voltage drop layer, the controller outputs a high level signal to the Power Header included in the target voltage drop layer through the voltage drop control unit included in the target voltage drop layer.

[0093] A controller connected through an OR gate inputs a first control signal and a second control signal to the OR gate, wherein at least one of the first control signal and the second control signal is a low-level signal; the low-level signal output by the OR gate is inverted into a high-level signal through an inverter, and a high-level signal is output to a Power Header included in the target voltage drop layer.

[0094] (2) The controller triggers the disconnection of the Power Header included in the target voltage drop layer through a high-level signal, so that the Power Header reduces the voltage delivered to the IP.

[0095] The high-level signal can trigger the Power Header included in the target voltage drop layer to disconnect, so that the diode in the Power Header will be connected in series between the power supply and the IP, so that the diode will consume the voltage delivered from the power supply to the IP, thereby reducing the voltage delivered from the power supply to the IP.

[0096] In some embodiments, the controller reduces the voltage delivered from the power supply to the IP through the target voltage drop layer; and other voltage drop layers among the multiple voltage drop layers are in a non-working state; accordingly, the processing of other voltage drop layers can be implemented by the following steps (3) to (4), including:

[0097] (3) For other pressure drop layers except the target pressure drop layer among the multiple pressure drop layers, the controller outputs a low level signal to the Power Header included in the other pressure drop layers through the pressure drop control unit included in the other pressure drop layers.

[0098] A controller connected through the OR gate inputs a first control signal and a second control signal to the OR gate, wherein at least one of the first control signal and the second control signal is a high level signal;

[0099] The high-level signal output by the OR gate is inverted into a low-level signal through an inverter, and the low-level signal is output to the Power Header included in other voltage drop layers.

[0100] (4) The Power Header included in other voltage drop layers is triggered to turn on through a low-level signal, so that the Power Header is connected in series between the power supply and the IP as a wire.

[0101] The low-level signal can trigger the Power Header included in other voltage drop layers to turn on, so that the diode in the Power Header will be short-circuited, so that the diode will not consume the voltage delivered by the power supply to the IP, nor will it reduce the voltage delivered by the power supply to the IP, that is, other voltage drop layers will not interfere with the power switch circuit.

[0102] In the embodiment of the present application, the output voltage can be adjusted by adjusting the number of enabled layers (the number of used voltage drop layers) of the multi-layer stacking unit (multiple voltage drop layers) of the power switch circuit. On the premise that the provided leakage current is sufficient for the register in the IP to maintain data, more or fewer stacking layers can be enabled for different power supply voltages to increase or decrease the output voltage, thereby increasing the adjustable range of the output voltage.

[0103] In some embodiments, the controller may recover from the standby state by following steps 805-806.

[0104] Step 805: When it is determined that the IP is changed from the standby state to the working state, the controller sends a wake-up signal to the first buffer, so that the first buffer transmits the wake-up signal to the target voltage drop layer.

[0105] The controller sends a wake-up signal to the first buffer, and the first buffer receives the wake-up signal and transmits the wake-up signal to the target voltage drop layer. In some embodiments, when the voltage delivered by the power supply to the IP is reduced through multiple voltage drop layers, the controller sends the wake-up signal to the first buffer so that the first buffer transmits the wake-up signal to the multiple voltage drop layers.

[0106] Step 806 : In response to the wake-up signal, the controller controls the target voltage drop layer to stop working, so as to restore the voltage delivered by the power supply to the IP.

[0107] The controller outputs a low-level signal to the Power Header included in the target voltage drop layer through the voltage drop control unit included in the target voltage drop layer, and triggers the Power Header included in the target voltage drop layer to turn on through the low-level signal, so that the Power Header is connected in series between the power supply and the IP as a wire, thereby not consuming the voltage delivered to the IP by the power supply.

[0108] In some embodiments, the process of the controller restoring the voltage delivered by the power supply to the IP is similar to the process of reducing the voltage delivered by the power supply to the IP, and is also restored level by level. Accordingly, the process of the controller restoring the voltage delivered by the power supply to the IP by controlling the voltage drop layer to stop working may be:

[0109] In an embodiment of the present application, when the IP is in standby mode, the voltage transmitted from the power supply to the IP can be reduced through multiple voltage drop layers; and because there are multiple voltage drop layers, more voltage can be reduced, so that the voltage transmitted to the IP will be relatively small, thereby reducing the vulnerability power consumption of the IP, that is, the power consumption saving effect can be improved.

[0110] Furthermore, since the Power Switch no longer needs to recover from zero voltage to the working voltage of the power supply when exiting from the sleep state, the exit time is greatly shortened compared to the recovery from zero voltage to the working voltage in the related art, which is only about one-third of the related art, thereby improving the recovery efficiency.

[0111] Please refer to Fig. 9 , which shows a flow chart of a control method of a power switch circuit shown in an exemplary embodiment of the present application. The method includes:

[0112] Step 901: When it is determined that the IP is in a standby state, the controller sends a standby signal to the first buffer, so that the first buffer transmits the standby signal to a plurality of voltage drop layers.

[0113] In some embodiments, this step is the same as step 801 and will not be repeated here.

[0114] In some embodiments, see Fig.10When the IP is in working state, the controller controls multiple voltage drop layers to be in idle state and maintain the idle state; and starts waiting for the IP to enter the standby state, at which time the multiple voltage drop layers are in the standby zero state.

[0115] Step 902: In response to the standby signal, the controller determines the voltage drop parameters, where the voltage drop parameters include a start-up sequence of multiple voltage drop layers and a start-up time interval between two adjacent voltage drop layers.

[0116] The controller can determine the startup sequence of multiple voltage drop layers according to the connection sequence of the voltage drop layers in the power switch circuit; for example, the power switch circuit includes three voltage drop layers, namely, voltage drop layer 1, voltage drop layer 2, and voltage drop layer 3, and voltage drop layer 1, voltage drop layer 2, and voltage drop layer 3 are sequentially connected in series between the power supply and the IP; then the startup sequence of the three voltage drop layers can be voltage drop layer 1, voltage drop layer 2, and voltage drop layer 3. In some embodiments, the startup time intervals of two adjacent voltage drop layers can be equal or unequal; in the embodiment of the present application, the startup time intervals of two adjacent voltage drop layers are equal and are both the first preset duration as an example for explanation.

[0117] Step 903: The controller starts the multiple pressure drop layers in sequence based on the start-up sequence of the multiple pressure drop layers and the start-up time interval between two adjacent pressure drop layers.

[0118] The controller starts the first pressure drop layer based on the start-up sequence of the multiple pressure drop layers; and starts counting the standby interval; when the standby interval count reaches the interval between the first pressure drop layer and the second pressure drop layer, the second pressure drop layer is started; the standby interval count is restarted, and when the standby interval count reaches the interval between the second pressure drop layer and the third pressure drop layer, the third pressure drop layer is enabled, and so on, until all the pressure drop layers are started.

[0119] For example, see Fig.10 When the IP is in standby state zero, it is not necessary to turn on the voltage drop layer for voltage reduction; when the IP is in standby state one, one voltage drop layer is enabled, that is, one layer of diodes is enabled; when the standby interval count reaches the first preset duration, the IP is in standby state two, two voltage drop layers are enabled, that is, two layers of diodes are enabled; when the standby interval count reaches the first preset duration again, the IP is in standby state three, three voltage drop layers are enabled, that is, three layers of diodes are enabled, and the standby is completed at this time, and the IP remains in standby state.

[0120] Step 904: The controller reduces the voltage delivered by the power supply to the IP through a plurality of voltage drop layers.

[0121] In some embodiments, the step of the controller reducing the voltage delivered from the power supply to the IP through multiple voltage drop layers is similar to the step of the controller reducing the voltage delivered from the power supply to the IP through the target voltage drop layer, and is not repeated here.

[0122] Step 905: When it is determined that the IP is changed from the standby state to the working state, the controller sends a wake-up signal to the first buffer, so that the first buffer transmits the wake-up signal to the multiple voltage drop layers.

[0123] In some embodiments, this step is similar to step 805 and will not be described in detail here. Fig.10 , when it is determined that the IP is changed from the standby state to the working state, the recovery starts and the recovery starts from recovery zero.

[0124] Step 906: In response to the wake-up signal, the controller determines the recovery parameters, where the recovery parameters include a recovery sequence of the multiple voltage drop layers and a recovery time interval between two adjacent voltage drop layers.

[0125] The controller determines the recovery order of the multiple pressure drop layers based on the start-up order of the multiple pressure drop layers; for example, the recovery order of the multiple pressure drop layers is opposite to the start-up order of the multiple pressure drop layers. The recovery time intervals of two adjacent pressure drop layers may be equal or unequal; in the embodiment of the present application, the recovery time intervals of two adjacent pressure drop layers are equal and both are the second preset time lengths as an example for explanation.

[0126] Step 907: The controller restores the multiple pressure drop layers in sequence based on the restoration sequence of the multiple pressure drop layers and the restoration time interval between two adjacent pressure drop layers.

[0127] The controller first restores the first pressure drop layer based on the recovery order of multiple pressure drop layers; and starts to count the standby interval; when the standby interval count reaches the interval between the first pressure drop layer and the second pressure drop layer, the second pressure drop layer is restored; the standby interval count is restarted, and when the standby interval count reaches the interval between the second pressure drop layer and the third pressure drop layer, the third pressure drop layer is restored, and so on, until multiple pressure drop layers are restored.

[0128] For example, see Fig.10At the beginning of recovery, when the IP is in recovery state zero, the voltage drop layer does not need to be restored; when the IP is in recovery state one, one voltage drop layer is restored, that is, one layer of diodes needs to be restored, and the controller stops working by controlling one target voltage drop layer; when the standby interval count reaches the second preset time, the IP is in recovery state two, and two voltage drop layers are restored, that is, two layers of diodes need to be restored, and the controller stops working by controlling two target voltage drop layers; when the standby interval count reaches the second preset time again, the IP is in recovery state three, and three voltage drop layers are restored, that is, three layers of diodes need to be restored, and the controller stops working by controlling three target voltage drop layers, and the recovery is completed at this time.

[0129] Step 908: The controller controls the multiple voltage drop layers to stop working, so as to restore the voltage delivered by the power supply to the IP.

[0130] In some embodiments, the step in which the controller controls multiple voltage drop layers to stop working to restore the voltage delivered by the power supply to the IP is similar to the step in which the controller controls the target voltage drop layer to stop working to restore the voltage delivered by the power supply to the IP in step 806, and will not be repeated here.

[0131] In an embodiment of the present application, the controller can control multiple voltage drop layers to enter a working state, and can also control multiple voltage drop layers to enter a working mode layer by layer, and can also recover from the working mode layer by layer; and the controller can also parameterize the waiting time to facilitate the modification of the waiting time according to the different characteristics of the circuit.

[0132] In addition, in order to enter and exit the standby mode of the multi-layer stack faster and safer, the controller sets multiple shortcuts to skip unnecessary states, and automatically chooses whether to use shortcuts to accelerate according to the parameters specified when the upper layer is instantiated. For example, the controller does not care about multiple pressure drop layers entering the working mode one by one, but directly controls multiple pressure drop layers to enter the working mode at one time, thereby achieving acceleration.

[0133] An embodiment of the present application further provides a computer-readable medium storing at least one program code, which is loaded and executed by the processor to implement the control method of the power switch circuit shown in the above embodiments.

[0134] An embodiment of the present application further provides a computer program product, which stores at least one program code, and the at least one program code is loaded and executed by the processor to implement the control method of the power switch circuit shown in the above embodiments.

[0135] In some embodiments, the computer program product involved in the embodiments of the present application may be deployed and executed on one terminal, or on multiple terminals located at one location, or on multiple terminals distributed at multiple locations and interconnected by a communication network. Multiple terminals distributed at multiple locations and interconnected by a communication network may constitute a blockchain system.

[0136] Those skilled in the art should be aware that in one or more of the above examples, the functions described in the embodiments of the present application can be implemented with hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein the communication media include any media that facilitates the transmission of a computer program from one place to another. The storage medium can be any available medium that a general or special-purpose computer can access.

[0137] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A power switch circuit, characterized in that: The power switch circuit includes: a first buffer and a plurality of voltage drop layers; The plurality of voltage drop layers are sequentially connected in series, and a first voltage drop layer of the plurality of voltage drop layers is electrically connected to an output end of the first buffer and a power source respectively; The last voltage drop layer of the plurality of voltage drop layers is electrically connected to a mature design IP of a circuit module with independent functions in the controlled chip; The first buffer is used to receive a standby signal and transmit the standby signal to the plurality of voltage drop layers; The plurality of voltage drop layers are used to reduce the voltage delivered from the power supply to the IP in response to the standby signal.

2. The power switch circuit according to claim 1, characterized in that: The voltage drop layer includes a voltage drop control unit and a plurality of switch elements Power Header; The multiple Power Headers are connected in sequence, and the input end of the first Power Header among the multiple Power Headers is electrically connected to the output end of the voltage drop control unit; The input ends of the multiple Power Headers are electrically connected to the output end of the first buffer and the power supply respectively, and the output ends of the multiple Power Headers are electrically connected to the IP; The voltage drop control unit is used to control the switches of the multiple power headers; The Power Header is used to reduce the voltage delivered by the power supply to the IP when in an on state.

3. The power switch circuit according to claim 2, characterized in that: The Power Header includes a transistor and a power switch; The base of the transistor and one end of the Power Switch are electrically connected to the output end of the first buffer and the power supply respectively, the collector of the transistor and the other end of the Power Switch are electrically connected to the IP respectively, and the emitter of the transistor is electrically connected to the output end of the voltage drop control unit.

4. The power switch circuit according to claim 3, characterized in that: The pressure drop layer also includes a second buffer; The input end of the second buffer is electrically connected to the collector of the transistor and the other end of the Power Switch respectively, and the output end of the second buffer is electrically connected to the emitter of the transistor included in the next Power Header.

5. The power switch circuit according to claim 2, characterized in that: The voltage drop control unit comprises: an OR gate and an inverter; The input end of the OR gate is electrically connected to the controller, the output end of the OR gate is electrically connected to the input end of the inverter, and the output end of the inverter is electrically connected to the input end of the Power Header.

6. A chip, characterized in that: The chip comprises the power switch circuit according to any one of claims 1 to 5.

7. A terminal, characterized in that: The terminal comprises the chip according to claim 6.

8. A control method, characterized in that: The control method is applied to the power switch circuit according to any one of claims 1 to 5, and the method comprises: When it is determined that the IP is in a standby state, sending a standby signal to the first buffer so that the first buffer transmits the standby signal to the plurality of voltage drop layers; In response to the standby signal, a voltage delivered by the power supply to the IP is reduced through the plurality of voltage drop layers.

9. The method according to claim 8, characterized in that In response to the standby signal, reducing the voltage delivered by the power supply to the IP through the plurality of voltage drop layers comprises: In response to the standby signal, determining a first number of pressure drop layers currently required; determining the first number of target pressure drop layers among the plurality of pressure drop layers; The voltage delivered from the power source to the IP is reduced through the target voltage drop layer.

10. The method according to claim 9, characterized in that The voltage drop layer includes a voltage drop control unit and a plurality of switch elements Power Headers; the plurality of Power Headers are connected in sequence, and the input end of the first Power Header among the plurality of Power Headers is electrically connected to the output end of the voltage drop control unit; the input ends of the plurality of Power Headers are electrically connected to the output end of the first buffer and the power supply, respectively, and the output ends of the plurality of Power Headers are electrically connected to the IP; The step of reducing the voltage delivered from the power source to the IP through the target voltage drop layer includes: For any target voltage drop layer, outputting a high level signal to a plurality of power headers included in the target voltage drop layer through a voltage drop control unit included in the target voltage drop layer; The high level signal is used to trigger the disconnection of multiple power headers included in the target voltage drop layer, so that the multiple power headers reduce the voltage delivered by the power supply to the IP.

11. The method according to claim 9 or 10, characterized in that: The method further comprises: For other pressure drop layers among the multiple pressure drop layers except the target pressure drop layer, outputting low level signals to multiple Power Headers included in the other pressure drop layers through a pressure drop control unit included in the other pressure drop layers; The low-level signal is used to trigger the conduction of multiple Power Headers included in the other voltage drop layers, so that the multiple Power Headers are connected in series between the power supply and the IP as wires.

12. The method according to claim 10, characterized in that The voltage drop control unit includes an OR gate and an inverter; the input end of the OR gate is electrically connected to the controller, the output end of the OR gate is electrically connected to the input end of the inverter, and the output end of the inverter is electrically connected to the input end of the Power Header; The step of outputting a high level signal to a plurality of PowerHeaders included in the target voltage drop layer through the voltage drop control unit included in the target voltage drop layer comprises: A controller connected to the OR gate inputs a first control signal and a second control signal to the OR gate, wherein at least one of the first control signal and the second control signal is a low level signal; The low-level signal output by the OR gate is inverted into a high-level signal by the inverter, and the high-level signal is output to a plurality of power headers included in the target voltage drop layer.

13. The method according to claim 9, characterized in that The determining of the first number of pressure drop layers currently required comprises: Determine the minimum voltage of the IP, the minimum voltage being the minimum voltage required for the IP to maintain the data in the registers included therein; determine the voltage that needs to be reduced based on the voltage provided by the power supply and the minimum voltage; determine the first number of voltage drop layers currently required based on the voltage reduced by each voltage drop layer in the multiple voltage drop layers and the voltage that needs to be reduced; or, Determine the standby state of the IP, different standby states require different voltages so that the IP maintains the data in the registers included therein; and obtain a first layer number matching the standby state.

14. The method according to claim 8, characterized in that In response to the standby signal, reducing the voltage delivered by the power supply to the IP through the plurality of voltage drop layers comprises: In response to the standby signal, determining a voltage drop parameter, the voltage drop parameter including a start-up sequence of a plurality of voltage drop layers and a start-up time interval between two adjacent voltage drop layers; Based on the start-up sequence of the multiple pressure drop layers and the start-up time interval between two adjacent pressure drop layers, start the multiple pressure drop layers in sequence; The voltage transmitted from the power source to the IP is reduced by the plurality of voltage drop layers.

15. The method according to claim 8, characterized in that The method further comprises: When it is determined that the IP is changed from the standby state to the working state, sending a wake-up signal to the first buffer so that the first buffer transmits the wake-up signal to the multiple voltage drop layers; In response to the wake-up signal, the voltage delivered from the power supply to the IP is restored by controlling the plurality of voltage drop layers to stop working.

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