Low-power-consumption circuit of memory and implementation method of low-power-consumption circuit

Abstract

The embodiment of the invention provides a memory low power consumption circuit and an implementation method thereof, and the circuit comprises a first control logic circuit, a second control logic circuit, a third control logic circuit, a first integrated gated clock, a first register, a second register, a second integrated gated clock and a memory. And generating a sleep control signal by using the second control logic circuit, and generating a target clock signal by using the second integrated gated clock, so that the memory is recovered from a sleep state according to the sleep control signal and the target clock signal, then the clock is started, and a read-write function is executed. When the input clock of the memory is subjected to gating management, the memory is enabled to enter a sleep mode with lower power consumption during the clock closing period, and the power consumption of the memory is further reduced.

Description

Technical Field

[0001] The invention relates to the field of microcontrol technology, and specifically discloses a memory low-power consumption circuit and an implementation method thereof. Background Art

[0002] Static random access memory is widely used in chips, especially in microcontroller units. The first, second and even third level cache memory or tightly coupled memory often use static random access memory as a storage unit. In order to reduce the power consumption of static random access memory, low power consumption design is usually performed on static random access memory. However, the current low power consumption design generally only gates the input clock of static random access memory, which is insufficient to reduce the power consumption of static random access memory. It is necessary to further reduce the power consumption of static random access memory. Summary of the invention

[0003] In view of the above problems, a memory low power consumption circuit and a method for implementing a memory low power consumption circuit are proposed to overcome the above problems or at least partially solve the above problems:

[0004] A memory low power consumption circuit comprises a first control logic circuit, a second control logic circuit, a third control logic circuit, a first integrated gated clock, a first register, a second register, a second integrated gated clock and a memory, wherein the output end of the first control logic circuit is connected to the second control logic circuit, the third control logic circuit, the first register and the second register, the input end of the first integrated gated clock is connected to the third control logic circuit, the output end of the first integrated gated clock is connected to the first register, the second register and the second integrated gated clock, and the output ends of the first register, the second register, the second control logic circuit and the second integrated gated clock are connected to the memory,

[0005] When reading and writing the memory, according to different cycles of the preset system clock, the first integrated gated clock is used to recover the clocks of the first register and the second register, generate a target read and write enable signal and a target chip select signal, use the second control logic circuit to generate a sleep control signal, and use the second integrated gated clock to generate a target clock signal, so that the memory is first recovered from the sleep state according to the target read and write enable signal, the target chip select signal, the sleep control signal and the target clock signal, and then the clock is turned on to perform the read and write functions.

[0006] Optionally, the memory low power consumption circuit also includes: a first AND gate and a first OR gate, wherein the output ends of the first control logic circuit and the second register are connected to the first AND gate, the first AND gate is connected to the first OR gate, and the output end of the first OR gate is connected to the second integrated gated clock.

[0007] Optionally, the memory low power consumption circuit further includes: a second OR gate, wherein the output end of the third control logic circuit is connected to the second OR gate, and the output end of the second OR gate is connected to the first integrated gated clock.

[0008] Optionally, the first control logic circuit includes a third register, a fourth OR gate and a fourth register connected in sequence.

[0009] Optionally, the second control logic circuit includes a fifth register, a sixth register, a NOT gate and a multiplexer connected in sequence.

[0010] Optionally, the third control logic circuit includes a seventh register, an eighth register and a fifth OR gate connected in sequence.

[0011] Optionally, the first control logic circuit is used to generate a first read / write enable signal and a first clock signal according to a read / write request to the memory in a first preset clock cycle, and to generate a first chip select signal according to the first clock signal in a second preset clock cycle; the third control logic circuit is used to generate a second clock signal according to the first clock signal in a second preset clock cycle; the second control logic circuit is used to generate a sleep control signal according to the first clock signal in a third preset clock cycle; the first register is used to generate a second read / write enable signal according to the first read / write enable signal in a third preset clock cycle, and to use the second read / write enable signal as a target read / write enable signal; the second register is used to generate a second chip select signal according to the first chip select signal in a third preset clock cycle, and to use the second chip select signal as a target chip select signal; the first integrated gated clock is used to generate a third clock signal according to the second clock signal in a third preset clock cycle; the second integrated gated clock is used to generate a fourth clock signal according to the third clock signal, the first chip select signal and the second chip select signal in a fourth preset clock cycle, and to use the fourth clock signal as a target clock signal.

[0012] Optionally, the first integrated gated clock is further used to receive a system clock enable signal, and determine whether to control the third clock signal according to the system clock enable signal.

[0013] Optionally, the second control logic circuit is further configured to receive a sleep control mode selection signal, and select an output sleep control signal from the generated sleep control signal and the input sleep control signal according to the sleep control mode selection signal.

[0014] A method for implementing a memory low power consumption circuit comprises the following steps:

[0015] When reading and writing the memory, the first control logic circuit receives a read and write request for the memory as a first clock cycle, and in the first clock cycle, the first control logic circuit is used to generate a first read and write enable signal and a first clock signal according to the read and write request;

[0016] In a second clock cycle, using the first control logic circuit to generate a first chip select signal according to the first clock signal, and using the third control logic circuit to generate a second clock signal according to the first clock signal;

[0017] In a third clock cycle, using the second control logic circuit to generate a sleep control signal according to the first clock signal, using the first register to generate a second read / write enable signal according to the first read / write enable signal, and using the second read / write enable signal as a target read / write enable signal; using the second register to generate a second chip select signal according to the first chip select signal, and using the second chip select signal as a target chip select signal; using the first integrated gated clock to generate a third clock signal according to the second clock signal in a third preset clock cycle; using the memory to recover from a sleep state according to the sleep control signal, the target read / write enable signal, and the target chip select signal;

[0018] In the fourth clock cycle, the second integrated gated clock is used to generate a fourth clock signal according to the third clock signal, the first chip select signal and the second chip select signal, and the fourth clock signal is used as the target clock signal; the memory is used to start the clock according to the target clock signal, and perform read and write functions.

[0019] The embodiments of the present invention have the following advantages:

[0020] In an embodiment of the present invention, a memory low power consumption circuit includes a first control logic circuit, a second control logic circuit, a third control logic circuit, a first integrated gated clock, a first register, a second register, a second integrated gated clock and a memory, wherein an output end of the first control logic circuit is connected to the second control logic circuit, the third control logic circuit, the first register and the second register, an input end of the first integrated gated clock is connected to the third control logic circuit, an output end of the first integrated gated clock is connected to the first register, the second register and the second integrated gated clock, and output ends of the first register, the second register, the second control logic circuit and the second integrated gated clock are connected to the storage, and when reading and writing the memory, the second control logic circuit is used to generate a sleep control signal, and the second integrated gated clock is used to generate a target clock signal, so that the memory is first restored from a sleep state according to the sleep control signal and the target clock signal, and then the clock is turned on to perform a read and write function, so that while performing gating management on the input clock of the memory, the memory is also enabled to enter a sleep mode with lower power consumption during the clock shutdown period, thereby further reducing the power consumption of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solution of the present invention, the accompanying drawings required for use in the description of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0022] Figure 1 is a schematic diagram of a low-power memory circuit provided by some embodiments of the present invention;

[0023] Figure 2 is a schematic diagram of the structure of a first control logic circuit provided by some embodiments of the present invention;

[0024] Figure 3 is a timing diagram of a first control logic circuit processing a signal provided by some embodiments of the present invention;

[0025] Figure 4 is a schematic diagram of the structure of a second control logic circuit provided in some embodiments of the present invention;

[0026] Figure 5 is a timing diagram of a second control logic circuit processing a signal provided by some embodiments of the present invention;

[0027] Figure 6 is a schematic diagram of the structure of a third control logic circuit provided by some embodiments of the present invention;

[0028] Figure 7 is a timing diagram of a third control logic circuit and a first integrated gated clock processing signal provided by some embodiments of the present invention;

[0029] Figure 8 is a flow chart of a method for implementing a memory low power consumption circuit provided by some embodiments of the present invention;

[0030] Fig. 9 is a timing diagram of a memory low power consumption circuit processing signal provided by some embodiments of the present invention;

[0031] Fig.10 is another timing diagram of a memory low power consumption circuit processing signal provided by some embodiments of the present invention;

[0032] Fig.11 is another timing diagram of a memory low power circuit processing signal provided by some embodiments of the present invention,

[0033] Among them, in the accompanying drawings, 1-first control logic circuit, 2-second control logic circuit, 3-third control logic circuit, 4-first integrated gated clock, 5-first register, 6-second register, 7-second integrated gated clock, 8-memory, 9-first AND gate, 10-first OR gate, 11-second OR gate, 12-third register, 13-fourth OR gate, 14-fourth register, 15-fifth register, 16-sixth register, 17-NOT gate, 18-multiplexer, 19-seventh register, 20-eighth register, 21-fifth OR gate. DETAILED DESCRIPTION

[0034] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] Reference Figure 1, shows a memory low power consumption circuit provided by some embodiments of the present invention, the memory low power consumption circuit comprises a first control logic circuit 1, a second control logic circuit 2, a third control logic circuit 3, a first integrated gated clock 4, a first register 5, a second register 6, a second integrated gated clock 7 and a memory 8, wherein the output end of the first control logic circuit is connected to the second control logic circuit, the third control logic circuit, the first register and the second register, the input end of the first integrated gated clock is connected to the third control logic circuit, the output end of the first integrated gated clock is connected to the first register, the second register and the second integrated gated clock, and the output ends of the first register, the second register, the second control logic circuit and the second integrated gated clock are connected to the storage,

[0036] When reading and writing the memory, according to different cycles of the preset system clock, the first integrated gated clock is used to recover the clocks of the first register and the second register, generate a target read and write enable signal and a target chip select signal, use the second control logic circuit to generate a sleep control signal, and use the second integrated gated clock to generate a target clock signal, so that the memory is first recovered from the sleep state according to the target read and write enable signal, the target chip select signal, the sleep control signal and the target clock signal, and then the clock is turned on to perform the read and write functions.

[0037] In some embodiments of the present invention, the first control logic circuit is used to generate a first read / write enable signal and a first clock signal according to a read / write request to the memory in a first preset clock cycle, and to generate a first chip select signal according to the first clock signal in a second preset clock cycle; the third control logic circuit is used to generate a second clock signal according to the first clock signal in a second preset clock cycle; the second control logic circuit is used to generate a sleep control signal according to the first clock signal in a third preset clock cycle; the first register is used to generate a second read / write enable signal according to the first read / write enable signal in a third preset clock cycle, and use the second read / write enable signal as a target read / write enable signal; the second register is used to generate a second chip select signal according to the first chip select signal in a third preset clock cycle, and use the second chip select signal as a target chip select signal; the first integrated gated clock is used to generate a third clock signal according to the second clock signal in a third preset clock cycle; the second integrated gated clock is used to generate a fourth clock signal according to the third clock signal, the first chip select signal and the second chip select signal in a fourth preset clock cycle, and use the fourth clock signal as a target clock signal.

[0038] In some embodiments of the present invention, the memory may be a static random access memory.

[0039] Figure 1 The memory low-power circuit in the microcontroller system can be a part of the logic circuit related to the static random access memory in a microcontroller system, and can receive signals from other logic units or configuration registers in the microcontroller system, wherein the signal includes: an input signal wr / rd_en (read / write request) of the first control logic circuit, the read / write request can be generated from the outside of the entire microcontroller system, or an external signal input into the microcontroller system, and then a read / write request obtained after the microcontroller system internal logic processing, which is only a control signal indicating that the static random access memory needs to be read or written; the second part is a signal GLB_CLK_EN (system clock enable signal, external input, used to determine whether the clock of the static random access memory external control logic circuit needs to be controlled by the first integrated gated clock, when the system clock enable signal is set to 1, the clock of the static random access memory external control logic circuit is not controlled by the first integrated gated clock; when the system clock enable signal is set to 0, the clock of the static random access memory external control logic circuit is controlled by the first integrated gated clock. Gated clock control), DFT_CLKEN (an enable signal for testability design of static random access memory. When the signal is set to 1, the clock of the static random access memory is not controlled by the second integrated gated clock; when the signal is set to 0, the clock of the static random access memory is controlled by the second integrated gated clock), slp_user_ctrl (a user-controlled static random access memory sleep signal, which comes from the configuration register and is implemented by the user writing the register. This surface signal is only valid when the slp_mode_sel signal is 0), slp_mode_sel (a sleep control mode selection signal of the static random access memory, which comes from an external register and can be configured by the user. When the sleep control mode selection signal is set to 1, the sleep control signal SLP input to the static random access memory is automatically generated by the second control logic circuit; when the sleep control mode selection signal is set to 0, the sleep control signal SLP input to the static random access memory is equal to slp_user_ctrl), etc., as well as the microcontroller system clock input signal GLB_CLK_IN (system clock signal, external input, completely free, not controlled by the gated clock).

[0040] The input signals of the static random access memory include a target clock signal clk of the static random access memory, a sleep control signal SLP, a target chip select signal ce and a target read / write enable signal wen.

[0041] In some embodiments of the present invention, the sleep control signal SLP is a type of signal related to sleep enable on the static random access memory. Commonly used static random access memory may have other sleep or low power mode enable signals with similar functions to the sleep control signal SLP, such as DSLP (deep sleep), etc., and its control logic is similar to the control logic of SLP.

[0042] exist Figure 1 In the diagram, arrows are used to indicate the direction of the signal.

[0043] In some embodiments of the present invention, the first integrated gated clock is further used to receive a system clock enable signal, and determine whether to control the third clock signal according to the system clock enable signal.

[0044] In some embodiments of the present invention, the second control logic circuit is further configured to receive a sleep control mode selection signal, and select an output sleep control signal from the generated sleep control signal and the input sleep control signal according to the sleep control mode selection signal.

[0045] The peripheral logic circuit of the static random access memory often needs to jump before actually reading and writing the static random access memory. Therefore, if an integrated gated clock is used to control the clocks of the peripheral logic circuit and the static random access memory at the same time, the input clock of the static random access memory will flip several times, and the ultimate low-power design of the static random access memory cannot be achieved. Using the first integrated gated clock and the second integrated gated clock, two integrated gated clocks can be used to achieve independent control of the input clock of the static random access memory and the clock of the peripheral logic circuit of the static random access memory. The first integrated gated clock is used to control the clock of the peripheral logic part of the static random access memory, and the second integrated gated clock is used to control the clock of the peripheral logic part of the static random access memory. Control the input clock of the static random access memory. When initiating a read or write request, first recover the clock of the peripheral logic part to generate the chip select signal ce and the read or write enable signal wen input to the static random access memory. When all the signals required for reading and writing are recovered, the input clock clk of the static random access memory can be recovered, and clk can be accurately controlled according to the requirements of the number of read and write times. While using the gated clock to control the clock of the static random access memory, the clock of the peripheral logic circuit of the static random access memory can be gated to the extreme, reducing the power consumption of the peripheral logic circuit to the minimum; and automatically control the static random access memory to enter the longest sleep state, reducing the power consumption of the static random access memory to the minimum.

[0046] In some embodiments of the present invention, see Figure 1The memory low power consumption circuit also includes: a first AND gate 9 and a first OR gate 10, wherein the output ends of the first control logic circuit and the second register are connected to the first AND gate, the first AND gate is connected to the first OR gate, and the output end of the first OR gate is connected to the second integrated gated clock.

[0047] In some embodiments of the present invention, see Figure 1 , the memory low power consumption circuit also includes: a second OR gate 11, wherein the output end of the third control logic circuit is connected to the second OR gate, and the output end of the second OR gate is connected to the first integrated gated clock.

[0048] In some embodiments of the present invention, see Figure 2 The first control logic circuit includes a third register 12, a fourth OR gate 13 and a fourth register 14 connected in sequence.

[0049] See also Figure 1 and Figure 3 , the first control logic circuit receives a read / write request wr / rd_en generated by an external device or a system, generates a first read / write enable signal wen_i and a first clock signal clk_en according to the read / write request to the memory in a first preset clock cycle, and generates a first chip select signal ce_i according to the first clock signal in a second preset clock cycle, wherein the functional result realized by the first control logic circuit is:

[0050] In the first preset clock cycle T0-T1: receiving a read / write request wr / rd_en, and setting wr / rd_en to 1, indicating that the system needs to perform a read / write operation on the memory;

[0051] In the second preset clock cycle T0-T2: wr / rd_en is OR-operated with the original signal through the fourth OR gate after the third register to obtain the first clock signal clk_en, which lasts one clock longer than wr / rd_en;

[0052] In the third preset clock cycle T1-T3: clk_en obtains the first chip selection signal ce_i through the fourth register, so ce_i is clk_en delayed by 1 clock.

[0053] In some embodiments of the present invention, see Figure 4 The second control logic circuit includes a fifth register 15, a sixth register 16, a NOT gate 17 and a multiplexer 18 connected in sequence.

[0054] See also Figure 5, the second control logic circuit is used to generate the sleep control signal SLP of the memory. It is controlled by the sleep control mode selection signal slp_mode_sel, the user-controlled static random access memory sleep signal slp_user_ctrl and the first clock signal clk_en, wherein the function result realized by the second control logic circuit is (synchronized with the timing of the first control logic circuit):

[0055] slp_mode_sel is continuously 1; slp_user_ctrl is configured by the user and may be 0 or 1, which is invalid at this time.

[0056] In the first preset clock cycle and the second preset clock cycle T0-T2: clk en is set to 1;

[0057] In the third preset clock cycle and the fourth preset clock cycle T2-T4: the SLP signal is set to 0, and the memory wakes up from the sleep state.

[0058] The present invention uses a gated clock and related control logic circuits to control the memory input clock and automatically control external logic according to user configuration, thereby achieving clock control of the memory peripheral logic circuit and automatically controlling the memory to enter a sleep state.

[0059] In some embodiments of the present invention, see Figure 6 The third control logic circuit includes a seventh register 19, an eighth register 20 and a fifth OR gate 21 which are connected in sequence.

[0060] See also Figure 7 The third control logic circuit works together with the subsequent first integrated gated clock and the logic circuit between the two to generate the third clock signal clk_0 of the controller peripheral logic circuit. When GLB_CLK_IN is 1, the third clock signal clk_0 is not controlled.

[0061] The timing of the third control logic circuit and the subsequent first integrated gated clock together generating the third clock signal clk_0 is as follows:

[0062] In the first preset clock cycle and the second preset clock cycle T0-T2: clk_en is set to 1;

[0063] In the second preset clock cycle and the third preset clock cycle T1-T3: obtaining clk_01 after clk_en is delayed by 1 clock through the seventh register;

[0064] In the third preset clock cycle and the fourth preset clock cycle T2-T4: obtaining clk_02 after clk_en is delayed by 2 clocks through the eighth register;

[0065] In the second preset clock cycle to the fourth preset clock cycle T1-T4: clk_01 and clk_02 are processed by the fifth OR gate to obtain clk_03;

[0066] In the third preset clock cycle and the fourth preset clock cycle T2-T4: clk_0 obtained by the first integrated gated clock is clk_03 which is delayed by 1 clock.

[0067] See also Figure 8 A method for implementing a memory low power consumption circuit of the present invention comprises the following steps:

[0068] S1, when reading and writing the memory, taking the first control logic circuit receiving the read and write request for the memory as a first clock cycle, and in the first clock cycle, using the first control logic circuit to generate a first read and write enable signal and a first clock signal according to the read and write request;

[0069] S2, in a second clock cycle, using the first control logic circuit to generate a first chip select signal according to the first clock signal, and using the third control logic circuit to generate a second clock signal according to the first clock signal;

[0070] S3, in a third clock cycle, using the second control logic circuit to generate a sleep control signal according to the first clock signal, using the first register to generate a second read / write enable signal according to the first read / write enable signal, and using the second read / write enable signal as a target read / write enable signal; using the second register to generate a second chip select signal according to the first chip select signal, and using the second chip select signal as a target chip select signal; using the first integrated gated clock to generate a third clock signal according to the second clock signal in a third preset clock cycle; using the memory to recover from a sleep state according to the sleep control signal, the target read / write enable signal, and the target chip select signal;

[0071] S4, in the fourth clock cycle, use the second integrated gated clock to generate a fourth clock signal according to the third clock signal, the first chip select signal and the second chip select signal, and use the fourth clock signal as the target clock signal; use the memory to start the clock according to the target clock signal, and perform read and write functions.

[0072] A method for implementing a low-power memory circuit of the present invention performs extreme gating on the clock of the peripheral logic circuit of the controller to reduce the power consumption of the peripheral logic circuit to a minimum; and automatically controls the memory to enter a sleep state for the longest time to achieve extreme control of the power consumption of the memory and its peripheral logic circuit.

[0073] See also Fig. 9 , the system clock enable signal GLB_CLK_EN is 0, the enable signal DFT_CLKEN of the static random access memory testability design is 0, and the sleep control mode selection signal slp_mode_sel of the static random access memory is 1. The timing diagram is a read / write operation. Assuming that in the first clock cycle T0-T1, wr / rd_en is set to 1, the timing results of the timing diagram are as follows:

[0074] In the first clock cycle and the second clock cycle T0-T2: clk_en is set to 1;

[0075] In the third clock cycle and the fourth clock cycle T2-T4: SLP is pulled low, and the memory is restored from the sleep state; at the same time, clk_1 is restored;

[0076] At T3 of the fourth clock cycle: At this moment, clk_1 is restored, and T3 is used as the sampling edge to sample ce and wen (the timing of wen and ce is completely consistent, the default is 0, reading is valid when it is 0, and writing is valid when it is 1).

[0077] The third clock signal clk_0 is only valid in the three clock cycles starting from time T2, and is gated for the rest of the time, thus ensuring that the peripheral logic circuit of the memory can achieve correct functions; the fourth clock signal clk_1 is only valid at time T3, and for a read / write operation, its clock has been controlled to the extreme; the SLP signal is restored from the sleep state (set to 0) one clock before the actual reading and writing, and is set to 1 at the next clock of the reading and writing, which can ensure the normal reading and writing functions of the memory while keeping the memory in the sleep state as much as possible. The memory low-power circuit of the present invention reduces the power consumption of the memory to the maximum extent.

[0078] See also Fig.10 , the system clock enable signal GLB_CLK_EN is 0, the enable signal DFT_CLKEN of the static random access memory testability design is 0, and the sleep control mode selection signal slp_mode_sel of the static random access memory is 1. The timing diagram shows that two consecutive read / write operations are performed first, and then three consecutive read / write operations are performed after three clock cycles. Assuming that the first clock cycle T0-T1, wr / rd_en is set to 1, the timing result of the timing diagram is the same as Fig. 9 In comparison, only clk_1 is different.

[0079] See also Fig.11, the system clock enable signal GLB_CLK_EN is 0, the enable signal DFT_CLKEN of the static random access memory testability design is 1, and the sleep control mode selection signal slp_mode_sel of the static random access memory is 1. The timing diagram of the memory low power circuit, wherein the timing diagram is first two consecutive read / write operations, and then three consecutive read / write operations after three clock cycles. Assuming that the first clock cycle T0-T1, wr / rd_en is set to 1, the timing result of the timing diagram is the same as Fig.10 In comparison, the only difference is clk_0, which is no longer gated and is consistent with GLB_CLK_IN.

[0080] It should be noted that in the implementation method of a low-power memory circuit of the present invention, the memory only takes a typical static random access memory that only requires one clock to read and write as an example. In actual applications, the read and write delays of the static random access memory may vary. In this case, it can be implemented by simply modifying the first control logic circuit or the circuit structure of the memory.

[0081] As for the method embodiment, since it is basically similar to the device embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the device embodiment.

[0082] The above is a detailed introduction to a power supply monitoring device and method for a solid state hard disk. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for general technicians in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A memory low power consumption circuit, characterized in that: The device comprises a first control logic circuit, a second control logic circuit, a third control logic circuit, a first integrated gated clock, a first register, a second register, a second integrated gated clock and a memory, wherein the output end of the first control logic circuit is connected to the second control logic circuit, the third control logic circuit, the first register and the second register, the input end of the first integrated gated clock is connected to the third control logic circuit, the output end of the first integrated gated clock is connected to the first register, the second register and the second integrated gated clock, and the output ends of the first register, the second register, the second control logic circuit and the second integrated gated clock are connected to the memory, When reading and writing the memory, according to different cycles of the preset system clock, the first integrated gated clock is used to recover the clocks of the first register and the second register, generate a target read and write enable signal and a target chip select signal, use the second control logic circuit to generate a sleep control signal, and use the second integrated gated clock to generate a target clock signal, so that the memory is first recovered from the sleep state according to the target read and write enable signal, the target chip select signal, the sleep control signal and the target clock signal, and then the clock is turned on to perform the read and write functions.

2. The memory low power consumption circuit according to claim 1, characterized in that: The memory low power consumption circuit also includes: a first AND gate and a first OR gate, wherein the output ends of the first control logic circuit and the second register are connected to the first AND gate, the first AND gate is connected to the first OR gate, and the output end of the first OR gate is connected to the second integrated gated clock.

3. The memory low power consumption circuit according to claim 1, characterized in that: The memory low power consumption circuit further includes: a second OR gate, wherein the output end of the third control logic circuit is connected to the second OR gate, and the output end of the second OR gate is connected to the first integrated gated clock.

4. The memory low power consumption circuit according to claim 1, characterized in that: The first control logic circuit includes a third register, a fourth OR gate and a fourth register which are connected in sequence.

5. The memory low power consumption circuit according to claim 1, characterized in that: The second control logic circuit includes a fifth register, a sixth register, a NOT gate and a multiplexer which are connected in sequence.

6. The memory low power consumption circuit according to claim 1, characterized in that: The third control logic circuit includes a seventh register, an eighth register and a fifth OR gate which are connected in sequence.

7. The memory low power consumption circuit according to claim 1, characterized in that: The first control logic circuit is used to generate a first read / write enable signal and a first clock signal according to a read / write request to the memory in a first preset clock cycle, and to generate a first chip select signal according to the first clock signal in a second preset clock cycle; The third control logic circuit is used to generate a second clock signal according to the first clock signal in a second preset clock cycle; The second control logic circuit is used to generate a sleep control signal according to the first clock signal in a third preset clock cycle; The first register is used to generate a second read / write enable signal according to the first read / write enable signal in a third preset clock cycle, and use the second read / write enable signal as a target read / write enable signal; the second register is used to generate a second chip select signal according to the first chip select signal in a third preset clock cycle, and use the second chip select signal as a target chip select signal; The first integrated gated clock is used to generate a third clock signal according to the second clock signal in a third preset clock cycle; the second integrated gated clock is used to generate a fourth clock signal according to the third clock signal, the first chip select signal and the second chip select signal in a fourth preset clock cycle, and use the fourth clock signal as the target clock signal.

8. The memory low power consumption circuit according to claim 7, characterized in that: The first integrated gated clock is further used to receive a system clock enable signal, and determine whether to control the third clock signal according to the system clock enable signal.

9. The memory low power consumption circuit according to claim 7, characterized in that: The second control logic circuit is further configured to receive a sleep control mode selection signal, and select an output sleep control signal from the generated sleep control signal and the input sleep control signal according to the sleep control mode selection signal.

10. A method for implementing a memory low power consumption circuit, characterized in that: The following steps are involved: When reading and writing the memory, the first control logic circuit receives a read and write request for the memory as a first clock cycle, and in the first clock cycle, the first control logic circuit is used to generate a first read and write enable signal and a first clock signal according to the read and write request; In a second clock cycle, using the first control logic circuit to generate a first chip select signal according to the first clock signal, and using the third control logic circuit to generate a second clock signal according to the first clock signal; In a third clock cycle, using the second control logic circuit to generate a sleep control signal according to the first clock signal, using the first register to generate a second read / write enable signal according to the first read / write enable signal, and using the second read / write enable signal as a target read / write enable signal; using the second register to generate a second chip select signal according to the first chip select signal, and using the second chip select signal as a target chip select signal; using the first integrated gated clock to generate a third clock signal according to the second clock signal in a third preset clock cycle; using the memory to recover from a sleep state according to the sleep control signal, the target read / write enable signal, and the target chip select signal; In a fourth clock cycle, using the second integrated gated clock to generate a fourth clock signal according to the third clock signal, the first chip select signal and the second chip select signal, and using the fourth clock signal as a target clock signal; The memory is used to start the clock according to the target clock signal and perform read and write functions.

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