Register verification device and method

Abstract

The invention relates to a register verification device and method, the device comprises a mirror image register, the bit number of the mirror image register is the same as that of a target register, and the mirror image register is coupled with the target register and used for receiving a data synchronization signal sent by a target processor after receiving the data synchronization signal; carrying out reverse sequence backup on the data in the target register; wherein the data synchronization signal represents that the target processor completes updating of data in the target register; and the comparison circuit is respectively coupled with the target register and the mirror image register, and is used for carrying out alignment comparison on the data in the target register and the inverted data in the mirror image register and outputting a comparison result.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of data processing technology, and more specifically, to a register verification device and method. Background Art

[0002] The control function selection of the processor is realized through the data of the register. When the data of the register is rewritten, the corresponding function of the processor will also change. In the actual application of the processor, the data of some key registers will directly affect the correctness of the processor function, so additional processing is required for the design and monitoring of the register.

[0003] In actual operation, registers are very susceptible to external interference and illegal rewriting. Once a register is illegally rewritten, it will have a corresponding impact on the function of the processor. Therefore, how to effectively monitor whether the register data is illegally rewritten is an urgent problem to be solved. Summary of the invention

[0004] An object of an embodiment of the present disclosure is to provide a register verification device according to a first aspect of the present disclosure, comprising:

[0005] A mirror register, the number of bits of the mirror register is the same as the number of bits of the target register, the mirror register is coupled to the target register, and is used to perform a reverse backup of the data in the target register after receiving a data synchronization signal sent by the target processor; wherein the data synchronization signal indicates that the target processor has completed updating the data in the target register;

[0006] A comparison circuit is coupled to the target register and the mirror register respectively, and is used to compare the data in the target register with the reverse data in the mirror register and output a comparison result.

[0007] Optionally, the target register and the mirror register are L-bit registers, and the comparison circuit includes L parallel comparators;

[0008] The mirror register is coupled to the target register, including: a p-th storage bit in a first direction of the target register and a p-th storage bit in a second direction of the mirror register are connected via a line;

[0009] The comparison circuit is coupled to the target register and the mirror register respectively, comprising: a first input terminal of the pth comparator is connected to the pth storage bit in the first direction of the target register through a line, and a second input terminal of the pth comparator is connected to the pth storage bit in the second direction of the mirror register through a line;

[0010] Wherein, 1≤p≤L, L≥2, p and L are positive integers, and the first direction and the second direction are opposite directions.

[0011] Optionally, a clock circuit is also included;

[0012] The clock circuit is used to output a clock signal to the comparison circuit;

[0013] The comparison circuit is configured to perform a bit-by-bit comparison on the data in the target register and the inverse data in the mirror register under the triggering of the clock signal and output a comparison result.

[0014] Optionally, the clock frequency of the clock circuit is the same as the clock frequency of the system clock of the target processor, or the clock frequency of the clock circuit is 1 / S of the clock frequency of the system clock of the target processor, where S is a positive integer power of 2, and the target processor is the processor corresponding to the target register.

[0015] Optionally, it further includes a logic operation circuit; the target register includes M storage areas, each of which includes N storage bits;

[0016] The logic operation circuit is coupled to the target register, and is used to perform corresponding logic operations on the data in the N storage bits in each of the storage areas in the target register and output the operation results, wherein the logic operation corresponding to the data in the N storage bits in the m-th storage area matches the data configuration rule of the target processor for the N storage bits in the m-th storage area;

[0017] Wherein, N≥2, M≥1, 1≤m≤M, N, M and m are positive integers, and the target processor is a processor corresponding to the target register.

[0018] Optionally, the logic operation circuit includes M parallel logic operators, each of which has N input terminals;

[0019] The logic operation circuit is coupled to the target register, and includes: N input terminals of the mth logic operator and N storage bits of the mth storage area of ​​the target register are connected in a one-to-one correspondence.

[0020] Optionally, N is 2, and the logical operation is an XOR operation between N-bit data in the same storage area.

[0021] Optionally, the clock circuit is used to output a clock signal to the logic operation circuit;

[0022] The logic operation circuit is configured to perform corresponding logic operations on the N-bit data in each of the storage areas in the target register under the triggering of the clock signal and output the operation results.

[0023] Optionally, a monitoring circuit is also included;

[0024] The monitoring circuit is coupled to the comparison circuit and the logic operation circuit respectively, and is used to output a verification result for the target register according to the comparison result and the operation result.

[0025] Optionally, a channel switching circuit is also included;

[0026] The comparison circuit is coupled with the target register, including: the comparison circuit is coupled with the target register through the channel switching circuit;

[0027] The channel switching circuit is used to switch the comparison circuit to be connected to the target register or to be connected to the test signal output circuit;

[0028] The test signal output circuit is used to output first test data of all "1"s and second test data of all "0".

[0029] According to a second aspect of the present disclosure, a register verification method is provided, comprising:

[0030] After receiving a data synchronization signal sent by the target processor, backing up the data in the target register in reverse order to the mirror register, wherein the data synchronization signal indicates that the target processor has completed updating the data in the target register, and the mirror register has the same number of bits as the target register;

[0031] Performing a bitwise comparison of the data in the target register and the reverse order data of the data in the mirror register by a comparison circuit and outputting a comparison result;

[0032] A verification result for the target register is output according to the comparison result.

[0033] Optionally, the target register and the mirror register are L-bit registers, and the comparison circuit includes L parallel comparators;

[0034] The step of backing up the data in the target register to the mirror register in reverse order includes:

[0035] Reading data in the p-th storage bit in the first direction of the target register, and writing the read data into the p-th storage bit in the second direction of the mirror register;

[0036] The comparing circuit compares the data in the target register and the reverse order data in the mirror register, including:

[0037] The data in the p-th storage bit in the first direction of the target register is read through the p-th comparator as the first data, the data in the p-th storage bit in the second direction of the mirror register is read as the corresponding data of the first data, and the first data and the corresponding data of the first data are compared; wherein, 1≤p≤L, L≥2, p and L are positive integers, and the first direction and the second direction are opposite directions.

[0038] Optionally, the comparison circuit is coupled to a clock circuit, and the clock circuit is used to output a clock signal to the comparison circuit;

[0039] The comparing circuit compares the data in the target register and the reverse order data in the mirror register and outputs the comparison result, including:

[0040] Under the triggering of the clock signal, the comparison circuit compares the data in the target register and the reverse data in the mirror register bit by bit and outputs the comparison result.

[0041] Optionally, the clock frequency of the clock circuit is the same as the clock frequency of the system clock of the target processor, or the clock frequency of the clock circuit is 1 / S of the clock frequency of the system clock of the target processor, where S is a positive integer power of 2.

[0042] Optionally, the method further comprises:

[0043] Perform corresponding logic operations on the N-bit data in each of the storage areas in the target register through a logic operation circuit and output the operation result, wherein the logic operation corresponding to the N-bit data in the m-th storage area matches the data configuration rule of the target processor for the N storage bits of the m-th storage area, the target register includes M storage areas, each of the storage areas includes N storage bits, N≥2, M≥1, 1≤m≤M, and N, M and m are positive integers;

[0044] A verification result for the target register is output according to the comparison result and the operation result.

[0045] Optionally, the logic operation circuit includes M parallel logic operators, each of which has N input terminals;

[0046] Among them, the N input terminals of the mth logic operator and the N storage bits of the mth storage area of ​​the target register are connected in a one-to-one correspondence.

[0047] Optionally, performing corresponding logic operations on the N-bit data in each of the storage areas in the target register by means of a logic operation circuit and outputting the operation results includes:

[0048] A corresponding XOR operation is performed on the N-bit data in each of the storage areas in the target register through a logic operation circuit and the XOR operation result is output.

[0049] Optionally, the logic operation circuit is coupled to a clock circuit, and the clock circuit is used to output a clock signal to the logic operation circuit;

[0050] The step of performing corresponding logic operations on the N-bit data in each of the storage areas in the target register by means of a logic operation circuit and outputting the operation result comprises:

[0051] Under the triggering of the clock signal, a logic operation circuit performs corresponding logic operations on the N-bit data in each of the storage areas in the target register and outputs the operation results.

[0052] Optionally, outputting a verification result for the target register according to the comparison result and the operation result includes:

[0053] When an abnormality occurs in either the comparison result or the operation result, a verification result indicating that the target register has been illegally rewritten is output.

[0054] Optionally, a channel switching circuit is coupled between the comparison circuit and the target register;

[0055] The channel switching circuit is used to switch the comparison circuit to be connected to the target register or to be connected to the test signal output circuit;

[0056] Before performing a bitwise comparison on the data in the target register and the reverse order data of the data in the mirror register by the comparison circuit and outputting the comparison result, the method further includes:

[0057] Controlling the channel switching circuit to switch the comparison circuit to be connected to the test signal output circuit;

[0058] Control the test signal output circuit to output first test data of all "1", and compare the first test data with the inverse data of the data in the mirror register by the comparison circuit to obtain a first test result;

[0059] Control the test signal output circuit to output second test data of all "0", and compare the second test data with the inverse data of the data in the mirror register by the comparison short circuit to obtain a second test result;

[0060] When both the first test result and the second test result are normal, the channel switching circuit is controlled to switch the comparison circuit to be connected to the target register.

[0061] One beneficial effect of the disclosed embodiment is that the register verification device includes a mirror register, the number of bits of the mirror register is the same as that of the target register, the mirror register is coupled to the target register, and is used to perform reverse backup of the data in the target register; a comparison circuit, the comparison circuit is coupled to the target register and the mirror register, and is used to compare the data in the target register and the reverse data of the data in the mirror register and output the comparison result. When the target register is illegally rewritten due to external interference, the data in the target register will change accordingly, while the reverse data of the data in the mirror register that is compared with the data in the target register will remain unchanged, so different comparison results of the bit data can be obtained through the comparison circuit, and thus the comparison result can be used to determine that the target register has been interfered with and illegally rewritten. This structure can effectively monitor the illegal rewriting of the target register and ensure the normal operation of the target processor.

[0062] Other features and advantages of the embodiments of the present disclosure will become apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure.

[0064] Figure 1 A schematic diagram of the circuit structure of a register verification device provided according to an embodiment of the present disclosure;

[0065] Figure 2 A schematic diagram of the circuit structure of another embodiment of a register verification device provided according to an embodiment of the present disclosure;

[0066] Figure 3 A schematic diagram of the circuit structure of another embodiment of a register verification device provided according to an embodiment of the present disclosure;

[0067] Figure 4 A schematic diagram of the circuit structure of another embodiment of a register verification device provided according to an embodiment of the present disclosure;

[0068] Figure 5 A schematic diagram of the circuit structure of another embodiment of a register verification device provided according to an embodiment of the present disclosure;

[0069] Figure 6 A schematic diagram of the circuit structure of another embodiment of a register verification device provided according to an embodiment of the present disclosure;

[0070] Figure 7 A flowchart of a register verification method provided according to an embodiment of the present disclosure;

[0071] Figure 8 A step diagram of a register verification method provided according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0072] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless otherwise specifically stated.

[0073] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0074] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0075] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0076] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0077] <Device Example>

[0078] The present disclosure provides a register verification device, which is coupled to a target register and is used to monitor whether the target register is illegally rewritten. Figure 1 As shown, the device includes a mirror register and a comparison circuit, wherein the number of bits of the mirror register is the same as that of the target register, for example, the mirror register and the target register can be 8-bit registers. The mirror register is coupled to the target register and is used to perform a reverse backup of the data in the target register after receiving a data synchronization signal sent by the target processor.

[0079] The target processor is the processor corresponding to the target register, and the rewriting of the data in the target register by the target processor is called "legal rewriting". When the target processor legally rewrites the data in the target register, the target processor will send a data synchronization signal. When the mirror register receives the data synchronization signal, the mirror register will reversely back up the data in the target register that has been legally rewritten. In other words, the reverse data of the data in the mirror register is mirror-symmetric to the data in the target register, and the mirror register reversely backs up the data in the target register after receiving the data synchronization signal sent by the target processor. Therefore, the data synchronization signal can be used to indicate that the target processor has completed the update of the data in the target register, and at this time, the updated data needs to be reversely backed up from the target register in the mirror register.

[0080] The comparison circuit is coupled to the target register and the mirror register respectively, and the comparison circuit is used to compare the reverse data of the data in the target register and the data in the mirror register in a bitwise manner, and then output the comparison result. As described above, after the target processor legally rewrites the data in the target register, the data in the target register will be backed up in reverse order to the mirror register. Therefore, after the target processor legally rewrites the data in the target register, the reverse data of the data in the target register and the data in the mirror register should be one-to-one corresponding and the same. Therefore, after the reverse data of the data in the target register and the data in the mirror register are compared in a bitwise manner by the comparison circuit, a comparison result of the same or different bitwise data can be obtained.

[0081] Registers are susceptible to external interference during actual operation, such as radiation or electromagnetic interference, which may cause register rewriting. The rewriting of registers caused by interference is called "illegal rewriting".

[0082] Since the mirror register is backed up in reverse order according to the data synchronization signal, the mirror register will not be triggered to perform reverse backup when the target register is illegally rewritten, that is, the mirror register will not perform reverse backup of the illegally rewritten data of the target register, so that the comparison circuit can detect whether an illegal rewrite has occurred. Specifically:

[0083] If a comparison circuit is used to perform a bitwise comparison on the reverse order of the data in the target register and the data in the mirror register, and different comparison results are obtained for the bitwise data, it means that the target register or the mirror register has been illegally overwritten, and the verification device will report an error so that the target processor can rewrite the data to the target register to ensure that the data in the target register is correct.

[0084] If neither the target register nor the mirror register has been illegally rewritten, when a comparison circuit is used to perform a bitwise comparison on the reverse order of the data in the target register and the data in the mirror register, a comparison result with the same bitwise data will be obtained. The comparison result with the same bitwise data can be used to indicate that the target register has not been illegally rewritten.

[0085] In one embodiment, the comparison circuit periodically compares the data in the target register and the reverse data in the mirror register and outputs the comparison result. The time length of the cycle can be determined according to the actual working environment of the target register. For example, when the working environment of the target register is susceptible to external radiation or electromagnetic interference, the time length of the cycle can be appropriately shortened so that the comparison circuit performs the comparison at a higher frequency; conversely, when the working environment of the target register is relatively stable, the time length of the cycle can be appropriately extended so that the comparison circuit performs the comparison at a lower frequency. This can not only achieve the purpose of real-time monitoring of whether the target register is illegally rewritten, but also save energy to a certain extent.

[0086] The advantage of the above embodiment is that when the target register is interfered with by the outside world and illegally rewritten, the data in the target register will change accordingly, while the reverse data of the data in the mirror register that is compared with the data in the target register will remain unchanged, so a different comparison result can be obtained through the comparison circuit, and the comparison result can be used to determine that the target register has been interfered with and illegally rewritten. This structure can effectively monitor the illegal rewriting of the target register and ensure the normal operation of the target processor.

[0087] In one embodiment, both the target register and the mirror register are L-bit registers, and the comparison circuit includes L comparators arranged in parallel, where L is a positive integer greater than or equal to 2. The number of storage bits of the target register and the mirror register is equal, and the number of storage bits of the target register and the mirror register can be determined according to actual working needs. For example, the target register and the mirror register can be 8-bit registers or 16-bit registers.

[0088] In the case where the target register and the mirror register include L storage bits, the mirror register is coupled to the target register, further comprising: the p-th storage bit in the first direction of the target register and the p-th storage bit in the second direction of the mirror register are connected via a line, wherein 1≤p≤L, and p is a positive integer. Figure 2 As shown, the first direction can be the direction from the low bit to the high bit of the target register, or the direction from the high bit to the low bit of the target register. In contrast, the second direction is the opposite direction of the first direction.

[0089] In this embodiment, the p-th storage bit of the target register in the first direction is connected to the p-th storage bit of the mirror register in the second direction by a line. Figure 2 As shown, Figure 2 The target register and mirror register shown in are 8-bit registers, and the first direction is Figure 2 As shown in FIG. 1 , the second direction is the opposite direction to the first direction. When the p-th storage bit of the target register in the first direction is connected to the p-th storage bit of the mirror register in the second direction through a line, if P is 1, it means that the highest bit of the target register is connected to the lowest bit of the mirror register through a line; if P is 8, it means that the lowest bit of the target register is connected to the highest bit of the mirror register through a line; similarly, when P is another positive integer, the storage bits on the target register and the mirror register are also connected by lines according to the above rules, which will not be described in detail here.

[0090] In the above embodiment, the comparison circuit includes L comparators with the same number of storage bits as the target register and the mirror register, and the L comparators are arranged in parallel. In the case where the comparison circuit includes L comparators, the comparison circuit is coupled to the target register and the mirror register respectively, and further includes: the first input terminal of the pth comparator is connected to the pth storage bit in the first direction of the target register through a line, and the second input terminal of the pth comparator is connected to the pth storage bit in the second direction of the mirror register through a line. Figure 3 As shown, the p-th storage bit of the target register in the first direction is connected to the p-th storage bit of the mirror register in the second direction through a line. Therefore, the first input terminal and the second input terminal of the p-th comparator are connected to the two respectively, and the data stored in the two storage bits can be compared by the comparator to obtain a comparison result of whether they are the same, and then further determine whether the target register has been illegally rewritten based on the comparison result.

[0091] The advantage of the above embodiment is that, by means of L comparators arranged in parallel, the data in the target register and the reverse order data in the mirror register can be compared simultaneously, thereby improving the verification efficiency of the verification device on the target register.

[0092] In one embodiment, the register verification device further comprises a clock circuit. Figure 3As shown, the clock circuit can output a clock signal to the comparison circuit. The clock circuit is an oscillating circuit that can move accurately like a clock. When the clock circuit oscillates, it will generate a clock signal of a period of time. The clock signal can play the role of a timer, and the comparison circuit works step by step according to the beat under the triggering of the clock signal. In this embodiment, the comparison circuit is configured to compare the data in the target register and the reverse data of the data in the mirror register under the triggering of the clock signal, and output the comparison result to the outside. For example, after the clock signal is triggered, the comparison circuit starts to compare the data in the target register with the reverse data of the data in the mirror register, and outputs the comparison result to the outside.

[0093] Based on the above embodiment, the clock frequency of the clock circuit is the same as the clock frequency of the system clock of the target processor, or the clock frequency of the clock circuit is 1 / S of the clock frequency of the system clock of the target processor, where S is a positive integer power of 2. In actual application, the target register and the corresponding target processor may be provided with a clock circuit and a system clock circuit respectively. The relationship between the clock frequencies of the two may be the same or different.

[0094] When the clock frequencies of the two are different, the clock frequency of the system clock of the target processor can be specifically set to the positive integer power of 2 of the clock frequency of the clock circuit of the target register. Setting the clock frequency of the system clock of the target processor to the positive integer power of 2 of the clock frequency of the clock circuit of the target register can increase the detection frequency of the comparison circuit in the verification device, so as to promptly detect illegal rewriting of the target register.

[0095] In one embodiment, the register verification device further includes a logic operation circuit, the target register includes M storage areas, each storage area includes N storage bits, wherein N≥2, M≥1, 1≤m≤M, and N, M and m are positive integers. Figure 4 As shown, in this embodiment, the target register is divided into M storage areas, each storage area includes N storage bits. For example, the target register is an 8-bit register, and the target register is divided into 4 storage areas, each storage area includes 2 storage bits; the target register can also be divided into 2 storage areas, each storage area includes 4 storage bits.

[0096] In this embodiment, the logic operation circuit is coupled to the target register, and the logic operation circuit is used to perform corresponding logic operations on the data of the N storage bits in each storage area in the target register, and output the operation result to the outside. The logic operation can be used to verify whether the data in the storage bits in each storage area in the target register matches the data configuration rule of the N storage bits in the mth storage area of ​​the target processor. According to the data configuration rule of the target processor corresponding to the target register, the logic operation can be an XOR operation. In the case where the logic operation is an XOR operation, the data in the N storage bits in each storage area in the target register are XORed and the operation result is obtained, and it is checked whether the operation result matches the data configuration rule for the N storage bits in the mth storage area in the target processor. If the two match, it proves that the data in the target register is correct, that is, the target processor has not been illegally rewritten; on the contrary, if the two do not match, it proves that the data in the target register is incorrect, that is, the target processor has been illegally rewritten.

[0097] For example, the target register is an 8-bit register, and the target register is divided into 4 storage areas, each of which includes 2 storage bits. The target processor has the following data configuration rules for the 2 storage bits: when the 2 storage bits are "00" or "11", the XOR value is 0, which represents an illegal configuration; when the 2 storage bits are "01" or "10", the XOR value is 1, which represents a legal configuration. Assuming that the initial data of the target register is 01-01-01-01, a logic operation circuit is used to perform an XOR operation on the initial data on the 2 storage bits in the same storage area, and the XOR value is 1. This XOR value matches the data configuration rule in the target processor, proving that the target register is legally configured at this time and there is no illegal rewriting of the target register.

[0098] When at a certain moment, the target register is disturbed by external factors and the initial data on a certain storage bit inside it is rewritten, for example, the initial data on the first bit is rewritten from "1" to "0". At this time, the initial data of the target register is 11-01-01-01. At this time, the logic operation circuit performs an XOR operation on the data on the two storage bits in the same storage area, where the XOR operation value of the data on the two storage bits in the "11" storage area is 0. This XOR operation value does not match the data configuration rule in the target processor, which proves that the target register is illegally configured at this time, that is, the target register has been illegally rewritten.

[0099] On the basis of the above embodiment, the logic operation circuit includes M logic operators arranged in parallel, each of which has N input terminals. In the case where the logic operation circuit includes M logic operators, each of which has N input terminals, the logic operation circuit is coupled to the target register, and further includes the N input terminals of the mth logic operator being connected one-to-one with the N storage bits of the mth storage area of ​​the target register.

[0100] The advantage of the above embodiment is that, by means of M logic operators arranged in parallel, logic budgeting can be performed on the data on the storage bits in each storage area in the target register at the same time, thereby improving the verification efficiency of the verification device on the target register.

[0101] In one embodiment, the clock circuit can output a clock signal to the logic operation circuit. In this embodiment, the logic operation circuit is configured to perform corresponding logic operations on the N-bit data in each storage area in the target register under the triggering of the clock signal, and output the operation result to the outside. In other words, the logic operation circuit also works step by step according to the beat under the triggering of the clock signal. For example, after the clock signal is triggered, the logic operation circuit will start to perform corresponding logic operations on the N-bit data in each storage area in the target register, such as XOR operations, and output the operation results to the outside.

[0102] In one embodiment, the register verification device further includes a monitoring circuit, see Figure 5 As shown, the monitoring circuit is coupled with the comparison circuit and the logic operation circuit respectively, and the monitoring circuit is used to output the verification result of the target register according to the comparison result of the comparison circuit and the operation result of the logic operation circuit. When the comparison circuit has a comparison result of different bit data, it proves that the target register has been illegally rewritten; when the operation result of the logic operation circuit is that the logic operation result of any storage area is illegally configured, it can also prove that the target register has been illegally rewritten. Therefore, as long as any of the comparison result and the logic operation result is abnormal, the verification device will output the verification result that the target register has been illegally rewritten. Only when the comparison result and the operation result are normal, the verification device can output the verification result that the target register has not been illegally rewritten.

[0103] For example, the target register is an 8-bit register, the initialization data of the target register is 10-01-10-10, and the initialization data in the mirror register is 01-01-10-01. When at a certain moment, the target register is disturbed by external interference, and the data on the first and second bits are affected. The "10" on the first and second bits are rewritten to "01". At this time, the data stored in the target register is 01-01-10-10. At this time, the comparison circuit compares the "01" in the target register and the "10" in the mirror register, and obtains different comparison results for the bit data. However, at this time, since the data on the first and second bits are rewritten at the same time, that is, "10" is rewritten to "01", the XOR operation values ​​before and after the rewrite are both 1. At this time, the logical operation result shows that the configuration rule is met. However, the monitoring circuit will make a comprehensive judgment based on the comparison result and the logical operation result. Since the comparison circuit has a different comparison result for the bit data, it can be proved that the target register has been interfered with and an illegal rewrite has occurred.

[0104] In one embodiment, the register verification device further includes a channel switching circuit, which is arranged between the comparison circuit and the target register. The channel switching circuit is used to switch the comparison circuit to connect to the target register or to connect to the test signal output circuit. The function of the test signal output circuit is to verify whether the performance of the comparison circuit is normal, and to prevent the comparison circuit performance from being abnormal and affecting whether the verification register is illegally rewritten.

[0105] When the test signal output circuit is actually used, it can be used to output the first test data of all "1" and the second test data of all "0", so as to compare the data stored in the storage bit in the mirror register through the comparison circuit to achieve the purpose of verifying whether the performance of the comparison circuit is normal. For example, the mirror register is an 8-bit register, and the initialization data of the mirror register is 01-01-01-01. When the comparison circuit needs to be verified, the test signal output circuit first outputs the first test data of all "1", that is, the initialization data in the test signal circuit is 11-11-11-11, and the initialization data in the test signal circuit and the initialization data in the mirror register are compared according to the comparison logic of the comparison circuit, and the first comparison result with different bit data is output externally. Then the test signal output circuit outputs the second test data of all "0", that is, the initialization data in the test signal circuit is 00-00-00-00, and the initialization data in the test signal circuit and the initialization data in the mirror register are compared according to the comparison logic of the comparison circuit, and the second comparison result with different bit data is output externally. By combining the first comparison result and the second comparison result, it can be determined that the performance of the comparison circuit is normal.

[0106] <Method Example>

[0107] The present disclosure provides a method for verifying a register. Figure 7 As shown, the register verification method of the embodiment of the present disclosure may include the following steps S710 to S730:

[0108] S710, after receiving the data synchronization signal sent by the target processor, back up the data in the target register in reverse order to the mirror register, wherein the data synchronization signal indicates that the target processor has completed updating the data in the target register, and the mirror register has the same number of bits as the target register.

[0109] The target register is a register that needs to be verified whether an illegal rewrite occurs. In this embodiment, the target register is coupled with the mirror register, and is used to reversely back up the data in the target register to the mirror register after receiving the data synchronization signal sent by the target processor. The target processor is a processor corresponding to the target register, and the rewrite of the data in the target register by the target processor is called "legal rewrite". When the target processor legally rewrites the data in the target register, the target processor will send a data synchronization signal. When the mirror register receives the data synchronization signal, the mirror register will reversely back up the data in the target register that has been legally rewritten. In other words, the reverse data of the data in the mirror register is mirror-symmetric with the data in the target register, the mirror register has the same number of bits as the target register, and the mirror register reversely backs up the data in the target register after receiving the data synchronization signal sent by the target processor. Therefore, the data synchronization signal can be used to indicate that the target processor has completed the update of the data in the target register, and at this time, the updated data needs to be reversely backed up from the target register to the mirror register.

[0110] For example, the initialization data of the target register is 10-01-10-10. When the mirror register receives the data synchronization signal sent by the target processor, it indicates that the target processor has completed the update of the data in the target register. At this time, the mirror register will back up the updated data of the target register in reverse order. Therefore, the reverse backup data in the mirror register is 01-01-10-01.

[0111] S720, performing a bitwise comparison on the data in the target register and the reverse order data of the data in the mirror register through a comparison circuit and outputting a comparison result.

[0112] S730: Output a verification result for the target register according to the comparison result.

[0113] The comparison circuit is coupled to the target register and the mirror register respectively, and the comparison circuit is used to compare the reverse data of the data in the target register and the data in the mirror register in a bitwise manner, and then output the comparison result. As described above, after the target processor legally rewrites the data in the target register, the data in the target register will be backed up in reverse order to the mirror register. Therefore, after the target processor legally rewrites the data in the target register, the reverse data of the data in the target register and the data in the mirror register should be one-to-one corresponding and the same. Therefore, after the reverse data of the data in the target register and the data in the mirror register are compared in a bitwise manner by the comparison circuit, a comparison result of the same or different bitwise data can be obtained.

[0114] Registers are susceptible to external interference during actual operation, such as radiation or electromagnetic interference, which may cause register rewriting. The rewriting of registers caused by interference is called "illegal rewriting".

[0115] Since the mirror register is backed up in reverse order according to the data synchronization signal, the mirror register will not be triggered to perform reverse backup when the target register is illegally rewritten, that is, the mirror register will not perform reverse backup of the illegally rewritten data of the target register, so that the comparison circuit can detect whether an illegal rewrite has occurred. Specifically:

[0116] If a comparison circuit is used to perform a bitwise comparison on the reverse order of the data in the target register and the data in the mirror register, and different comparison results are obtained for the bitwise data, it means that the target register or the mirror register has been illegally overwritten, and the verification device will report an error so that the target processor can rewrite the data to the target register to ensure that the data in the target register is correct.

[0117] If neither the target register nor the mirror register has been illegally rewritten, when a comparison circuit is used to perform a bitwise comparison on the reverse order of the data in the target register and the data in the mirror register, a comparison result with the same bitwise data will be obtained. The comparison result with the same bitwise data can be used to indicate that the target register has not been illegally rewritten.

[0118] For example, the initialization data of the target register is 10-01-10-10, and the initialization data of the mirror register is 01-01-10-01. When the first bit of the target register is disturbed and rewritten, it will be rewritten from the initial "1" to "0". At this time, the data in the target register is 00-01-10-01, but the reverse data of the data in the mirror register is still "1". Therefore, when the comparison circuit is used to compare the reverse data of the data in the target register and the data in the mirror register, different comparison results for the bit data will be obtained. The different comparison results for the bit data indicate that the target register has been illegally rewritten. Therefore, it can be determined that the target register has been interfered with by external factors.

[0119] In one embodiment, the comparison circuit periodically compares the data in the target register and the reverse data in the mirror register and outputs the comparison result. The time length of the cycle can be determined according to the actual working environment of the target register. For example, when the working environment of the target register is susceptible to external radiation or electromagnetic interference, the time length of the cycle can be appropriately shortened so that the comparison circuit performs the comparison at a higher frequency; conversely, when the working environment of the target register is relatively stable, the time length of the cycle can be appropriately extended so that the comparison circuit performs the comparison at a lower frequency. This can not only achieve the purpose of real-time monitoring of whether the target register is illegally rewritten, but also save energy to a certain extent.

[0120] The advantage of the above embodiment is that when the target register is interfered with by the outside world and illegally rewritten, the data in the target register will change accordingly, while the reverse data of the data in the mirror register that is compared with the data in the target register will remain unchanged, so a different comparison result can be obtained through the comparison circuit, and the comparison result can be used to determine that the target register has been interfered with and illegally rewritten. This structure can effectively monitor the illegal rewriting of the target register and ensure the normal operation of the target processor.

[0121] In one embodiment, the target register and the mirror register are L-bit registers, and the comparison circuit includes L parallel comparators;

[0122] S710, backing up the data in the target register to the mirror register in reverse order, including:

[0123] Reading data in the p-th storage bit in the first direction of the target register, and writing the read data into the p-th storage bit in the second direction of the mirror register;

[0124] S720, performing a bitwise comparison of the data in the target register and the reverse order data of the data in the mirror register by a comparison circuit, including:

[0125] Reading data in the p-th storage bit in the first direction of the target register as first data through the P-th comparator, reading data in the p-th storage bit in the second direction of the mirror register as the matching data of the first data, and comparing the first data with the comparison data of the first data;

[0126] Wherein, 1≤p≤L, L≥2, p and L are positive integers, and the first direction and the second direction are opposite directions.

[0127] In this embodiment, both the target register and the mirror register are L-bit registers, and the comparison circuit includes L comparators arranged in parallel, where L is a positive integer greater than or equal to 2. The number of storage bits of the target register and the mirror register is equal, and the number of storage bits of the target register and the mirror register can be determined according to actual work needs. For example, the target register and the mirror register can be 8-bit registers or 16-bit registers.

[0128] In the case where the target register and the mirror register include L storage bits, the pth storage bit in the first direction of the target register and the pth storage bit in the second direction of the mirror register are connected by a line, where 1≤p≤L, and p is a positive integer. The first direction can be the direction from the low bit to the high bit of the target register, or the direction from the high bit to the low bit of the target register. In contrast, the second direction is the opposite direction of the first direction.

[0129] In this embodiment, the p-th storage bit of the target register in the first direction is connected to the p-th storage bit of the mirror register in the second direction by a line. Figure 2 As shown, Figure 2 The target register and mirror register shown in are 8-bit registers, and the first direction is Figure 2 As shown in FIG. 1 , the second direction is the opposite direction to the first direction. When the p-th storage bit of the target register in the first direction is connected to the p-th storage bit of the mirror register in the second direction through a line, if P is 1, it means that the highest bit of the target register is connected to the lowest bit of the mirror register through a line; if P is 8, it means that the lowest bit of the target register is connected to the highest bit of the mirror register through a line; similarly, when P is another positive integer, the storage bits on the target register and the mirror register are also connected by lines according to the above rules, which will not be described in detail here.

[0130] In the above embodiment, the comparison circuit includes L comparators having the same number of storage bits as the target register and the mirror register, and the L comparators are arranged in parallel. In the case where the comparison circuit includes L comparators, the first input terminal of the pth comparator is connected to the pth storage bit in the first direction of the target register through a line, and the second input terminal of the pth comparator is connected to the pth storage bit in the second direction of the mirror register through a line.

[0131] Since the p-th storage bit of the target register in the first direction is connected to the p-th storage bit of the mirror register in the second direction through a line, when the mirror register performs a reverse backup of the data in the target register, the data read in the p-th storage bit of the target register in the first direction will be written into the p-th storage bit in the second direction, thereby completing the reverse backup.

[0132] Similarly, since the first input terminal of the pth comparator is connected to the pth storage bit in the first direction of the target register through a line, and the second input terminal of the pth comparator is connected to the pth storage bit in the second direction of the mirror register through a line, the pth comparator will read the data on the pth storage bit in the first direction of the target register as the first data, and temporarily store it in the comparator. At the same time, the pth comparator will also read the data on the pth storage bit in the second direction of the mirror register as the counter-bit data of the first data, and then compare the first data with the counter-bit data.

[0133] In one embodiment, the comparison circuit is coupled to a clock circuit, and the clock circuit is used to output a clock signal to the comparison circuit;

[0134] Step S720, performing a bitwise comparison on the data in the target register and the reverse order data of the data in the mirror register by a comparison circuit and outputting a comparison result, including:

[0135] Under the triggering of the clock signal, the data in the target register and the reverse order data in the mirror register are compared bit by bit and the comparison result is output.

[0136] In this embodiment, a clock circuit is also included, and the clock circuit can output a clock signal to the comparison circuit. The clock circuit is an oscillating circuit that can move accurately like a clock. When the clock circuit oscillates, a clock signal of a period of time is generated. The clock signal can play the role of a timer, and the comparison circuit works step by step according to the beat under the triggering of the clock signal. When the clock signal is triggered, the data in the target register and the reverse data of the data in the mirror register are compared in bitwise order, and the comparison result is output externally.

[0137] In one embodiment, the clock frequency of the clock circuit is the same as the clock frequency of the system clock of the target processor, or the clock frequency of the clock circuit is 1 / S of the clock frequency of the system clock of the target processor, where S is a positive integer power of 2. In actual applications, the target register and the corresponding target processor may be provided with a clock circuit and a system clock circuit respectively. The relationship between the clock frequencies of the two may be the same or different.

[0138] When the clock frequencies of the two are different, the clock frequency of the system clock of the target processor can be specifically set to the positive integer power of 2 of the clock frequency of the clock circuit of the target register. Setting the clock frequency of the system clock of the target processor to the positive integer power of 2 of the clock frequency of the clock circuit of the target register can increase the detection frequency of the comparison circuit in the verification device, so as to promptly detect illegal rewriting of the target register.

[0139] In one embodiment, the method further includes: step S740, performing corresponding logic operations on the N-bit data in each of the storage areas in the target register through a logic operation circuit and outputting the operation result, wherein the logic operation corresponding to the N-bit data in the M-th storage area matches the data configuration rule of the target processor for the N storage bits of the m-th storage area, wherein the target register includes M storage areas, each of the storage areas includes N storage bits, N≥2, M≥1, 1≤m≤M, and N, M and m are positive integers;

[0140] S750: Output a verification result for the target register according to the comparison result and the operation result.

[0141] The register verification device also includes a logic operation circuit, and the target register includes M storage areas, each storage area includes N storage bits, wherein N≥2, M≥1, 1≤m≤M, and N, M, and m are positive integers. In this embodiment, the target register is divided into M storage areas, each storage area includes N storage bits, for example, the target register is an 8-bit register, the target register is divided into 4 storage areas, each storage area includes 2 storage bits; the target register can also be divided into 2 storage areas, each storage area includes 4 storage bits.

[0142] In this embodiment, the logic operation circuit is coupled to the target register, and the logic operation circuit is used to perform corresponding logic operations on the data of the N storage bits in each storage area in the target register, and output the operation result to the outside. The logic operation can be used to verify whether the data in the storage bits in each storage area in the target register matches the data configuration rule of the N storage bits in the mth storage area of ​​the target processor. According to the data configuration rule of the target processor corresponding to the target register, the logic operation can be an XOR operation. In the case where the logic operation is an XOR operation, the data in the N storage bits in each storage area in the target register are XORed and the operation result is obtained, and it is verified whether the operation result matches the data configuration rule for the N storage bits in the mth storage area in the target processor. If the two match, it proves that the data in the target register is correct, that is, the target processor has not been illegally rewritten; on the contrary, if the two do not match, it proves that the data in the target register is incorrect, that is, the target processor has been illegally rewritten.

[0143] For example, the target register is an 8-bit register, and the target register is divided into 4 storage areas, each of which includes 2 storage bits. The target processor has the following data configuration rules for the 2 storage bits: when the 2 storage bits are "00" or "11", the XOR value is 0, which represents an illegal configuration; when the 2 storage bits are "01" or "10", the XOR value is 1, which represents a legal configuration. Assuming that the initial data of the target register is 01-01-01-01, a logic operation circuit is used to perform an XOR operation on the initial data on the 2 storage bits in the same storage area, and the XOR value is 1. This XOR value matches the data configuration rule in the target processor, proving that the target register is legally configured at this time and there is no illegal rewriting of the target register.

[0144] When at a certain moment, the target register is disturbed by external factors and the initial data on a certain storage bit inside it is rewritten, for example, the initial data on the first bit is rewritten from "1" to "0". At this time, the initial data of the target register is 11-01-01-01. At this time, the logic operation circuit performs an XOR operation on the data on the two storage bits in the same storage area, where the XOR operation value of the data on the two storage bits in the "11" storage area is 0. This XOR operation value does not match the data configuration rule in the target processor, which proves that the target register is illegally configured at this time, that is, the target register has been illegally rewritten.

[0145] On the basis of the above embodiment, the logic operation circuit includes M logic operators arranged in parallel, and each logic operator has N input terminals. In the case where the logic operation circuit includes M logic operators, and each logic operator has N input terminals, the N input terminals of the mth logic operator are connected to the N storage bits of the mth storage area of ​​the target register in a one-to-one correspondence.

[0146] In one embodiment, step S740, performing corresponding logic operations on the N-bit data in each of the storage areas in the target register by a logic operation circuit and outputting the operation results, includes:

[0147] Under the triggering of the clock signal, a corresponding logical operation is performed on the N-bit data in each of the storage areas in the target register through a logical operation and the operation result is output.

[0148] In this embodiment, a clock circuit is also included, and the clock circuit can output a clock signal to the logic operation circuit. When the clock signal is triggered, the logic operation circuit performs corresponding logic operations on the N-bit data in each storage area in the target register, and outputs the operation results.

[0149] In one embodiment, step S740, performing corresponding logic operations on the N-bit data in each of the storage areas in the target register by a logic operation circuit and outputting the operation results, includes:

[0150] A corresponding XOR operation is performed on the N-bit data in each of the storage areas in the target register through a logic operation circuit and the XOR operation result is output.

[0151] In this embodiment, the logic operation circuit can perform corresponding XOR operations on the N-bit data in each of the storage areas in the target register and output the XOR operation result. For example, the target processor has the following data configuration rule on 2 storage bits: when the 2 storage bits are "00" or "11", the XOR operation value is 0, which represents an illegal configuration; when the 2 storage bits are "01" or "10", the XOR operation value is 1, which represents a legal configuration. A logic operation circuit is used to perform an XOR operation on the data on the 2 storage bits in the same storage area of ​​the target register, and the XOR operation value is 1, which means that the XOR operation value matches the data configuration rule in the target processor, thereby proving that the target register is legally configured and there is no illegal rewriting of the target register.

[0152] In one embodiment, S750, a verification result for the target register is output according to the comparison result and the operation result.

[0153] In this embodiment, a monitoring circuit is also included, which is coupled to the comparison circuit and the logic operation circuit respectively. The monitoring circuit is used to output the verification result of the target register according to the comparison result of the comparison circuit and the operation result of the logic operation circuit. When the comparison circuit has a comparison result of different bit data, it proves that the target register has been illegally rewritten; when the operation result of the logic operation circuit is that the logic operation result of any storage area is illegally configured, it can also prove that the target register has been illegally rewritten. Therefore, as long as any of the comparison result and the logic operation result is abnormal, the verification device will output the verification result that the target register has been illegally rewritten. Only when the comparison result and the operation result are normal, the verification device can output the verification result that the target register has not been illegally rewritten.

[0154] In one embodiment, a channel switching circuit is coupled between the comparison circuit and the target register;

[0155] The channel switching circuit is used to switch the comparison circuit to be connected to the target register or to be connected to the test signal output circuit;

[0156] Before performing a bitwise comparison on the data in the target register and the reverse order data of the data in the mirror register by the comparison circuit and outputting the comparison result, the method further includes:

[0157] Step S750, controlling the channel switching circuit to switch the comparison circuit to be connected to the test signal output circuit;

[0158] Step S760, controlling the test signal output circuit to output first test data of all "1", performing a bitwise comparison between the first test data and the inverse data of the data in the mirror register through the comparison circuit to obtain a first test result;

[0159] Step S770, controlling the test signal output circuit to output second test data of all "0s", performing a bitwise comparison between the second test data and the inverse data of the data in the mirror register through the comparison short circuit, and obtaining a second test result;

[0160] Step S780: When both the first test result and the second test result are normal, control the channel switching circuit to switch the comparison circuit to the target register connection.

[0161] The register verification device also includes a channel switching circuit, which is arranged between the comparison circuit and the target register. The channel switching circuit is used to switch the comparison circuit to connect with the target register or to connect with the test signal output circuit. The function of the test signal output circuit is to verify whether the performance of the comparison circuit is normal, and to prevent the verification device from verifying whether the register is illegally rewritten when the comparison circuit performance is abnormal.

[0162] When the test signal output circuit is actually used, it can be used to output the first test data of all "1" and the second test data of all "0", so as to compare the data stored in the storage bit in the mirror register through the comparison circuit to achieve the purpose of verifying the performance of the comparison circuit. For example, the mirror register is an 8-bit register, and the initialization data of the mirror register is 01-01-01-01. When the comparison circuit needs to be verified, the test signal output circuit first outputs the first test data of all "1", that is, the initialization data in the test signal circuit is 11-11-11-11, and the initialization data in the test signal circuit and the initialization data in the mirror register are compared according to the comparison logic of the comparison circuit, and the first comparison result with different bit data is output externally. Then the test signal output circuit outputs the second test data of all "0", that is, the initialization data in the test signal circuit is 00-00-00-00, and the initialization data in the test signal circuit and the initialization data in the mirror register are compared according to the comparison logic of the comparison circuit, and the second comparison result with different bit data is output externally. The performance of the comparison circuit can be determined to be normal by combining the first comparison result and the second comparison result.

[0163] See also Figure 8 As shown, the overall steps of the register verification method of this embodiment are:

[0164] S810, after receiving the data synchronization signal sent by the target processor, back up the data in the target register to the mirror register in reverse order;

[0165] S820, the test signal output circuit outputs first test data of all "1"s and second test data of all "0"s;

[0166] S830, performing a bitwise comparison between the test data and the reverse order data of the data in the mirror register through a comparison circuit to obtain a test result;

[0167] S840, when the test result indicates that the performance of the comparison circuit is normal, the comparison circuit performs a bitwise comparison on the data in the target register and the reverse data in the mirror register and outputs the comparison result;

[0168] S850, performing corresponding logic operations on the N-bit data in each of the storage areas in the target register through a logic operation circuit and outputting the operation result, wherein the logic operation corresponding to the N-bit data in the m-th storage area matches the data configuration rule of the target processor for the N storage bits of the m-th storage area, wherein the target register includes M storage areas, each of the storage areas includes N storage bits, N≥2, M≥1, 1≤m≤M, N, M and m are positive integers, and the target processor is the processor corresponding to the target register;

[0169] S860: Output a verification result for the target register according to the comparison result and the operation result.

[0170] It should be noted that all actions to obtain signals, information or data in this application are carried out in compliance with the relevant data protection laws and policies of the country where they are located, and with the authorization given by the corresponding device / account owner.

[0171] Each embodiment in the present disclosure is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device and equipment embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0172] The above describes specific embodiments of the present disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0173] The flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems, methods and computer program products according to multiple embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of an instruction, and a part of a module, a program segment or an instruction contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or the flowchart, and the combination of the boxes in the block diagram and / or the flowchart can be implemented by a dedicated hardware-based system that performs the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions. It is well known to those skilled in the art that it is equivalent to implement it by hardware, implement it by software, and implement it by combining software and hardware.

[0174] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A register verification device, It is characterized in that include: A mirror register, the number of bits of the mirror register is the same as the number of bits of the target register, the mirror register is coupled to the target register, and is used to perform a reverse backup of the data in the target register after receiving a data synchronization signal sent by the target processor; wherein the data synchronization signal indicates that the target processor has completed updating the data in the target register; A comparison circuit is coupled to the target register and the mirror register respectively, and is used to compare the data in the target register with the reverse data in the mirror register and output a comparison result.

2. The device according to claim 1, It is characterized in that The target register and the mirror register are L-bit registers, and the comparison circuit includes L parallel comparators; The mirror register is coupled to the target register, including: a p-th storage bit in a first direction of the target register and a p-th storage bit in a second direction of the mirror register are connected via a line; The comparison circuit is coupled to the target register and the mirror register respectively, comprising: a first input terminal of the pth comparator is connected to the pth storage bit in the first direction of the target register through a line, and a second input terminal of the pth comparator is connected to the pth storage bit in the second direction of the mirror register through a line; Wherein, 1≤p≤L, L≥2, p and L are positive integers, and the first direction and the second direction are opposite directions.

3. The device according to claim 1, It is characterized in that Also includes a clock circuit; The clock circuit is used to output a clock signal to the comparison circuit; The comparison circuit is configured to perform a bit-by-bit comparison on the data in the target register and the inverse data in the mirror register under the triggering of the clock signal and output a comparison result.

4. The device according to claim 3, It is characterized in that The clock frequency of the clock circuit is the same as the clock frequency of the system clock of the target processor, or the clock frequency of the clock circuit is 1 / S of the clock frequency of the system clock of the target processor, where S is a positive integer power of 2, and the target processor is the processor corresponding to the target register.

5. The device according to any one of claims 1 to 4, It is characterized in that Also includes a logic operation circuit; the target register includes M storage areas, each of the storage areas includes N storage bits; The logic operation circuit is coupled to the target register, and is used to perform corresponding logic operations on the data in the N storage bits in each of the storage areas in the target register and output the operation results, wherein the logic operation corresponding to the data in the N storage bits in the m-th storage area matches the data configuration rule of the target processor for the N storage bits in the m-th storage area; Wherein, N≥2, M≥1, 1≤m≤M, N, M and m are positive integers, and the target processor is a processor corresponding to the target register.

6. The device according to claim 5, It is characterized in that The logic operation circuit includes M parallel logic operators, each of which has N input terminals; The logic operation circuit is coupled to the target register, and includes: N input terminals of the mth logic operator and N storage bits of the mth storage area of ​​the target register are connected in a one-to-one correspondence.

7. The device according to claim 5, It is characterized in that The N is 2, and the logic operation is an exclusive OR operation between N-bit data in the same storage area.

8. The device according to any one of claims 5 to 7, It is characterized in that The clock circuit is used to output a clock signal to the logic operation circuit; The logic operation circuit is configured to perform corresponding logic operations on the N-bit data in each of the storage areas in the target register under the triggering of the clock signal and output the operation results.

9. The device according to any one of claims 5 to 8, It is characterized in that Also includes monitoring circuits; The monitoring circuit is coupled to the comparison circuit and the logic operation circuit respectively, and is used to output a verification result for the target register according to the comparison result and the operation result.

10. The device according to any one of claims 1 to 9, It is characterized in that Also included is a channel switching circuit; The comparison circuit is coupled with the target register, including: the comparison circuit is coupled with the target register through the channel switching circuit; The channel switching circuit is used to switch the comparison circuit to be connected to the target register or to be connected to the test signal output circuit; The test signal output circuit is used to output first test data of all "1" and second test data of all "0".

11. A register verification method, It is characterized in that include: After receiving a data synchronization signal sent by the target processor, backing up the data in the target register in reverse order to the mirror register, wherein the data synchronization signal indicates that the target processor has completed updating the data in the target register, and the mirror register has the same number of bits as the target register; Performing a bitwise comparison of the data in the target register and the reverse order data of the data in the mirror register by a comparison circuit and outputting a comparison result; A verification result for the target register is output according to the comparison result.

12. The method according to claim 11, It is characterized in that The target register and the mirror register are L-bit registers, and the comparison circuit includes L parallel comparators; The step of backing up the data in the target register to the mirror register in reverse order includes: Reading data in the p-th storage bit in the first direction of the target register, and writing the read data into the p-th storage bit in the second direction of the mirror register; The comparing circuit compares the data in the target register and the reverse order data in the mirror register, including: The data in the p-th storage bit in the first direction of the target register is read through the p-th comparator as the first data, the data in the p-th storage bit in the second direction of the mirror register is read as the corresponding data of the first data, and the first data and the corresponding data of the first data are compared; wherein, 1≤p≤L, L≥2, p and L are positive integers, and the first direction and the second direction are opposite directions.

13. The method according to claim 11, It is characterized in that The comparison circuit is coupled to a clock circuit, and the clock circuit is used to output a clock signal to the comparison circuit; The comparing circuit compares the data in the target register and the reverse order data in the mirror register and outputs the comparison result, including: Under the triggering of the clock signal, the comparison circuit compares the data in the target register and the reverse data in the mirror register bit by bit and outputs the comparison result.

14. The method according to claim 13, It is characterized in that The clock frequency of the clock circuit is the same as the clock frequency of the system clock of the target processor, or the clock frequency of the clock circuit is 1 / S of the clock frequency of the system clock of the target processor, where S is a positive integer power of 2.

15. The method according to claim 11, It is characterized in that The method further comprises: Perform corresponding logic operations on the N-bit data in each of the storage areas in the target register through a logic operation circuit and output the operation result, wherein the logic operation corresponding to the N-bit data in the m-th storage area matches the data configuration rule of the target processor for the N storage bits of the m-th storage area, the target register includes M storage areas, each of the storage areas includes N storage bits, N≥2, M≥1, 1≤m≤M, and N, M and m are positive integers; A verification result for the target register is output according to the comparison result and the operation result.

16. The method according to claim 15, It is characterized in that The logic operation circuit includes M parallel logic operators, each of which has N input terminals; Among them, the N input terminals of the mth logic operator and the N storage bits of the mth storage area of ​​the target register are connected in a one-to-one correspondence.

17. The method according to claim 15, It is characterized in that The step of performing corresponding logic operations on the N-bit data in each of the storage areas in the target register by means of a logic operation circuit and outputting the operation result comprises: A corresponding XOR operation is performed on the N-bit data in each of the storage areas in the target register through a logic operation circuit and the XOR operation result is output.

18. The method according to any one of claims 15 to 17, It is characterized in that The logic operation circuit is coupled to a clock circuit, and the clock circuit is used to output a clock signal to the logic operation circuit; The step of performing corresponding logic operations on the N-bit data in each of the storage areas in the target register by means of a logic operation circuit and outputting the operation result comprises: Under the triggering of the clock signal, a logic operation circuit performs corresponding logic operations on the N-bit data in each of the storage areas in the target register and outputs the operation results.

19. The method according to claim 15, It is characterized in that Outputting a verification result for the target register according to the comparison result and the operation result includes: When an abnormality occurs in either the comparison result or the operation result, a verification result indicating that the target register has been illegally rewritten is output.

20. The method according to claim 11, It is characterized in that A channel switching circuit is coupled between the comparison circuit and the target register; The channel switching circuit is used to switch the comparison circuit to be connected to the target register or to be connected to the test signal output circuit; Before performing a bitwise comparison on the data in the target register and the reverse order data of the data in the mirror register by the comparison circuit and outputting the comparison result, the method further includes: Controlling the channel switching circuit to switch the comparison circuit to be connected to the test signal output circuit; Control the test signal output circuit to output first test data of all "1", and compare the first test data with the inverse data of the data in the mirror register by the comparison circuit to obtain a first test result; Control the test signal output circuit to output second test data of all "0", and compare the second test data with the inverse data of the data in the mirror register by the comparison short circuit to obtain a second test result; When both the first test result and the second test result are normal, the channel switching circuit is controlled to switch the comparison circuit to be connected to the target register.

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