Method, device and medium for obtaining log-likelihood ratio information of LDPC algorithm

Abstract

The present application discloses a method, device and medium for obtaining log-likelihood ratio information of an LDPC algorithm, and relates to the field of flash memory technology. The method includes: obtaining a data sequence to be decoded and an LDPC check matrix; wherein the LDPC check matrix includes multiple candidate row check sequences; performing row check processing according to the data sequence to be decoded and the LDPC check matrix to obtain a row check result; according to the row check result, determining a target row check sequence from multiple candidate row check sequences; performing sequence superposition processing on the target row check sequence to obtain a weight sequence; performing mapping processing according to the data sequence to be decoded, the weight sequence and a preset index mapping table to obtain log-likelihood ratio information, so as to perform LDPC decoding processing for flash memory error correction according to the data sequence to be decoded and the log-likelihood ratio information. The log-likelihood ratio information of the LDPC decoding algorithm can be quickly obtained, so that the LDPC decoding algorithm takes into account both faster decoding speed and stronger decoding capability.

Description

Technical Field

[0001] The present application relates to the field of flash memory technology, and in particular to a method, device and medium for obtaining log-likelihood ratio information of an LDPC algorithm. Background Art

[0002] The LDPC (Low-Density Parity-Check) algorithm is the mainstream algorithm for flash memory data error correction. There are two types of LDPC algorithms, namely the LDPC hard decoding algorithm and the LDPC soft decoding algorithm. Among them, the LDPC hard decoding algorithm has a fast execution speed and a small delay, but the decoding ability is relatively weak; the LDPC soft decoding algorithm has a strong decoding ability, but a slow speed and a large delay. The current mainstream solution is to use the two algorithms in combination, that is, first use the LDPC hard decoding algorithm, and if the decoding fails, then use the LDPC soft decoding algorithm; such a decoding solution can ensure good decoding ability, but requires more flash memory data recovery time, which is easy to cause data recovery timeout; it is also difficult to take into account both faster decoding speed and stronger decoding ability. Therefore, how to make the LDPC decoding algorithm take into account both faster decoding speed and stronger decoding ability is an urgent problem to be solved. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a method, device and medium for obtaining log-likelihood ratio information of an LDPC algorithm, which can quickly obtain the log-likelihood ratio information of an LDPC decoding algorithm, so that the LDPC decoding algorithm can take into account both faster decoding speed and stronger decoding capability.

[0004] In a first aspect, an embodiment of the present application provides a method for obtaining log-likelihood ratio information of an LDPC algorithm, comprising:

[0005] Obtaining a data sequence to be decoded and an LDPC check matrix; wherein the LDPC check matrix includes a plurality of candidate row check sequences;

[0006] Performing row check processing according to the to-be-decoded data sequence and the LDPC check matrix to obtain a row check result;

[0007] Determining a target row check sequence from a plurality of candidate row check sequences according to the row check result;

[0008] Performing sequence superposition processing on the target row check sequence to obtain a weight sequence;

[0009] Mapping processing is performed according to the data sequence to be decoded, the weight sequence and a preset index mapping table to obtain log-likelihood ratio information, so as to perform LDPC decoding processing for flash memory error correction according to the data sequence to be decoded and the log-likelihood ratio information.

[0010] According to some embodiments of the present application, performing row check processing according to the to-be-decoded data sequence and the LDPC check matrix to obtain a row check result includes:

[0011] Acquire a plurality of the candidate row check sequences from the LDPC check matrix;

[0012] Performing dot product processing on each of the candidate row check sequences and the to-be-decoded data sequence to obtain an initial check value of each of the candidate row check sequences; performing modulo-2 operation processing on each of the initial check values ​​to obtain a row check value of each of the candidate row check sequences;

[0013] The row verification result of each of the candidate row verification sequences is determined according to the row verification value of each of the candidate row verification sequences.

[0014] According to some embodiments of the present application, determining the row verification result of each of the candidate row verification sequences according to the row verification value of each of the candidate row verification sequences includes:

[0015] When the row check value of the candidate row check sequence is not equal to zero, determining that the row check result of the candidate row check sequence is a check failure;

[0016] When the row check value of the candidate row check sequence is equal to zero, it is determined that the row check result of the candidate row check sequence is a check pass.

[0017] According to some embodiments of the present application, the row verification result includes: verification pass and verification fail; and determining a target row verification sequence from a plurality of candidate row verification sequences according to the row verification result includes:

[0018] When the row verification result is verification failure, the candidate row verification sequence for which the row verification result is verification failure is determined as the target row verification sequence.

[0019] According to some embodiments of the present application, there are at least two target row check sequences, and the plurality of target row check sequences have the same number of columns; performing sequence superposition processing on the target row check sequences to obtain a weight sequence includes:

[0020] Determining the column position and column position order of the target row check sequence;

[0021] In multiple target row check sequences, each element corresponding to the same column position is accumulated to obtain a weight value of each column position;

[0022] The weight sequence is generated according to the column position order and the weight value of each column position.

[0023] According to some embodiments of the present application, the mapping process is performed according to the to-be-decoded data sequence, the weight sequence, and a preset index mapping table to obtain log-likelihood ratio information, including:

[0024] Determine the column position and column position order of the data sequence to be decoded and the weight sequence; wherein the data sequence to be decoded and the weight sequence have the same number of columns;

[0025] At the same column position, obtaining a data value to be decoded of the data sequence to be decoded and obtaining a weight value of a weight sequence; and determining a log-likelihood ratio value corresponding to the column position in the index mapping table according to the data value to be decoded and the weight value;

[0026] After traversing all the column positions, the log-likelihood ratio value corresponding to each column position is obtained;

[0027] An LLR value sequence is generated according to the position order and the log-likelihood ratio values ​​corresponding to each of the column positions, and the LLR value sequence is determined as the log-likelihood ratio information.

[0028] According to some embodiments of the present application, the index mapping table includes: a first mapping table and a second mapping table; and determining the log-likelihood ratio value corresponding to the column position in the index mapping table according to the data value to be solved and the weight value includes:

[0029] When the value of the data to be solved is 0, determining a first mapping table;

[0030] The log-likelihood ratio value corresponding to the column position is determined from the first mapping table according to the weight value.

[0031] According to some embodiments of the present application, determining the log-likelihood ratio value corresponding to the column position in the index mapping table according to the data value to be solved and the weight value further includes:

[0032] When the value of the data to be solved is 1, determining a second mapping table;

[0033] The log-likelihood ratio value corresponding to the column position is determined from the second mapping table according to the weight value.

[0034] In a second aspect, an embodiment of the present application provides an electronic device comprising at least one processor and a memory for communicating with the at least one processor; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method for obtaining log-likelihood ratio information of the LDPC algorithm as described in any one of the embodiments of the first aspect.

[0035] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute a method for obtaining log-likelihood ratio information of an LDPC algorithm as described in any one of the embodiments of the first aspect.

[0036] The embodiment of the present application includes: in the process of performing LDPC error correction processing of flash memory, first, obtaining a data sequence to be decoded and an LDPC check matrix; wherein the LDPC check matrix includes multiple candidate row check sequences; then, performing row check processing according to the data sequence to be decoded and the LDPC check matrix to obtain a row check result; then, according to the row check result, determining a target row check sequence from multiple candidate row check sequences; then, performing sequence superposition processing on the target row check sequence to obtain a weight sequence; through the sequence superposition processing, quickly determining the weight sequence, providing a reliable reference for the subsequent determination of log-likelihood ratio information; finally, according to the data sequence to be decoded, the weight sequence and the preset The index mapping table is used for mapping processing to obtain log-likelihood ratio information, so as to perform LDPC decoding processing for flash memory error correction according to the data sequence to be decoded and the log-likelihood ratio information; by setting the index mapping table, the log-likelihood ratio information is quickly determined according to the data sequence to be decoded and the weight sequence, which is beneficial to reducing the delay of the overall LDPC decoding algorithm; in addition, the log-likelihood ratio information is applied to the LDPC hard decoding processing, which can effectively improve the decoding capability and convergence speed of the LDPC decoding algorithm; that is, the embodiment of the present application can quickly obtain the log-likelihood ratio information of the LDPC decoding algorithm, so that the LDPC decoding algorithm can take into account both faster decoding speed and stronger decoding capability.

[0037] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained through the structures particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic flow chart of the steps of a method for obtaining log-likelihood ratio information of an LDPC algorithm provided by an embodiment of the present application;

[0039] Figure 2This is a schematic diagram of a specific process of obtaining a weight sequence through row verification processing and sequence superposition processing provided by an embodiment of the present application;

[0040] Figure 3 is a schematic diagram of an index mapping table provided in an embodiment of the present application;

[0041] Figure 4 It is a comparative schematic diagram of a data sequence to be decoded, a weight sequence and an LLR sequence provided by an embodiment of the present application;

[0042] Figure 5 It is a schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0044] It should be understood that in the description of the present application, the orientation descriptions, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0045] It should be noted that although a logical order is shown in the flowchart in the description of the present application, in some cases, the steps shown or described may be performed in an order different from that in the flowchart. In the description of the present application, a number of means one or more, and a plurality of means two or more. The description of "first" and "second" is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0047] First, some terms used in this application are explained:

[0048] Flash memory error correction technology: It is a key means to improve the data reliability of storage devices, and the LDPC (Low-density Parity-check) algorithm is one of the efficient methods. The LDPC algorithm is widely used in NAND flash memory due to its excellent error correction capability.

[0049] LLR (Log-Likelihood Ratio) is a metric commonly used in signal detection and information theory to quantify the relative likelihood of the presence or absence of a signal.

[0050] The present application discloses a method for obtaining log-likelihood ratio information of an LDPC algorithm, an electronic device, and a computer-readable storage medium, and relates to the field of flash memory technology. The method includes: obtaining a data sequence to be decoded and an LDPC check matrix; wherein the LDPC check matrix includes multiple candidate row check sequences; performing row check processing according to the data sequence to be decoded and the LDPC check matrix to obtain a row check result; according to the row check result, determining a target row check sequence from multiple candidate row check sequences; performing sequence superposition processing on the target row check sequence to obtain a weight sequence; performing mapping processing according to the data sequence to be decoded, the weight sequence, and a preset index mapping table to obtain log-likelihood ratio information, so as to perform LDPC decoding processing for flash memory error correction according to the data sequence to be decoded and the log-likelihood ratio information. The log-likelihood ratio information of the LDPC decoding algorithm can be quickly obtained, so that the LDPC decoding algorithm takes into account both faster decoding speed and stronger decoding capability.

[0051] The embodiments of the present application are further described below in conjunction with the accompanying drawings.

[0052] First, as Figure 1 As shown, Figure 1 It is a flowchart of the steps of a method for obtaining log-likelihood ratio information of an LDPC algorithm provided by an embodiment of the present application; the method for obtaining log-likelihood ratio information of an LDPC algorithm may include but is not limited to steps S110 to S150.

[0053] Step S110: Obtain a data sequence to be decoded and an LDPC check matrix; wherein the LDPC check matrix includes a plurality of candidate row check sequences.

[0054] Step S120: Perform row check processing according to the data sequence to be decoded and the LDPC check matrix to obtain a row check result.

[0055] Step S130: determining a target row check sequence from a plurality of candidate row check sequences according to the row check result.

[0056] Step S140: performing sequence superposition processing on the target row check sequence to obtain a weight sequence.

[0057] Step S150: Mapping processing is performed according to the data sequence to be decoded, the weight sequence and the preset index mapping table to obtain log-likelihood ratio information, so as to perform LDPC decoding processing for flash memory error correction according to the data sequence to be decoded and the log-likelihood ratio information.

[0058] Specifically, the data sequence S to be decoded consists of binary digits 0 and 1; the data sequence S to be decoded is recorded as: .

[0059] Specifically, the LDPC check matrix H is a matrix with m rows and n columns, denoted as:

[0060] .

[0061] It should be noted that the column weight information of the LDPC check matrix H is k, and the column weight information k refers to: the number of elements "1" in each column vector in the LDPC check matrix H. The LDPC check matrix H satisfies that the number of "1" in each column vector is fixed, and there are k.

[0062] It should be emphasized that LDPC codes can be divided into regular and irregular codes according to the H matrix. In a regular LDPC code, the row weights of each row are consistent and the column weights of each column are consistent. Inconsistent row weights or column weights are called irregular LDPC codes. Regular LDPC codes are commonly used, and the processing object of this application is regular LDPC codes.

[0063] Specifically, each row vector in the LDPC check matrix H is the candidate row check sequence in step S110 of the embodiment of the present application. The candidate row check sequence is used as a row check formula to perform check processing with the data sequence S to be decoded.

[0064] Specifically, the row verification results include: verification passed and verification failed.

[0065] Specifically, in step S150, performing LDPC decoding processing for flash memory error correction according to the data sequence to be decoded and the log-likelihood ratio information includes: inputting the data sequence to be decoded and the log-likelihood ratio information into the LDPC error correction engine for decoding.

[0066] In the embodiment of the present application, through steps S110 to S150, in the process of performing LDPC error correction processing on the flash memory, first, a data sequence to be decoded and an LDPC check matrix are obtained; wherein the LDPC check matrix includes multiple candidate row check sequences; then, a row check processing is performed according to the data sequence to be decoded and the LDPC check matrix to obtain a row check result; then, according to the row check result, a target row check sequence is determined from multiple candidate row check sequences; then, a sequence superposition processing is performed on the target row check sequence to obtain a weight sequence; the weight sequence is quickly determined by the sequence superposition processing, so as to provide a reliable reference for the subsequent determination of the log-likelihood ratio information; finally, according to the data sequence to be decoded, the weight sequence is determined. The weight sequence and the preset index mapping table are mapped to obtain log-likelihood ratio information, so as to perform LDPC decoding processing for flash memory error correction according to the data sequence to be decoded and the log-likelihood ratio information; by setting the index mapping table, the log-likelihood ratio information is quickly determined according to the data sequence to be decoded and the weight sequence, which is beneficial to reducing the delay of the overall LDPC decoding algorithm; in addition, the log-likelihood ratio information is applied to the LDPC hard decoding process, which can effectively improve the decoding capability and convergence speed of the LDPC decoding algorithm; therefore, the embodiment of the present application can quickly obtain the log-likelihood ratio information of the LDPC decoding algorithm, so that the LDPC decoding algorithm can take into account both faster decoding speed and stronger decoding capability.

[0067] According to some embodiments of the present application, step S120 is further described. Step S120: performing row check processing according to the data sequence to be decoded and the LDPC check matrix to obtain a row check result, including but not limited to steps S121 to S123.

[0068] Step S121: Acquire multiple candidate row check sequences from the LDPC check matrix.

[0069] Step S122: performing dot product processing on each candidate row check sequence and the to-be-decoded data sequence to obtain an initial check value of each candidate row check sequence; performing modulo-2 operation processing on each initial check value to obtain a row check value of each candidate row check sequence.

[0070] Step S123: determining the row verification result of each candidate row verification sequence according to the row verification value of each candidate row verification sequence.

[0071] It can be understood that the LDPC check matrix H includes multiple row vectors, and multiple candidate row check sequences can be obtained from the LDPC check matrix. The candidate row check sequence of the i-th row can be expressed as:

[0072] , where i represents the row number, and the row number i is less than or equal to the number of rows m of the LDPC check matrix H.

[0073] Specifically, the candidate row check sequence of the first row obtained can be expressed as:

[0074] .

[0075] It can be understood that the candidate row check sequence is composed of binary digits 0 and 1; 1 in the candidate row check sequence (ie, the row check formula) indicates that the corresponding bit of the to-be-decoded data sequence at the corresponding position participates in the check.

[0076] Through step S121, a plurality of candidate row check sequences are obtained to lay a data foundation for performing dot product processing.

[0077] Specifically, the dot product processing in step S122 refers to: the sum of the products of the corresponding positions between the two vectors. In step S122, each candidate row check sequence is subjected to dot product processing with the data sequence to be decoded to obtain the initial check value of each candidate row check sequence, which can be performed simultaneously to improve the check efficiency, thereby facilitating improving the overall efficiency of obtaining the log-likelihood ratio information of the LDPC decoding algorithm.

[0078] For example, a dot product is performed between the candidate row check sequence of the first row and the data sequence to be decoded S to obtain the initial check value of the candidate row check sequence of the first row, and a modulo-2 operation is performed on the initial check value to obtain the row check value ; Row check value The specific calculation process is:

[0079] .

[0080] It is understandable that, because the initial check value is processed by modulo-2 operation, all row check values ​​have only two values: 0 or 1.

[0081] It can be understood that, through step S122, the row check values ​​of other candidate row check sequences can be obtained.

[0082] According to some embodiments of the present application, step S123 is further described. Step S123: based on the row check value of each candidate row check sequence, the row check result of each candidate row check sequence is determined, including but not limited to: when the row check value of the candidate row check sequence is not equal to zero, the row check result of the candidate row check sequence is determined to be a check failure; when the row check value of the candidate row check sequence is equal to zero, the row check result of the candidate row check sequence is determined to be a check pass.

[0083] Specifically, for an example, suppose the data sequence S to be decoded is: [1, 0, 1, 1, 0, 0, 1, 1, 0].

[0084] When the candidate row check sequence is h = [0, 0, 0, 0, 0, 0, 0, 1], the check value is 0 and the check passes.

[0085] When the candidate row check sequence is h = [1, 0, 0, 0, 0, 0, 0, 1], the check value is 1, which is not equal to zero, and the check fails.

[0086] Through steps S121 to S123, the row verification results of each candidate row verification sequence are determined, providing a reliable reference for the subsequent selection of a target row verification sequence.

[0087] According to some embodiments of the present application, the row verification result includes: verification passed and verification failed; further describing step S130, step S130: according to the row verification result, determining the target row verification sequence from multiple candidate row verification sequences, including: when the row verification result is verification failed, determining the candidate row verification sequence with the row verification result of verification failed as the target row verification sequence. Provide a reliable reference for the subsequent calculation of the weight sequence.

[0088] According to some embodiments of the present application, step S140 is further described, which includes but is not limited to: when there is only one target row check sequence, sequence superposition processing is performed on this target row check sequence to obtain a weight sequence, and the weight sequence is the target row check sequence itself.

[0089] According to some embodiments of the present application, there are at least two target row check sequences, and the number of columns of the multiple target row check sequences is the same; step S140 is further described. Step S140: sequence superposition processing is performed on the target row check sequence to obtain a weight sequence, including but not limited to steps S141 to S143.

[0090] Step S141: Determine the column position and column position order of the target row check sequence.

[0091] Step S142: In multiple target row check sequences, corresponding elements at the same column position are accumulated to obtain weight values ​​of each column position.

[0092] Step S143: Generate a weight sequence according to the column position order and the weight value of each column position.

[0093] It can be understood that the row check failure indicates that: there is a bit flip at the position of the to-be-decoded data sequence corresponding to bit 1 in the candidate row check sequence where the row check failed.

[0094] It can be understood that in the weight sequence obtained by superimposing the target row check sequence determined to have failed check, the weight value corresponding to each column position is less than or equal to the column weight information k of the LDPC check matrix. In the weight sequence, the larger the weight value corresponding to a column position, the greater the probability of data bit flipping at the corresponding position in the data sequence to be solved.

[0095] Through step S141 to step S143, the weight sequence can be quickly determined through sequence superposition processing, providing a reliable reference for the subsequent determination of log-likelihood ratio information.

[0096] Combination Figure 2 , an example is given to illustrate the specific process of obtaining the weight sequence through row verification processing and sequence superposition processing.

[0097] Specifically, an LDPC check matrix H with m=5 rows and n=3 columns, and a data sequence to be decoded including three data elements For example.

[0098] First, determine that the LDPC check matrix H includes: Figure 2 The five candidate row check sequences shown are: , and perform row check processing according to the data sequence to be decoded and the LDPC check matrix, and obtain the row check result as follows Figure 2 shown.

[0099] Secondly, the row verification result is used as the candidate row verification sequence for verification failure: , determined as the target row check sequence.

[0100] Then, for the three target row check sequences, the corresponding elements at the same column position are accumulated to obtain the weight values ​​of each column position as follows: Figure 2 The weight values ​​corresponding to the first column are: ; The weight values ​​corresponding to the second column are: ; The weight values ​​corresponding to the third column are: .

[0101] Finally, generate Figure 2 The weight sequence shown .

[0102] According to some embodiments of the present application, step S150 is further described. Step S150: mapping processing is performed according to the data sequence to be decoded, the weight sequence and the preset index mapping table to obtain log-likelihood ratio information, including but not limited to steps S151 to S154.

[0103] Step S151: Determine the column position and column position order of the data sequence to be decoded and the weight sequence; wherein the number of columns of the data sequence to be decoded and the weight sequence are the same.

[0104] Step S152: at the same column position, obtain the data value to be decoded of the data sequence to be decoded and the weight value of the weight sequence; and determine the log-likelihood ratio value corresponding to the column position in the index mapping table according to the data value to be decoded and the weight value.

[0105] Step S153: After traversing all column positions, the log-likelihood ratio corresponding to each column position is obtained.

[0106] Step S154: Generate an LLR value sequence according to the position order and the log-likelihood ratio values ​​corresponding to each column position, and determine the LLR value sequence as log-likelihood ratio information.

[0107] Specifically, the index mapping table includes: a first mapping table and a second mapping table.

[0108] According to some embodiments of the present application, step S152 is further described, wherein the log-likelihood ratio value corresponding to the column position is determined in the index mapping table based on the data value to be solved and the weight value, including: when the data value to be solved is 0, determining the first mapping table; and determining the log-likelihood ratio value corresponding to the column position from the first mapping table based on the weight value.

[0109] According to some embodiments of the present application, step S152 is further described, wherein the log-likelihood ratio value corresponding to the column position is determined in the index mapping table based on the data value to be solved and the weight value, and also includes: when the data value to be solved is 1, determining the second mapping table; and determining the log-likelihood ratio value corresponding to the column position from the second mapping table based on the weight value.

[0110] It should be noted that the weight value in the weight sequence is less than or equal to the column weight information k of the LDPC check matrix, so the weight value range is 0 to k. An LLR value needs to be given to all possible weight values ​​in the index mapping table. The LLR value in the index mapping table can be set according to the actual situation, and this application does not make specific restrictions on this.

[0111] Through steps S151 to S154, the embodiment of the present application can combine the preset index mapping table, according to the bit information of the corresponding positions of the data sequence to be decoded and the weight sequence, quickly determine the LLR value of the corresponding position of the data sequence to be decoded, and generate the LLR sequence according to multiple LLR values; that is, quickly generate the log-likelihood ratio information required for flash memory LDPC decoding. So that after the probability information of the data sequence to be decoded and the log-likelihood ratio information is input into the LDPC decoding unit, the error correction capability of the LDPC decoding algorithm is greatly improved.

[0112] Combination Figure 3 and Figure 4, an example is given to illustrate the specific process of determining the LLR sequence according to the to-be-decoded data sequence and the weight sequence in combination with the index mapping table. Figure 3 As shown, the index mapping table provided in the embodiment of the present application includes a first mapping table and a second mapping table.

[0113] Specifically, when the data value to be decoded in the first column of the obtained data sequence to be decoded is 1, and the weight value of the first column of the obtained weight sequence is 0, then according to the data value to be decoded 1, Figure 3 The index mapping table shown in FIG. 1 determines to select the second mapping table, and further, determines the LLR value to be -7 in the second mapping table according to the weight value 0. Then, when the data value to be decoded in the second column of the obtained data sequence to be decoded is 0 and the weight value of the second column of the obtained weight sequence is 1, the data value to be decoded is 0 from the following table: Figure 3 In the index mapping table shown in FIG. 1 , the first mapping table is determined to be selected. Further, the LLR value is determined to be 5 in the first mapping table according to the weight value 1. Similarly, the weight values ​​corresponding to the positions of each column are obtained, and finally the following is generated: Figure 4 The LLR sequence shown.

[0114] In summary, the embodiment of the present application, by quickly acquiring the probability information of the flash memory bit (i.e., the log-likelihood ratio information), performs LDPC decoding processing on the data sequence to be decoded and the log-likelihood ratio information, thereby greatly improving the error correction capability of the LDPC decoding algorithm; and while improving the decoding capability, the data recovery time is ensured to be within a certain range, reducing the probability of data recovery timeout. It can be seen that the decoding capability of the LDPC decoding algorithm based on the log-likelihood ratio information quickly acquired by the embodiment of the present application is stronger than that of the LDPC hard decoding algorithm, and the decoding speed is faster than that of the LDPC soft decoding algorithm. It takes into account both faster decoding speed and stronger decoding capability.

[0115] Second, as Figure 5 As shown, the present invention also provides an electronic device, including:

[0116] The processor 501 may be implemented by a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0117] The memory 502 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 502 can store an operating system and other application programs. When the technical solution provided in the embodiment of this specification is implemented by software or firmware, the relevant program code is stored in the memory 502, and the processor 501 calls and executes the method for obtaining the log-likelihood ratio information of the LDPC algorithm in the embodiment of the present application;

[0118] Input / output interface 503, used to implement information input and output;

[0119] Communication interface 504, used to realize communication interaction between the present apparatus and other devices, which can be realized by wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.);

[0120] A bus 505 that transmits information between various components of the device (e.g., the processor 501, the memory 502, the input / output interface 503, and the communication interface 504);

[0121] The processor 501 , the memory 502 , the input / output interface 503 and the communication interface 504 are connected to each other in communication within the device via the bus 505 .

[0122] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, which stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute a method for obtaining log-likelihood ratio information of an LDPC algorithm as described in any of the above embodiments.

[0123] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage devices. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and are implemented to be located in one place, or may also be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0124] It will be appreciated by those skilled in the art that all or some of the steps and systems in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically include computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0125] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above-mentioned implementation mode. Technical personnel familiar with the field can also make various equivalent deformations or substitutions without violating the spirit of the present application. These equivalent deformations or substitutions are all included in the scope defined by the present application.

Claims

1. A method for obtaining log-likelihood ratio information of an LDPC algorithm, characterized in that: include: Obtaining a data sequence to be decoded and an LDPC check matrix; wherein the LDPC check matrix includes a plurality of candidate row check sequences; Performing row check processing according to the to-be-decoded data sequence and the LDPC check matrix to obtain a row check result; Determining a target row check sequence from a plurality of candidate row check sequences according to the row check result; Performing sequence superposition processing on the target row check sequence to obtain a weight sequence; Mapping processing is performed according to the data sequence to be decoded, the weight sequence and a preset index mapping table to obtain log-likelihood ratio information, so as to perform LDPC decoding processing for flash memory error correction according to the data sequence to be decoded and the log-likelihood ratio information; The performing row check processing according to the to-be-decoded data sequence and the LDPC check matrix to obtain a row check result includes: Acquire a plurality of the candidate row check sequences from the LDPC check matrix; Performing dot product processing on each of the candidate row check sequences and the to-be-decoded data sequence to obtain an initial check value of each of the candidate row check sequences; performing modulo-2 operation processing on each of the initial check values ​​to obtain a row check value of each of the candidate row check sequences; Determining the row verification result of each of the candidate row verification sequences according to the row verification value of each of the candidate row verification sequences; The mapping process is performed according to the to-be-decoded data sequence, the weight sequence and a preset index mapping table to obtain log-likelihood ratio information, including: Determine the column position and column position order of the data sequence to be decoded and the weight sequence; wherein the data sequence to be decoded and the weight sequence have the same number of columns; At the same column position, obtaining a data value to be decoded of the data sequence to be decoded and obtaining a weight value of a weight sequence; and determining a log-likelihood ratio value corresponding to the column position in the index mapping table according to the data value to be decoded and the weight value; After traversing all the column positions, the log-likelihood ratio value corresponding to each column position is obtained; An LLR value sequence is generated according to the position order and the log-likelihood ratio values ​​corresponding to each of the column positions, and the LLR value sequence is determined as the log-likelihood ratio information.

2. The method for obtaining log-likelihood ratio information of the LDPC algorithm according to claim 1, characterized in that: The determining the row verification result of each of the candidate row verification sequences according to the row verification value of each of the candidate row verification sequences comprises: When the row check value of the candidate row check sequence is not equal to zero, determining that the row check result of the candidate row check sequence is a check failure; When the row check value of the candidate row check sequence is equal to zero, it is determined that the row check result of the candidate row check sequence is a check pass.

3. The method for obtaining log-likelihood ratio information of the LDPC algorithm according to claim 1 or 2, characterized in that: The row verification result includes: verification passed and verification failed; and determining a target row verification sequence from a plurality of candidate row verification sequences according to the row verification result includes: When the row verification result is verification failure, the candidate row verification sequence for which the row verification result is verification failure is determined as the target row verification sequence.

4. The method for obtaining log-likelihood ratio information of the LDPC algorithm according to claim 1, characterized in that: There are at least two target row check sequences, and the number of columns of the multiple target row check sequences is the same; The performing sequence superposition processing on the target row check sequence to obtain a weight sequence includes: Determining the column position and column position order of the target row check sequence; In multiple target row check sequences, each element corresponding to the same column position is accumulated to obtain a weight value of each column position; The weight sequence is generated according to the column position order and the weight value of each column position.

5. The method for obtaining log-likelihood ratio information of the LDPC algorithm according to claim 1, characterized in that: The index mapping table includes: a first mapping table and a second mapping table; determining the log-likelihood ratio value corresponding to the column position in the index mapping table according to the to-be-solved data value and the weight value includes: When the value of the data to be solved is 0, determining a first mapping table; The log-likelihood ratio value corresponding to the column position is determined from the first mapping table according to the weight value.

6. The method for obtaining log-likelihood ratio information of the LDPC algorithm according to claim 5, characterized in that: The step of determining the log-likelihood ratio value corresponding to the column position in the index mapping table according to the to-be-solved data value and the weight value further includes: When the value of the data to be solved is 1, determining a second mapping table; The log-likelihood ratio value corresponding to the column position is determined from the second mapping table according to the weight value.

7. An electronic device, characterized in that: It includes at least one processor and a memory for communicating with the at least one processor; the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method for obtaining log-likelihood ratio information of the LDPC algorithm as described in any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the method for obtaining log-likelihood ratio information of an LDPC algorithm as described in any one of claims 1 to 6.

Images