DMA (Direct Memory Access) system and data transfer method

Abstract

The embodiment of the invention discloses a DMA (Direct Memory Access) system and a data transfer method, which are used for improving the data transmission efficiency of the DMA system. The DMA system comprises a read instruction splitting module, a write instruction splitting module, a read instruction splitting cache module in communication connection with the read instruction splitting module and the write instruction splitting module, and arbiters in communication connection with the read instruction splitting module and the write instruction splitting module, wherein the arbiters comprise a read arbiter and a write arbiter. Through the DMA system provided by the scheme, pipeline processing can be performed on the instruction, and write instruction processing can be performed on the target data under the condition that the target data is read back, so that the write instruction execution efficiency of the target data is improved, the time period required to be consumed for reading and writing the data is shortened, and the data transmission efficiency of direct memory access is improved.

Description

Technical Field

[0001] The present application relates to the field of direct memory access and data transfer, and in particular to a DMA system and a data transfer method. Background Art

[0002] Direct memory access, also known as direct cache access (DMA), can be applied to microcontroller units (MCUs). A DMA system is a device that can be used to transfer data.

[0003] In actual applications, due to the limitations of the DMA system's own structure and bus protocols, for peripheral requests, the DMA system often needs to perform a read data operation first, and then perform a write operation based on the read data after reading the data to be transferred. In this data transfer process, the read and write operations are performed linearly, and the data transfer efficiency is low. It is necessary to wait for the feedback of the bus transmission to be valid before executing the next transmission.

[0004] How to improve the data transmission efficiency of the DMA system is a technical problem to be solved by this application. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a DMA system and a data transfer method to improve the data transmission efficiency of the DMA system.

[0006] In a first aspect, an embodiment of the present application provides a DMA system, the DMA system is communicatively connected to a bus matrix, the DMA system comprises: a read instruction splitting module, a write instruction splitting module, a read instruction splitting cache module communicatively connected to the read instruction splitting module and the write instruction splitting module, and an arbitrator communicatively connected to the read instruction splitting module and the write instruction splitting module, the arbitrator comprising a read arbitrator and a write arbitrator;

[0007] A read instruction splitting module performs read instruction splitting on the acquired peripheral request, and instructs the read arbitrator to perform read arbitration on the split read instructions. If the read arbitrator feeds back that the read arbitration is valid, the target read instruction with valid read arbitration is stored in the read instruction splitting cache module, wherein the peripheral request is used to request to read data from a first location and write it to a second location;

[0008] The read arbitrator is used to perform read arbitration and send the target read instruction valid for read arbitration to the bus matrix through the host interface to read the target data from the first position;

[0009] The write instruction splitting module, when the target data has been read, obtains the target read instruction from the read instruction splitting cache module and performs write instruction splitting, and instructs the write arbitrator to perform write arbitration on the split write instructions;

[0010] The write arbitrator is used to perform write arbitration and send the target data to the bus matrix through the host interface according to the target write instruction valid in the write arbitration, so as to write the target data to the second position.

[0011] In a second aspect, an embodiment of the present application provides a data transfer method, which is applied to a DMA system, comprising:

[0012] Obtaining a peripheral device request, wherein the peripheral device request is used to request to read data from a first location and write data to a second location;

[0013] Performing read instruction splitting on the peripheral device request by a read instruction splitting module;

[0014] Performing read arbitration on the split read instructions through a read arbitrator;

[0015] storing a target read instruction valid for read arbitration to a read instruction splitting cache module, and sending the target read instruction to a bus matrix through a host interface to read target data from the first location;

[0016] In the case where the target data has been read, performing write instruction splitting on the target read instruction in the read instruction splitting cache module through a write instruction splitting module;

[0017] Perform write arbitration on the split write instructions through a write arbitrator;

[0018] The target data is sent to the bus matrix through the host interface according to the target write instruction valid in the write arbitration, so as to write the target data to the second position.

[0019] In a third aspect, an embodiment of the present application provides an electronic device, comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of the method of the second aspect.

[0020] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the method of the second aspect are implemented.

[0021] In a fifth aspect, an embodiment of the present application provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute part or all of the steps of the method of the second aspect.

[0022] In an embodiment of the present application, a DMA system includes a read instruction splitting module, a write instruction splitting module, a read instruction splitting cache module that is communicatively connected to the read instruction splitting module and the write instruction splitting module, and an arbitrator that is communicatively connected to the read instruction splitting module and the write instruction splitting module, wherein the arbitrator includes a read arbitrator and a write arbitrator. Among them, the read instruction splitting module can be used to perform read instruction splitting on peripheral requests, and instruct the read arbitrator to perform arbitration on the split read instructions. When the read arbitration is valid, the target read instruction is stored in the read instruction splitting cache module, so that the write instruction splitting module can be informed that there is a split read instruction with valid read arbitration. Once the target data is read back through the split read instruction, the write instruction splitting module can start to execute the write instruction splitting without waiting for all data to be read back. Among them, the arbitrator includes a read arbitrator and a write arbitrator, which can support the simultaneous execution of the read arbitration function and the write arbitration function. The DMA system provided by this solution can implement pipeline processing for instructions, and can start executing write instruction processing on the target data when the target data is read back, thereby improving the efficiency of executing write instructions on the target data, shortening the time cycle required for reading and writing data, and thus improving the data transmission efficiency of direct memory access. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0024] Figure 1a It is a schematic diagram of a flow chart of a DMA system transferring data in a related technology in one embodiment of the present application;

[0025] Figure 1b This is a schematic diagram of a communication connection scenario of a DMA system in one embodiment of the present application;

[0026] Figure 1c It is one of the structural schematic diagrams of a DMA system in one embodiment of the present application;

[0027] Figure 1d This is a schematic diagram comparing the process of transferring data in a DMA system in one embodiment of the present application;

[0028] Figure 2 This is a second structural diagram of a DMA system in an embodiment of the present application;

[0029] Figure 3 This is a third structural diagram of a DMA system in an embodiment of the present application;

[0030] Figure 4 This is a fourth structural diagram of a DMA system in an embodiment of the present application;

[0031] Figure 5 This is a fifth structural diagram of a DMA system in an embodiment of the present application;

[0032] Figure 6 It is a schematic diagram of task-level splitting granularity of a DMA system in one embodiment of the present application;

[0033] Figure 7 It is a schematic diagram of a read and write instruction processing flow of a DMA system in one embodiment of the present application;

[0034] Figure 8 This is one of the flow charts of a data transfer method in an embodiment of the present application;

[0035] Fig. 9 This is the second flow chart of a data transfer method in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application. The numbering of the drawings in this application is only used to distinguish the various steps in the scheme, and is not used to limit the execution order of the various steps. The specific execution order is subject to the description in the specification.

[0037] In actual applications, the DMA system can transfer data between different peripherals and different memories, that is, read data from a certain location and write the read data to another location. In related technologies, the DMA system needs to execute a read instruction first, and then execute a write instruction after reading the data to be transferred.

[0038] See also Figure 1aIn the DMA system of the related art, the process of transferring data by the DMA system is shown. Based on the request of the peripheral device, the DMA system first performs read instruction splitting, requests arbitration for the split read instructions, and performs bus transfer on the read instructions after the arbitration is valid to read the data to be transferred. After reading back the data to be transferred, the write instruction splitting is performed, requests arbitration for the split write instructions, and performs bus transfer on the write instructions after the arbitration is valid to write the read back data.

[0039] based on Figure 1a As can be seen from the process shown, the DMA system needs to execute the read instruction first, read back the data, and then execute the splitting and writing of the write instruction. This linear sequential processing method makes the transmission efficiency of the DMA system low, and it often takes multiple cycles to achieve an effective data transmission. This processing method is limited by the architecture of the DMA system itself and it is difficult to improve efficiency.

[0040] In order to solve the problems existing in the prior art, the embodiment of the present application provides a DMA system, where DMA is an IP core (Intellectual Property Core) in a chip, such as Figure 1b As shown, the DMA system provided in the embodiment of the present application is connected to the bus matrix. Optionally, the bus matrix can be connected to the central processing unit (CPU) and multiple peripherals. The bus matrix is ​​used to realize the communication connection between the peripherals, the CPU, and the DMA, and the DMA system can realize the reading and writing of data through the bus in the bus matrix. The peripherals can specifically refer to various auxiliary devices or modules connected to the processor (CPU) in the chip.

[0041] like Figure 1c As shown, the DMA system provided by the embodiment of the present application includes: a read instruction splitting module, a write instruction splitting module, a read instruction splitting cache module communicatively connected to the read instruction splitting module and the write instruction splitting module, and an arbitrator communicatively connected to the read instruction splitting module and the write instruction splitting module, the arbitrator including a read arbitrator and a write arbitrator.

[0042] A read instruction splitting module performs read instruction splitting on the acquired peripheral request and instructs the read arbitrator to perform read arbitration on the split read instructions. If the read arbitrator feedbacks that the read arbitration is valid, the target read instruction with valid read arbitration is stored in the read instruction splitting cache module, wherein the peripheral request is used to request to read data from a first location and write it to a second location.

[0043] Among them, the peripheral request is a request initiated by the peripheral that can be used to implement data reading and writing, and the read instruction splitting module is used to perform read instruction splitting on the peripheral request. The splitting process can be performed according to preset rules and granularity. After splitting the read instruction, the read instruction splitting module requests the read arbitrator to perform read arbitration on the split read instruction. The read arbitrator can perform arbitration based on preset read arbitration and rules, such as determining whether the parameter information such as the address of the read instruction is valid, arbitrating and selecting the channel for executing the read instruction, etc.

[0044] After the read arbitrator feeds back a valid read arbitration result to the read instruction splitting module, the read arbitrator stores the valid read instructions after the read arbitration into the read instruction splitting cache module so that the write instruction splitting module can perform related operations of the write instructions on the read data.

[0045] The read arbitrator is used to perform read arbitration and send the target read instruction with read arbitration being effective to the bus matrix through the host interface to read the target data from the first position.

[0046] The first position specifically refers to the data reading position specified by the target read instruction. In practical applications, the first position may be a designated storage position of a peripheral device or memory connected to the bus matrix. In the embodiment of the present application, the target data to be transferred is obtained by reading the target data at the first position, and the target data will be temporarily stored in the cache of the DMA system, and then the target data will be called when the write instruction is subsequently executed, so that the target data is written to the second position, so as to realize the transfer of the target data at the first position to the second position.

[0047] After the read arbiter arbitrates that the read instruction is valid, the host interface executes the valid read instruction and transmits the data to the bus matrix. The read data can be stored in the data cache by the arbiter for subsequent execution of the write instruction.

[0048] The write instruction splitting module, when the target data has been read, obtains the target read instruction from the read instruction splitting cache module and performs write instruction splitting, and instructs the write arbitrator to perform write arbitration on the split write instructions.

[0049] In this solution, the write instruction splitting module can obtain the target read instruction from the read instruction splitting cache module to perform write instruction splitting when the target data has been read and the corresponding split read instruction is stored in the read instruction splitting cache module. Accordingly, instruction splitting can be performed according to preset splitting rules and granularity, and the specific splitting rules of the above read instructions and write instructions can be set according to actual needs.

[0050] After the write instruction is split, the write instruction splitting module requests the write arbitrator to perform write arbitration on the split write instruction, for example, determining whether the address and other parameter information of the write instruction are valid, arbitrating and selecting the channel for executing the write instruction, etc.

[0051] The write arbitrator is used to perform write arbitration and send the target data to the bus matrix through the host interface according to the target write instruction valid in the write arbitration, so as to write the target data to the second position.

[0052] The second position specifically refers to the data write position specified by the target write instruction. In practical applications, the second position may be a designated storage position of a peripheral device or memory connected to the bus matrix. In the embodiment of the present application, the pre-read target data is called, and the target data is written to the second position according to the target write instruction, so as to realize the transfer of the target data at the first position to the second position.

[0053] In the DMA system of this scheme, the arbitrator includes a write arbitrator and a read arbitrator, and the read arbitrator and the write arbitrator can perform arbitration in parallel to realize separate arbitration of read and write. In the case where the DMA system has multiple channels, the read arbitrator and the write arbitrator can be specifically used to select the channel with the highest priority according to the configuration of the descriptor and the fixed priority of each channel, so as to initiate a transmission. During the arbitration process, if the fixed priorities of the two channels are the same, arbitration can be performed in a polling manner. In the case of a large number of read and write instructions, the DMA system provided in the embodiment of the present application can perform read and write arbitration on the read and write instructions in parallel, and the parallel execution of the read arbitration function and the write arbitration function can significantly improve the efficiency of instruction arbitration in the DMA system.

[0054] In this solution, the data read back by the read instruction can be temporarily stored in the data cache. Any channel in the DMA system is configured with a corresponding data cache, and the data caches corresponding to different channels can be independent of each other.

[0055] In an application scenario, the data to be read back by the read instruction may be large. If a linear read-write method is used, all the data must be read back before the splitting, arbitration and transmission of the write instruction can be executed. In this solution, when the write instruction splitting module stores the target data in the data cache, it can obtain the split read instruction from the read instruction splitting cache module to continue to execute the splitting and arbitration of the write instruction, without waiting for all the data requested by the peripheral to be read back before starting to process the write instruction. Compared with the linear method of completing the data read back first and then executing the data write, the DMA system of this solution can start the splitting and arbitration of the write instruction when a part of the data is read back, and then write the part of the data that has been read back in the data cache as soon as possible. While executing the writing of the target data, the splitting, arbitration and transmission of the write instruction can also be executed synchronously, thereby improving the efficiency of the write instruction processing without affecting the data read back based on the read instruction, and writing the read back data to the required location as soon as possible, thereby shortening the overall time consumption of data reading and writing, and effectively improving the overall efficiency of data reading and writing.

[0056] See also Figure 1d , a rectangle represents a clock cycle, and the content in the rectangle represents the steps executed in this clock cycle, from left to right, representing the steps executed by DMA in sequence. The DMA system of related technology often adopts a linear processing method, first performing the splitting, arbitration and transmission of read instructions, and only after the data to be read and written is transmitted, the splitting, arbitration and transmission of write instructions can be performed. Assuming that the splitting, arbitration and transmission of instructions each consume one clock cycle, then based on the linear processing method, completing a data read and write requires the splitting, arbitration and transmission steps of the read and write instructions in sequence, which consumes 6 clock cycles.

[0057] In comparison, each module in the DMA system of this scheme can implement pipeline processing. In the process of processing read instructions, the read instruction splitting module can split the first read instruction in the first clock cycle (i.e., read instruction splitting 1), and split the second read instruction in the second clock cycle, thereby continuously performing pipeline splitting processing on multiple read instructions. Correspondingly, the read arbitrator performs arbitration on the above-mentioned first split read instruction in the second clock cycle (i.e., read request arbitration 1), and performs arbitration on the second split read instruction in the third clock cycle, thereby continuously performing arbitration on multiple split read instructions. Correspondingly, the read instruction transmission also adopts the above-mentioned pipeline processing method. Compared with the DMA system of the related art that executes read and write instructions, this scheme adopts a pipeline processing method, which can efficiently implement pipeline processing for multiple read instructions, and is more efficient than the read instruction processing of the prior art.

[0058] Correspondingly, the DMA system of this solution can also be executed in a pipeline manner when processing write instructions to improve processing efficiency. Among them, the execution condition of the write instruction splitting of this solution is that the target data has been read back and the split read instructions corresponding to the target data are stored in the above-mentioned read instruction splitting cache module. That is, when a part of the input to be written (i.e., the target data) has been read back, the writing can be started for the read back target data, so that the target data can be written to the required location as soon as possible without waiting for all the data to be read back.

[0059] The DMA system provided in the embodiment of the present application includes a read instruction splitting cache module for storing split read instructions that have passed the read arbitration, which can facilitate the write instruction splitting module to execute the write instruction processing as soon as possible when the target data is read back, so as to write the target data to the required location as soon as possible. Moreover, since the read-write instruction splitting modules are independent of each other, and the read-write arbitration modules are also independent of each other, the read instruction processing function and the write instruction processing function can be implemented in parallel. Therefore, there is no need to wait for a cycle to complete before entering the next cycle, and pipeline operation can be achieved, which effectively improves the efficiency of DMA system transmission.

[0060] In practical applications, peripheral requests may require data reading and writing between memory and memory, between peripherals and peripherals, and between peripherals and memory. The DMA system provided in the embodiment of the present application is implemented in a pipeline manner during the data reading and writing process, and read instructions and write instructions can be processed in parallel. Compared with the linear processing of read and write instructions in the related art, the DMA system in the embodiment of the present application can effectively improve the efficiency of the memory to memory mode by 20%, and can improve the efficiency of the memory to memory mode by 50% under multiple AHB bus master interfaces.

[0061] Based on the solution provided in the above embodiment, optionally, Figure 2 As shown, the DMA system further includes a bus control module and a bus selector which is communicatively connected to the arbiter and the bus control module, and the bus control module includes a plurality of host interfaces and instruction cache modules respectively corresponding to the plurality of host interfaces:

[0062] The arbitrator is used to send the target instruction with valid arbitration to the bus selector, wherein the target instruction includes the target read instruction and / or the target write instruction;

[0063] The bus selector is used to determine a target host interface for executing the target instruction from a plurality of host interfaces, and store the target instruction in an instruction cache module corresponding to the target host interface;

[0064] The bus control module is used to execute the instructions in the corresponding instruction cache module through the host interface.

[0065] After the arbitrator performs arbitration on the instruction, it sends the arbitration-valid instruction to the bus selector. The read arbitrator performs read arbitration on the read instruction, and after the arbitration is valid, the read arbitrator sends the valid read instruction to the bus selector. Correspondingly, the write arbitrator performs write arbitration on the write instruction, and after the write arbitration is valid, the write arbitrator sends the valid write instruction to the bus selector.

[0066] After receiving the arbitration-valid instruction, the bus selector can determine the host interface used to transmit the instruction according to information such as the address in the instruction, so as to send the instruction to the location pointed to by the address through the host interface.

[0067] The bus matrix can be used to achieve interconnection between multiple devices. The DMA system in this solution communicates with the bus matrix through the host interface to achieve instruction reception and transmission and data transmission. The DMA system can be configured with one or more host interfaces. When multiple host interfaces are configured, different host interfaces can be connected to different buses in the bus matrix. The above-mentioned bus selector can determine which host interface to transmit the arbitration valid instruction to based on information such as the address of the instruction.

[0068] The bus control module includes one or more host interfaces, and any host interface is correspondingly configured with an instruction cache module, which is used to store the instructions to be sent by the corresponding host interface. After the bus selector sends the arbitration valid instruction to a host interface of the bus control module, if the host interface is in an idle state, the received instruction can be converted to match the bus protocol, and then the converted instruction can be sent to the bus. If the host interface is busy when receiving the instruction, for example, it is processing other instructions, then the instruction can be stored in the instruction cache of the host interface first. If there are many instructions to be processed, they can be arranged in sequence in the instruction cache of the host interface so that the host interface can execute and process multiple instructions in the instruction cache in sequence.

[0069] The bus control module can be used to perform bus conversion on the instruction according to the bus protocol, that is, if the instruction needs to be sent to the AHB bus, the instruction is converted to match the AHB bus protocol and then sent through the host interface. In practical applications, it can also be converted to AXI or other types of buses.

[0070] Through the solution provided by the embodiment of the present application, the arbitrator transmits the arbitration-valid instruction to the bus control module through the bus selector, without waiting for the instruction execution to be completed, and the arbitrator can continue to perform arbitration, effectively improving the arbitration efficiency. In the case where the bus control module includes multiple host interfaces, any host interface is configured with a corresponding instruction cache module. After the bus selector determines the host interface for executing the instruction, the instruction can be sent to the instruction cache of the host interface for storage, so that the host interface can process the instructions in the corresponding instruction cache module in an orderly manner. This solution can efficiently implement instruction caching, and the instructions to be transmitted are stored through the instruction cache module corresponding to the host interface, so as to avoid the instruction transmission efficiency affecting the arbitration efficiency of the arbitrator, thereby improving the overall transmission efficiency of the instruction.

[0071] Based on the solution provided in the above embodiment, optionally, Figure 3 As shown, the DMA system further includes a data control module which is communicatively connected to the read instruction splitting module, the write instruction splitting module and the arbitrator;

[0072] The read arbitrator is further used to store the target data read from the first position into the data control module;

[0073] The write instruction splitting module is specifically used to obtain the target read instruction from the read instruction splitting cache module and perform write instruction splitting when the target data exists in the data control module, and instruct the write arbitrator to perform write arbitration on the split write instructions.

[0074] In the embodiment of the present application, the data control module is connected to the read instruction splitting module, the write instruction splitting module and the arbitrator respectively. Among them, the read instruction splitting module sends the split read instruction to the read arbitrator to request read arbitration. After the read arbitration is valid and the target data is read back through the read instruction, the arbitrator stores the read back target data in the data control module. The target data stored in the data control module can be called by the write instruction splitting module and sent to the bus through the arbitrator to write the target data to the desired location.

[0075] Based on the solution provided in the above embodiment, optionally, Figure 4 As shown, the data control module includes a data type conversion submodule and a data cache submodule;

[0076] The data cache submodule is used to store the target data;

[0077] The data bit width conversion submodule is used to convert the bit width of the target data into the bus matrix bit width.

[0078] In this embodiment, the data control module includes a data cache submodule and a data type conversion submodule. The data cache submodule is used to store the target data read back based on the read instruction so as to provide the target data when executing data write. The data type conversion submodule can be used to convert the bit width of the target data, for example, Figure 4 Two data type conversion submodules are shown, namely, a data narrow to wide module and a data wide to narrow module. The data type conversion submodule can perform data type conversion according to the difference between the actual bit width of the target data and the bit width of the bus matrix, so as to ensure that the bit width of the target data of the output value bus meets the matrix bit width rule.

[0079] Based on the solution provided by the above embodiment, the data cache submodule includes a first-in first-out storage module;

[0080] Among them, the read instruction splitting module is also used to identify whether the storage space of the first-in first-out storage module meets the preset data reading conditions before executing the read instruction splitting on the obtained peripheral request, and execute the read instruction splitting on the obtained peripheral request if it meets the conditions.

[0081] In an embodiment of the present application, the data cache submodule in the above-mentioned data control module is specifically a first-in-first-out storage module, which can also be called a FIFO (First Input First Output) memory, which can perform first-in-first-out ordered processing on ordered incoming data.

[0082] Among them, before executing the read instruction splitting module, it first judges the available storage space of the first-in first-out storage module, and starts to split the read instruction when it determines that there is space in the FIFO memory to accommodate the read-back target data, so as to avoid the problem of insufficient space to store the read-back target data.

[0083] For example, the preset data reading condition may specifically refer to that the available storage space in the FIFO memory is greater than or equal to the preset capacity value. Alternatively, the capacity value required to be occupied by the target data to be read back is first determined based on the read instruction, and the preset data reading condition may specifically refer to that the available storage space in the FIFO memory is greater than or equal to the capacity value required to be occupied by the above target data.

[0084] Based on the solution provided in the above embodiment, optionally, Figure 5 As shown, the DMA system includes multiple DMA channels, and the DMA system also includes:

[0085] The request control module receives a peripheral request initiated by a peripheral, determines a target DMA channel for processing the peripheral request based on a mapping relationship, and instructs the target DMA channel to process the peripheral request.

[0086] In an embodiment of the present application, the request control module can be connected to the read instruction splitting module. The request control module is used to receive a peripheral request initiated by a peripheral, and determine a DMA channel for processing the peripheral request according to a mapping relationship. Among them, the DMA system often has multiple channels, and the mapping relationship between the DMA channel and the peripheral request can be limited by pre-configuration. Based on the mapping relationship, the request control module can select a target DMA channel for processing the peripheral request from multiple DMA channels. Then, the DMA performs subsequent processing on the peripheral request through the target DMA channel.

[0087] In addition, after receiving the peripheral request, the request control module can also be used to determine the enabling state of the control DMA system to ensure that the DMA system is in a state capable of processing the peripheral request.

[0088] Through the solution provided in the embodiment of the present application, the request control module can ensure that the peripheral request is processed through the matching DMA channel, and can also control the enable status of the DMA system, effectively improving the processing effectiveness of the DMA system for peripheral requests.

[0089] Based on the solution provided in the above embodiment, optionally, the read arbitrator is specifically used for:

[0090] Determine a first channel for executing the target read instruction based on a preset read arbitration rule;

[0091] Sending the target read instruction with read arbitration enabled to the bus matrix through the first channel through the host interface to read target data from the first location;

[0092] The target data is stored in a data buffer corresponding to the first channel.

[0093] When the DMA system includes multiple channels, the request control module determines which DMA channel performs split processing on the peripheral request according to the mapping relationship. In this solution, the read arbiter is also used to determine which DMA channel to perform the read back of the target data, thereby improving the effectiveness of executing the read instruction.

[0094] Based on the solution provided in the above embodiment, optionally, the write instruction splitting module is specifically used to:

[0095] When the read instruction splitting cache module is in a non-empty state and the amount of data stored in the data cache corresponding to the first channel meets a preset data writing condition, obtaining the target read instruction from the read instruction splitting cache module and performing write instruction splitting;

[0096] The write arbitrator is instructed to perform write arbitration on the split write instructions.

[0097] In an embodiment of the present application, the write instruction splitting module determines whether to start executing the write instruction splitting according to the storage state of the read instruction splitting cache module and the amount of data in the data cache. Among them, if the read instruction splitting cache module is in a non-empty state, it indicates that there is a post-split read instruction with valid read arbitration. The data cache corresponding to the first channel can specifically be a data cache submodule corresponding to the first channel in the data control module. If the amount of data stored in the data cache meets the preset data writing condition, it indicates that data for supporting the execution of write instructions has been stored in the data cache. In this case, the write instruction splitting module can determine that there are post-split read instructions that have been executed, and there is data that can be written, so that the write instruction splitting can be started. Specifically, the post-split read instruction is obtained from the above-mentioned read instruction splitting cache module to perform subsequent write instruction splitting processing.

[0098] Through the solution provided in the embodiment of the present application, write instruction splitting can determine whether to start executing write instruction splitting from the two aspects of reading instructions and reading back data, effectively improving the effectiveness of subsequent write instruction execution of read back data.

[0099] Based on the solution provided by the above embodiment, optionally, the write arbitrator is further used to send information for executing the target write instruction to the bus control module through the bus selector;

[0100] Among them, the bus control module is specifically used to read the data to be written from the data cache corresponding to the first channel according to the information of the target write instruction, and convert the data to be written according to the bus protocol and send it to the bus matrix through the host interface to write the data to be written to the second position, wherein the data to be written includes at least part of the target data.

[0101] In this step, the write arbiter is used to send information for executing the target write instruction to the bus selector, and the information is used to implement the target write instruction, which may include parameter information such as address. The information is sent to the bus control module through the bus selector, and the bus control module converts the write data according to the bus protocol and sends it to the bus matrix to execute the write instruction, thereby writing the target data to the desired second location.

[0102] Based on the solution provided in the above embodiment, optionally, the read instruction splitting module is specifically used to perform read instruction splitting according to a first preset task granularity, and the write instruction splitting module is specifically used to perform write instruction splitting according to a second preset task granularity.

[0103] In the embodiment of the present application, the splitting granularity can be set according to actual needs, and the first preset task granularity and the second preset task granularity can be the same or different, that is, the granularity of the read instruction splitting and the write instruction splitting can be the same or different. Figure 6 As shown, the splitting can be performed using Single or Burst granularity to split the instructions into granularities suitable for execution processing.

[0104] In actual applications, the task-level splitting rules can be set flexibly. Taking the AHB bus as an example, it can be set to split according to the bus Burst. The specific splitting granularity of the Burst can be flexibly set according to actual needs, such as splitting according to the number of transactions. Alternatively, it can be set to split according to the bus Single, that is, splitting according to the number of transactions.

[0105] The task-level splitting can flexibly set the amount of data executed in one clock cycle to achieve single-cycle transfer volume control. After the splitting is completed, the AHB bus Bus transfer and AHB bus Single transfer can be executed according to the split granularity. For example, if split according to Burst, a group of data transfers can be executed in one clock cycle, and this group of data can contain multiple consecutive instructions. If split according to Single, a single instruction transfer can be executed in one clock cycle.

[0106] Below, as Figure 7 As shown, this scheme is described in detail with an example.

[0107] The read instruction flow is as follows (such as Figure 7 Left side):

[0108] Step 1: Through the peripheral request module, the peripheral request is selected to the corresponding DMA channel. Specifically, a channel for executing instruction splitting can be selected from multiple DMA channels according to a preset mapping relationship.

[0109] Step 2: Wait for the peripheral request to be valid. Specifically, the DMA system can check its own enable status to determine that it is in a normal state. If the determination is invalid, for example, the DMA system is in a non-enabled state, the DMA state change can be controlled by an enable instruction. If there are other abnormalities that cause the DMA system to be in an abnormal state, it can enter a state of waiting for transmission.

[0110] Step 3: The read instruction split module determines whether the data FIFO module has enough space to store the data to be read back. If the space is not enough, it can enter the waiting state for transmission.

[0111] Step 4: If the data space is sufficient to store the read-back data, the read instruction splitting is started, and a read arbitration request is initiated to the read arbitrator based on the split read instruction.

[0112] Step 5: After waiting for the read arbitrator to return that the channel arbitration is valid, write the split read instruction into the read instruction split buffer.

[0113] Step 6: After the read arbitrator arbitration is effective, the corresponding information of the channel is transmitted to the bus control module through the bus selector. The information may include parameters such as read address and read mode to support the implementation of the read instruction.

[0114] Step 7: When the bus control module determines that it is in a non-busy state, the bus control module can convert the above corresponding information into a form that complies with the bus protocol for transmission to the bus.

[0115] Step 8: The data read back by the host interface of the bus control module is returned to the read arbitrator module according to the bus selector, and the read arbitrator module returns it to the data cache of the aforementioned channel according to the channel information.

[0116] The write instruction splitting process is as follows (such as Figure 7 Right side):

[0117] Step 1: When the write instruction splitting module confirms that the read instruction splitting cache is not empty and the number of data in the data cache is sufficient, it starts to split the write instruction.

[0118] Step 2: Send the instructions and arbitration request information split from the write instruction to the write arbitrator module.

[0119] Step 3: Wait for the write arbitrator arbitration to be effective, and the arbitrator will pass the write instruction, address and other information to the bus control module through the bus selection module.

[0120] Step 4: The bus control module will call the cache data from the aforementioned data cache according to the information transmitted by the write arbitrator, and convert it into the corresponding bus protocol and transmit it to the bus to execute data writing.

[0121] In the DMA system provided by the embodiment of the present application, the read instruction splitting module can be used to perform read instruction splitting on the peripheral request, and instruct the read arbitrator to perform arbitration on the split read instruction. When the read arbitration is valid, the target read instruction is stored in the read instruction splitting cache module, so that it is convenient for the write instruction splitting module to know that there is a split read instruction with valid read arbitration. Once the target data is read back through the split read instruction, the write instruction splitting module can start to execute the write instruction splitting without waiting for all the data to be read back. Among them, the arbitrator includes a read arbitrator and a write arbitrator, which can support the simultaneous execution of the read arbitration function and the write arbitration function. Through the DMA system provided by this scheme, pipeline processing can be implemented for instructions, and write instruction processing can be started for the target data when the target data is read back, thereby improving the execution efficiency of the write instruction for the target data, shortening the time cycle consumed by reading and writing data, and thus improving the data transmission efficiency of direct memory access.

[0122] In order to solve the problems existing in the related art, the embodiment of the present application also provides a data transfer method, which is applied to a DMA system, such as Figure 8 As shown, the following steps are included:

[0123] S81: Obtain a peripheral device request, where the peripheral device request is used to request to read data from a first location and write data to a second location;

[0124] S82: performing read instruction splitting on the peripheral device request through a read instruction splitting module;

[0125] S83: performing read arbitration on the split read instructions through a read arbitrator;

[0126] S84: storing the target read instruction with valid read arbitration into the read instruction splitting cache module, and sending the target read instruction to the bus matrix through the host interface to read the target data from the first position;

[0127] S85: When the target data has been read, performing write instruction splitting on the target read instruction in the read instruction splitting cache module through a write instruction splitting module;

[0128] S86: Perform write arbitration on the split write instructions through the write arbitrator;

[0129] S87: Send the target data to the bus matrix through the host interface according to the target write instruction that is valid in the write arbitration, so as to write the target data to the second position.

[0130] Among them, the execution subject of the embodiment of the present application can be specifically a DMA system, which includes a read instruction splitting module, a write instruction splitting module, a read instruction splitting cache module and an arbitrator, and the arbitrator includes a read arbitrator and a write arbitrator.

[0131] The above peripheral request is initiated by the peripheral and can be used to implement data reading and writing requests. In the process of executing read instruction splitting for the peripheral request, the splitting can be performed according to the preset rules and granularity. After splitting the read instruction, the read arbitrator can perform arbitration based on the preset read arbitration and rules, such as determining whether the parameter information such as the address of the read instruction is valid, arbitrating and selecting the channel for executing the read instruction, etc.

[0132] After the read arbitration result is valid, on the one hand, the valid read instruction of the read arbitration is stored in the read instruction splitting cache module, so that the write instruction splitting module performs the related operations of the write instruction on the read back data. On the other hand, the valid arbitration read instruction is executed through the host interface, so that the data is read by transmitting it to the bus matrix. The read back data can be stored in the data cache for subsequent execution of the write instruction.

[0133] When the target data has been read and the corresponding split read instruction is stored in the read instruction split cache module, write instruction splitting is performed on the target read instruction in the read instruction split cache module. Accordingly, instruction splitting can be performed according to preset splitting rules and granularity, and the specific splitting rules of the above read instructions and write instructions can be set according to actual needs.

[0134] After the write instructions are split, write arbitration is performed on the split write instructions, for example, determining whether the address and other parameter information of the write instructions are valid, arbitrating and selecting a channel for executing the write instructions, and so on.

[0135] In one application scenario, the DMA system can have multiple channels. The read arbitrator and the write arbitrator can be used to select the highest priority channel according to the configuration of the descriptor and the fixed priority of each channel to initiate the transmission. During the arbitration process, if the fixed priorities of the two channels are the same, arbitration can be performed in a polling manner. In the case of a large number of read and write instructions, this solution can perform read and write arbitration for the read and write instructions in parallel. The parallel execution of the read arbitration function and the write arbitration function can significantly improve the efficiency of instruction arbitration.

[0136] Through the solution provided in the embodiment of the present application, pipeline processing can be implemented for instructions, and write instruction processing can be started on the target data when the target data is read back, thereby improving the efficiency of executing write instructions on the target data and shortening the time cycle required for reading and writing data, thereby improving the data transmission efficiency of direct memory access.

[0137] Based on the solution provided in the above embodiment, optionally, Fig. 9 As shown, after the above step S84, that is, after sending the target read instruction to the bus matrix through the host interface to read the target data from the first position, it also includes:

[0138] S91: storing the target data in a data cache;

[0139] Wherein, when the target data has been read, performing write instruction splitting on the target read instruction in the read instruction splitting cache module by a write instruction splitting module includes:

[0140] S92: When the read instruction splitting cache module is in a non-empty state and the amount of data stored in the data cache meets a preset data writing condition, perform write instruction splitting on the target read instruction in the read instruction splitting cache module through a write instruction splitting module.

[0141] In this solution, the data read back by the read instruction can be temporarily stored in the data cache. For example, for a DMA system including multiple channels, any channel is configured with a corresponding data cache, and the data caches corresponding to different channels can be independent of each other.

[0142] In an application scenario, the data to be read back by the read instruction may be large. If a linear read-write method is used, all the data must be read back before the splitting, arbitration and transmission of the write instruction can be executed. In this solution, when the target data is stored in the data cache, the instructions in the read instruction splitting cache module can be split and arbitrated for the write instruction, without waiting for all the data requested by the peripheral device to be read back before starting to process the write instruction. Compared with the linear method of completing the data read back first and then executing the data write, this solution can start the splitting and arbitration of the write instruction when part of the data is read back, and then write the part of the data that has been read back in the data cache as soon as possible. While executing the writing of the target data, the splitting, arbitration and transmission of the write instruction can also be executed synchronously, thereby improving the efficiency of the write instruction processing without affecting the data read back based on the read instruction, and writing the read back data to the required location as soon as possible, thereby shortening the overall time consumption of data reading and writing, and effectively improving the overall efficiency of data reading and writing.

[0143] In practical applications, peripheral requests may require data reading and writing between memory and memory, between peripherals and peripherals, and between peripherals and memory. The embodiment of the present application provides a solution that adopts a pipeline method in the data reading and writing process, and the read instruction and the write instruction can be processed in parallel. Compared with the linear processing method of read and write instructions in the related art, this solution can effectively improve the efficiency of the memory to memory mode by 20%, and can improve the efficiency of the memory to memory mode by 50% under multiple AHB bus master interfaces.

[0144] Preferably, the embodiment of the present application further provides a data transfer device, and the module in the device provided by the embodiment of the present application can implement the method steps provided by the above method embodiment. And the device provided by the embodiment of the present application can achieve the technical effects that can be achieved by the above method embodiment.

[0145] Preferably, an embodiment of the present application also provides an electronic device, including a processor, a memory, and a computer program stored in the memory and executable on the processor. When the computer program is executed by the processor, each process of the above-mentioned data transfer method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be described here.

[0146] The embodiment of the present application also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, each process of the above-mentioned data transfer method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it is not repeated here. The computer-readable storage medium is, for example, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0147] An embodiment of the present application also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. The computer program can be operated to enable a computer to execute part or all of the steps of the above-mentioned data transfer method embodiment and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0148] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0149] The present application is described with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, and the combination of the process and / or box in the flowchart and / or block diagram can be realized by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for realizing the function specified in one process or multiple processes in the flowchart and / or one box or multiple boxes in the block diagram.

[0150] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0151] These computer program instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0152] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0153] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0154] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0155] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0156] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0157] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A DMA system, It is characterized in that The DMA system is communicatively connected to the bus matrix, and the DMA system includes: a read instruction splitting module, a write instruction splitting module, a read instruction splitting cache module communicatively connected to the read instruction splitting module and the write instruction splitting module, and an arbitrator communicatively connected to the read instruction splitting module and the write instruction splitting module, and the arbitrator includes a read arbitrator and a write arbitrator; A read instruction splitting module performs read instruction splitting on the acquired peripheral request, and instructs the read arbitrator to perform read arbitration on the split read instructions. If the read arbitrator feeds back that the read arbitration is valid, the target read instruction with valid read arbitration is stored in the read instruction splitting cache module, wherein the peripheral request is used to request to read data from a first location and write it to a second location; The read arbitrator is used to perform read arbitration and send the target read instruction valid for read arbitration to the bus matrix through the host interface to read the target data from the first position; The write instruction splitting module, when the target data has been read, obtains the target read instruction from the read instruction splitting cache module and performs write instruction splitting, and instructs the write arbitrator to perform write arbitration on the split write instructions; The write arbitrator is used to perform write arbitration and send the target data to the bus matrix through the host interface according to the target write instruction valid in the write arbitration, so as to write the target data to the second position.

2. The DMA system according to claim 1, It is characterized in that It also includes a bus control module and a bus selector that is communicatively connected to the arbiter and the bus control module, wherein the bus control module includes a plurality of host interfaces and instruction cache modules corresponding to the plurality of host interfaces respectively. The arbitrator is used to send the target instruction with valid arbitration to the bus selector, wherein the target instruction includes the target read instruction and / or the target write instruction; The bus selector is used to determine a target host interface for executing the target instruction from a plurality of host interfaces, and store the target instruction in an instruction cache module corresponding to the target host interface; The bus control module is used to execute the instructions in the corresponding instruction cache module through the host interface.

3. The DMA system as claimed in claim 2, It is characterized in that It also includes a data control module that is communicatively connected to the read instruction splitting module, the write instruction splitting module, and the arbitrator; The read arbitrator is further used to store the target data read from the first position into the data control module; The write instruction splitting module is specifically used to obtain the target read instruction from the read instruction splitting cache module and perform write instruction splitting when the target data exists in the data control module, and instruct the write arbitrator to perform write arbitration on the split write instructions.

4. The DMA system as claimed in claim 3, It is characterized in that The data control module includes a data type conversion submodule and a data cache submodule; The data cache submodule is used to store the target data; The data bit width conversion submodule is used to convert the bit width of the target data into the bus matrix bit width.

5. The DMA system as claimed in claim 4, It is characterized in that The data cache submodule includes a first-in first-out storage module; Among them, the read instruction splitting module is also used to identify whether the storage space of the first-in first-out storage module meets the preset data reading conditions before executing the read instruction splitting on the obtained peripheral request, and execute the read instruction splitting on the obtained peripheral request if it meets the conditions.

6. The DMA system as claimed in claim 4, It is characterized in that The DMA system includes a plurality of DMA channels, and the DMA system further includes: The request control module receives a peripheral request initiated by a peripheral, determines a target DMA channel for processing the peripheral request based on a mapping relationship, and instructs the target DMA channel to process the peripheral request.

7. The DMA system as claimed in claim 6, It is characterized in that The read arbitrator is specifically used for: Determine a first channel for executing the target read instruction based on a preset read arbitration rule; Sending the target read instruction with read arbitration enabled to the bus matrix through the first channel through the host interface to read target data from the first location; The target data is stored in a data buffer corresponding to the first channel.

8. The DMA system as claimed in claim 7, It is characterized in that The write instruction splitting module is specifically used for: When the read instruction splitting cache module is in a non-empty state and the amount of data stored in the data cache corresponding to the first channel meets a preset data writing condition, obtaining the target read instruction from the read instruction splitting cache module and performing write instruction splitting; The write arbitrator is instructed to perform write arbitration on the split write instructions.

9. The DMA system as claimed in claim 8, It is characterized in that The write arbiter is further used to send information for executing the target write instruction to the bus control module through the bus selector; Among them, the bus control module is specifically used to read the data to be written from the data cache corresponding to the first channel according to the information of the target write instruction, and convert the data to be written according to the bus protocol and send it to the bus matrix through the host interface to write the data to be written to the second position, wherein the data to be written includes at least part of the target data.

10. The DMA system according to any one of claims 1 to 9, It is characterized in that The read instruction splitting module is specifically used to split multiple read instructions that meet the first preset task granularity from the peripheral request, and the write instruction splitting module is specifically used to split multiple write instructions that meet the second preset task granularity from the peripheral request.

11. A data transfer method, It is characterized in that Applicable to DMA systems, including: Obtaining a peripheral device request, wherein the peripheral device request is used to request to read data from a first location and write data to a second location; Performing read instruction splitting on the peripheral device request by a read instruction splitting module; Performing read arbitration on the split read instructions through a read arbitrator; storing a target read instruction valid for read arbitration to a read instruction splitting cache module, and sending the target read instruction to a bus matrix through a host interface to read target data from the first position; In the case where the target data has been read, performing write instruction splitting on the target read instruction in the read instruction splitting cache module through a write instruction splitting module; Perform write arbitration on the split write instructions through a write arbitrator; The target data is sent to the bus matrix through the host interface according to the target write instruction valid in the write arbitration, so as to write the target data to the second position.

12. The method according to claim 11, It is characterized in that After sending the target read instruction to the bus matrix through the host interface to read the target data from the first position, the method further includes: Storing the target data in a data cache; Wherein, when the target data has been read, performing write instruction splitting on the target read instruction in the read instruction splitting cache module by a write instruction splitting module includes: When the read instruction splitting cache module is in a non-empty state and the amount of data stored in the data cache meets a preset data writing condition, a write instruction splitting module is used to perform write instruction splitting on the target read instruction in the read instruction splitting cache module.

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