Conversion circuit for converting GMII interface into RGMII interface

Abstract

The invention discloses a conversion circuit for converting a GMII interface into an RGMII interface. The conversion circuit comprises a first ODDR module, a first data conversion unit and a second data conversion unit, the first ODDR module is used for determining a sending clock signal of the RGMII interface according to the initial clock signal of the GMII interface; the first data conversion unit is used for caching the initial data signal of the first GMII interface and the initial data signal of the second GMII interface to obtain a first cache signal and a second cache signal, and selecting the corresponding cache signal as a data signal sent by the RGMII interface based on the initial clock signal and the rate; and the second data conversion unit is used for respectively performing cache processing and exclusive-or operation on the first control signal and the second control signal of the GMII to obtain a fifth cache signal and a sixth cache signal, and selecting the corresponding cache signal as a control signal sent by the RGMII based on the initial clock signal. The universality is high, and data transmission is stable and efficient.

Description

Technical Field

[0001] The present application generally relates to the field of communication technology, and specifically to a conversion circuit for converting a GMII interface to an RGMII interface. Background Art

[0002] GMII (Gigabit Media Independent Interface) interface and RGMII (Gigabit Media Independent Interface) interface are two commonly used Ethernet physical layer interfaces. Among them, GMII and RGMII are two different standards for network interfaces. GMII provides a standard Gigabit Ethernet interface, while RGMII is a simplified version of the interface that reduces the number of signal lines and is usually used in high-speed network applications. However, in the GMII to RGMII conversion process, different clock domains are involved, and there are differences in clock frequencies at different rates, which leads to unstable data transmission and affects transmission efficiency. Therefore, we provide a conversion circuit for GMII interface to RGMII interface to solve the above problems. Summary of the invention

[0003] In view of the above defects or deficiencies in the prior art, it is desirable to provide a conversion circuit for converting a GMII interface to an RGMII interface, which has strong versatility, stable data transmission and high efficiency.

[0004] The present application provides a conversion circuit for converting a GMII interface to an RGMII interface, comprising: a first ODDR module, a first data conversion unit and a second data conversion unit which are communicatively connected;

[0005] The first ODDR module is used to determine the RGMII interface sending clock signal according to the GMII interface initial clock signal;

[0006] The first data conversion unit is used to cache the first GMII interface initial data signal and the second GMII interface initial data signal to obtain a first cache signal and a second cache signal, and select the first cache signal or the second cache signal as the RGMII interface send data signal based on the GMII interface initial clock signal and rate;

[0007] The second data conversion unit is used to perform cache processing and XOR operation on the first control signal of the GMII interface and the second control signal of the GMII interface respectively to obtain a fifth cache signal and a sixth cache signal, and based on the GMII interface initial clock signal, select the fifth cache signal or the sixth cache signal as the RGMII interface sending control signal.

[0008] According to the technical solution provided in the embodiment of the present application, the first ODDR module has:

[0009] A first clock input port, used to obtain an initial clock signal of the GMII interface;

[0010] A first data input port, used for transmitting the current clock signal to the first data output port when the rising edge of the initial clock signal of the GMII interface occurs;

[0011] A second data input port, used to transmit the current clock signal to the first data output port when the falling edge of the initial clock signal of the GMII interface occurs;

[0012] The first data output port is used to output the clock signal transmitted by the first data input port or the second data input port as a clock signal sent by the RGMII interface.

[0013] According to the technical solution provided in the embodiment of the present application, the first data conversion unit includes:

[0014] A first data cache module is used to obtain a first GMII interface initial data signal and perform cache processing to obtain a first cache signal;

[0015] A selection module, used for acquiring the first GMII interface initial data signal and the second GMII interface initial data signal, and selecting a corresponding data signal as an output data signal according to a rate;

[0016] A second data cache module, used for performing cache processing on the output data signal to obtain a second cache signal;

[0017] The second ODDR module is used to select the first buffer signal or the second buffer signal as a data signal sent by the RGMII interface based on the initial clock signal of the GMII interface.

[0018] According to the technical solution provided in the embodiment of the present application, the selection module has:

[0019] A first data input port, used to obtain a first GMII interface initial data signal;

[0020] A second data input port, used to obtain a second GMII interface initial data signal;

[0021] A third data input port is used to obtain the rate;

[0022] A data selection port is used to select the first GMII interface initial data signal as an output data signal when the rate is a first rate, and to select the second GMII interface initial data signal as an output data signal when the rate is a second rate; the first rate is less than the second rate.

[0023] According to the technical solution provided in the embodiment of the present application, the second ODDR module has:

[0024] The second clock input port is used to obtain the initial clock signal of the GMII interface;

[0025] a third data input port, configured to receive the first buffer signal, and transmit the current first buffer signal to the second data output port when a rising edge of the GMII interface initial clock signal occurs;

[0026] a fourth data input port, configured to receive the second buffer signal, and transmit the current second buffer signal to the second data output port when the falling edge of the GMII interface initial clock signal occurs;

[0027] The second data output port is used to send and output the first buffer signal or the second buffer signal as a data signal of the RGMII interface.

[0028] According to the technical solution provided in the embodiment of the present application, the first GMII interface initial data signal is a GMII interface lower 4-bit data signal, and the second GMII interface initial data signal is a GMII interface upper 4-bit data signal.

[0029] According to the technical solution provided in the embodiment of the present application, the second data conversion unit includes:

[0030] A second data cache module is used to obtain the first control signal of the GMII interface and the second control signal of the GMII interface, and perform cache processing on them respectively to obtain a third cache signal and a fourth cache signal;

[0031] an operation module, configured to perform an XOR operation on the third cache signal and the fourth cache signal to obtain a fifth cache signal;

[0032] The second data cache module is further used to cache the third cache signal to obtain a sixth cache signal;

[0033] The third ODDR module is used to select the fifth buffer signal or the sixth buffer signal as the RGMII interface sending control signal based on the GMII interface initial clock signal.

[0034] According to the technical solution provided in the embodiment of the present application, the third ODDR module has:

[0035] The third clock input port is used to obtain the initial clock signal of the GMII interface;

[0036] a fifth data input port, for receiving the fifth buffer signal, and transmitting the current fifth buffer signal to the third data output port when the rising edge of the GMII interface initial clock signal occurs;

[0037] a sixth data input port, for receiving the sixth buffer signal, and transmitting the current sixth buffer signal to the third data output port when the falling edge of the GMII interface initial clock signal occurs;

[0038] The third data output port is used to output the fifth cache signal or the sixth cache signal as a RGMII interface sending control signal.

[0039] It can be seen from the above technical solution that the present application has at least the following beneficial effects:

[0040] The present application discloses a conversion circuit for converting a GMII interface to an RGMII interface. The conversion circuit comprises: a first ODDR module, a first data conversion unit and a second data conversion unit which are communicatively connected; wherein the first ODDR module determines a clock signal for sending an RGMII interface according to an initial clock signal of the GMII interface; the first data conversion unit performs a cache process on the first GMII interface initial data signal and the second GMII interface initial data signal to obtain a first cache signal and a second cache signal, and selects the first cache signal or the second cache signal as a data signal for sending an RGMII interface based on the initial clock signal and rate of the GMII interface; the second data conversion unit performs a cache process and an XOR operation on a first control signal of the GMII interface and a second control signal of the GMII interface respectively to obtain a fifth cache signal and a sixth cache signal, and selects the fifth cache signal or the sixth cache signal as a control signal for sending an RGMII interface based on the initial clock signal of the GMII interface.

[0041] The present application cooperates with the first ODDR module, the first data conversion unit and the second data conversion unit. During the GMII to RGMII conversion process, no matter in which clock domain, the final output RGMII interface sending clock signal, RGMII interface sending data signal and RGMII interface sending control signal can maintain clock alignment and these three signals and the GMII interface initial clock signal can maintain phase alignment, thereby achieving strong versatility and stable and efficient data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Other features, objects and advantages of the present application will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings.

[0043] Figure 1 A schematic diagram of a conversion circuit for converting a GMII interface to an RGMII interface.

[0044] Figure 2 This is the schematic diagram of the conversion circuit.

[0045] Numbers in the figure: 1, first ODDR module; 2, first data cache module; 3, selection module; 4, second data cache module; 5, second ODDR module; 6, operation module; 7, third ODDR module. DETAILED DESCRIPTION

[0046] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the invention are shown in the accompanying drawings.

[0047] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0048] In order to make the description of the following embodiments clear and concise, a brief introduction to the related technology is first given:

[0049] In the prior art, the GMII interface uses an 8-bit data interface, and its working clock is generally 125MHz, while the RGMII interface uses a 4-bit data interface, and the working clock is also 125MHz at a rate of 1Gbps, but the clock frequency will be reduced accordingly at rates of 10Mbps and 100Mbps. In the process of GMII to RGMII conversion, due to the difference in clock frequencies at different rates, different clock domains may cause clock domain crossing problems, which will increase the probability of metastable states, thereby affecting system stability, and if the clock is not managed properly, it may cause a decrease in data transmission rate and affect network performance. Therefore, this application designs the following solution to solve the above problems.

[0050] In order to make the conversion circuit for converting the GMII interface to the RGMII interface provided in the embodiment of the present application clearer and easier to understand, the conversion circuit is introduced below in conjunction with the accompanying drawings. Figure 1 As shown, this figure is a schematic diagram of a conversion circuit for converting a GMII interface to an RGMII interface provided in an embodiment of the present application, and the conversion circuit includes:

[0051] A first ODDR module 1, a first data conversion unit and a second data conversion unit that are communicatively connected;

[0052] The first ODDR module 1 is used to determine the RGMII interface sending clock signal according to the GMII interface initial clock signal;

[0053] Specifically, the first ODDR module 1 has:

[0054] The first clock input port is used to obtain the initial clock signal of the GMII interface; wherein the first ODDR module 1 uses the initial clock signal of the GMII interface to control the corresponding data to switch between the rising edge and the falling edge.

[0055] The first data input port is used to transmit the current clock signal to the first data output port when the rising edge of the initial clock signal of the GMII interface occurs; that is, the first data input port is used to provide data output at the rising edge of the clock.

[0056] The second data input port is used to transmit the current clock signal to the first data output port when the falling edge of the initial clock signal of the GMII interface occurs; that is, the second data input port is used to provide data output at the falling edge of the clock.

[0057] The first data output port is used to send and output the clock signal transmitted by the first data input port or the second data input port as a clock signal of the RGMII interface; that is, the first data output port is used to output corresponding data, so that in each clock cycle, the data can be updated once at the rising edge and falling edge of the clock, thereby achieving double data rate output.

[0058] It should be noted that the type of the first ODDR module 1 is, for example, an ODDR (Output Double Data Rate) module, which is a primitive in Xilinx FPGA, and is used to implement double data rate output of data in the IOB (Input / Output Block) of the FPGA. That is, the ODDR module can output data at two opposite edges (rising edge and falling edge) of the clock signal, thereby achieving a double data rate.

[0059] like Figure 2 As shown, ODDR1 represents the first ODDR module 1, c in ODDR1 represents the first clock input port, D1 in ODDR1 represents the first data input port, D2 in ODDR1 represents the second data input port, and Q in ODDR1 represents the first data output port. Figure 2 The gmii_tx_clk in the GMII interface represents the initial clock signal. Figure 2The rgmii_txc in it represents the clock signal sent by the RGMII interface. In the process of GMII to RGMII conversion, since the data signal sent by the RGMII interface and the control signal sent by the RGMII interface will generate a certain delay when passing through the corresponding ODDR module, the clock signal sent by the RGMII interface must also use the ODDR module to synchronize the clock phase. Specifically, for example, use gmii_tx_clk as the input clock signal of ODDR1, D1 of ODDR1 inputs "1", and D2 of ODDR1 inputs "0", then the Q of ODDR1 is output as the RGMII interface sending clock signal rgmii_txc with the same phase as the RGMII interface sending data signal rgmii_txd[3:0] and the RGMII interface sending control signal rgmii_tx_ctl.

[0060] A first data conversion unit is used to cache the first GMII interface initial data signal and the second GMII interface initial data signal to obtain a first cache signal and a second cache signal, and select the first cache signal or the second cache signal as a data signal sent by the RGMII interface based on the GMII interface initial clock signal and rate;

[0061] Specifically, the first data conversion unit includes:

[0062] The first data cache module 2 is used to obtain the initial data signal of the first GMII interface and perform cache processing to obtain a first cache signal; the first data cache module 2 temporarily stores the corresponding data in order to match the rate and timing between the GMII interface and the RGMII interface. Figure 2 As shown, data cache mode 1 represents the first data cache module 2, Figure 2 The gmii_txd[3:0] in the figure represents the initial data signal of the first GMII interface. The data buffer module 1 can buffer the gmii_txd[3:0] for 2 clock cycles and output it to the second ODDR module 5 .

[0063] The selection module 3 is used to obtain the first GMII interface initial data signal and the second GMII interface initial data signal, and select the corresponding data signal as the output data signal according to the rate; here, the first GMII interface initial data signal is the GMII interface lower 4-bit data signal, and the second GMII interface initial data signal is the GMII interface upper 4-bit data signal.

[0064] The type of the selection module 3 is, for example, a selector. Figure 2 As shown, the selection module 3 has:

[0065] A first data input port, used to obtain a first GMII interface initial data signal;

[0066] The second data input port is used to obtain the initial data signal of the second GMII interface; here, Figure 2 gmii_txd[7:4] in represents the initial data signal of the second GMII interface.

[0067] The third data input port is used to obtain the rate; Figure 2 As shown, speed indicates the rate.

[0068] The data selection port is used to select the first GMII interface initial data signal as the output data signal when the rate is the first rate, and to select the second GMII interface initial data signal as the output data signal when the rate is the second rate; the first rate is less than the second rate. The first rate is, for example, 100M / 10M, and the second rate is, for example, 1000M. That is, when the rate is 1000M, gmii_txd[7:4] is selected for output, and when the rate is 100M / 10M, gmii_txd[3:0] is selected for output, and the corresponding signal output by the selector is transmitted to the second data cache module 4.

[0069] The second data cache module 4 is used to cache the output data signal to obtain a second cache signal; the second data cache module 4 temporarily stores the corresponding data in order to match the rate and timing between the GMII interface and the RGMII interface. Figure 2 As shown, the data cache module 2 represents the second data cache module 4. The data cache module 2 can cache the output data signal for one clock cycle, and the selector can also delay the corresponding data signal for one clock cycle. The sum of the two is consistent with the delay period of the data cache module 1, ensuring the clock synchronization of the RGMII interface signal, that is, obtaining the second cache signal.

[0070] The second ODDR module 5 is used for selecting the first buffer signal or the second buffer signal as the data signal sent by the RGMII interface based on the initial clock signal of the GMII interface.

[0071] Wherein, the second ODDR module 5 has:

[0072] The second clock input port is used to obtain the initial clock signal of the GMII interface; wherein the second clock input port uses the initial clock signal of the GMII interface to control the corresponding data to switch between the rising edge and the falling edge.

[0073] The third data input port is used to receive the first cache signal and transmit the current first cache signal to the second data output port when the rising edge of the GMII interface initial clock signal occurs; that is, the third data input port is used to provide data output at the rising edge of the clock.

[0074] The fourth data input port is used to receive the second cache signal and transmit the current second cache signal to the second data output port when the falling edge of the GMII interface initial clock signal occurs; that is, the fourth data input port is used to provide data output at the falling edge of the clock.

[0075] The second data output port is used to send and output the first cache signal or the second cache signal as a data signal via the RGMII interface. That is, the second data output port is used to output corresponding data, so that in each clock cycle, the data can be updated once at the rising edge and the falling edge of the clock, thereby achieving double data rate output.

[0076] It should be noted that the type of the second ODDR module 5 is, for example, an ODDR (Output Double Data Rate) module, which is a primitive in Xilinx FPGA, and is used to implement double data rate output of data in the IOB (Input / Output Block) of the FPGA. That is, the ODDR module can output data at two opposite edges (rising edge and falling edge) of the clock signal, thereby achieving double data rate. Figure 2 As shown, ODDR2 represents the second ODDR module 5, c in ODDR2 represents the second clock input port, D1 in ODDR2 represents the third data input port, D2 in ODDR2 represents the fourth data input port, and Q in ODDR2 represents the second data output port. Figure 2 The rgmii_txd[3:0] in the RGMII interface indicates the data signal sent by the RGMII interface. The Q of ODDR2 is output as dual-edge rgmii_txd[3:0], the rising edge data is gmii_txd[3:0], the falling edge data is gmii_txd[7:4] at 1000M, and gmii_txd[3:0] at 100M / 10M.

[0077] The second data conversion unit is used to perform cache processing and XOR operation on the first control signal of the GMII interface and the second control signal of the GMII interface respectively to obtain a fifth cache signal and a sixth cache signal, and based on the initial clock signal of the GMII interface, select the fifth cache signal or the sixth cache signal as the RGMII interface sending control signal.

[0078] Specifically, the second data conversion unit includes:

[0079] The second data cache module 4 is used to obtain the first control signal of the GMII interface and the second control signal of the GMII interface, and perform cache processing respectively to obtain a third cache signal and a fourth cache signal; Figure 2As shown, gmii_tx_en represents the first control signal of the GMII interface, and gmii_tx_er represents the second control signal of the GMII interface. After gmii_tx_en is cached for one clock cycle by the data cache module 2, a third cache signal is obtained. The third cache signal is cached again in the second data cache module 4 and enters the operation module 6 at the same time. After gmii_tx_er is cached for one clock cycle by the data cache module 2, a fourth cache signal is obtained. The fourth cache signal enters the operation module 6.

[0080] The operation module 6 is used to perform an XOR operation on the third cache signal and the fourth cache signal to obtain a fifth cache signal; here, the type of the operation module 6 is, for example, an XOR device. Figure 2 As shown, D1 of the XOR device represents the first operation input port, D2 of the XOR device represents the second operation input port, and Q of the XOR device represents the first operation output port. D1 of the XOR device is used to receive the third cache signal, and D2 of the XOR device is used to receive the fourth cache signal. After the XOR device performs the XOR operation, Q outputs it to the third ODDR module 7.

[0081] The second data cache module 4 is further used to cache the third cache signal to obtain a sixth cache signal; wherein the third cache signal is cached for 1 clock cycle by the data cache module 2 to obtain the sixth cache signal and transmit it to the third ODDR module 7.

[0082] The third ODDR module 7 is used to select the fifth buffer signal or the sixth buffer signal as the RGMII interface sending control signal based on the GMII interface initial clock signal.

[0083] Wherein, the third ODDR module 7 has:

[0084] The third clock input port is used to obtain the initial clock signal of the GMII interface; wherein the third clock input port uses the initial clock signal of the GMII interface to control the corresponding data to switch between the rising edge and the falling edge.

[0085] The fifth data input port is used to receive the fifth cache signal and transmit the current fifth cache signal to the third data output port when the rising edge of the GMII interface initial clock signal occurs; that is, the fifth data input port is used to provide data output at the rising edge of the clock.

[0086] The sixth data input port is used to receive the sixth cache signal and transmit the current sixth cache signal to the third data output port when the falling edge of the GMII interface initial clock signal occurs; that is, the sixth data input port is used to provide data output at the falling edge of the clock.

[0087] The third data output port is used to output the fifth cache signal or the sixth cache signal as a RGMII interface transmission control signal. That is, the third data output port is used to output corresponding data, so that in each clock cycle, the data can be updated once at the rising edge and the falling edge of the clock, thereby achieving double data rate output.

[0088] It should be noted that the type of the third ODDR module 7 is, for example, an ODDR (Output Double Data Rate) module, which is a primitive in Xilinx FPGA, and is used to implement double data rate output of data in the IOB (Input / Output Block) of the FPGA. That is, the ODDR module can output data at two opposite edges (rising edge and falling edge) of the clock signal, thereby achieving double data rate. Figure 2 As shown, ODDR3 represents the third ODDR module 7, c in ODDR3 represents the third clock input port, D1 in ODDR3 represents the fifth data input port, D2 in ODDR3 represents the sixth data input port, Q in ODDR3 represents the third data output port, and rgmii_tx_ctl represents the RGMII interface sending the control signal. The Q interface of ODDR3 outputs rgmii_tx_ctl, the rising edge transmission signal of rgmii_tx_ctl is gmii_tx_en, and the falling edge transmission signal is the XOR value of gmii_tx_en and gmii_tx_er. Since the XOR device is delayed by one clock cycle, the data cache module 2 is delayed by one clock cycle, so rgmii_tx_ctl and rgmii_txd[3:0] are clock synchronized.

[0089] The RGMII interface adopts a dual-edge DDR mode to transmit data, and the GMII interface adopts a single-edge SDR (signaled data rate) mode to transmit data. The present application designs a first ODDR module 1, a first data conversion unit, and a second data conversion unit for communication connection to be used together to convert single-edge data into dual-edge data. In the process of GMII to RGMII conversion, no matter which clock domain it is in, before transmitting data between different clock domains, the present solution is used to perform clock and phase synchronization to ensure that the final output RGMII interface sends a clock signal, the RGMII interface sends a data signal, and the RGMII interface sends a control signal to maintain clock alignment, and that these three signals maintain phase alignment with the GMII interface initial clock signal, thereby achieving strong versatility, stable data transmission, and efficient effects.

[0090] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in the present application.

Claims

1. A conversion circuit for converting a GMII interface to an RGMII interface, characterized in that: include: A first ODDR module, a first data conversion unit, and a second data conversion unit that are communicatively connected; The first ODDR module is used to determine the RGMII interface sending clock signal according to the GMII interface initial clock signal; The first data conversion unit is used to cache the first GMII interface initial data signal and the second GMII interface initial data signal to obtain a first cache signal and a second cache signal, and select the first cache signal or the second cache signal as the RGMII interface send data signal based on the GMII interface initial clock signal and rate; The second data conversion unit is used to perform cache processing and XOR operation on the first control signal of the GMII interface and the second control signal of the GMII interface respectively to obtain a fifth cache signal and a sixth cache signal, and based on the GMII interface initial clock signal, select the fifth cache signal or the sixth cache signal as the RGMII interface sending control signal.

2. A conversion circuit for converting a GMII interface to an RGMII interface according to claim 1, characterized in that: The first ODDR module has: A first clock input port, used to obtain an initial clock signal of the GMII interface; A first data input port, used for transmitting the current clock signal to the first data output port when the rising edge of the initial clock signal of the GMII interface occurs; A second data input port, used to transmit the current clock signal to the first data output port when the falling edge of the initial clock signal of the GMII interface occurs; The first data output port is used to output the clock signal transmitted by the first data input port or the second data input port as a clock signal sent by the RGMII interface.

3. A conversion circuit for converting a GMII interface to an RGMII interface according to claim 1, characterized in that: The first data conversion unit comprises: A first data cache module is used to obtain a first GMII interface initial data signal and perform cache processing to obtain a first cache signal; A selection module, used for acquiring the first GMII interface initial data signal and the second GMII interface initial data signal, and selecting a corresponding data signal as an output data signal according to a rate; A second data cache module, used for performing cache processing on the output data signal to obtain a second cache signal; The second ODDR module is used to select the first buffer signal or the second buffer signal as a data signal sent by the RGMII interface based on the initial clock signal of the GMII interface.

4. A conversion circuit for converting a GMII interface to an RGMII interface according to claim 3, characterized in that: The selection module has: A first data input port, used to obtain a first GMII interface initial data signal; A second data input port, used to obtain a second GMII interface initial data signal; A third data input port is used to obtain the rate; A data selection port is used to select the first GMII interface initial data signal as an output data signal when the rate is a first rate, and to select the second GMII interface initial data signal as an output data signal when the rate is a second rate; the first rate is less than the second rate.

5. The conversion circuit for converting a GMII interface to an RGMII interface according to claim 3, characterized in that: The second ODDR module has: The second clock input port is used to obtain the initial clock signal of the GMII interface; a third data input port, configured to receive the first buffer signal, and transmit the current first buffer signal to the second data output port when a rising edge of the GMII interface initial clock signal occurs; a fourth data input port, configured to receive the second buffer signal, and transmit the current second buffer signal to the second data output port when the falling edge of the GMII interface initial clock signal occurs; The second data output port is used to send and output the first buffer signal or the second buffer signal as a data signal of the RGMII interface.

6. A conversion circuit for converting a GMII interface to an RGMII interface according to any one of claims 3 to 5, characterized in that: The first GMII interface initial data signal is a GMII interface lower 4-bit data signal, and the second GMII interface initial data signal is a GMII interface upper 4-bit data signal.

7. The conversion circuit for converting a GMII interface to an RGMII interface according to claim 1, characterized in that: The second data conversion unit includes: A second data cache module is used to obtain the first control signal of the GMII interface and the second control signal of the GMII interface, and perform cache processing on them respectively to obtain a third cache signal and a fourth cache signal; an operation module, configured to perform an XOR operation on the third cache signal and the fourth cache signal to obtain a fifth cache signal; The second data cache module is further used to cache the third cache signal to obtain a sixth cache signal; The third ODDR module is used to select the fifth buffer signal or the sixth buffer signal as the RGMII interface sending control signal based on the GMII interface initial clock signal.

8. The conversion circuit for converting a GMII interface to an RGMII interface according to claim 7, characterized in that: The third ODDR module has: The third clock input port is used to obtain the initial clock signal of the GMII interface; a fifth data input port, for receiving the fifth buffer signal, and transmitting the current fifth buffer signal to the third data output port when the rising edge of the GMII interface initial clock signal occurs; a sixth data input port, for receiving the sixth buffer signal, and transmitting the current sixth buffer signal to the third data output port when the falling edge of the GMII interface initial clock signal occurs; The third data output port is used to output the fifth cache signal or the sixth cache signal as a RGMII interface sending control signal.

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