Communication circuit, embedded control circuit, chip and electronic equipment

Abstract

The embodiment of the invention provides a communication circuit, an embedded control circuit, a chip and electronic equipment, and the communication circuit comprises a range configuration module which is used for receiving an address range of a storage space which is configured by the embedded control circuit and can be accessed by a host; the address configuration module is used for receiving a target address accessed by the host configured by the host; the data interface module is used for receiving data written into the target address by the host or data read from the storage space for the host to read; the interface control circuit is used for reading data of a target address and writing the data into the data interface module under the condition that a read request of a host is received; and writing the data of the data interface module into the target address under the condition that a write request of the host is received. According to the embodiment of the invention, through the communication circuit arranged in the embedded control circuit, the host can access the storage space of the embedded control circuit, a debugger is not needed to be connected with an SWD interface, and compared with a software mode, the efficiency and the reliability are higher.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a communication circuit, an embedded control circuit, a chip and an electronic device. Background Art

[0002] At present, there are two main methods for debugging embedded controller (EC) chips. One is to read and write EC chip information based on the Serial Wire Debug (SWD) debugging protocol. In this case, the host processor cannot directly obtain EC chip information and must connect the SWD interface through the debugger to obtain chip information. The other is to configure the forwarding interface with software and read and write chip information through the shared memory channel. During the forwarding process, the software needs to make address judgments. Compared with hardware forwarding, the software forwarding efficiency is insufficient. In addition, as the amount of forwarded data increases, problems are prone to occur, resulting in the unusable forwarding channel. Summary of the invention

[0003] In view of the above problems, the embodiments of the present application provide a communication circuit, an embedded control circuit, a chip and an electronic device to solve the above technical problems.

[0004] In the first aspect, the embodiment of the present application provides a communication circuit, which is applied to an embedded control circuit, and the communication circuit includes: a range configuration module, which is used to receive the address range of the storage space that can be accessed by the host configured by the embedded control circuit; an address configuration module, which is used to receive the target address of the host access configured by the host; a data interface module, which is used to receive the data written by the host to the target address, or the data read from the storage space for the host to read; an interface control circuit, which is used to read the data of the target address and write it to the data interface module when receiving a read request from the host; or write the data of the data interface module to the target address when receiving a write request from the host. Through the embodiment of the present application, the host can access the storage space of the embedded control circuit through the communication circuit set in the embedded control circuit, without using a debugger to connect the SWD interface, and it is more efficient and reliable than the software method.

[0005] In a second aspect, an embodiment of the present application further provides an embedded control circuit, comprising a bus interface circuit and the above-mentioned communication circuit, wherein the above-mentioned communication circuit is connected to the bus interface circuit.

[0006] In a third aspect, an embodiment of the present application further provides a chip, comprising the above-mentioned embedded control circuit or communication circuit.

[0007] In a fourth aspect, an embodiment of the present application further provides an electronic device, comprising the above-mentioned chip or embedded control circuit or communication circuit.

[0008] The communication circuit, embedded control circuit, chip and electronic device provided in the embodiments of the present application can solve the problem that the host needs to connect the debugger to the SWD interface to access the storage space of the embedded control circuit, and the problem that the software method has low efficiency and reliability. Through the embodiments of the present application, the host can access the storage space of the embedded control circuit through the communication circuit arranged in the embedded control circuit, without the need to use a debugger to connect the SWD interface, and the hardware forwarding method is more efficient and reliable than the software method.

[0009] These and other aspects of the present application will become more clearly understood in the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0011] Figure 1 A schematic diagram of an electronic device provided in an embodiment of the present application is shown.

[0012] Figure 2 A structural block diagram of a communication circuit provided in an embodiment of the present application is shown.

[0013] Figure 3 A structural block diagram of another communication circuit provided in an embodiment of the present application is shown.

[0014] Figure 4 A structural block diagram of an embedded control circuit provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0015] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0016] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0017] In the embodiments of the present application, it should be noted that, in this article, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0018] Moreover, the terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0019] In the description of the embodiments of the present application, words such as "example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "example" or "for example" in the embodiments of the present application is not to be interpreted as being more preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.

[0020] In addition, the "plurality" in the embodiments of the present application refers to two or more than two. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two or more. For example, including at least one means including one, two or more, and there is no limit on which ones are included. For example, including at least one of A, B and C, then A, B, C, A and B, A and C, B and C, or A, B and C can be included.

[0021] It should be noted that, in the embodiments of the present application, "and / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after are in an "or" relationship.

[0022] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0023] The communication circuit 100 provided in the embodiment of the present application can be applied in Figure 1 In the electronic device 200 shown, the electronic device 200 includes a host 21, an embedded control circuit 22 and a bus 23, wherein the host 21 includes a host processor 211; the embedded control circuit 22 may include a bus interface circuit 221, a processor 222, and a storage space 225, wherein the storage space 225 may include a memory 223 and a peripheral register 224, etc., wherein the embedded control circuit 22 communicates with the host 21 through the bus 23, the processor 222 may access the storage space of the embedded control circuit 22 such as the memory 223 and the peripheral register 224 through the internal bus, and the processor 222 and the host 21 may communicate through the bus interface circuit 221. The embedded control circuit 22 is used to manage the peripherals of the electronic device 200, which may include one or more peripheral modules 226, the peripherals may include but are not limited to a touchpad, a USB interface, a mouse, etc., and the peripheral module 226 may include a touchpad control module, a USB control module, a mouse control module, etc. Optionally, the bus 23 may include but is not limited to an LPC (Low Pin Count, LPC for short) bus, a serial peripheral interface (SPI for short) bus, an enhanced serial peripheral interface (eSPI for short) bus, etc. Correspondingly, the bus interface circuit 221 may include an LPC slave circuit, an SPI slave circuit, or an eSPI slave circuit; the host 21 may include an LPC master circuit, an SPI master circuit, or an eSPI master circuit. Optionally, the electronic device 200 may be a laptop computer, etc.

[0024] The communication circuit 100 provided in the embodiment of the present application is disposed in the embedded control circuit 22 , and is used to enable the host 21 to access the storage space 225 of the embedded control circuit 22 .

[0025] Figure 2 1 shows a schematic diagram of the structure of the communication circuit 100 provided in an embodiment of the present application. Figure 2As shown, the communication circuit 100 may include a range configuration module 101, an address configuration module 102, a data interface module 103 and an interface control circuit 104. The range configuration module 101 is used to receive the address range of the storage space that can be accessed by the host configured by the embedded control circuit; the address configuration module 102 is used to receive the target address that the host configures to access the host; the data interface module 103 is used to receive the data written by the host to the target address, or the data read from the storage space for the host to read; the interface control circuit 104 is used to read the data of the target address configured in the address configuration module 102 and write it into the data interface module 103 when receiving a read request from the host; or write the data of the data interface module 103 into the target address configured in the address configuration module 102 when receiving a write request from the host. Through the embodiment of the present application, the host can access the storage space of the embedded control circuit through the communication circuit set in the embedded control circuit, without using a debugger to connect the SWD interface, and realize data forwarding through hardware. On the one hand, the interface control circuit can read the target address configured by the host from the address configuration module, avoiding the address judgment process in the data forwarding implemented by the software method, which is more efficient than the software method; on the other hand, as the amount of forwarded data increases, the software method is prone to failure, and the hardware method is more reliable when forwarding large amounts of data. It can be seen that the use of the embodiment of the present application is more efficient and more reliable.

[0026] As an implementation, the range configuration module 101 may receive a base address and an address length configured by the embedded control circuit. As an implementation, the range configuration module 101 may include one or more registers that may receive an address range configured by the embedded control circuit, such as a base address and an address length.

[0027] Exemplarily, the processor of the embedded control circuit configures the address range of the storage space in the embedded control circuit that is allowed to be accessed by the host in the range configuration module 101. In some examples, one address range may be included, that is, a continuous storage space. In some examples, multiple address ranges may be included, that is, multiple storage spaces, and the multiple storage spaces may be discontinuous. For example, one address range is the address range of the memory space that is allowed to be accessed, and another address range is the address range of the peripheral register. Any address range may include a base address and an address length.

[0028] As an implementation method, the interface control circuit 104 and the storage space of the embedded control circuit can be connected through an internal bus or a bus matrix. For example, the interface control circuit 104 can be connected to the peripheral register through a first bus, and the interface control circuit 104 can be connected to the memory of the embedded control circuit through a second bus.

[0029] As an implementation manner, the interface control circuit 104 may be connected to the bus interface circuit of the embedded control circuit via an internal bus.

[0030] As an implementation, the address configuration module 102 may include one or more registers, and the host may write the target address into the one or more registers. The interface control circuit 104 may read the target address accessed by the host from the one or more registers.

[0031] As an implementation, the data interface module 103 may include one or more registers, which may be accessed by the host and the interface control circuit 104. The host may read data from the one or more registers, or write data to the one or more registers. The interface control circuit 104 may read data from the one or more registers and write the data to the target address configured in the address configuration module 102, or read data from the target address configured in the address configuration module 102 and write the data to the one or more registers.

[0032] Exemplarily, when the host writes data to the storage space of the embedded control circuit, the host writes the data to one or more registers of the data interface module 103 and configures the target address in the address configuration module 102. The host initiates a write request to the interface control circuit 104. After receiving the write request, the interface control circuit 104 reads the target address from the address configuration module 102, reads data from one or more registers of the data interface module 103, and writes the read data to the target address configured in the address configuration module 102.

[0033] Exemplarily, when the host reads data from the storage space of the embedded control circuit, the host configures the target address in the address configuration module 102. The host initiates a read request to the interface control circuit 104. After receiving the read request, the interface control circuit 104 reads the target address from the address configuration module 102, reads data from the target address, and writes the read data into one or more registers of the data interface module 103. The host reads data from one or more registers of the data interface module 103.

[0034] In some embodiments, Figure 3 As shown, the communication circuit 100 may further include a mode configuration module 105. The mode configuration module 105 is used to receive the operation mode configured by the host, wherein the operation mode includes an address self-adding mode. Figure 3 As shown, the address configuration module 102 is used to self-add the target address if the address self-add instruction of the host is received when the operation mode is configured as the self-add mode. With this implementation, when the host accesses a storage space, it is not necessary to configure the target address every time, which can improve the efficiency of the host accessing the storage space of the embedded control circuit.

[0035] Exemplarily, when the host accesses a continuous storage space in the embedded control circuit, when accessing the first address of the continuous storage space, the first address is configured in the address configuration module 102, and an access request is sent to the interface control circuit 104, and the interface control circuit 104 reads the first address from the address configuration module 102. When accessing the address after the first address, an address self-addition instruction is sent. When the address configuration module 102 is configured as the self-addition mode in the operation mode, if the address self-addition instruction of the host is received, the target address is self-added. The interface control circuit 104 responds to the access request (read request or write request) of the host and reads the target address from the address configuration module 102, and the target address is the target address after self-addition. The host does not need to update the address before each access, and the access efficiency is greatly improved.

[0036] For example, when the host writes data to a continuous storage space in the embedded control circuit, when the host writes the first address of the continuous storage space, the host configures the first address (i.e., the target address) in the address configuration module 102, and sends a write request to the interface control circuit 104 to write the data written to the first address to the data interface module 103. The interface control circuit 104 reads the first address from the address configuration module 102, reads data from the data interface module 103 and writes the first address. When the host writes to the address after the first address, the host sends an address self-addition instruction. When the address configuration module 102 is configured as the self-addition mode in the operation mode, if the address self-addition instruction of the host is received, the target address is self-added. The host sends a write request, and writes the data of an address after the first address to the data interface module 103. In response to the write request of the host, the interface control circuit 104 reads the target address from the address configuration module 102, and the target address is the target address after self-addition (i.e., an address after the first address). The interface control circuit 104 writes the data in the data interface module 103 to the target address, and so on, until the host completes writing to the continuous addresses.

[0037] For example, when the host reads data from a continuous storage space in the embedded control circuit, when the host reads the first address of the continuous storage space, the host configures the first address (i.e., the target address) in the address configuration module 102, and sends a read request to the interface control circuit 104. The interface control circuit 104 reads the first address from the address configuration module 102, and writes the data read from the first address into the data interface module 103. The host reads the data of the first address from the data interface module 103. When the host reads the address after the first address, the host sends an address self-addition instruction. When the address configuration module 102 is configured as the self-addition mode in the operation mode, if the address self-addition instruction of the host is received, the target address is self-added. The host sends a read request to read the data of an address after the first address. In response to the read request of the host, the interface control circuit 104 reads the target address from the address configuration module 102, and the target address is the target address after self-addition (i.e., an address after the first address). The interface control circuit 104 reads data from the target address and writes the read data into the data interface module 103. The host reads data from the data interface module 103 again, that is, data of an address after the first address, and so on, until the host completes writing to the continuous addresses.

[0038] In some embodiments, Figure 3 As shown, the communication circuit 100 may further include a bit width configuration module 106. The bit width configuration module 106 is used to receive the data bit width of the data interface module 103 configured by the host. The interface control circuit 104 is also used to write data to the data interface module 103 or read data from the data interface module 103 based on the data bit width configured in the bit width configuration module 106. Exemplarily, the bit width configuration module 106 may include one or more registers, and the data bit width is stored in the one or more registers.

[0039] As an implementation, the data interface module 103 may include multiple registers. The interface control circuit 104 is also used to read data from one or more registers corresponding to the data bit width configured in the bit width configuration module 106, or write data to one or more registers corresponding to the data bit width.

[0040] Exemplarily, the data interface module 103 may include 4 registers, each of which is one byte in size, and the 4 registers are numbered 0, 1, 2, and 3, respectively. When the data bit width is configured as a single byte, that is, one access operation reads or writes one byte of data, the interface control circuit 104 can read data from the register numbered 0 (that is, the data written by the host to the target address of the embedded control circuit) or write data to the register numbered 0 (that is, the data read from the target address of the embedded control circuit). When the data bit width is configured as a double byte, that is, one access operation reads or writes two bytes of data, the interface control circuit 104 can read data from the registers numbered 0 and 1 in sequence or write data to the registers numbered 0 and 1 in sequence. When the data bit width is configured as four bytes, the interface control circuit 104 can read data from the registers numbered 0 to 3 in sequence or write data to the registers numbered 0 to 3 in sequence.

[0041] In some embodiments, Figure 3 As shown, the communication circuit 100 may further include: a permission configuration module 107. The permission configuration module 107 is used to receive access permission configuration data of the address range configured by the embedded control circuit. The interface control circuit 104 is also used to access the target address based on the access permission configuration data configured in the permission configuration module 107.

[0042] As an implementation method, Figure 3 As shown, the permission configuration module 107 may include: a write protection configuration unit 1071, which is used to receive write protection configuration data of an address range.

[0043] As an implementation method, Figure 3 As shown, the permission configuration module 107 may include: a read protection configuration unit 1072, which is used to receive read protection configuration data of an address range.

[0044] As an implementation method, Figure 3 As shown, the permission configuration module 107 may include: a write protection configuration unit 1071, used to receive write protection configuration data of an address range; and a read protection configuration unit 1072, used to receive read protection configuration data of an address range.

[0045] As an implementation manner, the address range of the storage space that can be accessed by the host configured by the embedded control circuit may include an address range, and the access permission configuration data configured in the permission configuration module 107 is used to indicate whether the address access allows reading or whether it allows writing. As an implementation manner, the address range of the storage space that can be accessed by the host configured by the embedded control circuit may include multiple address ranges, and multiple access permission configuration data are configured in the permission configuration module 107, and any access permission configuration data is used to indicate whether the storage space in the address range corresponding to it allows reading or whether it allows writing. Exemplarily, the storage space corresponding to an address range may allow reading and writing, or allow reading but not allowing writing. For example, an address range of the memory space may allow reading but not allowing writing, and an address range of the peripheral register may allow reading and writing.

[0046] In some embodiments, Figure 3 As shown, the communication circuit 100 may further include an enable configuration module 108. The enable configuration module is used to receive access enable configuration data configured by the embedded control circuit; the interface control circuit 104 is also used to determine whether to access the target address based on the access enable configuration data configured in the enable configuration module 108. As an implementation, the enable configuration module 108 may include one or more registers. Exemplarily, the processor of the embedded control circuit may configure an enable flag in the enable configuration module 108 when powered on, and the interface control circuit 104 determines whether to access the storage space of the embedded control circuit based on the enable flag.

[0047] In some embodiments, Figure 3 As shown, the communication circuit 100 may further include a status indication module 109. The status indication module 109 can be accessed by the host. The interface control circuit 104 is also used to set an error flag in the status indication module 109 when an access error occurs. The host can read the error flag to determine whether an access error occurs. As an implementation, the status indication module 109 may include one or more registers.

[0048] In some embodiments, Figure 3 As shown, the communication circuit 100 may further include an error indication module 110. The error indication module 110 can be accessed by the host. The interface control circuit 104 is also used to write access error error information in the error indication module 110 when an access error occurs.

[0049] As an implementation manner, the interface control circuit 104 is further used to set an error flag in the status indication module 109 when the target address configured in the address configuration module 102 exceeds the address range configured in the range configuration module 101. As a further implementation manner, the interface control circuit 104 is further used to write error information indicating that the target address exceeds the address range in the error indication module 110 when the target address exceeds the address range.

[0050] As an implementation manner, the interface control circuit 104 is further used to, when a read operation is performed on the read protection address, set an error flag in the status indication module 109. As a further implementation manner, the interface control circuit 104 is further used to, when a read operation is performed on the read protection address, write error information indicating that a read operation is performed on the read protection address in the error indication module 110.

[0051] As an implementation mode, the interface control circuit 104 is further used to set the error flag in the status indication module 109 when a write operation is performed on the write address. As a further implementation mode, the interface control circuit 104 is further used to write error information indicating that a write operation is performed on a write-protected address in the error indication module 110 when a write operation is performed on the write address.

[0052] As an implementation mode, the interface control circuit 104 is further used to set an error flag in the status indication module when at least one of the following conditions is met: the target address exceeds the address range, the read protection address is read, or the write address is written. Correspondingly, the interface control circuit 104 is further used to write corresponding error information in the error indication module when the target address exceeds the address range, the read protection address is read, or the write address is written.

[0053] The embodiment of the present application also provides an embedded control circuit, which may include: a bus interface circuit for communicating with a host processor; any of the communication circuits described above in the embodiment of the present application, the communication circuit being connected to the bus interface circuit. The storage space of the embedded control circuit is accessed by the communication circuit provided in the embedded control circuit, without the need to use a debugger to connect to the SWD interface, and is more efficient and reliable than the software method.

[0054] Figure 4 The structure block diagram of the embedded control circuit of the embodiment of the present application is shown as follows: Figure 4 As shown, the embedded control circuit 400 may include: a bus interface circuit 41 , a communication circuit 42 and a storage space 43 .

[0055] The bus interface circuit 41 is used to communicate with the host processor. Optionally, the bus interface circuit 41 and the host processor can be connected via a bus, and the bus may include but is not limited to an LPC (Low Pin Count, referred to as LPC) bus, a serial peripheral interface (Serial Peripheral Interface, referred to as SPI) bus, an enhanced serial peripheral interface (EnhancedSerial Peripheral Interface, referred to as eSPI) bus, etc. Correspondingly, the bus interface circuit 41 may include an LPC slave circuit, an SPI slave circuit, or an eSPI slave circuit. The host may include an LPC master circuit, an SPI master circuit, or an eSPI master circuit.

[0056] The communication circuit 42 and the bus interface circuit 41 may be connected via an internal bus 44. The communication circuit 42 and the storage space 43 may be connected via a bus matrix 45. The storage space 43 may include a memory space 431 and one or more peripheral registers 432. For example, Figure 4 As shown, the communication circuit 42 is connected to the storage space 43 via an Advanced High Performance Bus (AHB bus) matrix. As a master module of the AHB bus, the communication circuit 42 initiates access to the storage space 43 in response to an access request processed by the host.

[0057] like Figure 4 As shown, the communication circuit 42 may include a range configuration module 4201, an address configuration module 4202, a data interface module 4203 and an interface control circuit 4204. The range configuration module 4201 is used to receive the address range of the storage space that can be accessed by the host configured by the embedded control circuit, and optionally, the range configuration module 4201 may include a first register; the address configuration module 4202 is used to receive the target address accessed by the host configured by the host, and optionally, the address configuration module 4202 may include a second register; the data interface module 4203 is used to receive data written by the host to the target address, or data read from the storage space for the host to read, and optionally, the data interface module 4203 may include a register set, which may include one or more registers; the interface control circuit 4204 is used to read the data of the target address configured in the address configuration module 4202 and write it into the data interface module when receiving a read request from the host; or write the data of the data interface module into the target address configured in the address configuration module 4202 when receiving a write request from the host.

[0058] In some embodiments, Figure 4As shown, the communication circuit 42 may further include a mode configuration module 4205. The mode configuration module 4205 is used to receive the operation mode configured by the host, wherein the operation mode includes an address self-adding mode. Figure 4 As shown, the address configuration module 4202 is used to perform self-addition on the target address if the address self-addition instruction of the host is received when the operation mode is configured as the self-addition mode. With this implementation, when the host accesses a storage space, it is not necessary to configure the target address every time the access is made, which can improve the efficiency of the host accessing the storage space of the embedded control circuit. Optionally, the mode configuration module 4205 may include a third register.

[0059] In some embodiments, Figure 4 As shown, the communication circuit 42 may further include a bit width configuration module 4206. The bit width configuration module 4206 is used to receive the data bit width of the data interface module 4203 configured by the host. The interface control circuit 4204 is also used to write data to the data interface module 4203 or read data from the data interface module 4203 based on the data bit width configured in the bit width configuration module 4206. Exemplarily, the bit width configuration module 4206 may include a fourth register.

[0060] In some embodiments, Figure 4 As shown, the communication circuit 42 may further include: a permission configuration module 4207. The permission configuration module 4207 is used to receive access permission configuration data of the address range configured by the embedded control circuit. The interface control circuit 4204 is also used to access the target address based on the access permission configuration data configured in the permission configuration module 4207. Optionally, the permission configuration module 4207 may include a fifth register.

[0061] In some embodiments, Figure 4 As shown, the communication circuit 42 may further include an enable configuration module 4208. The enable configuration module is used to receive access enable configuration data configured by the embedded control circuit; the interface control circuit 4204 is also used to determine whether to access the target address based on the access enable configuration data configured in the enable configuration module 4208. As an implementation, the enable configuration module 4208 may include one or more registers. Exemplarily, the processor of the embedded control circuit may configure an enable flag in the enable configuration module 4208 when powered on, and the interface control circuit 4204 determines whether to access the storage space of the embedded control circuit based on the enable flag. Optionally, the enable configuration module 4208 may include a sixth register.

[0062] In some embodiments, Figure 4As shown, the communication circuit 42 may also include a status indication module 4209. The status indication module 4209 can be accessed by the host. The interface control circuit 4204 is also used to set the error flag in the status indication module 4209 when an access error occurs. The host can read the error flag to determine whether an access error occurs. As an implementation, the status indication module 4209 may include one or more registers. Optionally, the status indication module 4209 may include a seventh register.

[0063] In some embodiments, Figure 4 As shown, the communication circuit 42 may further include an error indication module 4210. The error indication module 4210 can be accessed by the host. The interface control circuit 4204 is also used to write error information of the access error in the error indication module 4210 when an access error occurs. Optionally, the error indication module 4210 may include an eighth register.

[0064] The embodiment of the present application also provides a chip, which includes the above-mentioned communication circuit or embedded control circuit. The chip is also called an integrated circuit (IC), and the chip can be but is not limited to a SOC (System on Chip, chip-level system) chip or a SIP (system in package, system-level package) chip. The chip accesses the storage space of the embedded control circuit through a communication circuit provided in the embedded control circuit, without the need to use a debugger to connect the SWD interface, and is more efficient and reliable than the software method.

[0065] The embodiment of the present application also provides an electronic device, which includes a device body and a chip as described above provided in the device body. The electronic device may be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a human body composition analyzer, a mobile power supply, a wireless charger, a fast charging charger, a car charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car central control screen, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smart phones, laptops, tablet computers, and POS (point of sales terminal). Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights. The electronic device accesses the storage space of the embedded control circuit through a communication circuit provided in the embedded control circuit, without the need to use a debugger to connect the SWD interface, and is more efficient and reliable than the software method.

[0066] The above are only preferred embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any technical personnel in the field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A communication circuit, characterized in that: Applied to an embedded control circuit, the communication circuit comprises: A range configuration module, configured to receive an address range of a storage space configured by the embedded control circuit and accessible by a host; An address configuration module, configured to receive a target address for access by the host configured by the host; A data interface module, used for receiving data written by the host to the target address, or data read from the storage space for reading by the host; The interface control circuit is used to read the data of the target address and write it into the data interface module when receiving a read request from the host; or to write the data of the data interface module into the target address when receiving a write request from the host.

2. The communication circuit according to claim 1, characterized in that The communication circuit further comprises: A mode configuration module, used for receiving an operation mode configured by the host, wherein the operation mode includes an address self-addition mode; The address configuration module is used to perform self-increment on the target address if an address self-increment instruction from the host is received when the operation mode is configured as the self-increment mode.

3. The communication circuit according to claim 1, characterized in that The communication circuit further comprises: A bit width configuration module, used for receiving the data bit width of the data interface module configured by the host; The interface control circuit is further used to write data to the data interface module or read data from the data interface module based on the data bit width.

4. The communication circuit according to claim 3, characterized in that: The data interface module includes a plurality of registers; The interface control circuit is further configured to read data from one or more registers corresponding to the data bit width, or write data to one or more registers corresponding to the data bit width, based on the data bit width.

5. The communication circuit according to claim 1, characterized in that The communication circuit further comprises: A permission configuration module, used to receive access permission configuration data of the address range configured by the embedded control circuit; The interface control circuit is further configured to access the target address based on the access permission configuration data.

6. The communication circuit according to claim 5, characterized in that The permission configuration module includes: a write protection configuration unit, configured to receive write protection configuration data of the address range; and / or The read protection configuration unit is used to receive the read protection configuration data of the address range.

7. The communication circuit according to claim 1, characterized in that: The communication circuit further comprises: An enabling configuration module, configured to receive access enabling configuration data configured by the embedded control circuit; The interface control circuit is further used to determine whether to access the target address based on the access enable configuration data.

8. The communication circuit according to claim 1, characterized in that The communication circuit further comprises: a status indication module, accessible by the host; The interface control circuit is also used to set an error flag in the status indication module when an access error occurs.

9. The communication circuit according to claim 8, characterized in that The communication circuit further comprises: an error indication module, accessible by the host; The interface control circuit is further used to write access error error information into the error indication module when an access error occurs.

10. The communication circuit according to claim 8, characterized in that The interface control circuit is further used to set an error flag in the status indication module to a position when the target address exceeds the address range, a read operation is performed on a read protection address, or a write operation is performed on a write address.

11. The communication circuit according to claim 9, characterized in that The interface control circuit is further used to write corresponding error information in the error indication module when the target address exceeds the address range, a read operation is performed on the read protection address, or a write operation is performed on the write address.

12. The communication circuit according to claim 1, wherein: The storage space includes a peripheral register of the embedded control circuit and / or a memory of the embedded control circuit.

13. An embedded control circuit, characterized in that: include: a bus interface circuit for communicating with a host processor; The communication circuit according to any one of claims 1 to 12, wherein the communication circuit is connected to the bus interface circuit.

14. A chip, characterized in that: It comprises the communication circuit according to any one of claims 1 to 12 or the embedded control circuit according to claim 13.

15. An electronic device, characterized in that: The invention comprises a device body and the chip as claimed in claim 14 arranged in the device body.

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