Data access mode perceived soft and hard collaborative dynamic graph processing equipment

Abstract

The invention discloses software and hardware collaborative dynamic graph processing equipment capable of sensing a data access mode, which belongs to the field of graph calculation optimization, and comprises a memory controller used for reading graph structure data and updated edge data into a chip and caching the graph structure data in a graph structure cache; the priority scheduler is used for identifying the vertexes of which the degrees are higher than a threshold value in the updated edge data and the edges connected with the vertexes as high-priority data, permanently residing in the high-priority on-chip cache, identifying the other vertexes and the connected edges as low-priority data, and caching in the low-priority on-chip cache; the update edge distributor is used for reading the update edge data from the high-priority on-chip cache and the low-priority on-chip cache, dividing the update edge data into N groups according to the ID of the source vertex, and respectively distributing the N groups of update edge data to the N graph update processing units; wherein the graph updating processing unit is used for inserting the received updating edge data into the graph structure data. The updating efficiency of the dynamic graph can be improved.

Description

Technical Field

[0001] The present invention belongs to the field of graph computing optimization, and more specifically, relates to a data access mode-aware soft-hard collaborative dynamic graph processing device. Background Art

[0002] In today's information society, data is growing at an alarming rate, especially complex network structure data, such as social networks, recommendation systems, Internet of Things (IoT) networks, etc. These data are usually represented in the form of graphs. Taking social networks as an example, each social network user can be regarded as a node in the graph. These nodes can contain the user's personal information, such as user name, avatar, age, gender and other attributes. The social relationships between users (such as friend relationships, follow relationships) can be represented by edges. For example, if user A follows user B, there will be an edge pointing from A to B in the graph. The friendships between users will change over time, new friendships will create new edges, and the severance of existing relationships will result in the deletion of edges. The dynamic and scalable nature of graph data has brought unprecedented challenges to data processing technology.

[0003] Dynamic graph computing usually includes graph update operations performed on the graph structure, that is, inserting new edge data into the graph data, and performing graph analysis operations such as BFS and PageRank on the updated graph. Existing solutions use PMA-based structures or tree-based structures to store graph structures. Based on the PMA structure, there are gaps between the data stored in the array, and elements need to be moved when inserting or deleting to avoid changing the entire data structure after each insertion or deletion. However, the edges of its vertices share an array, and there are conflicts between different updates. In addition, when there are insufficient gaps, there will be a large amount of data movement overhead, and the graph update efficiency is low; based on the tree structure, this type of data structure usually uses a search tree to support fast queries, and optimizes on non-leaf nodes or leaf nodes of the tree, but its structural characteristics still lead to discontinuous data storage. The operations of traversing all vertices and traversing all edges during graph analysis will have a large amount of random memory access overhead, and the efficiency of graph analysis cannot be guaranteed.

[0004] The above solutions either have problems with poor data locality and high computational complexity of dynamic graph analysis, or require large overhead to search and move data, and cannot achieve efficient graph analysis and graph updates at the same time. Summary of the invention

[0005] In view of the defects of the prior art and the need for improvement, the present invention provides a data access mode-aware soft-hard collaborative dynamic graph processing device, which aims to propose a new processing architecture to improve the update efficiency of dynamic graphs based on the dynamicity and scalability of dynamic graphs.

[0006] To achieve the above object, the present invention provides a data access mode-aware soft-hard collaborative dynamic graph processing device, comprising: a memory controller, a priority scheduler, a low-priority on-chip cache, a high-priority on-chip cache, a graph structure cache, an update edge distributor, and N graph update processing units; N≥2;

[0007] A memory controller is used to read the graph structure data and the update edge data of the current update batch stored in the off-chip memory into the chip, and cache the graph structure data in the graph structure cache; the update edge data includes the edges to be inserted into the graph structure, each edge is represented by the source vertex and the destination vertex it is connected to, and each vertex has a unique ID;

[0008] Priority scheduler, used to update edge data with a degree higher than the threshold Degree λ The vertices and the edges connected to these vertices are identified as high-priority data and permanently reside in the high-priority on-chip cache, and the remaining vertices and the edges connected to them are identified as low-priority data and cached in the low-priority on-chip cache according to the preset cache replacement strategy;

[0009] An update edge distributor, used for reading update edge data from the high priority on-chip cache and the low priority on-chip cache, and dividing the update edge data into N groups according to the ID of the source vertex, and distributing them to the N graph update processing units respectively;

[0010] The graph update processing unit is used to perform a graph update operation to insert the received update edge data into the graph structure data.

[0011] Furthermore, the threshold Degree λ The calculation methods include:

[0012] Identify the vertices whose degrees in the updated edge data are lower than a preset threshold λ as low-degree vertices, and identify the remaining vertices as high-degree vertices;

[0013] according to Calculate the threshold Degree λ ;

[0014] Among them, b represents the size of the current update batch, y represents the total number of edges connected to low-degree vertices, and x represents the total number of edges connected to high-degree vertices.

[0015] Furthermore, the graph update processing unit is further configured to perform a preprocessing operation before performing the graph update operation; the preprocessing operation includes:

[0016] Sort the received updated edge data according to the destination vertex ID.

[0017] Furthermore, the preprocessing operation also includes:

[0018] Redundant edges in the received update edge data are removed.

[0019] Furthermore, the updated edge data is divided into N groups according to the ID of the source vertex, including:

[0020] For each source vertex, perform ID mod N operation and group the edges connected to the source vertices with the same operation results into the same group;

[0021] Here, mod represents the modulo operation.

[0022] Furthermore, the graph structure data is stored in the graph structure cache in the form of a hierarchical index; the hierarchical index includes: a vertex block array, a common array, a redundant index array and a hierarchical index tree;

[0023] The vertex block array includes V vertex blocks corresponding to the V vertices in the graph structure data one by one, each vertex block is indexed by a vertex ID and includes L+1 slots; V is the number of vertices in the graph structure data;

[0024] For the i-th vertex block in the vertex block array, its first slot is used to store the degree of the i-th vertex Degree i ; If 0≤Degree i ≤L, the destination vertices corresponding to the i-th vertex are all stored in the i-th vertex block; otherwise, the L-1 destination vertices corresponding to the i-th vertex are stored in the 2nd to Lth slots of the i-th vertex block, and the remaining destination vertices are stored in the next-level structure, and the L+1th slot of the i-th vertex block stores a pointer to the next-level structure; if L <Degree i ≤L+A, the next level structure is a normal array; if L+A≤Degree i ≤L+M, the next level structure is a redundant index array; if Degree i >L+M, the next level structure is a hierarchical index tree;

[0025] A normal array is used to store at most A vertices;

[0026] The redundant index array includes an index array and a gap array; the gap array is used to store at most M vertices, the gap array includes one or more storage blocks of equal size, and the vertices are stored in the gap array in order according to IDs; the first vertex ID in each storage block is stored in the index array in order;

[0027] The hierarchical index tree is a tree structure, where its internal nodes are learning nodes and its leaf nodes are redundant index arrays or ordinary arrays; a learning node includes a machine learning model and a learning index array; the machine learning model is used to predict the position of a vertex in the corresponding learning index array according to the ID of the vertex; the learning index array includes one or more entry blocks of equal size, and the vertices are stored in the learning index array in order according to their IDs;

[0028] The entries in the entry block include four types: unused type, edge type, block type, and pointer type; among them, the entries of the unused type are free entries, the entries of the edge type are the entries storing the destination vertex, the entries of the block type are the entries in the entry block where data movement has occurred and there are no child nodes, and the entries of the pointer type are the entries in the entry block with child nodes;

[0029] Among them, L, A, and M are all positive integers, and A < M.

[0030] Furthermore, the graph update operation includes:

[0031] For the edge (v, u) to be inserted, obtain the degree Degree of its source vertex v and the vertex block where the source vertex v is located. If 0 ≤ Degree ≤ L, then execute the vertex block insertion step; if L < Degree ≤ L + A, then execute the ordinary array insertion step; if L + A < Degree ≤ L + M, then execute the redundant array insertion step; if Degree > L + M, then execute the hierarchical index tree insertion step;

[0032] The vertex block insertion step includes:

[0033] Judge whether there is remaining space in the current vertex block. If so, insert the destination vertex u into the current vertex block; otherwise, create an ordinary array for the current vertex block, and store the destination vertex u and the data in the current vertex block after merging them in the current vertex block and the created ordinary array;

[0034] The ordinary array insertion step includes:

[0035] Judge whether there is remaining space in the current ordinary array. If so, insert the destination vertex u into the current ordinary array; otherwise, upgrade the current ordinary array to a redundant index array and clear the current ordinary array;

[0036] The redundant index array insertion step includes:

[0037] (S1) Determine the storage block in the gap array where the destination vertex u should be inserted according to the index array in the current redundant index array. If there is remaining space in this storage block, insert the destination vertex u into this storage block in order and update the index array, and the redundant index array insertion step ends; if there is no remaining space in this storage block, then go to (S2);

[0038] (S2) If there is remaining space in the gap array, calculate the total distance of data movement after inserting the destination vertex u in order, and transfer to (S3); if there is no remaining space in the gap array, transfer to (S4);

[0039] (S3) If the total distance of data movement Distance ≤ Distance_Max, insert the destination vertex u into the gap array in order, and the redundant index array insertion step ends; if Distance> Distance_Max, and the total space of the gap array does not reach M, then go to (S5); if Distance> Distance_Max, and the total space of the gap array reaches M, then go to (S6);

[0040] (S4) If the total space of the gap array does not reach M, then proceed to (S5); if the total space of the gap array reaches M, then proceed to (S6);

[0041] (S5) After expanding a storage block for the gap array, the data in the gap array and the destination vertex u are merged and evenly distributed in each storage block, and the index array is updated, and the redundant index array insertion step is completed;

[0042] (S6) upgrading the current redundant index array to a hierarchical index tree, clearing the current redundant index array, and ending the redundant index array insertion step;

[0043] Wherein, Distance_Max is the preset distance threshold;

[0044] The steps for inserting into a hierarchical index tree include:

[0045] (T1) taking the root node of the current level index tree as the current node;

[0046] (T2) If the current node is a learning node, the machine learning model of the current node is used to predict the position p of the destination vertex u in the learning index array, and the process goes to step (T3); if the current node is a redundant index array, the redundant index array insertion step is executed, and the hierarchical index tree insertion step ends; if the current node is a normal array, the normal array insertion step is executed, and the hierarchical index tree insertion step ends;

[0047] (T3) Determine the entry type corresponding to position p. If it is an unused type, insert the destination vertex u into the entry at position p and update the entry type to an edge type. If it is an edge type, proceed to (T4); if it is a block type, proceed to (T4); if it is a pointer type, enter the next layer of nodes and proceed to (T2);

[0048] (T4) If there is remaining space in the current entry block, the destination vertex u is inserted into the current entry block in sequence, and the type of each entry in the current entry block is set to the block type; otherwise, a normal array is created for the current entry block, the destination vertex u and the data in the current entry block are merged and stored in the created normal array, a pointer to the created normal array is set in the current entry block, and the type of each entry in the current entry block is set to the pointer type.

[0049] Furthermore, the vertex block size is an integer multiple of the cache line size.

[0050] Furthermore, the preset cache replacement strategy is any one of FIFO, LRU, and LFU.

[0051] Furthermore, the memory controller is also used to transfer the graph structure data to the off-chip memory after each graph update processing unit completes the graph update operation.

[0052] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects:

[0053] (1) In the present invention, the priority scheduler takes some vertices and connected edges with higher degrees in the update edge data as high priority data, and permanently stores them in the high priority on-chip cache. Based on the data locality of the dynamic graph, the high priority data has a high access frequency. By permanently storing these data in the cache, these data can be quickly obtained when executing the graph update operation and the subsequent graph analysis operation, thereby realizing data access pattern perception, which is conducive to improving the efficiency of the graph update operation and the graph analysis operation; the update edge distributor divides the update edge data into N different groups, and distributes them to N graph update processing units respectively, realizing the decomposition of the graph update task, and utilizing the hardware parallelism of the N graph update processing units, the efficiency of the graph update can be effectively improved. In general, the dynamic graph processing device provided by the present invention can effectively improve the update efficiency of the dynamic graph based on the perception of the data access pattern and the hardware parallelism, and is conducive to improving the efficiency of the subsequent graph analysis operation.

[0054] (2) In the preferred embodiment of the present invention, the threshold Degree for distinguishing high priority data from low priority data is adaptively calculated based on the degree of each vertex in the updated edge data. λ Specifically, we first identify high-degree vertices and low-degree vertices based on a preset threshold λ, and then Calculate the average degree of the high-degree vertices as the threshold Degree λIn the high-priority data finally identified, the degree of the vertices is higher than the average degree of the high-degree vertices. Since the graph structure used to characterize practical applications obeys a power-law distribution, that is, there are many low-degree vertices and few high-degree vertices, the present invention can accurately identify useful data and permanently reside in the high-priority on-chip cache through this identification method.

[0055] (3) In the preferred embodiment of the present invention, the graph update processing unit will sort the received update edge data according to the destination vertex ID before executing the graph update operation. On the one hand, the orderliness of the update edge data can reduce the number of movements when the update edge data is inserted, thereby reducing the data movement overhead. On the other hand, the orderliness of the update edge data is compatible with graph analysis algorithms such as TC, which is beneficial to improving the efficiency of subsequent graph analysis operations.

[0056] (4) In the preferred embodiment of the present invention, the graph update processing unit also removes redundant update edge data before executing the graph update operation, thereby avoiding useless operations and further reducing the update overhead.

[0057] (5) In the preferred embodiment of the present invention, the graph structure data is stored in the form of hierarchical indexing. Based on this storage method, vertices with different degrees will have different storage forms. For high-degree vertices, tree-structured storage is used to improve update efficiency; for low-degree vertices, array-type structure storage is used to ensure data locality, which is conducive to improving graph analysis efficiency. Corresponding to this storage form, when inserting and updating edges, a combination of horizontal expansion and vertical expansion is adopted to effectively reduce data movement overhead. At the same time, based on the index array in the redundant index data and the machine learning model in the learning index array, the storage location of the data can be quickly located, effectively reducing the search overhead, and efficient graph update operations and graph analysis operations can be achieved at the same time.

[0058] (6) In the preferred embodiment of the present invention, in the first-layer vertex block array in the hierarchical index, the data block size corresponding to each vertex is an integer multiple of the cache line size, so that the source vertex and its corresponding destination vertex (i.e., neighbor node) can be loaded into the cache at the same time, thereby effectively reducing the number of cache exchanges, reducing overhead and improving access efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 An architecture diagram of a data access mode-aware software-hardware collaborative dynamic graph processing device provided in an embodiment of the present invention;

[0060] Figure 2 A schematic diagram of a dynamic graph representation method for hierarchical indexing provided by an embodiment of the present invention;

[0061] Figure 3 A flowchart of a graph updating operation provided by an embodiment of the present invention;

[0062] Figure 4 A schematic diagram of an example of inserting a redundant index array provided by an embodiment of the present invention;

[0063] Figure 5 A schematic diagram of an example of learning index array insertion provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0065] In the present invention, the terms "first", "second", etc. (if any) in the present invention and the accompanying drawings are used to distinguish similar objects but not necessarily to describe a specific order or sequence.

[0066] In order to improve the update efficiency of dynamic graphs, the present invention provides a data access mode-aware software-hardware collaborative dynamic graph processing device, which uses software-hardware collaboration to identify high-priority data and low-priority data based on vertex degrees, and permanently stores high-priority data in the on-chip cache, thereby realizing the perception of data access patterns. At the same time, the dynamic graph update task is decomposed and distributed to multiple graph update processing units, and the parallelism of multiple graph update processing units is used to effectively improve the update efficiency of the dynamic graph. On this basis, an efficient dynamic graph storage method and update method are further realized, which ensures data locality and neighbor orderliness while realizing efficient search and data movement, and can effectively adjust the distance of data movement, while realizing efficient dynamic graph update and dynamic graph analysis.

[0067] Based on the above ideas, in one embodiment of the present invention, a data access mode-aware soft-hard collaborative dynamic graph processing device is provided, such as Figure 1 As shown, it includes: a memory controller, a priority scheduler, a low-priority on-chip cache, a high-priority on-chip cache, a graph structure cache, an update edge distributor, and N graph update processing units; N≥2.

[0068] In this embodiment, the memory controller is used to read the graph structure data and the update edge data of the current update batch stored in the off-chip memory into the chip, and cache the graph structure data in the graph structure cache;

[0069] It is easy to understand that graph structure data is used to represent applications such as social networks, recommendation systems, and Internet of Things (IoT) networks. Accordingly, this embodiment can effectively improve the update efficiency and analysis efficiency of the corresponding applications. The updated edge data includes edges to be inserted into the graph structure, each edge is represented by the source vertex and the destination vertex it connects, for example, it can be represented as (v,u), where v represents the source vertex and u represents the destination vertex; each vertex has a unique ID.

[0070] In this embodiment, the priority scheduler is used to update the edge data whose degree is higher than the threshold Degree λ The vertices and the edges connected to these vertices are identified as high-priority data and permanently reside in the high-priority on-chip cache, and the remaining vertices and the edges connected to them are identified as low-priority data and cached in the low-priority on-chip cache according to the preset cache replacement strategy.

[0071] Based on the data locality of dynamic graphs, high-priority data has a high access frequency. By permanently storing this data in the cache, it can be quickly retrieved when executing graph update operations and subsequent graph analysis operations. This achieves data access pattern awareness, which is beneficial to improving the efficiency of graph update operations and graph analysis operations.

[0072] Since the on-chip cache capacity is limited, in order to keep useful data permanently in the high-priority cache, the threshold Degree used to distinguish high-priority data from low-priority data is set. λ In traditional solutions, a threshold is often set directly, and the vertices with degrees higher than the threshold and the edges connected to them are regarded as high-priority data. However, the graph structure used to represent practical applications often obeys a power-law distribution, that is, there are many low-degree vertices and few high-degree vertices. The traditional recognition method cannot effectively identify high-priority data. To address this problem, this embodiment proposes a method for adaptively calculating the threshold Degree based on the degree of each vertex in the updated edge data. λ Specifically, in this embodiment, the threshold Degree λ The calculation methods include:

[0073] Identify the vertices whose degrees in the updated edge data are lower than a preset threshold λ as low-degree vertices, and identify the remaining vertices as high-degree vertices;

[0074] according to Calculate the threshold Degree λ ;

[0075] Among them, b represents the size of the current update batch, y represents the total number of edges connected to low-degree vertices, and x represents the total number of edges connected to high-degree vertices.

[0076] Based on the above identification method, in the high priority data finally identified by this embodiment, the degree of the vertex is higher than the average degree of the high degree vertices, thereby being able to accurately identify useful data and permanently reside in the high priority on-chip cache.

[0077] At the same time, the identified low priority data is too large to be stored in the low priority cache and can only be cached based on a preset cache replacement strategy. To improve cache replacement efficiency, in this embodiment, a lightweight cache replacement strategy such as FIFO, LRU, or LFU is preferably used.

[0078] In this embodiment, the update edge distributor is used to read the update edge data from the high priority on-chip cache and the low priority on-chip cache, and divide the update edge data into N groups according to the ID of the source vertex, and distribute them to the N graph update processing units respectively;

[0079] In this embodiment, the update edge distributor divides the update edge data into N groups and distributes them to N graph update processing units respectively, thereby realizing the decomposition of the update task.

[0080] Optionally, in this embodiment, the update edge distributor divides the update edge data into N groups according to the ID of the source vertex in the following manner:

[0081] For each source vertex, perform ID mod N operation and group the edges connected to the source vertices with the same operation results into the same group;

[0082] Here, mod represents the modulo operation.

[0083] In this embodiment, the graph update processing unit is used to perform a graph update operation to insert the updated edge data received into the graph structure data. Since the updated edge data involved in each graph update processing unit performing a graph update operation do not overlap, N graph update processing units can perform graph update operations in parallel, effectively improving the efficiency of graph update.

[0084] In order to further improve efficiency and reduce overhead, as a preferred implementation, in this implementation, the graph update processing unit is further used to perform a preprocessing operation before performing the graph update operation; the preprocessing operation includes:

[0085] Sort the received updated edge data according to the destination vertex ID.

[0086] By sorting the destination vertices, the orderliness of updating edge data can be guaranteed. On the one hand, the orderliness of updating edge data can reduce the number of movements when inserting updated edge data, thereby reducing data movement overhead. On the other hand, the orderliness of updating edge data is compatible with graph analysis algorithms such as TC, which is conducive to improving the efficiency of subsequent graph analysis operations.

[0087] Considering that there may be some redundancy in the updated edge data when the graph update operation is actually performed, in order to avoid useless operations and further reduce overhead, in this embodiment, before performing the graph update operation, the graph update processing unit performs a preprocessing operation further including:

[0088] Redundant edges in the received update edge data are removed.

[0089] The number N of graph update processing units is often set to a power of 2. In practical applications, it can be set accordingly according to the actual computing resources of the system.

[0090] In this embodiment, the memory controller is also used to transfer the graph structure data to the off-chip memory after each graph update processing unit completes the graph update operation.

[0091] In order to further improve the efficiency of dynamic graph updates and simultaneously realize efficient graph analysis operations, this embodiment also proposes a hierarchically indexed graph structure data storage form, and correspondingly proposes a locality-aware dynamic graph update mechanism. In the hierarchically indexed graph structure data storage form, vertex data is stored in vertex block arrays, ordinary arrays, redundant index arrays, or hierarchical index trees according to the degrees of vertices in the dynamic graph. In the locality-aware dynamic graph data update mechanism, when updating graph data, data movement is standardized to effectively adjust the movement distance of data in the data structure, thereby minimizing memory access overhead during graph updates. After the memory controller reads the graph structure data from the off-chip memory to the graph structure cache, the graph structure data will be stored in the graph structure cache in the form of a hierarchical index. When the graph update processing unit performs a graph update operation, it is specifically executed in accordance with the locality-aware dynamic graph update mechanism.

[0092] Specifically, Figure 2 As shown, in this embodiment, the hierarchical index includes: a vertex block array, a common array, a redundant index array and a hierarchical index tree;

[0093] The vertex block array includes V vertex blocks corresponding to the V vertices in the graph structure data one by one, each vertex block is indexed by a vertex ID and includes L+1 slots; V is the number of vertices in the graph structure data;

[0094] For the i-th vertex block in the vertex block array, its first slot is used to store the degree of the i-th vertex Degree i ; If 0≤Degree i ≤L, the destination vertices corresponding to the i-th vertex are all stored in the i-th vertex block; otherwise, the L-1 destination vertices corresponding to the i-th vertex are stored in the 2nd to Lth slots of the i-th vertex block, and the remaining destination vertices are stored in the next-level structure, and the L+1th slot of the i-th vertex block stores a pointer to the next-level structure; if L <Degreei ≤L+A, the next level structure is a normal array; if L+A≤Degree i ≤L+M, the next level structure is a redundant index array; if Degree i >L+M, the next level structure is a hierarchical index tree;

[0095] A normal array is used to store at most A vertices;

[0096] The redundant index array includes an index array and a gap array; the gap array is used to store at most M vertices, the gap array includes one or more storage blocks of equal size, and the vertices are stored in the gap array in order according to IDs; the first vertex ID in each storage block is stored in the index array in order;

[0097] The hierarchical index tree is a tree structure, whose internal nodes are learning nodes and leaf nodes are redundant index arrays or ordinary arrays; the learning node includes a machine learning model and a learning index array; the machine learning model is used to predict the position of the vertex in the corresponding learning index array according to the vertex ID; the learning index array includes one or more entry blocks of equal size, and the vertices are stored in the learning index array in order according to the ID;

[0098] The entries in the entry block include four types: unused type, edge type, block type and pointer type; among them, the unused type entries are free entries, the edge type entries are entries that store the destination vertex, the block type entries are entries in the entry block where data movement has occurred and there are no child nodes, and the pointer type entries are entries in the entry block where there are child nodes;

[0099] Among them, L, A and M are all positive integers, and A <M。

[0100] In practical applications, the machine learning model in the learning node can adopt models such as linear regression (LR). These models can approximate the cumulative distribution function (CDF) when predicting, thereby effectively predicting the position of a key value in an ordered array.

[0101] In the graph structure data storage form of hierarchical index, vertices with different degrees will have different storage forms. For high-degree vertices, tree structure storage is used to improve update efficiency; for low-degree vertices, array type structure storage is used to ensure data locality and help improve graph analysis efficiency.

[0102] As a preferred embodiment, in this embodiment, the size of each vertex block is the size of a cache line, so that the source vertex and its corresponding destination vertex (i.e., neighbor node) can be loaded into the cache simultaneously, effectively reducing the number of cache exchanges, reducing overhead, and improving access efficiency. In some other embodiments of the present invention, the size of each vertex block can also be set to an integer multiple of the cache line size.

[0103] Based on the hierarchical index-based graph structure data storage form, as Figure 3 shown, in this embodiment, the graph update operations performed by the graph update processing unit include:

[0104] For the edge (v, u) to be inserted, obtain the degree Degree of its source vertex v and the vertex block where the source vertex v is located. If 0 ≤ Degree ≤ L, then perform the vertex block insertion step; if L < Degree ≤ L + A, then perform the ordinary array insertion step; if L + A < Degree ≤ L + M, then perform the redundant array insertion step; if Degree > L + M, then perform the hierarchical index tree insertion step.

[0105] The vertex block insertion step includes:

[0106] Judge whether there is remaining space in the current vertex block. If so, insert the destination vertex u into the current vertex block; otherwise, create an ordinary array for the current vertex block, and store the merged data of the destination vertex u and the data in the current vertex block in the current vertex block and the created ordinary array.

[0107] The ordinary array insertion step includes:

[0108] Judge whether there is remaining space in the current ordinary array. If so, insert the destination vertex u into the current ordinary array; otherwise, upgrade the current ordinary array to a redundant index array and clear the current ordinary array;

[0109] It is easy to understand that upgrading the current ordinary data to a redundant index array specifically means that after creating a new redundant index array, store the data in the current ordinary array and the destination vertex u in the storage format of the redundant index array, and modify the pointer pointing to the current ordinary array to point to the created redundant index array;

[0110] The redundant index array insertion step includes:

[0111] (S1) Determine the storage block in the gap array where the destination vertex u should be inserted according to the index array in the current redundant index array. If there is remaining space in this storage block, insert the destination vertex u into this storage block in order and update the index array, and the redundant index array insertion step ends; if there is no remaining space in this storage block, then go to (S2);

[0112] (S2) If there is remaining space in the gap array, calculate the total distance of data movement after inserting the destination vertex u in order, and transfer to (S3); if there is no remaining space in the gap array, transfer to (S4);

[0113] In this embodiment, the total distance of data movement refers to the sum of the distances moved by each data after insertion, and its upper limit is a preset distance threshold Distance_Max;

[0114] (S3) If the total data movement distance Distance ≤ Distance_Max, the destination vertex u is inserted into the gap array in order, and the redundant index array insertion step is completed; at this time, the insertion of the destination vertex u will cause data movement between storage blocks,

[0115] If Distance>Distance_Max, and the total space of the gap array does not reach M, then go to (S5) to expand the redundant index array;

[0116] If Distance>Distance_Max, and the total space of the gap array reaches M, then go to (S6);

[0117] This embodiment determines whether to perform inter-block data movement based on both the data movement distance and the total space of the gap array, thereby avoiding excessive data movement overhead;

[0118] (S4) If the total space of the gap array does not reach M, then proceed to (S5) to expand the redundant index array; if the total space of the gap array reaches M, then proceed to (S6);

[0119] (S5) After expanding a storage block for the gap array, the data in the gap array and the destination vertex u are merged and evenly distributed in each storage block, and the index array is updated, and the redundant index array insertion step is completed;

[0120] In this embodiment, after each expansion of the redundant index array, the data therein will be merged and evenly distributed in each storage block, thereby reducing the number of data movements in subsequent insertion operations;

[0121] (S6) upgrading the current redundant index array to a hierarchical index tree, clearing the current redundant index array, and ending the redundant index array insertion step;

[0122] It is easy to understand that upgrading the current redundant index array to a hierarchical index tree specifically means that after creating a new hierarchical index tree, the data in the current redundant index array and the destination vertex u are stored in the storage format of the hierarchical index tree, and the pointer to the current redundant index array is modified to a pointer to the created hierarchical index tree.

[0123] The steps for inserting into a hierarchical index tree include:

[0124] (T1) taking the root node of the current level index tree as the current node;

[0125] (T2) If the current node is a learning node, the machine learning model of the current node is used to predict the position p of the destination vertex u in the learning index array, and the process goes to step (T3); if the current node is a redundant index array, the redundant index array insertion step is executed, and the hierarchical index tree insertion step ends; if the current node is a normal array, the normal array insertion step is executed, and the hierarchical index tree insertion step ends;

[0126] (T3) Determine the entry type corresponding to position p. If it is an unused type, insert the destination vertex u into the entry at position p and update the entry type to an edge type. If it is an edge type, proceed to (T4); if it is a block type, proceed to (T4); if it is a pointer type, enter the next layer of nodes and proceed to (T2);

[0127] (T4) If there is remaining space in the current entry block, the destination vertex u is inserted into the current entry block in sequence, and the type of each entry in the current entry block is set to the block type; otherwise, a normal array is created for the current entry block, the destination vertex u and the data in the current entry block are merged and stored in the created normal array, a pointer to the created normal array is set in the current entry block, and the type of each entry in the current entry block is set to the pointer type.

[0128] Based on the above update mechanism, when inserting and updating edges, a combination of horizontal expansion and vertical expansion is adopted to effectively reduce the data movement overhead. At the same time, based on the index array in the redundant index data and the machine learning model in the learning index array, the storage location of the data can be quickly located, which effectively reduces the search overhead and can simultaneously realize efficient graph update operations and graph analysis operations.

[0129] by Figure 4An example is shown to describe the insertion process of the redundant index array in detail, where the index array size is 2, the block size is 4, the redundant index array stores the edges of the vertex with vertex ID 2, the initial index array is [6, 16], and the gap array is updated to [6, 8, \, \, 16, 17, \, \], where \ represents the gap. There are mainly three situations when inserting. When inserting edge (2,5) (2,9), there is enough space in the first block, so the block is moved and then the data is inserted into the gap array [5,6,8,9,16,17,\,\]. Finally, the index array is updated to [5,16]. Then, edge (2,7) is inserted. There is not enough space in the first block, but there is enough space in the block as a whole. So the data can be moved between blocks and inserted. The gap array is updated to [5,6,7,8,9,16,17,\]. Finally, the index array is updated to [5,9]. Finally, edge (2,11) (2,12) is inserted. There is no remaining space in the block, so the space is expanded, a block is added, and the elements are evenly distributed in each block. The gap array is updated to [5,6,7,\,8,9,11,\,12,16,17,\], and the index array is updated to [5,8,12].

[0130] by Figure 5 An example shown in FIG. 1 describes in detail the insertion process of the learning index array. The learning index array is recorded as array, the block size is 4, and the first 4 spaces (1 block) are used as an example for explanation. There are mainly three situations during insertion. When inserting edge (3,6), the predicted position of 6 in the learning index array should be 3, recorded as np.model(v), which indicates the position of v in the learning index array predicted by the model. Since the position class type of array[3] is unused (U) at this time, 6 is directly inserted at this position, and the position type is changed to edge (E); when inserting edge (3,4), the predicted position of 4 is 2. At this time, the position of array[2] is already used by 5, whose type is edge (E), and there is a conflict. Therefore, the elements are moved horizontally in the block, and a gap position is found to insert 4. Then, the entry type of the entire block is changed to block (Block); when inserting edge (3,3), there is not enough space to accommodate 3, so the data is merged, a redundant index array is created to store the merged data, and the entry type in the block is changed to a pointer type pointing to the redundant index array.

[0131] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A data access mode-aware soft-hard collaborative dynamic graph processing device, characterized in that: include: Memory controller, priority scheduler, low priority on-chip cache, high priority on-chip cache, graph structure cache, update edge distributor, and N graph update processing units; N≥2； The memory controller is used to read the graph structure data and the updated edge data of the current update batch stored in the off-chip memory into the chip, and cache the graph structure data in the graph structure cache; The updated edge data includes edges to be inserted into the graph structure, each edge is represented by its connected source vertex and destination vertex, and each vertex has a unique ID; The priority scheduler is used to update edge data with a degree higher than a threshold Degree λ The vertices and the edges connected to these vertices are identified as high priority data, which are permanently resident in the high priority on-chip cache, and the remaining vertices and the edges connected to them are identified as low priority data, which are cached in the low priority on-chip cache according to a preset cache replacement strategy; The update edge distributor is used to read the update edge data from the high priority on-chip cache and the low priority on-chip cache, and divide the update edge data into N groups according to the ID of the source vertex, and distribute them to the N graph update processing units respectively; The graph update processing unit is used to perform a graph update operation to insert the received update edge data into the graph structure data.

2. The data access mode-aware soft-hard collaborative dynamic graph processing device according to claim 1, characterized in that: The threshold degree λ The calculation methods include: Identify the vertices whose degrees in the updated edge data are lower than a preset threshold λ as low-degree vertices, and identify the remaining vertices as high-degree vertices; according to Calculate the threshold Degree λ ; Among them, b represents the size of the current update batch, y represents the total number of edges connected to low-degree vertices, and x represents the total number of edges connected to high-degree vertices.

3. The data access mode-aware soft-hard collaborative dynamic graph processing device according to claim 1 or 2, characterized in that: The graph update processing unit is further configured to perform a preprocessing operation before performing the graph update operation; the preprocessing operation includes: Sort the received updated edge data according to the destination vertex ID.

4. The data access mode-aware soft-hard collaborative dynamic graph processing device according to claim 3, characterized in that: The pre-processing operation also includes: Redundant edges in the received update edge data are removed.

5. The data access mode-aware soft-hard collaborative dynamic graph processing device according to claim 1 or 2, characterized in that: The updating edge data is divided into N groups according to the ID of the source vertex, including: For each source vertex, perform ID mod N operation and group the edges connected to the source vertices with the same operation results into the same group; Among them, mod represents the modulo operation.

6. The data access mode-aware soft-hard collaborative dynamic graph processing device according to claim 1 or 2, characterized in that: The graph structure data is stored in the graph structure cache in the form of a hierarchical index; the hierarchical index includes: a vertex block array, a common array, a redundant index array and a hierarchical index tree; The vertex block array includes V vertex blocks corresponding to the V vertices in the graph structure data one by one, each vertex block is indexed by a vertex ID and includes L+1 slots; V is the number of vertices in the graph structure data; For the i-th vertex block in the vertex block array, its first slot is used to store the degree of the i-th vertex Degree i ; If 0≤Degree i ≤L, the destination vertices corresponding to the ith vertex are all stored in the ith vertex block; otherwise, the L-1 destination vertices corresponding to the ith vertex are stored in the 2nd to Lth slots of the ith vertex block, and the remaining destination vertices are stored in the next-level structure, and the L+1th slot of the ith vertex block stores a pointer to the next-level structure; if L<Degree i ≤L+A, the next level structure is a normal array; if L+A≤Degree i ≤L+M, the next level structure is a redundant index array; if Degree i >L+M, then the next level structure is a hierarchical index tree; The ordinary array is used to store at most A vertices; The redundant index array includes an index array and a gap array; the gap array is used to store at most M vertices, the gap array includes one or more storage blocks of equal size, and the vertices are stored in the gap array in order according to IDs; the first vertex ID in each storage block is stored in the index array in order; The hierarchical index tree is a tree structure, wherein the internal nodes are learning nodes, and the leaf nodes are redundant index arrays or ordinary arrays; the learning nodes include a machine learning model and a learning index array; the machine learning model is used to predict the position of the vertex in the corresponding learning index array according to the ID of the vertex; the learning index array includes one or more entry blocks of equal size, and the vertices are stored in the learning index array in order according to the ID; The entries in the entry block include four types: unused type, edge type, block type, and pointer type. Among them, the entries of the unused type are free entries, the entries of the edge type are the entries storing the destination vertex, the entries of the block type are the entries in the entry block where data movement has occurred and there are no child nodes, and the entries of the pointer type are the entries in the entry block with child nodes. Wherein, L, A, and M are all positive integers, and A < M.

7. The data access mode-aware soft-hard collaborative dynamic graph processing device according to claim 6, characterized in that: The graph update operation includes: For the edge (v, u) to be inserted, obtain the degree Degree of its source vertex v and the vertex block where the source vertex v is located. If 0 ≤ Degree ≤ L, then execute the vertex block insertion step; if L < Degree ≤ L + A, then execute the ordinary array insertion step; if L + A < Degree ≤ L + M, then execute the redundant array insertion step; if Degree > L + M, then execute the hierarchical index tree insertion step. The vertex block insertion step includes: Judge whether there is remaining space in the current vertex block. If so, insert the destination vertex u into the current vertex block; otherwise, create an ordinary array for the current vertex block, and store the merged data of the destination vertex u and the data in the current vertex block in the current vertex block and the created ordinary array. The ordinary array insertion step includes: Judge whether there is remaining space in the current ordinary array. If so, insert the destination vertex u into the current ordinary array; otherwise, upgrade the current ordinary array to a redundant index array and clear the current ordinary array. The redundant index array insertion step includes: (S1) Determine the storage block in the gap array where the destination vertex u should be inserted according to the index array in the current redundant index array. If there is remaining space in this storage block, insert the destination vertex u into this storage block in order and update the index array, and the redundant index array insertion step ends; if there is no remaining space in this storage block, go to (S2). (S2) If there is remaining space in the gap array, calculate the total data movement distance generated after inserting the destination vertex u in order and go to (S3); if there is no remaining space in the gap array, go to (S4). (S3) If the total data movement distance Distance ≤ Distance_Max, insert the destination vertex u into the gap array in order, and the redundant index array insertion step ends; if Distance > Distance_Max and the total space of the gap array has not reached M, go to (S5); if Distance > Distance_Max and the total space of the gap array has reached M, go to (S6). (S4) If the total space of the gap array has not reached M, go to (S5); if the total space of the gap array has reached M, go to (S6). (S5) After expanding a storage block for the gap array, evenly distribute the data in the gap array together with the destination vertex u among the storage blocks and update the index array, and the redundant index array insertion step ends. (S6) Upgrade the current redundant index array to a hierarchical index tree and clear the current redundant index array, and the redundant index array insertion step ends. Wherein, Distance_Max is the preset distance threshold; The hierarchical index tree inserting step comprises: (T1) taking the root node of the current level index tree as the current node; (T2) If the current node is a learning node, the machine learning model of the current node is used to predict the position p of the destination vertex u in the learning index array, and the process proceeds to step (T3); if the current node is a redundant index array, the redundant index array insertion step is executed, and the hierarchical index tree insertion step ends; if the current node is a normal array, the normal array insertion step is executed, and the hierarchical index tree insertion step ends; (T3) Determine the entry type corresponding to position p. If it is an unused type, insert the destination vertex u into the entry at position p, and update the entry type to an edge type, and perform the hierarchical index tree insertion step technology; if it is an edge type, proceed to (T4); if it is a block type, proceed to (T4); if it is a pointer type, enter the next layer of nodes and proceed to (T2); (T4) If there is remaining space in the current entry block, the destination vertex u is inserted into the current entry block in sequence, and the type of each entry in the current entry block is set to the block type; otherwise, a normal array is created for the current entry block, the destination vertex u and the data in the current entry block are merged and stored in the created normal array, a pointer to the created normal array is set in the current entry block, and the type of each entry in the current entry block is set to the pointer type.

8. The data access mode-aware soft-hard collaborative dynamic graph processing device according to claim 6, characterized in that: The vertex block size is an integer multiple of the cache line size.

9. The data access mode-aware soft-hard collaborative dynamic graph processing device according to claim 1 or 2, characterized in that: The preset cache replacement strategy is any one of FIFO, LRU, and LFU.

10. The data access mode-aware soft-hard collaborative dynamic graph processing device according to claim 1 or 2, characterized in that: The memory controller is also used to transfer the graph structure data to the off-chip memory after each graph update processing unit completes the graph update operation.

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