BMC chip firmware upgrading method, BMC chip, equipment and storage medium

Abstract

The invention relates to a BMC chip firmware upgrading method. The BMC chip firmware upgrading method comprises the steps of setting a firmware update start identification bit and a firmware update completion identification bit based on a preset firmware update state module; responding to a to-be-updated firmware program obtained by the main processor, and setting a firmware update start identification position as a first identification through a firmware update state module; the main processor executes firmware updating based on the to-be-updated firmware program, responds to firmware updating completion, and positions a firmware updating completion identifier as a first identifier through a firmware updating state module; detecting a firmware update start identification bit in the firmware update state module based on the coprocessor, if the firmware update start identification bit is a first identification, detecting a firmware update completion identification bit in the firmware update state module after a preset time interval, and if the firmware update completion identification bit is the first identification, clearing the firmware update completion identification bit, and if the firmware update completion identification bit is not the first identification, resetting the main processor. The reliability of the updating process is improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a BMC chip firmware upgrade method, a BMC chip, a device and a storage medium. Background Art

[0002] At present, the BMC (Baseboard Management Controller) chip is a server remote management chip that can be used to remotely control the restart of the server and monitor the operation of the basic components of the server. Due to the needs of server business and the repair of firmware security vulnerabilities, the firmware program in the BMC chip firmware upgrade method usually needs to be updated. The firmware program of the BMC chip firmware upgrade method is usually stored in flash (a non-volatile memory). At present, there are three main methods for updating the firmware program in the BMC flash chip: (1) directly burning the BMC flash chip through a flash burner, and then soldering the flash chip to the board; (2) after the u-boot (Universal Bootloader, open source boot loader) program on the BMC chip firmware upgrade method is started, the flash controller of the BMC chip firmware upgrade method is driven by the u-boot program to burn the flash; (3) after the host is started, the flash is burned through the h2b module of the BMC chip firmware upgrade method.

[0003] However, during the BMC chip firmware upgrade method, the server will be in an unmanageable state, and the flash burning may fail. Once the firmware update fails, the server will not be able to power off and restart. Therefore, it is very necessary to develop a stable and reliable firmware update method and BMC chip firmware upgrade method that is easy for operation and maintenance personnel to operate. Summary of the invention

[0004] Based on this, the present application provides a BMC chip firmware upgrade method, device, equipment and storage medium to solve the problems existing in the prior art.

[0005] In a first aspect, a BMC chip firmware upgrade method is provided, the method comprising:

[0006] A firmware update start flag and a firmware update completion flag are set based on a preset firmware update status module; in response to the main processor acquiring the firmware program to be updated, the firmware update start flag is set to the first flag through the firmware update status module;

[0007] The main processor executes a firmware update based on the firmware program to be updated, and in response to the firmware update being completed, sets a firmware update completion flag position to a first flag through a firmware update status module;

[0008] Based on the coprocessor, the firmware update start flag in the firmware update status module is detected. If the firmware update start flag is a first flag, the firmware update completion flag in the firmware update status module is detected after a preset time interval. If the firmware update completion flag is a first flag, the firmware update completion flag is cleared. If the firmware update completion flag is not the first flag, the main processor is reset.

[0009] According to an achievable manner in the embodiment of the present application, the method further includes:

[0010] Storing the current firmware program of the main processor and the firmware program to be updated in the storage module;

[0011] If the coprocessor detects and determines that the firmware update completion flag in the firmware update status module is not the first flag after the preset time interval, the coprocessor obtains the current firmware program from the storage module and controls the main processor to write the current firmware program.

[0012] According to an achievable method in an embodiment of the present application, in response to the main processor acquiring the firmware program to be updated, setting the firmware start update flag position to the first flag through the firmware update status module includes:

[0013] The main processor drives the network port of the remote connection module to obtain the firmware program to be updated from the remote network and stores it in the storage module;

[0014] Backing up the current firmware program currently in use to the first space of the storage module, and setting the first space to a read-only mode;

[0015] Obtaining the encryption type of the firmware program to be updated, and determining a corresponding decryption algorithm according to the encryption type;

[0016] Decrypting the firmware program to be updated based on the decryption algorithm by a preset firmware verification module;

[0017] In response to the firmware program to be updated being successfully decrypted, based on the firmware verification module, storing the decrypted firmware to be updated in the second space of the storage module, and setting the second space to a read-only mode;

[0018] In response to the decrypted firmware to be updated being stored in the second space of the storage module, the data verification mark position is set to the first mark by the firmware verification module;

[0019] In response to the data verification flag being the first flag, the firmware update start flag is set to the first flag through the firmware update status module.

[0020] According to an achievable manner in an embodiment of the present application, the main processor executes a firmware update based on the firmware program to be updated, and in response to the firmware update being completed, sets a firmware update completion flag position to a first flag through a firmware update status module, including:

[0021] Burning the firmware program to be updated into the main processor flash controller, and resetting the main processor after the burning of the main processor flash controller is completed, wherein the main processor flash controller is used to store the program that the main processor is powered on and runs;

[0022] The main processor executes the firmware program to be updated based on the main processor flash controller. If the execution is successful, the firmware update completion mark position is set to the first mark through the firmware update status module.

[0023] According to an achievable manner in the embodiment of the present application, the method further includes:

[0024] In response to the firmware update being completed, resetting and starting the main processor, if the main processor is reset and started successfully, clearing the firmware update start flag bit through the firmware update status module;

[0025] In response to the firmware update start flag being cleared, the storage module clears the read-only mode set in the first space.

[0026] According to an achievable method in an embodiment of the present application, if the coprocessor detects and determines that the firmware update completion flag in the firmware update status module is not the first flag after the preset time interval, the current firmware program is obtained from the storage module, and the main processor is controlled to write the current firmware program, including:

[0027] If the coprocessor detects and determines that the firmware update completion flag in the firmware update status module is not the first flag after the preset time interval, the main processor flash controller is reset to obtain the current firmware program from the storage module;

[0028] Burning the current firmware program into the main processor flash controller, and after the burning of the main processor flash controller is completed, resetting the main processor;

[0029] The main processor executes the current firmware program based on the main processor flash controller.

[0030] According to an achievable manner in the embodiment of the present application, it is characterized in that the method further includes:

[0031] Obtaining a target task thread processed by the main processor;

[0032] In response to the main processor executing firmware update based on the firmware program to be updated, the target task thread is processed based on the coprocessor.

[0033] In a second aspect, a BMC chip is provided, comprising: a main processor, a coprocessor and a firmware update status module, wherein the main processor and the coprocessor are respectively connected to the firmware update status module for communication;

[0034] The firmware update status module is used to: set a firmware update start flag and a firmware update completion flag based on a preset firmware update status module;

[0035] The main processor is used to: in response to obtaining the firmware program to be updated, set the firmware start update mark position to the first mark through the firmware update status module; perform firmware update based on the firmware program to be updated, and in response to the firmware update being completed, set the firmware update completion mark position to the first mark through the firmware update status module;

[0036] The coprocessor is used to: detect the firmware update start flag in the firmware update status module; if the firmware update start flag is a first flag, then after a preset time interval, detect the firmware update completion flag in the firmware update status module; if the firmware update completion flag is a first flag, clear the firmware update completion flag; if the firmware update completion flag is not the first flag, reset the main processor.

[0037] In a third aspect, a computer device is provided, comprising:

[0038] at least one processor; and

[0039] a memory communicatively connected to the at least one processor; wherein,

[0040] The memory stores computer instructions that can be executed by the at least one processor, and the computer instructions are executed by the at least one processor to enable the at least one processor to perform the method involved in the first aspect above.

[0041] In a fourth aspect, a computer-readable storage medium is provided, on which computer instructions are stored, characterized in that the computer instructions are used to enable a computer to execute the method involved in the first aspect above.

[0042] According to the technical content provided by the embodiments of the present application, the present application sets a firmware start update flag and a firmware complete update flag based on a preset firmware update status module; in response to the main processor acquiring the firmware program to be updated, the firmware start update flag is set to the first flag through the firmware update status module; the main processor executes firmware update based on the firmware program to be updated, and in response to the completion of the firmware update, the firmware complete update flag is set to the first flag through the firmware update status module; based on the coprocessor detecting the firmware start update flag in the firmware update status module, if the firmware start update flag is the first flag, then after a preset time interval, detecting the firmware update complete flag in the firmware update status module, if the firmware complete update flag is the first flag, clearing the firmware update complete flag, if the firmware complete update flag is not the first flag, resetting the main processor, thereby solving the problem that the chip cannot restart after the BMC firmware update fails, avoiding the situation that the chip main processor cannot operate normally due to the firmware unavailability during the update process, increasing the reliability of the BMC main processor firmware update process, and increasing the efficiency of the firmware update. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A flowchart of a method for upgrading BMC chip firmware in one embodiment;

[0044] Figure 2 A flowchart of a BMC chip firmware upgrade method in one embodiment;

[0045] Figure 3 A schematic diagram of a BMC chip in an embodiment;

[0046] Figure 4 A schematic diagram of a BMC chip firmware upgrade device in one embodiment;

[0047] Figure 5 A block diagram of a BMC chip in one embodiment;

[0048] Figure 6 FIG. 4 is a schematic structural diagram of a computer device in one embodiment. DETAILED DESCRIPTION

[0049] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0050] Figure 1 A flowchart of a BMC chip firmware upgrade method provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the method may include the following steps:

[0051] Step 101: setting a firmware update start flag and a firmware update completion flag based on a preset firmware update status module.

[0052] Specifically, Figure 1 As shown, combined with Figure 2 In order to improve the stability of BMC firmware update, reduce the system startup time after firmware update, and simplify the firmware update steps, the present invention provides a method for updating BMC firmware with the assistance of BMC coprocessor. Before the BMC chip updates the main processor firmware, the firmware start update flag of the firmware update status module in the SCU (System Control Unit) firmware update status register is set.

[0053] Step 102: In response to the main processor acquiring the firmware program to be updated, the firmware update status module sets the firmware update start flag position to the first flag.

[0054] Specifically, the main processor obtains the main processor firmware program to be updated from the remote network, and sets the firmware update start mark position 1 of the firmware update status module in the SCU, where 1 represents the first mark and can also be replaced by other numbers or letters, etc., which is not limited in this embodiment.

[0055] Step 103: the main processor executes firmware update based on the firmware program to be updated, and in response to the firmware update being completed, sets the firmware update completion flag position to the first flag through the firmware update status module.

[0056] Specifically, the main processor executes the updated firmware program. If it runs successfully, the firmware update completion flag bit in the firmware update status register in the SCU is set, and the firmware update completion flag bit in the firmware update status module is set to 1.

[0057] Step 104: Based on the coprocessor, the firmware update start flag in the firmware update status module is detected. If the firmware update start flag is a first flag, then after a preset time interval, the firmware update completion flag in the firmware update status module is detected. If the firmware update completion flag is a first flag, the firmware update completion flag is cleared. If the firmware update completion flag is not the first flag, the main processor is reset.

[0058] Specifically, the coprocessor detects that the firmware start update flag position in the firmware update flag register in the SCU is 1, and after a preset time interval, detects whether the firmware update completion flag position is 1. If the firmware update completion flag position is 1, the firmware completion flag position is cleared. If the firmware update completion flag position is not 1, for example, the firmware update completion flag position is 0, the coprocessor writes the backup successfully started firmware program to the flash and resets the main processor.

[0059] It can be seen that the embodiment of the present application sets the firmware start update flag and the firmware complete update flag based on a preset firmware update status module; in response to the main processor acquiring the firmware program to be updated, the firmware start update flag is set to the first flag through the firmware update status module; the main processor executes firmware update based on the firmware program to be updated, and in response to the completion of the firmware update, the firmware complete update flag is set to the first flag through the firmware update status module; based on the coprocessor detecting the firmware start update flag in the firmware update status module, if the firmware start update flag is the first flag, then after a preset time interval, the firmware update completion flag in the firmware update status module is detected, if the firmware complete update flag is the first flag, then the firmware complete update flag is cleared, if the firmware complete update flag is not the first flag, then the main processor is reset. The present application solves the problem that the chip cannot be restarted after the BMC firmware update fails, avoids the situation that the chip main processor cannot operate normally due to the unavailability of the firmware during the update process, increases the reliability of the firmware update process of the BMC main processor, and increases the efficiency of the firmware update.

[0060] In one embodiment of the present application, the method also includes: storing the current firmware program of the main processor and the firmware program to be updated in a storage module; if the coprocessor detects and determines that the firmware update completion flag in the firmware update status module is not the first flag after a preset time interval, then obtaining the current firmware program from the storage module and controlling the main processor to write the current firmware program.

[0061] Specifically, the main processor stores the current firmware program and the firmware program to be updated in the storage module DDR (Double Data Rate Static Random-Access Memory) through DMA (Direct Memory Access) for backup. Among them, the current firmware program is the firmware program currently being used by the main processor, and the firmware program to be updated is the firmware program to be updated by the main processor. Based on the coprocessor detecting the firmware start update flag in the firmware update status module, if the firmware start update flag is the first flag, then after a preset time interval, the firmware update completion flag in the firmware update status module is detected. If the coprocessor detects and determines that the firmware update completion flag in the firmware update status module is not the first flag after the preset time interval, the main processor is reset, and the current firmware program is obtained from the storage module DDR at the same time, and the main processor is controlled to write the current firmware program. In addition, the updated firmware can be directly written into the DDR of the BMC chip by the host OS through the h2b, espi and other module interfaces of the BMC chip.

[0062] The embodiment of the present application stores the current firmware program of the main processor and the firmware program to be updated in the storage module. If the coprocessor detects and determines that the firmware of the main processor is unsuccessful after a preset time interval, the current firmware program is obtained from the storage module, and the main processor is controlled to write the current firmware program, which solves the problem that the chip cannot restart after the BMC firmware update fails, avoids the situation where the chip main processor cannot operate normally due to the firmware unavailability during the update process, and increases the reliability of the BMC main processor firmware update process. The user only needs to write the firmware program to be updated to the DDR memory, and the operation of restoring the main processing operation after a failure is automatically performed by the coprocessor, without the need for additional manual operation, which increases the efficiency of the firmware update. At the same time, the stability of the server operation is improved through the auxiliary management of the main processor firmware update process by the coprocessor and the takeover of some important server management tasks.

[0063] In one embodiment of the present application, the method further includes: acquiring a target task thread processed by a main processor; and processing the target task thread based on a coprocessor in response to the main processor executing a firmware update based on the firmware program to be updated.

[0064] Specifically, Figure 3 As shown, Figure 3 A BMC chip with a main processor and a coprocessor is provided. The main processor adopts an arma7 processor with a high operating frequency, can execute various tasks for remote management of a server, control a flash controller to read and write firmware programs, and control a network card controller to obtain updated firmware through a network. The coprocessor adopts an arm-m3 processor with a low operating frequency, mainly runs an rtos program, and monitors performance indicators such as server fans and CPU temperatures in real time. In this embodiment, the target task thread processed by the main processor is obtained, and in response to the main processor executing a firmware update based on the firmware program to be updated, the coprocessor processes the target task thread. The coprocessor can assist in monitoring the firmware update status of the main processor, and in the case of a failure in the firmware update of the main processor, temporarily take over some of the main processor's work, and restore the normal operation of the main processor as soon as possible. During the firmware update process of the main processor, some work, such as server power on and off, voltage detection, fan management, etc., can be temporarily transferred to the coprocessor for processing.

[0065] In one implementation, the coprocessor can temporarily take over some important server management tasks that the main processor needs to handle after detecting the start firmware update flag in the SCU firmware update register, such as monitoring the server voltage through the ADC interface, remotely powering on and off the server, and obtaining the server temperature through the i2c interface.

[0066] It can be seen that the embodiment of the present application solves the problem that the chip cannot restart after the BMC firmware update fails, and avoids the situation where the chip main processor cannot operate normally due to the unavailability of firmware during the update process. At the same time, the stability of the server operation is improved through the coprocessor's auxiliary management of the main processor's firmware update process and the takeover of some important server management tasks.

[0067] In one embodiment of the present application, in response to the main processor obtaining the firmware program to be updated, the firmware update start identification position is set to the first identification through the firmware update status module, including: the main processor drives the network port through the remote connection module to obtain the firmware program to be updated from the remote network and stores it in the storage module; the current firmware program currently in use is backed up to the first space of the storage module, and the first space is set to read-only mode; the encryption type of the firmware program to be updated is obtained, and the corresponding decryption algorithm is determined according to the encryption type; the firmware program to be updated is decrypted based on the decryption algorithm by a preset firmware verification module; in response to the successful decryption of the firmware program to be updated, the decrypted firmware to be updated is stored in the second space of the storage module based on the firmware verification module, and the second space is set to read-only mode; in response to the decrypted firmware to be updated being stored in the second space of the storage module, the data verification identification position is set to the first identification through the firmware verification module; in response to the data verification identification position being the first identification, the firmware start update identification position is set to the first identification through the firmware update status module.

[0068] Specifically, Figure 3 As shown, the BMC chip provided in the embodiment of the present application also has a preset firmware verification module. The main processor drives the network port through the emac module to obtain the main processor firmware program to be updated from the remote network and stores it in the DDR. The main processor reads the currently used spl program and u-boot program into the DDR for backup in DMA mode through the flash controller. This part of the DDR space is the first space, and this part of the DDR space is set to read-only. The firmware program to be updated is the spl program and the u-boot program encrypted and signed by the hash algorithm. The main processor configures the encryption and decryption module to perform data verification on the firmware to be updated and the encryption and decryption module to perform verification and decryption operations on the encrypted and signed firmware program according to the size of the firmware program and the encryption type. After the verification and decryption are successful, the verification and encryption and decryption module writes the decrypted program back to the DDR. This part of the DDR space is the second space, and this part of the address space is configured as read-only, and the data verification success flag is configured. The data verification flag position is set to the first flag through the firmware verification module, and in response to the data verification flag position being the first flag, the firmware start update flag position is set to the first flag through the firmware update status module.

[0069] It can be seen that the embodiment of the present application ensures the security and stability of the current firmware program during the update process by backing up the current firmware program to the first space of the storage module and setting the space to read-only mode, thereby preventing system crashes caused by update failures or interruptions. The firmware program to be updated is encrypted and decrypted using the corresponding decryption algorithm according to the encryption type after acquisition. This process enhances the security of the firmware update package during transmission and storage, and prevents the firmware from being unauthorizedly accessed or tampered with. The firmware verification module is used to verify the decrypted firmware to be updated to ensure that the firmware data is not damaged or tampered with during transmission and storage, thereby improving the success rate of the firmware update and the stability of the system. After the firmware is successfully decrypted and verified, it is stored in the second space of the storage module and set to read-only mode, further ensuring the integrity and security of the firmware data.

[0070] In one embodiment of the present application, the method also includes: in response to the completion of the firmware update, resetting and starting the main processor, if the main processor is reset and started successfully, clearing the firmware update start flag through the firmware update status module; in response to the firmware update start flag being cleared, the storage module clears the read-only mode set to the first space.

[0071] Specifically, the main processor executes a firmware update based on the firmware program to be updated. In response to the firmware update being completed, the firmware update completion flag is set to the first flag through the firmware update status module, and the main processor is reset and started. If the main processor is reset and started successfully, the firmware update start flag is cleared through the firmware update status module; in response to the firmware update start flag being cleared, the storage module clears the read-only mode set in the first space. For example, the main processor is successfully reset and started, and the firmware update completion flag is configured to 1, and the read-only protection of the corresponding DDR address space of the backed-up current firmware and the firmware to be updated is canceled.

[0072] In one embodiment of the present application, the main processor executes a firmware update based on the firmware program to be updated, and in response to the completion of the firmware update, the firmware update completion identifier position is set to the first identifier through the firmware update status module, including: burning the firmware program to be updated into the main processor flash controller, and after the burning of the main processor flash controller is completed, resetting the main processor, wherein the main processor flash controller is used to store the program that the main processor is powered on and runs; the main processor executes the firmware program to be updated based on the main processor flash controller, and if the execution is successful, the firmware update completion identifier position is set to the first identifier through the firmware update status module.

[0073] Specifically, Figure 2 As shown, combined with Figure 3, the main processor flash controller is used to store the spl, u-boot and kernel programs that are powered on and run by the main processor. Burn the firmware program to be updated into the main processor flash controller. After the main processor flash controller is burned, reset the main processor, wherein the main processor flash controller is used to store the program that is powered on and run by the main processor; the main processor executes the firmware program to be updated based on the main processor flash controller. If the execution is successful, the firmware update completion flag position is set to the first flag through the firmware update status module. For example, the firmware update completion flag position is set to 1.

[0074] In one embodiment of the present application, if the coprocessor detects and determines that the firmware update completion flag in the firmware update status module is not the first flag after a preset time interval, the current firmware program is obtained from the storage module, and the main processor is controlled to write the current firmware program, including: if the coprocessor detects and determines that the firmware update completion flag in the firmware update status module is not the first flag after a preset time interval, the main processor flash controller is reset, and the current firmware program is obtained from the storage module; the current firmware program is burned into the main processor flash controller, and after the burning of the main processor flash controller is completed, the main processor is reset; the main processor executes the current firmware program based on the main processor flash controller.

[0075] Specifically, Figure 2 As shown, combined with Figure 3 , the main processor flash controller is used to store the spl, u-boot and kernel programs that the main processor runs when it is powered on. If the coprocessor detects and determines that the firmware update completion flag in the firmware update status module is not the first flag after a preset time interval, the main processor flash controller is reset, and the current firmware program is obtained from the storage module; the current firmware program is burned into the main processor flash controller, and after the main processor flash controller is burned, the main processor is reset; the main processor executes the current firmware program based on the main processor flash controller. That is, if the main processor reset startup fails and the coprocessor does not detect the firmware update completion flag, the main processor flash controller is reset, and the backup firmware is written back to the main processor flash through the main processor flash controller in DMA mode, and the main processor and the main processor flash controller are controlled to reset.

[0076] The embodiments of the present application can promptly detect whether the firmware update is successfully completed by checking the identifier in the firmware update status module after a preset time interval. If the update is not completed, remedial measures are taken to prevent the system from entering an unstable state due to an incomplete firmware update. Resetting the flash controller of the main processor and re-obtaining the current firmware program from the storage module for burning is equivalent to a "reset" and "recovery" at the system level, which helps to solve system problems caused by any errors or anomalies that may occur during the firmware update process. Resetting the main processor after the main processor flash controller is burned ensures that the main processor starts on the new firmware program and avoids conflicts or inconsistencies between the old and new firmware. This smooth transition helps to reduce system downtime and improve user experience.

[0077] In one embodiment, the current firmware program written back to the main processor flash by the coprocessor can also be stored in the flash of the coprocessor, ensuring that if the server is abnormally powered off, the coprocessor can still quickly restore the firmware program in the main processor.

[0078] In one embodiment, the method also includes: receiving multiple firmware programs to be updated based on the main processor, writing the multiple firmware programs to be updated and the current firmware program into the firmware backup area of ​​the storage module, setting corresponding firmware type identification bits for the multiple firmware programs to be updated and the current firmware program, obtaining the target firmware type flag bit that the coprocessor writes back to the main processor flash controller, and the coprocessor writes the corresponding firmware program into the main processor flash controller based on the target flag bit.

[0079] Specifically, the main processor can receive multiple updated firmware programs, write them into the DDR firmware backup area, set the firmware type flag of the coprocessor to write back to the main processor flash in the SCU, and the coprocessor can selectively write the firmware program into the main processor flash. For example, the firmware type flag in the register can be represented as: 00, backup firmware; 01, update firmware program one; 10, update firmware program two.

[0080] It can be seen that the embodiment of the present application allows the main processor to receive multiple firmware programs to be updated, and write them together with the current firmware program into the firmware backup area of ​​the storage module. Doing so not only provides more options and flexibility for firmware updates, but also ensures the compatibility of the system under different update requirements. By setting corresponding firmware type identification bits for multiple firmware programs to be updated and the current firmware program, the system can clearly identify the type and version of each firmware program. After the coprocessor writes back the target firmware type flag bit, the corresponding firmware program is written to the main processor flash controller based on the flag bit, ensuring the accuracy and security of the firmware update, and avoiding system problems caused by firmware mismatch or erroneous updates.

[0081] In one embodiment, the present application provides a BMC chip with a coprocessor. Figure 3 As shown, the BMC chip includes: Main processor: It uses arma7 processor, which runs at a high frequency and can execute various tasks for remote management of the server, control the flash controller to read and write firmware programs, and control the network card controller to obtain updated firmware through the network. Coprocessor: It uses arm-m3 processor, which runs at a low frequency and mainly runs rtos programs to monitor server fan, CPU temperature and other performance indicators in real time. It assists in monitoring the firmware update status of the main processor, and temporarily takes over some of the main processor's work when the main processor firmware update fails, and restores the normal operation of the main processor as soon as possible. Main processor flash controller: It controls the read and write operations of the external flash of the main processor through the spi interface, supports memory mapping mode, four-wire read and write and DMA operations, has a fast read and write speed, and is used to store the firmware program running after the main processor is powered on. Coprocessor flash controller: controls the read and write operations of the coprocessor's external flash through the SPI interface. It is used for the coprocessor to read the RTOS program running after power-on. It can also be used to store the backup or updated program of the firmware program running when the main processor is powered on; firmware verification module: used to perform hash algorithm decryption and signature verification on the updated firmware; WDT module: used to control the selective reset of the main processor and related modules; eMAC: used to control the network card to obtain the updated firmware program from the remote through the network protocol; UART: prints the startup information and can also obtain the updated firmware program.

[0082] The embodiments of the present application avoid the situation in which the chip main processor cannot operate normally due to the flash controller being stuck due to misoperation or the updated firmware being unavailable during the firmware burning process, thereby increasing the reliability of the BMC main processor firmware update process. The user only needs to write the firmware program to be updated into the DDR memory, and the operation of restoring the main processing operation after a failure is automatically performed by the coprocessor, without the need for additional manual operations, thereby increasing the efficiency of the firmware update. At the same time, the coprocessor's auxiliary management of the main processor firmware update process and the takeover of some important server management tasks improves the stability of the server operation.

[0083] In one embodiment, the present application provides a BMC chip firmware upgrade device, such as Figure 4 As shown in the figure, it includes BMC chip, flash chip, DDR particles, RJ45 network port, and host computer. Two flash chips store the firmware programs executed by the main processor and coprocessor of the BMC chip when they are powered on. The BMC obtains the firmware program to be updated transmitted by the host computer through the network SSH protocol through the network port and stores it in the DDR or flash chip.

[0084] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in the application, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0085] Figure 5 A schematic diagram of the structure of a BMC chip provided in an embodiment of the present application includes: a main processor 501, a coprocessor 502 and a firmware update status module 503, wherein the main processor and the coprocessor are respectively connected to the firmware update status module in communication;

[0086] The firmware update status module 503 is used to: set a firmware update start flag and a firmware update completion flag based on a preset firmware update status module;

[0087] The main processor 501 is used to: in response to obtaining the firmware program to be updated, set the firmware start update mark position to the first mark through the firmware update status module; perform firmware update based on the firmware program to be updated, and in response to the firmware update being completed, set the firmware update completion mark position to the first mark through the firmware update status module;

[0088] The coprocessor 502 is used to: detect the firmware update start flag in the firmware update status module; if the firmware update start flag is a first flag, then after a preset time interval, detect the firmware update completion flag in the firmware update status module; if the firmware update completion flag is a first flag, clear the firmware update completion flag; if the firmware update completion flag is not the first flag, reset the main processor.

[0089] In one embodiment, it also includes: a storage module for storing the current firmware program of the main processor and the firmware program to be updated in the storage module; the coprocessor is also used for obtaining the current firmware program from the storage module and controlling the main processor to write the current firmware program if the coprocessor detects and determines that the firmware update completion flag in the firmware update status module is not the first flag after the preset time interval.

[0090] In one embodiment, it also includes: a firmware verification module; the main processor drives the network port through the remote connection module to obtain the firmware program to be updated from the remote network and stores it in the storage module; the current firmware program currently in use is backed up to the first space of the storage module, and the first space is set to read-only mode; the encryption type of the firmware program to be updated is obtained, and the corresponding decryption algorithm is determined according to the encryption type; the firmware program to be updated is decrypted based on the decryption algorithm by a preset firmware verification module; in response to the successful decryption of the firmware program to be updated, the decrypted firmware to be updated is stored in the second space of the storage module based on the firmware verification module, and the second space is set to read-only mode; in response to the decrypted firmware to be updated being stored in the second space of the storage module, the data verification flag position is set to the first flag by the firmware verification module; in response to the data verification flag position being the first flag, the firmware start update flag position is set to the first flag by the firmware update status module.

[0091] In one embodiment, the main processor is also used to: burn the firmware program to be updated into the main processor flash controller, and reset the main processor after the burning of the main processor flash controller is completed, wherein the main processor flash controller is used to store the program that the main processor is powered on and runs; the main processor executes the firmware program to be updated based on the main processor flash controller, and if the execution is successful, the firmware update completion identifier position is set to the first identifier through the firmware update status module.

[0092] In one embodiment, it also includes: in response to the completion of the firmware update, resetting and starting the main processor, if the main processor is reset and started successfully, clearing the firmware start update flag through the firmware update status module; in response to the firmware start update flag being cleared, the storage module clears the read-only mode set to the first space.

[0093] In one embodiment, the method further includes: if the coprocessor detects and determines that the firmware update completion flag in the firmware update status module is not the first flag after the preset time interval, resetting the main processor flash controller, obtaining the current firmware program from the storage module; burning the current firmware program into the main processor flash controller, and resetting the main processor after the main processor flash controller is burned;

[0094] The main processor executes the current firmware program based on the main processor flash controller.

[0095] In one embodiment, the method further includes: acquiring a target task thread processed by the main processor; and processing the target task thread based on the coprocessor in response to the main processor executing a firmware update based on the firmware program to be updated.

[0096] According to the specific embodiments provided in this application, the technical solution provided in this application can have the following advantages:

[0097] This avoids the situation where the chip main processor cannot operate normally due to the flash controller being stuck due to misoperation or the updated firmware being unavailable during the firmware burning process, and increases the reliability of the BMC main processor firmware update process. Users only need to write the firmware program to be updated to the DDR memory, and the operation of restoring the main processing operation after a failure is automatically performed by the coprocessor, without the need for additional manual operations, which increases the efficiency of firmware updates. At the same time, the coprocessor's auxiliary management of the main processor firmware update process and the takeover of some important server management tasks improves the stability of server operation.

[0098] The same or similar parts between the above embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0099] It should be noted that the embodiments of the present application may involve the use of user data. In actual applications, user-specific personal data can be used in the scheme described in this article within the scope permitted by applicable laws and regulations, provided that the applicable laws and regulations of the country are met (for example, the user's explicit consent, effective notification to the user, and the user's explicit authorization, etc.).

[0100] According to an embodiment of the present application, the present application also provides a computer device and a computer-readable storage medium. The present application also provides a computer device, including at least one processor and a memory connected to the at least one processor in communication; wherein the memory stores computer instructions executable by the at least one processor, and the computer instructions are executed by the at least one processor so that the at least one processor can execute the BMC chip firmware upgrade method described in any of the above embodiments.

[0101] like Figure 6 , is a block diagram of a computer device according to an embodiment of the present application. The computer device is intended to represent various forms of digital computers or mobile devices. The digital computer may include a desktop computer, a portable computer, a workbench, a personal digital assistant, a server, a mainframe computer, and other suitable computers. The mobile device may include a tablet computer, a smart phone, a wearable device, etc.

[0102] like Figure 6 As shown, the computer device 600 includes a computing unit 601, a ROM 602, a RAM 603, a bus 604, and an input / output (I / O) interface 605. The computing unit 601, the ROM 602, and the RAM 603 are connected to each other via the bus 604. The input / output (I / O) interface 605 is also connected to the bus 604.

[0103] The computing unit 601 can perform various processes in the method embodiment of the present application according to the computer instructions stored in the read-only memory (ROM) 602 or the computer instructions loaded from the storage unit 608 to the random access memory (RAM) 606. The computing unit 601 can be various general and / or special processing components with processing and computing capabilities. The computing unit 601 may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. In some embodiments, the method provided in the embodiment of the present application can be implemented as a computer software program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 608.

[0104] RAM 603 may also store various programs and data required for the operation of device 600. Part or all of a computer program may be loaded and / or installed on device 600 via ROM 602 and / or communication unit 609.

[0105] The input unit 606, output unit 607, storage unit 608 and communication unit 609 in the computer device 600 can be connected to the I / O interface 605. The input unit 606 can be, for example, a keyboard, a mouse, a touch screen, a microphone, etc. The output unit 607 can be, for example, a display, a speaker, an indicator light, etc. The device 600 can exchange information, data, etc. with other devices through the communication unit 609.

[0106] It should be noted that the device may also include other components necessary for normal operation, or may only include components necessary for implementing the solution of the present application, rather than all the components shown in the figure.

[0107] Various implementations of the systems and techniques described herein can be realized in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof.

[0108] The computer instructions for implementing the method of the present application can be written in any combination of one or more programming languages. These computer instructions can be provided to the computing unit 601, so that when the computer instructions are executed by the computing unit 601 such as a processor, the steps involved in the method embodiment of the present application are executed.

[0109] The present application also provides a computer-readable storage medium on which computer instructions are stored, and the computer instructions are used to enable a computer to execute the BMC chip firmware upgrade method described in any of the above embodiments.

[0110] The computer-readable storage medium provided in the present application may be a tangible medium that may contain or store computer instructions for executing the steps involved in the method embodiments of the present application. The computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, and other forms of storage media.

[0111] The above specific implementations do not constitute a limitation on the protection scope of this application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of this application should be included in the protection scope of this application.

Claims

1. A BMC chip firmware upgrade method, characterized in that: include: Setting a firmware update start flag and a firmware update completion flag based on a preset firmware update status module; In response to the main processor acquiring the firmware program to be updated, the firmware update start mark position is set to the first mark through the firmware update status module; The main processor executes a firmware update based on the firmware program to be updated, and in response to the firmware update being completed, sets a firmware update completion flag position to a first flag through a firmware update status module; Based on the coprocessor, the firmware update start flag in the firmware update status module is detected. If the firmware update start flag is a first flag, the firmware update completion flag in the firmware update status module is detected after a preset time interval. If the firmware update completion flag is a first flag, the firmware update completion flag is cleared. If the firmware update completion flag is not the first flag, the main processor is reset.

2. The BMC chip firmware upgrade method according to claim 1, characterized in that: The method further comprises: Storing the current firmware program of the main processor and the firmware program to be updated in the storage module; If the coprocessor detects and determines that the firmware update completion flag in the firmware update status module is not the first flag after the preset time interval, the coprocessor obtains the current firmware program from the storage module and controls the main processor to write the current firmware program.

3. The BMC chip firmware upgrade method according to claim 2, characterized in that: In response to the main processor acquiring the firmware program to be updated, the firmware update start mark position is set to the first mark by the firmware update status module, including: The main processor drives the network port of the remote connection module to obtain the firmware program to be updated from the remote network and stores it in the storage module; Backing up the current firmware program currently in use to the first space of the storage module, and setting the first space to a read-only mode; Obtaining the encryption type of the firmware program to be updated, and determining a corresponding decryption algorithm according to the encryption type; Decrypting the firmware program to be updated based on the decryption algorithm by a preset firmware verification module; In response to the firmware program to be updated being successfully decrypted, based on the firmware verification module, storing the decrypted firmware to be updated in the second space of the storage module, and setting the second space to a read-only mode; In response to the decrypted firmware to be updated being stored in the second space of the storage module, the data verification mark position is set to the first mark by the firmware verification module; In response to the data verification flag being the first flag, the firmware update start flag is set to the first flag through the firmware update status module.

4. The BMC chip firmware upgrade method according to claim 2, characterized in that: The main processor executes firmware update based on the firmware program to be updated, and in response to the firmware update being completed, sets the firmware update completion flag position to the first flag through the firmware update status module, including: Burning the firmware program to be updated into the main processor flash controller, and resetting the main processor after the burning of the main processor flash controller is completed, wherein the main processor flash controller is used to store the program that the main processor is powered on and runs; The main processor executes the firmware program to be updated based on the main processor flash controller. If the execution is successful, the firmware update completion mark position is set to the first mark through the firmware update status module.

5. The BMC chip firmware upgrade method according to claim 3, characterized in that: The method further comprises: In response to the firmware update being completed, resetting and starting the main processor, and if the main processor is successfully reset and started, clearing the firmware update start flag bit through the firmware update status module; In response to the firmware update start flag being cleared, the storage module clears the read-only mode set in the first space.

6. The BMC chip firmware upgrade method according to claim 4, characterized in that: If the coprocessor detects and determines that the firmware update completion flag in the firmware update status module is not the first flag after the preset time interval, the current firmware program is obtained from the storage module, and the main processor is controlled to write the current firmware program, including: If the coprocessor detects and determines that the firmware update completion flag in the firmware update status module is not the first flag after the preset time interval, the main processor flash controller is reset to obtain the current firmware program from the storage module; Burning the current firmware program into the main processor flash controller, and after the burning of the main processor flash controller is completed, resetting the main processor; The main processor executes the current firmware program based on the main processor flash controller.

7. The BMC chip firmware upgrade method according to claim 1, characterized in that: The method further comprises: Obtaining a target task thread processed by the main processor; In response to the main processor executing firmware update based on the firmware program to be updated, the target task thread is processed based on the coprocessor.

8. A BMC chip, characterized in that: include: A main processor, a coprocessor and a firmware update status module, wherein the main processor and the coprocessor are respectively communicatively connected with the firmware update status module; The firmware update status module is used to: set a firmware update start flag and a firmware update completion flag based on a preset firmware update status module; The main processor is used to: in response to obtaining the firmware program to be updated, set the firmware start update mark position to the first mark through the firmware update status module; perform firmware update based on the firmware program to be updated, and in response to the firmware update being completed, set the firmware update completion mark position to the first mark through the firmware update status module; The coprocessor is used to: detect the firmware update start flag in the firmware update status module; if the firmware update start flag is a first flag, then after a preset time interval, detect the firmware update completion flag in the firmware update status module; if the firmware update completion flag is a first flag, clear the firmware update completion flag; if the firmware update completion flag is not the first flag, reset the main processor.

9. A computer device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores computer instructions that can be executed by the at least one processor, and the computer instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having computer instructions stored thereon, characterized in that: The computer instructions are used to cause a computer to execute the method according to any one of claims 1 to 7.

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