Signal Processing Method, Driving Chip, Backlight Unit, and Display Device

Abstract

The present invention discloses a signal processing method, a driving chip, a backlight unit and a display device. The signal processing method includes: receiving a first analog signal and converting the first analog signal into a first digital signal; performing a compensation operation based on the first digital signal and compensation parameters to generate a second analog signal; and outputting the second analog signal to a next-level driving chip. Before the driving chip outputs a signal to a next-level driving chip, a compensation operation is performed on the output signal, which is beneficial to improving the quality of the output signal.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and in particular, to a signal processing method, a driving chip, a backlight unit, and a display device. Background Art

[0002] A Mini Light Emitting Diode (Mini-LED) backlight unit (BLU) is used in a Liquid Crystal Display (LCD) device, and can achieve local dimming, which is beneficial to improving the contrast of a display screen and reducing power consumption.

[0003] In the local dimming technology, the Mini-LED BLU is divided into multiple dimming regions, and the Mini-LEDs in each dimming region are controlled by the same driving chip, and the multiple dimming regions are respectively controlled by multiple driving chips. In the local dimming technology, usually, the multiple driving chips for respectively controlling the multiple dimming regions are connected in a single-wire series manner, and signal loss occurs during signal transmission, resulting in a gradual deterioration of signal quality during the step-by-step transmission, affecting the display effect. Summary of the Invention

[0004] The present invention provides a signal processing method, a driving chip, a backlight unit, and a display device to improve signal transmission quality.

[0005] In a first aspect of the present invention, a signal processing method is provided, including:

[0006] Receiving a first analog signal and converting the first analog signal into a first digital signal;

[0007] Performing a compensation operation based on the first digital signal and a compensation parameter to generate a second analog signal;

[0008] Outputting the second analog signal to a next-level driving chip.

[0009] In some embodiments, within one signal cycle, the duration of the amplitude of the second analog signal above the analog / digital conversion reference value is greater than the duration of the high level of the first digital signal.

[0010] In some embodiments, the compensation parameter is a time compensation parameter; the time compensation parameter is used to adjust the high-level duration of the first digital signal;

[0011] Performing a compensation operation based on the first digital signal and a compensation parameter to generate a second analog signal specifically includes:

[0012] Based on the time compensation parameter, perform a compensation operation on the high-level duration of the first digital signal to obtain a second digital signal;

[0013] Convert the second digital signal into a second analog signal.

[0014] In some embodiments, the compensation parameter is an amplitude compensation parameter; the second analog signal includes a rising stage and a steady state stage, and the amplitude compensation parameter is used to adjust the target voltage amplitude corresponding to the rising stage;

[0015] Generate a second analog signal based on the first digital signal and the compensation parameter, specifically including:

[0016] Based on the amplitude compensation parameter, adjust the target voltage amplitude corresponding to the rising stage of the second analog signal during the digital-to-analog conversion process, and convert the first digital signal into a second analog signal.

[0017] In some embodiments, before performing the compensation operation based on the first digital signal and the compensation parameter, it further includes:

[0018] Obtain the current rate information corresponding to the first digital signal; the rate information is the transmission rate of the first analog signal or the transmission rate of the first digital signal;

[0019] Confirm the compensation parameter according to the rate information.

[0020] In some embodiments, the first analog signal carries the rate information;

[0021] Obtain the rate information corresponding to the first digital signal, specifically including:

[0022] Directly extract the rate information from the first analog signal.

[0023] In some embodiments, obtain the rate information corresponding to the first digital signal, specifically including:

[0024] Calculate the transmission rate of the first analog signal to obtain the rate information; or,

[0025] Calculate the transmission rate of the first digital signal to obtain the rate information.

[0026] In some embodiments, confirm the compensation parameter according to the rate information, specifically including:

[0027] Confirm the compensation parameter corresponding to the rate information according to the rate information and compensation parameter comparison table.

[0028] In some embodiments, the rate information and compensation parameter comparison table is established based on the inherent loss of the target driver chip under the set transmission rate;

[0029] Alternatively, the rate information and compensation parameter look-up table is established based on the inherent loss of the target driving chip and the line loss between the target driving chip and the next-level driving chip at the set transmission rate.

[0030] A second aspect of the present invention provides a driving chip, comprising:

[0031] A first conversion module, configured to receive a first analog signal; and further configured to convert the first analog signal into a first digital signal;

[0032] A second conversion module, configured to perform a compensation operation based on the first digital signal and a compensation parameter to generate a second analog signal; and further configured to output the second analog signal to the next-level driving chip.

[0033] In some embodiments, the second conversion module is further configured to obtain the current rate information corresponding to the first digital signal; and further configured to confirm the compensation parameter according to the rate information.

[0034] In some embodiments, the driving chip further comprises:

[0035] A counting compensation module, configured to store a rate information and compensation parameter look-up table recording the correspondence between the rate information and the compensation parameter.

[0036] A third aspect of the present invention provides a backlight unit, comprising a plurality of driving chips connected in series; one driving chip is used to control one dimming area; wherein, at least one driving chip executes the signal processing method of any one of the above.

[0037] A fourth aspect of the present invention provides a display device, comprising the backlight unit of any one of the above.

[0038] The beneficial effects of the present invention are as follows:

[0039] The present invention provides a signal processing method, a driving chip, a backlight unit and a display device. The signal processing method comprises: receiving a first analog signal, and converting the first analog signal into a first digital signal; performing a compensation operation based on the first digital signal and a compensation parameter to generate a second analog signal; and outputting the second analog signal to the next-level driving chip. Before outputting a signal to the next-level driving chip, the driving chip performs a compensation operation on the output signal, which is beneficial to improving the quality of the output signal. Description of the Drawings

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly introduced below. Obviously, the drawings introduced below are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.

[0041] Figure 1 Schematic diagram of a driving chip and a Mini-LED connection structure in a backlight unit provided by an embodiment of the present invention;

[0042] Figure 2A Schematic diagram of a single driving chip in the related art;

[0043] Figure 2B Schematic diagram of the signal conversion process of a single driving chip in the related art;

[0044] Figure 3 One of the flowcharts of the signal processing method provided by an embodiment of the present invention;

[0045] Figure 4 Another flowchart of the signal processing method provided by an embodiment of the present invention;

[0046] Figure 5 One of the schematic diagrams of the signal conversion process of a single driving chip provided by an embodiment of the present invention;

[0047] Figure 6 Another schematic diagram of the signal conversion process of a single driving chip provided by an embodiment of the present invention;

[0048] Figure 7 Another flowchart of the signal processing method provided by an embodiment of the present invention;

[0049] Figure 8 Schematic diagram of the connection of driving chips provided by an embodiment of the present invention;

[0050] Figure 9 One of the schematic diagrams of the structure of the driving chip provided by an embodiment of the present invention;

[0051] Figure 10 Another schematic diagram of the structure of the driving chip provided by an embodiment of the present invention. Detailed implementation manners

[0052] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described below with reference to the accompanying drawings and embodiments. However, the exemplary embodiments can be implemented in various forms and should not be construed as limited to the embodiments described herein; on the contrary, these embodiments are provided to make the present invention more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, so their repeated description will be omitted. The words expressing positions and directions described in the present invention are illustrative with reference to the drawings, but can be changed according to needs, and all changes are included in the protection scope of the present invention. The drawings of the present invention are only used to illustrate the relative position relationship and do not represent the actual scale.

[0053] A Mini Light Emitting Diode (Mini-LED) BackLight Unit (BLU) is used in a Liquid Crystal Display (LCD) device, which can achieve Local Dimming, facilitating the improvement of the contrast of the display screen and the reduction of energy consumption.

[0054] In the Local Dimming technology, the Mini-LED BLU is divided into multiple dimming regions. The Mini-LEDs in each dimming region are controlled by the same driving chip, and multiple dimming regions are respectively controlled by multiple driving chips. In the Local Dimming technology, usually, multiple driving chips used to control multiple dimming regions are connected in a single-wire series manner. There is signal loss during signal transmission, resulting in a gradual deterioration of the signal quality during the step-by-step transmission, affecting the display effect.

[0055] Figure 1 Schematic diagram of the connection structure of the driving chip and Mini-LED in a backlight unit provided by an embodiment of the present invention; Figure 2A Schematic diagram of the structure of a single driving chip in the related art; Figure 2B Schematic diagram of the signal conversion process of a single driving chip in the related art.

[0056] For example, as Figure 1 shown, in the Local Dimming technology, the backlight unit includes multiple serially connected driving chips, such as the first-stage driving chip IC1, the second-stage driving chip IC2, and the third driving signal IC3, etc. The output of the upper-level driving chip serves as the input of the lower-level driving chip. Each driving chip is connected to at least one light-emitting diode LED. Each driving chip processes the driving signal input therein, extracts effective information, thereby controlling the lighting or turning off of the connected light-emitting diode LED.

[0057] In the related art, as Figure 2AAs shown in the figure, a single driving chip generally includes an input pin 1, an input module 2, a digital logic module 3, an output module 4, and an output pin 5. The input pin 1 is used to connect to a controller or to the output pin 5 of the previous-level driving chip for signal input. For example, the input pin of the first-level driving chip IC1 is usually connected to the controller. The controller, as a signal source device, is used to provide an initial driving signal. The input pin of the second-level driving chip IC2 is connected to the output pin 5 of the first driving chip IC1, and the input pin of the third-level driving chip IC3 is connected to the output pin 5 of the second-level driving chip IC2. When the backlight unit includes more partitions and driving chips, the connection method of the driving chips can be deduced by analogy and will not be elaborated here. The input module 2 is used to perform preliminary processing on the input signal. For example, the input signal is usually an analog signal, and the input module can be used to convert the analog signal into a digital signal to facilitate the transmission and recognition of the signal inside the driving chip. The digital logic module 3 can further process the converted digital signal, extract effective information from the driving signal, and thus perform corresponding operations, such as controlling the light-emitting diode LED to turn on or off, controlling the brightness of the light-emitting diode LED to turn on, etc. The output module 4 can be used to convert the digital signal into an analog signal again and output it as an output signal through the output pin to the next-level driving chip.

[0058] In the related art, as Figure 2B shown, in the process of the driving signal being transmitted inside a single driving chip, it is necessary to first convert the input signal into a digital signal, where the input signal is a first analog signal. In the process of converting the first analog signal into a digital signal, it is necessary to refer to the reference value of the analog-to-digital conversion. For example, when the amplitude of the first analog signal is greater than the reference value, the digital signal is at a high level, and when the amplitude of the first analog signal is less than the reference value, the digital signal is at a low level.

[0059] For example, as Figure 2BAs shown, in one rising-falling cycle of the first analog signal, the first analog signal first rises from the minimum amplitude to the steady-state amplitude H, maintains the steady-state amplitude H for the first time length t1, and then falls again to the minimum amplitude. The reference value for analog-to-digital conversion can be set to 0.8H. Since the first analog signal is a continuously changing signal and the digital signal is a discrete signal, when the input module detects that the amplitude of the first analog signal rises to be greater than or equal to 0.8H, the digital signal jumps from a low level to a high level; when the input module detects that the amplitude of the first analog signal falls to be less than or equal to 0.8H, the digital signal jumps from a high level to a low level. For example, the voltage range of the first analog signal can be 0 to 3.3V, the steady-state amplitude H of the first analog signal is 3.3V, and the minimum amplitude is 0. The reference value for analog-to-digital conversion can be set to 0.8H = 0.8×3.3V = 2.64V. When the amplitude of the first analog signal rises to be greater than or equal to 2.64V during the rising stage, the digital signal jumps from a low level to a high level; when the amplitude of the first analog signal falls to be less than or equal to 2.64V during the falling stage, the digital signal jumps from a high level to a low level. Within the second time length t2 when the amplitude of the first analog signal is greater than or equal to 0.8H, the digital signal remains at a high level state, that is, the duration of the high level of the digital signal is the second time length t2.

[0060] As Figure 2BAs shown, the output signal output by the current-stage driving chip to the next-stage driving chip is a second analog signal. Before the current-stage driving chip outputs a signal to the next-stage driving chip, it needs to convert the digital signal into a second analog signal first. Specifically, when the output module detects the moment when the digital signal jumps from a low level to a high level, it starts to output voltage to the next-stage driving chip, and the amplitude of the second analog signal gradually rises from 0 to the steady-state amplitude H; when the output module detects the moment when the digital signal jumps from a high level to a low level, it stops outputting voltage to the next-stage driving chip, and the amplitude of the second analog signal gradually decreases from the steady-state amplitude H to 0. Since the second analog signal is a continuous signal, the rise and fall of the signal amplitude are both continuous processes and cannot be completed instantaneously. Therefore, it takes a rise time of t11 for the amplitude of the second analog signal to increase from 0 to 0.8H, and it takes a fall time of t22 for the amplitude of the second analog signal to decrease from 0.8H to 0. For the next-stage driving chip, after receiving the second analog signal, it converts the second analog signal into a digital signal. The duration of the high level of this digital signal is the duration when the amplitude of the second analog signal is greater than or equal to 0.8H, that is, the third time length t3, and t3 = t2 - t11 + t12. Since usually, the rising process of the amplitude of the output voltage of the output module rising from 0 to the steady-state amplitude H is slower than the process of the amplitude of the output voltage decreasing from the steady-state amplitude H to 0, the rise time t11 required for the amplitude of the second analog signal to rise from 0 to 0.8H is greater than the fall time t12 for the amplitude of the second analog signal to decrease from the steady-state amplitude H to 0.8H, that is, t11 > t12. Thus, the third time length t3 = t2 - t11 + t12 is less than the second time length t2. That is to say, the duration of the high level of the digital signal obtained by the next-stage driving chip based on the second analog signal conversion is less than the duration of the high level of the digital signal obtained by the current-stage driving chip based on the first analog signal conversion. As a result, among multiple series-connected driving chips, for the later driving chips, the duration of the high level of the digital signal converted from the input signal is shorter and the signal quality is worse. As the number of series-connected driving chips increases, the later driving chips may not be able to recognize the correct driving signal at all, severely limiting the number of series-connected driving chips and the number of partitions of the backlight unit.

[0061] In view of this, the first aspect of the embodiments of the present invention provides a signal processing method to solve the above problems.

[0062] Figure 3 It is one of the flowcharts of the signal processing method provided by the embodiments of the present invention.

[0063] The signal processing method provided by the embodiment of the present invention can be applied to a driving chip, specifically to any one or more of a plurality of serially connected driving chips, to solve the problem that the signal quality of a plurality of serially connected driving chips deteriorates step by step. As Figure 3 shown, the signal processing method provided by the embodiment of the present invention includes the following steps:

[0064] S301: Receive a first analog signal and convert the first analog signal into a first digital signal.

[0065] In this step, the current-level driving chip can receive the first analog signal from the controller or from the previous-level driving chip. For example, the current-level driving chip can be the first-level driving chip, and the first-level driving chip can be directly connected to the controller and receive the first analog signal output by the controller. Again, for example, the current-level driving chip can be the Nth-level driving chip, where N is an integer greater than 1, and the Nth-level driving chip can receive the first analog signal output by the previous-level driving chip. No limitation is made here.

[0066] When the current-level driving chip converts the first analog signal into a first digital signal, it can perform the conversion with reference to a preset analog-to-digital conversion reference value. For example, when the amplitude of the first analog signal is greater than the reference value, the corresponding first digital signal is at a high level, and when the amplitude of the first analog signal is less than the reference value, the corresponding first digital signal is at a low level. In specific implementation, reference can be made to the foregoing related content, and details are not described here.

[0067] S302: Perform a compensation operation based on the first digital signal and a compensation parameter to generate a second analog signal.

[0068] In this step, by performing a compensation operation based on the first digital signal and a compensation parameter, a second analog signal is generated, so that within one rising-falling cycle, the time length during which the voltage amplitude of the second analog signal is greater than the analog-to-digital conversion reference value can be extended, and the quality of the second analog signal is improved.

[0069] Specifically, by extending the time length during which the voltage amplitude of the second analog signal is greater than the analog-to-digital conversion reference value within one rising-falling cycle, within one signal cycle, the duration during which the amplitude of the second analog signal is above the analog-to-digital conversion reference value can be made greater than the high-level duration of the first digital signal. Finally, the duration during which the amplitude of the second analog signal is above the analog-to-digital conversion reference value is made equal to or close to the duration during which the amplitude of the first analog signal is above the analog-to-digital conversion reference value, that is to say, the second time length t2 is made equal to or close to the third time length t3, so as to ensure the signal quality during transmission between serially connected chips.

[0070] In specific implementation, a compensation operation is performed based on the first digital signal and the compensation signal to generate a second analog signal, which can be carried out in at least the following two feasible ways:

[0071] Method 1

[0072] In this embodiment, the compensation parameter can be a time compensation parameter. The time compensation parameter is used to adjust the high-level duration of the first digital signal. Figure 4 This is the second flowchart of the signal processing method provided by the embodiment of the present invention. As Figure 4 shown, a compensation operation is performed based on the first digital signal and the compensation parameter to generate a second analog signal, which specifically includes the following steps:

[0073] S401: Based on the time compensation parameter, perform a compensation operation on the high-level duration of the first digital signal to obtain a second digital signal;

[0074] S402: Convert the second digital signal into a second analog signal.

[0075] Figure 5 This is one of the schematic diagrams of the signal conversion process of a single driving chip provided by the embodiment of the present invention. Specifically, as Figure 5 shown, the current-level driving chip first converts the first analog signal into a first digital signal, and then, based on the first digital signal, compensates the high-level duration of the first digital signal through the time compensation parameter to obtain a second digital signal. For example, as Figure 5 shown, the high-level duration of the first digital signal is the second time length t2. After compensating the high-level duration of the first digital signal based on the time compensation parameter t4, the high-level duration of the second digital signal obtained is the fourth time length t5, where t5 = t2 + t4. In the related art, within one rising-falling cycle, due to the inherent time loss during the transmission of the driving signal inside the driving chip, the time length during which the voltage amplitude of the second analog signal is greater than or equal to the reference value is usually shorter than the time length during which the voltage amplitude of the first analog signal is greater than or equal to the reference value. Therefore, in specific implementation, the value of the time compensation parameter t4 is usually positive, so that t5 > t2. Furthermore, when obtaining the second analog signal based on the second digital signal, within one rising-falling cycle, the time length during which the voltage amplitude of the second analog signal is greater than or equal to the reference value can be made equal to or close to the second time length t2, that is, the third time length t3 is made equal to or close to the second time length t2, thereby ensuring the signal quality of the input signal received by the next-level driving chip.

[0076] Method 2

[0077] In this embodiment, the compensation parameter may be an amplitude compensation parameter. Since the amplitude of the analog signal changes continuously, in a rise-fall cycle, the second analog signal includes a rising phase in which the amplitude gradually rises, a steady-state phase in which the amplitude remains stable, and a falling phase in which the amplitude gradually decreases, wherein the amplitude compensation parameter is used to increase the target voltage amplitude corresponding to the rising phase. Performing a compensation operation based on the first digital signal and the compensation parameter to generate the second analog signal specifically includes the following steps:

[0078] Based on the amplitude compensation parameter, the target voltage amplitude corresponding to the second analog signal in the rising phase is increased during the digital-to-analog conversion process to convert the first digital signal into the second analog signal.

[0079] Figure 6 The second schematic diagram of the signal conversion process of a single driver chip provided by an embodiment of the present invention. Specifically, Figure 6 As shown, the driver chip first converts the first analog signal into a first digital signal, and then, based on the first digital signal and the amplitude compensation parameter, increases the target voltage amplitude corresponding to the second analog signal in the rising phase during the digital-to-analog conversion process to convert the first digital signal into a second analog signal. Figure 6 As shown, in a rising-falling cycle, the voltage output by the current driver chip in the steady-state stage is a steady-state amplitude H, the reference value of the analog / digital conversion is 0.8H, and the amplitude compensation parameter is a. In specific implementation, the target voltage amplitude H' corresponding to the second analog signal in the rising stage can be adjusted upward relative to the steady-state amplitude H based on the amplitude compensation parameter a, so that H'=H+a. Since the driver chip cannot output the target voltage instantly, the voltage needs a certain amount of time to gradually increase to the target voltage, which is reflected in the waveform of the second analog signal in the rising stage. The larger the target voltage output by the driver chip, the faster the voltage changes, and the larger the corresponding driving signal climbing slope in the rising stage, which means that the rising time t11 for the amplitude of the driving signal to rise to the reference value of the analog / digital conversion is shorter. According to the third time length t3=t2-t11+t12, it can be known that the longer the third time length t3 is, the longer the time length of the voltage amplitude in the second analog signal is greater than or equal to the reference value. Compared with the related art, the embodiment of the present invention can increase the target voltage amplitude corresponding to the second analog signal in the rising stage through the amplitude compensation parameter, so that the target voltage amplitude is greater than the steady-state amplitude, thereby shortening the time for the amplitude of the second analog signal to reach the reference value of the analog / digital conversion, making the third time length t3 equal to or close to the second time length t2, thereby ensuring the signal quality of the input signal received by the next-level driver chip.

[0080] S303: Output the second analog signal to the next-stage driver chip.

[0081] In this step, the driving chip outputs the second analog signal to the next-level driving chip connected thereto. Since after the foregoing compensation operation, within one rising-falling cycle, the time length during which the voltage amplitude in the second analog signal is greater than the analog-to-digital conversion reference value is the same as or close to that of the second analog signal, the signal quality of the input signal received by the next-level driving chip can be ensured.

[0082] Figure 7 It is the third flowchart of the signal processing method provided by the embodiment of the present invention.

[0083] In some embodiments, as Figure 7 shown, before performing the compensation operation based on the first digital signal and the compensation parameter, the following steps are further included:

[0084] S701: Obtain the current rate information corresponding to the first digital signal;

[0085] S702: Confirm the compensation parameter according to the rate information.

[0086] In the related art, the maximum number of driving chips that the backlight unit can be connected in series is also affected by the signal transmission rate. Specifically, as Figure 2B shown, for a digital signal, the greater the rate of the digital signal, it means the faster the conversion frequency of the high and low levels, and the shorter the duration of the high level, that is, the second time length t2. Then, when converting the digital signal into the second analog signal, since the time loss caused by the rising time t11 of the second analog signal accounts for a larger proportion in the second time length t2, the proportion of the decrease in the third time length t3 compared to the second time length t2 increases, and the speed of deterioration of the driving signal quality accelerates, and finally the number of driving chips that the backlight unit can be connected in series decreases.

[0087] In this embodiment, before performing the compensation operation based on the first digital signal and the compensation parameter, the compensation parameter is first confirmed according to the current rate information corresponding to the first digital signal. Among them, the rate information can specifically be the transmission rate of the first analog signal or the transmission rate of the first digital signal. It should be noted that since the first digital signal is converted from the first analog signal, the rate information represented by the transmission rate of the first analog signal and the rate information represented by the transmission rate of the first digital signal are substantially the same.

[0088] Different compensation parameters can be set for different rate information. The corresponding relationship between the compensation parameter and the rate information satisfies that, under the set transmission rate (which can be the transmission rate of the first analog signal or the transmission rate of the first digital signal), after the compensation operation is performed using the compensation parameter corresponding to the transmission rate, the second time length t2 in the input signal received by the next-level driver chip can be made the same or similar to the second time length t2 in the input signal received by the current-level driver chip. Thus, for signals with different transmission rates, the second time length t2 in the input signal received by the next-level driver chip can be compensated accordingly, reducing the difference between the signal received by the current-level driver chip and the signal received by the next-level driver chip, and ensuring the quality of transmission of signals with different transmission rates between multiple driver chips connected in series.

[0089] In specific implementation, the current rate information corresponding to the first digital signal can be obtained in at least the following two ways:

[0090] Method 1

[0091] The rate information may be carried in the first analog signal, wherein the rate information carried in the first analog signal may be the transmission rate of the first analog signal, or the rate information of the first digital signal converted from the first analog signal. Specifically, when the controller outputs a driving signal, the driving signal input by the controller to the first-level driving chip carries the rate information, so that in the process of the driving signal being transmitted step by step in the driving chips at each level, the driving chips at each level can receive and identify the rate information. In a specific implementation, the driving chip can directly read the rate information from the first analog signal, and the process of confirming the rate information is relatively simple.

[0092] Method 2

[0093] The first analog signal may not carry rate information. The process of the driver chip acquiring the rate information corresponding to the first digital signal specifically includes: calculating the transmission rate of the first analog signal to obtain the rate information; or calculating the transmission rate of the first digital signal to obtain the rate information.

[0094] Specifically, for example, the signal input module may have a transmission rate calculation function, so that the transmission rate of the first analog signal may be calculated by the signal input module, thereby reducing the amount of information carried in the driving signal sent by the controller and improving transmission efficiency.

[0095] For example, the digital logic module may have a transmission rate calculation function, so that the transmission rate of the first digital signal may be calculated by the digital logic module, thereby reducing the amount of information carried in the driving signal sent by the controller and improving transmission efficiency.

[0096] For example, a functional module specifically used for calculating the signal transmission rate can also be set in the driving chip, which is not limited herein.

[0097] In some embodiments, in the step of confirming the compensation parameter according to the rate information, the compensation parameter corresponding to the rate information can be confirmed according to a pre-established rate information and compensation parameter comparison table.

[0098] For example, the rate information and compensation parameter comparison table can be stored in the driving chip, so that after the driving chip obtains the rate information, it can directly call the rate information and compensation parameter comparison table, and confirm the corresponding compensation parameter according to the rate information and compensation parameter comparison table. Specifically, the rate information and compensation parameter comparison table can be stored in the digital logic module. In some embodiments, the driving chip can also include a counting compensation module, and the rate information and compensation parameter comparison table can be stored in the counting compensation module, thereby improving data stability and reducing the working pressure of the digital logic module. The rate information and compensation parameter comparison table can also be stored in other modules, which is not limited herein.

[0099] Specifically, the rate information and compensation parameter comparison table of the target chip can be constructed by at least the following two methods, where the target chip is the chip for which the rate information and compensation parameter comparison table is to be constructed:

[0100] Method 1

[0101] Based on the inherent loss of the target driving chip at the set transmission rate, determine and record the compensation parameter corresponding to the transmission rate, and form a rate information and compensation parameter comparison table.

[0102] Among them, the set transmission rate can be the transmission rate of the first analog signal that can be set, that is, the transmission rate of the input signal received by the target driving chip. The set transmission rate can also be the transmission rate of the first digital signal converted from the first analog signal, which is not limited herein. Specifically, to refine the correspondence between the transmission rate and the compensation parameter, the compensation parameters corresponding to multiple different transmission rates can be measured and recorded respectively.

[0103] The inherent loss of the target driving chip, such as Figure 2B As shown, specifically, it refers to the difference between the second time length t2 and the third time length t3 when the target driving chip directly converts the digital signal into the second analog signal without performing a compensation operation. This fixed loss is mainly caused by the fact that the rise time t11 and the fall time t12 cannot be offset. In this embodiment, only the inherent loss of the target driving chip can be considered to reduce the construction difficulty of the rate information and compensation parameter comparison table.

[0104] In some embodiments, when the compensation parameter is the duration compensation parameter, the inherent loss of the target driving chip at the set transmission rate can be directly determined as the duration compensation parameter corresponding to this transmission rate.

[0105] In some embodiments, when the compensation parameter is the duration compensation parameter or the amplitude compensation parameter, the compensation parameter corresponding to the set transmission rate can also be determined through the following process: at the set transmission rate, adjust the magnitude of the compensation parameter. For different magnitudes of the compensation parameter, compare the length of the third time length t3 corresponding to the second analog signal and the length of the second time length t2 corresponding to the first analog signal. When the length of the third time length t3 corresponding to the second analog signal meets the preset requirement with the length of the second time length t2 corresponding to the first analog signal, record the compensation parameter at this time as the compensation parameter corresponding to this set transmission rate. For example, when the length of the third time length t3 corresponding to the second analog signal is the same as the length of the second time length t2 corresponding to the first analog signal, or when the difference between the length of the third time length t3 corresponding to the second analog signal and the length of the second time length t2 corresponding to the first analog signal is less than the set value, record the compensation parameter at this time as the compensation parameter corresponding to the target chip at this transmission rate.

[0106] Method 2

[0107] Based on the inherent loss of the target driving chip at the set transmission rate and the line loss between the target driving chip and the next-level driving chip, determine and record the compensation parameter corresponding to this transmission rate.

[0108] Figure 8 This is a schematic diagram of the connection of driving chips provided by the embodiments of the present invention.

[0109] As Figure 8 shown, during the transmission of the driving signal between the series-connected driving chips, in addition to the inherent loss during the transmission inside the driving chip, there may also be losses on the connection line between the upper-level driving chip and the lower-level driving chip. For example, during the transmission of the output signal of the upper-level driving chip on the connection line, due to reasons such as the voltage drop generated by the resistance of the connection line, the line loss may cause the time length of the voltage amplitude in the input signal of the lower-level driving chip being greater than or equal to the analog / digital conversion reference value to be further shortened. Therefore, when determining the compensation parameter corresponding to the set transmission rate, the inherent loss of the target driving chip and the line loss between the target driving chip and the next-level driving chip can be considered simultaneously to further ensure the signal quality received by the next-level driving chip.

[0110] In specific implementation, the compensation parameter corresponding to the set transmission rate can also be determined through the following process: at the set transmission rate, adjust the magnitude of the compensation parameter. For different magnitudes of the compensation parameter, compare the time length during which the voltage amplitude in the input signal of the next-level driver chip of the target driver chip is greater than or equal to the analog-to-digital conversion reference value, and the length of the second duration t2 corresponding to the first analog signal received by the target driver chip. When the preset requirements are met, record the compensation parameter at this time as the compensation parameter corresponding to the set transmission rate. For example, when the time length during which the voltage amplitude in the input signal of the next-level driver chip of the target driver chip is greater than or equal to the analog-to-digital conversion reference value is the same as the length of the second duration t2 corresponding to the first analog signal received by the target driver chip, or when the difference between the time length during which the voltage amplitude in the input signal of the next-level driver chip of the target driver chip is greater than or equal to the analog-to-digital conversion reference value and the length of the second time length t2 corresponding to the first analog signal received by the target driver chip is less than a specific value, record the compensation parameter at this time as the compensation parameter corresponding to the set transmission rate, thereby further ensuring the quality of the driving signal received by the next-level driver chip of the target driver chip.

[0111] Figure 9 One of the structural schematic diagrams of the driver chip provided by the embodiment of the present invention.

[0112] In the second aspect of the embodiment of the present invention, a driver chip is further provided. As Figure 9 shown, the driver chip includes a first conversion module 11 and a second conversion module 12.

[0113] The first conversion module 11 is used to receive the first analog signal. The first conversion module 11 is further used to convert the first analog signal into a first digital signal. In specific implementation, the first conversion module 11 may include an input module 11, which is not limited herein.

[0114] The second conversion module 12 is used to perform a compensation operation based on the first digital signal and the compensation parameter to generate a second analog signal. The second conversion module 12 is further used to output the second analog signal to the next-level driver chip. In specific implementation, the second conversion module 12 may include a digital logic module 3 and an output module 4, and the digital logic module 3 and the output module 4 cooperate to complete the compensation operation and the digital-to-analog conversion process.

[0115] In some embodiments, the compensation parameter is a time compensation parameter. The time compensation parameter is used to adjust the high-level duration of the first digital signal. In specific implementation, the digital logic module 3 is specifically used to perform a compensation operation on the high-level duration of the first digital signal based on the time compensation parameter to obtain a second digital signal. The output module 4 is specifically used to convert the second digital signal into a second analog signal.

[0116] In some embodiments, the compensation parameter is an amplitude compensation parameter. The second analog signal includes a rising stage and a steady state stage, and the amplitude compensation parameter is used to adjust the target voltage amplitude corresponding to the rising stage. The output module 4 is specifically configured to adjust the target voltage amplitude corresponding to the rising stage of the second analog signal during the digital-to-analog conversion process based on the amplitude compensation parameter, and convert the first digital signal into the second analog signal.

[0117] In some embodiments, the second conversion module 12 is further configured to obtain the current rate information corresponding to the first digital signal before performing the compensation operation based on the first digital signal and the compensation parameter, and confirm the compensation parameter according to the rate information.

[0118] The rate information may be the transmission rate of the first analog signal or the transmission rate of the first digital signal, which is not limited herein. In some embodiments, the rate information may be directly carried in the first analog signal. After the rate information is read by the input module, the rate information and the converted first digital signal may be sent to the second conversion module 12 together; or the rate information may be read from the first digital signal by the digital logic module 3, which is not limited herein. In some embodiments, the rate information is not directly carried in the first analog signal, and the signal input module may have a transmission rate calculation function, so that the transmission rate of the first analog signal can be calculated by the signal input module and sent to the second conversion module 12; or the digital logic module may have a transmission rate calculation function, so that the transmission rate of the first digital signal can be calculated by the digital logic module to obtain the rate information, which can reduce the amount of information carried in the driving signal sent by the controller and improve the transmission efficiency.

[0119] Figure 10 This is the second structural schematic diagram of the driving chip provided by the embodiments of the present invention.

[0120] When the second conversion module 12 confirms the compensation parameter according to the rate information, it may specifically confirm the compensation parameter corresponding to the rate information according to the rate information and compensation parameter look-up table. In some embodiments, the rate information and compensation parameter look-up table may be stored in the digital logic module 3. After obtaining the rate information, the digital logic module 3 may call the rate information and compensation parameter look-up table to confirm the compensation parameter corresponding to the rate information and use the compensation parameter for subsequent compensation operations.

[0121] In some embodiments, such as Figure 10As shown, the driving chip further includes a counting compensation module 6. The counting compensation module 6 is connected to the second conversion module 12. Specifically, the counting compensation module 6 can be connected to the digital logic module 3. A rate information and compensation parameter comparison table can be stored in the counting compensation module 6. After obtaining the rate information, the digital logic module 3 can obtain the compensation parameter corresponding to the rate information from the counting compensation module 6 and use this compensation parameter for subsequent compensation operations. No limitation is made here.

[0122] When the driving chip provided by the embodiment of the present invention is specifically applied, it can also refer to the relevant content in the signal processing method of the foregoing driving chip, which will not be elaborated here. Since the driving chip provided by the embodiment of the present invention performs a compensation operation on the output signal before outputting the signal to the next-level driving chip, it is beneficial to improve the quality of the output signal, thereby being beneficial to improving the quality of signal transmission step by step between multiple serially connected driving chips in the scenario of multiple driving chips connected in series, and further increasing the number of serially connected chips. When applied to the backlight unit, the number of partitions can be increased.

[0123] In the third aspect of the embodiment of the present invention, a backlight unit is further provided. As Figure 1 shown, the backlight unit includes multiple driving chips connected in series with each other. One driving chip is used to control one dimming area. At least one light-emitting unit is included in one dimming area. In specific implementation, the light-emitting unit can be a Mini LED or other light-emitting devices, and no limitation is made here. Among them, at least one driving chip can execute the signal processing method provided in any of the foregoing embodiments. The backlight unit provided by the embodiment of the present invention has the same or similar technical effects as the signal processing method provided in any of the foregoing embodiments when specifically implemented, which will not be elaborated here.

[0124] In the fourth aspect of the embodiment of the present invention, a display device is provided. The display device includes the backlight unit provided in any of the foregoing embodiments.

[0125] Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the present invention.

[0126] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these modifications and variations.

Claims

1. A signal processing method, characterized in that: include: receiving a first analog signal, and converting the first analog signal into a first digital signal; Performing a compensation operation based on the first digital signal and a compensation parameter to generate a second analog signal; wherein the compensation parameter is a time compensation parameter, and the time compensation parameter is used to adjust the high level duration of the first digital signal; or, the compensation parameter is an amplitude compensation parameter, and the amplitude compensation parameter is used to adjust the target voltage amplitude corresponding to the second analog signal in the rising stage; The second analog signal is output to the next-stage driver chip.

2. The method according to claim 1, characterized in that In a signal cycle, the duration that the amplitude of the second analog signal is above the analog / digital conversion reference value is greater than the duration of the high level of the first digital signal.

3. The method according to claim 1 or 2, characterized in that The performing a compensation operation based on the first digital signal and the compensation parameter to generate a second analog signal specifically includes: Based on the time compensation parameter, a compensation operation is performed on the high level duration of the first digital signal to obtain a second digital signal; The second digital signal is converted into the second analog signal.

4. The method according to claim 1 or 2, characterized in that: The second analog signal includes the rising phase and the steady-state phase; The performing a compensation operation based on the first digital signal and the compensation parameter to generate a second analog signal specifically includes: Based on the amplitude compensation parameter, the target voltage amplitude corresponding to the second analog signal in the rising phase is adjusted during the digital-to-analog conversion process, and the first digital signal is converted into the second analog signal.

5. The method according to claim 1 or 2, characterized in that: Before performing a compensation operation based on the first digital signal and the compensation parameter, the method further includes: Acquire current rate information corresponding to the first digital signal; the rate information is a transmission rate of the first analog signal or a transmission rate of the first digital signal; The compensation parameter is determined according to the rate information.

6. The method according to claim 5, characterized in that The first analog signal carries the rate information; Acquiring rate information corresponding to the first digital signal specifically includes: The rate information is extracted directly from the first analog signal.

7. The method according to claim 5, characterized in that Acquiring rate information corresponding to the first digital signal specifically includes: calculating the transmission rate of the first analog signal to obtain the rate information; or, The transmission rate of the first digital signal is calculated to obtain the rate information.

8. The method according to claim 5, characterized in that The confirming the compensation parameter according to the rate information specifically includes: According to the rate information and compensation parameter comparison table, the compensation parameter corresponding to the rate information is confirmed.

9. The method according to claim 8, characterized in that The rate information and compensation parameter comparison table is established according to the inherent loss of the target driver chip at the set transmission rate; Alternatively, the rate information and compensation parameter comparison table is established according to the inherent loss of the target driver chip at the set transmission rate and the line loss between the target driver chip and the next-level driver chip.

10. A driver chip, characterized in that: include: A first conversion module, configured to receive a first analog signal; Also used for converting the first analog signal into a first digital signal; A second conversion module is used to perform compensation operations based on the first digital signal and compensation parameters to generate a second analog signal; it is also used to output the second analog signal to the next-level driver chip; wherein the compensation parameter is a time compensation parameter, and the time compensation parameter is used to adjust the high-level duration of the first digital signal; or, the compensation parameter is an amplitude compensation parameter, and the amplitude compensation parameter is used to adjust the target voltage amplitude corresponding to the second analog signal in the rising stage.

11. The driver chip according to claim 10, characterized in that: The second conversion module is further used to obtain current rate information corresponding to the first digital signal; and is further used to confirm the compensation parameter according to the rate information.

12. The driver chip according to claim 11, characterized in that: Also includes: The counting compensation module is used to store a rate information and compensation parameter comparison table recording the comparison relationship between the rate information and the compensation parameter.

13. A backlight unit, characterized in that: It comprises a plurality of driver chips connected in series; one of the driver chips is used to control a dimming area; wherein at least one of the driver chips executes the signal processing method according to any one of claims 1 to 9.

14. A display device, characterized in that: Comprising the backlight unit as claimed in claim 13.

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