Semiconductor device and method for manufacturing EMI shielding using intense pulsed light irradiation

Abstract

Semiconductor devices and methods of making EMI shields using intense pulsed light irradiation are provided. A semiconductor device has a substrate and an electrical component disposed on the substrate. An encapsulant is deposited on the electrical component. A shielding layer is formed over the encapsulant. The shielding layer includes a plurality of graphene coated metal balls in the matrix. The sintered shield layer is irradiated with intense pulsed light (IPL).

Description

Technical Field

[0001] The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices and methods for fabricating electromagnetic interference (EMI) shielding layers using intense pulsed light irradiation. Background Art

[0002] Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide range of functions such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, power conversion, optoelectronic devices, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, networking, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automobiles, industrial controllers, and office equipment.

[0003] Semiconductor devices are often susceptible to electromagnetic interference (EMI), radio frequency interference (RFI), harmonic distortion, or other inter-device interference (such as capacitive, inductive, or conductive coupling, also known as crosstalk), which may interfere with their operation. High-speed analog or digital circuits such as radio frequency (RF) filters can also generate interference.

[0004] Conductive shielding layers can be formed on semiconductor packages to reduce interference. However, the typical shielding process using a sprayed metal layer on the package has several significant disadvantages. One major problem is that a time-consuming heat treatment is required to sinter the metal particles. Therefore, there is a need for an improved shielding layer and method of making the same. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1a-1c shows a semiconductor wafer having a plurality of semiconductor dies separated by saw streets;

[0006] Figure 2a-2g A process for forming a semiconductor package having a graphene-based shielding layer sintered by intense pulsed light irradiation is shown;

[0007] Figure 3a-3d Additional embodiments are shown; and

[0008] Figure 4a and 4b Integration of a semiconductor package into an electronic device is shown. DETAILED DESCRIPTION

[0009] The present invention is described in one or more embodiments in the following description with reference to the accompanying drawings, wherein the same reference numerals represent the same or similar elements. Although the present invention is described according to the best mode for achieving the purpose of the present invention, it will be understood by those skilled in the art that the present invention is intended to cover substitutions, modifications and equivalents that may be included in the spirit and scope of the present invention as defined by the appended claims and their equivalents, which are supported by the following disclosure and the accompanying drawings. The features shown in the figures are not necessarily drawn to scale. The elements assigned the same reference numerals in the figures have similar functions to each other. The term "semiconductor die" used herein refers to both the singular and plural forms of the word, and therefore may refer to both a single semiconductor device and a plurality of semiconductor devices.

[0010] Semiconductor devices are typically manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, and resistors, establish the relationship between voltage and current required to perform the circuit function.

[0011] Back-end manufacturing refers to cutting or dividing the finished wafer into individual semiconductor dies and packaging the semiconductor dies for structural support, electrical interconnection, and environmental isolation. In order to divide the semiconductor dies, the wafer is scribed and broken along the non-functional areas of the wafer (called saw streets or scribe lines). The wafer is divided using a laser cutting tool or a saw blade. After division, the individual semiconductor dies are arranged on a package substrate, which includes pins or contact pads for interconnection with other system components. The contact pads formed on the semiconductor die are then connected to the contact pads within the semiconductor package. The electrical connection can be made by a conductive layer, a bump, a stud bump, a conductive glue, or a wire bond. Encapsulant or other molding materials are deposited on the semiconductor package to provide physical support and electrical insulation. The completed semiconductor package is then inserted into the electrical system, and the functions of the semiconductor device can be used for other system components.

[0012] Figure 1aA semiconductor wafer 100 is shown having a base substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk materials for structural support. A plurality of semiconductor dies or electrical components 104 are formed on the wafer 100, separated by a passive inter-die wafer region or saw street 106. The saw street 106 provides a cutting area to divide the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm). Alternatively, the wafer 100 can be a mold surface, an organic or inorganic substrate, or a target substrate suitable for graphene transfer.

[0013] Figure 1b A cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back or inactive surface 108 and an active surface 110, the active surface 110 containing analog or digital circuits, which are implemented as active devices, passive devices, conductive layers and dielectric layers formed on or within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes and other circuit elements formed within the active surface 110 to implement analog or digital circuits, such as digital signal processors (DSPs), application specific integrated circuits (ASICs), memories, power devices, or other signal processing circuits. The semiconductor die 104 may also include IPDs for RF signal processing, such as inductors, capacitors, and resistors.

[0014] Conductive layer 112 is formed on active surface 110 using physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, electroless plating process or other suitable metal deposition process. Conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag) or other suitable conductive materials. Conductive layer 112 operates as a contact pad electrically connected to the circuit on active surface 110.

[0015] exist Figure 1c In the embodiment of the present invention, semiconductor wafer 100 is singulated through saw streets 106 using a saw blade or laser cutting tool 118 into individual semiconductor die 104. Individual semiconductor die 104 may be inspected and electrically tested after singulation to identify known good dies (KGDs) or known good units (KGUs).

[0016] Figure 2a-2g A process of forming a semiconductor package having a graphene-based shielding layer sintered by intense pulsed light (IPL) irradiation is shown. Figure 2aA cross-sectional view of a multilayer interconnect substrate 120 including conductive layers 122 and insulating layers 124 is shown. Although only a single substrate 120 suitable for forming a single semiconductor package is shown, hundreds or thousands of units that are part of a single substrate 120 are typically manufactured and processed using the same steps described herein that are performed together before being singulated from one another. A separate substrate 120 may also be used for each unit being manufactured, with the substrate being separated from one another. Figure 2a The steps shown are previously segmented and multiple individual substrates are placed on a common carrier for processing.

[0017] Conductive layer 122 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductive layer may be formed using PVD, CVD, electroplating, electroless plating, or another suitable metal deposition process. Conductive layer 122 provides horizontal electrical interconnects across substrate 120 and vertical electrical interconnects between the top and bottom surfaces of substrate 120. Portions of conductive layer 122 may be electrically shared or electrically isolated, depending on the design and function of semiconductor die 104 and other electrical components.

[0018] The insulating layer 124 includes one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials with similar insulating and structural properties. The insulating layer can be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer 124 provides isolation between the conductive layers 122. Any number of conductive layers 122 and insulating layers 124 can be interlaced to form the substrate 120. In other embodiments, any other suitable type of packaging substrate or lead frame is used for the substrate 120.

[0019] Electrical components 130a-130c are disposed on substrate 120 and are electrically and mechanically connected to conductive layer 122. For example, electrical component 130c may be a discrete electrical device such as a diode, a transistor, a resistor, a capacitor, and an inductor. Electrical components 130a and 130b may be or are similar to Figure 1c 1 , with bumps 114 oriented toward substrate 120. Electrical components 130a and 130b may be the same semiconductor die, or may have different functions that complement each other.

[0020] The electrical components 130 disposed on the substrate 120 may include other semiconductor dies, semiconductor packages, surface mount devices, RF components, and discrete electrical devices. Any electrical component 130 may have an integrated passive device (IPD) formed in or on the electrical component. Any number and type of electrical components may be mounted on the top or bottom surface of the substrate 120.

[0021] Electrical components 130a-130c are positioned on substrate 120 using a pick and place machine or operation. Electrical components 130a-130c are in contact with conductive layer 122 of substrate 120. Terminals 132 of electrical component 130c are electrically and mechanically connected to conductive layer 122 using solder or conductive glue 133. Electrical components 130a and 130b are electrically and mechanically connected to conductive layer 122 via reflow bumps 114.

[0022] exist Figure 2b In the process, an encapsulant or molding compound 140 is deposited on and around the electrical components 130a-130c and the substrate 120 using slurry printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. The encapsulant 140 can be a liquid or particulate polymer composite material, such as an epoxy resin, epoxy acrylate, or another suitable polymer, with or without a suitable filler. The encapsulant 140 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants. The top surface of one or more components 130 can be exposed from the encapsulant 140 to allow subsequent electrical, mechanical, or thermal connection after the encapsulant is deposited by using film-assisted molding or by back grinding.

[0023] exist Figure 2c 1, bumps 142 are formed on the bottom surface of substrate 120, opposite encapsulant 140. Bumps 142 are formed as described above for bumps 114 on semiconductor die 104. The panel of substrate 120 and encapsulant 140 is flipped over to form bumps 142. In embodiments where multiple cells are formed on a single substrate, the cells are segmented from one another, which exposes side surfaces 146 of each cell. Top surface 147 is a planar surface formed by a molding process or by back grinding encapsulant 140. Bumps 142 may be formed before or after segmentation. Segmentation may be performed between cells such as Figure 2c This may be done in the orientation shown, or when flipped over to form the bump 142 .

[0024] In order to solve electromagnetic interference (EMI), radio frequency interference (RFI), harmonic distortion and interference between devices, a shielding layer 150 is formed on the top surface 147 and the side surface 146 to reduce or suppress the influence of EMI, RFI and other interference between devices, such as Figure 2dShielding layer 150 is composed of metal balls with a graphene coating. The metal balls are typically silver or copper, but any other conductive material is used in other embodiments. The graphene-coated metal balls are suspended or disposed in a matrix to form a conductive ink. The conductive ink can be sprayed, sputtered, inkjet printed, or applied to semiconductor package 152 using any other suitable means, such as the means described above for forming conductive layer 122.

[0025] Figure 2e Detail of one of the graphene coated metal balls 158 of the shielding layer 150 is shown. The graphene coated metal ball 158 is formed of a core 160 and a graphene shell or coating 162 formed on and around the core. In one embodiment, the core 160 is Cu, Ag, Ni, a phase change material (PCM), or other suitable metal or similar material. In some embodiments, a mixture of some Cu cores 160 and some Ag cores 160 is used. Figure 2e Details of the graphene shell 162 formed as a mesh network around the core 160 are shown. The graphene shell 162 is an allotrope of carbon, having one or more layers of carbon atoms, each layer arranged in a two-dimensional (2D) honeycomb lattice. The graphene shell 162 can be formed by CVD, wet chemical synthesis or other suitable means. In some embodiments, a plurality of graphene coatings 162 are formed on each core 160.

[0026] For CVD, the core 160 is placed in a chamber heated to 900-1080° C. A gas mixture of CH4 / H2 / Ar is introduced into the chamber to initiate the CVD reaction. As the CVD reaction separates carbon atoms from hydrogen atoms, the carbon source decomposes in the high temperature reaction chamber, leaving a graphene shell 162 on the core 160. The release of carbon atoms on the core 160 forms a continuous sheet of graphene shell 162. Additional information related to forming the graphene coating 162 is disclosed in U.S. Patent No. 8,535,553, U.S. Patent No. 10,421,123, Korean Patent No. KR101465616, and Korean Patent No. KR101895114, which are all incorporated herein by reference.

[0027] Figure 2fFurther details of the shielding layer 150 formed by a plurality of graphene-coated metal balls 158 are shown. In one embodiment, the shielding layer 150 includes a matrix 164 and a plurality of cores 160, with the graphene coating 162 embedded in the matrix. In one embodiment, the matrix 164 is a thermosetting material, such as an epoxy resin or an adhesive with a binder and a filler, and the binder and filler contain aluminum oxide, Al, aluminum zinc oxide, or other materials with good conductive properties. The matrix 164 can be a thermal grease, such as silicon or a polymer type, such as polymethyl methacrylate (PMMA) or polyethylene terephthalate (PET). In other embodiments, the matrix 164 can be an epoxy resin, polyester, or acrylic resin. In another embodiment, the matrix 164 is a polymer or composite epoxy resin with dispersed graphene, carbon nanotubes, conductive polymers, etc. The shielding layer 150 can be applied as an ink of graphene-coated metal balls 158 floating in the matrix 164.

[0028] Each core 160 embedded in the matrix 164 is surrounded or covered by a graphene coating or shell 162. In one embodiment, the graphene shell 162 is a graphene paste or ink formed around a Cu or Ag core. In one embodiment, some cores 162 are formed of Cu and other cores are formed of Ag. The graphene coating 162 of each core 160 contacts the graphene coating of one or more adjacent cores. The cores 160 have sufficient density so that most (if not all) of the graphene coating around the core contacts at least one graphene coating around an adjacent core, and typically contacts the graphene coatings of multiple adjacent cores.

[0029] Each graphene-coated metal sphere 158 is in physical contact with an adjacent graphene-coated metal sphere within the matrix 164 to create a conductive path 178 that includes portions of the interconnected graphene shells 162 on adjacent spheres 158. The conductive paths 178 dissipate any charge, such as EMI or RFI, incident on the shielding layer 150 to ground. The dissipation of charge by many conductive paths, such as 178 in the spheres 158, reduces or suppresses the effects of EMI, RFI, and other inter-device interference.

[0030] To ensure that conductive paths 178 are established between all adjacent balls 158, package 152 is sintered, such as Figure 2g Sintering is performed using an IPL device 180. The IPL device 180 includes a xenon flash lamp 182 that emits light 184. A reflector 186 reflects the light 184 to increase the amount of light emitted downward toward the package 152. An ultraviolet filter 188 filters the light 184. A platform 189 holds the device being processed.

[0031] IPL uses intense pulses of incoherent light emitted over a range of wavelengths. In one embodiment, the IPL wavelength extends from approximately 350 nanometers to 1200 nanometers. A xenon flash lamp 182 produces a high output burst of broad spectrum light 184. The light 184 that strikes the substrate 164 with the balls 158 sinters the shield 150 to solidify the material and electrical connections between the balls. Sintering the shield 150 with IPL irradiation can be completed in only a few milliseconds, whereas conventional metal shields in the prior art require a heating process that typically takes between 30 and 90 minutes.

[0032] For the IPL irradiation process, multiple packages 152 are picked up and placed on a carrier or temporary substrate 190, which contains a sacrificial base material such as silicon, polymer, beryllium oxide, glass or other suitable low-cost rigid materials for structural support. An interface layer or double-sided tape 192 is formed or disposed on the carrier 190 as a temporary adhesive film, a thermal release layer or a UV release layer. The carrier 190 can be a circular or rectangular panel with a capacity for multiple packages at a time. Although only three units are shown, hundreds, thousands or more packages can be placed together on a common carrier 190 for sintering. The packages 152 can be on the same carrier 190 for segmentation, deposition of the shielding layer 150 and sintering. After sintering with the lamp 184, the packages 152 are picked up and placed into a larger electronic device or tape-and-reel for delivery to customers.

[0033] In some embodiments, before IPL irradiation, package 152 is placed in an oven for pretreatment. The oven temperature is set between 170°C and 280°C, and package 152 is heated between 30 seconds and 2 minutes. In one embodiment, package 152 is heated at 250°C for one minute. Oven pretreatment removes organic solvents from shielding layer 150. In some embodiments, after IPL irradiation, package 152 is placed in an oven for post-treatment. The oven temperature for post-treatment is between 90°C and 120°C, and the time length is between 5 and 10 minutes. Post-treatment in the oven stabilizes the sintered material.

[0034] Forming the package 152 by sintering through IPL irradiation increases the number of units per hour (UPH) that can be manufactured, thereby reducing manufacturing costs. In addition, the conductivity of graphene itself is ten times that of copper or silver, so the shielding layer 150 has enhanced EMI blocking capabilities compared to the prior art. The graphene coating 162 also reduces metal oxidation and ion migration.

[0035] Figure 3a-3d Additional embodiments of semiconductor packages formed with a graphene shielding layer and sintered using IPL irradiation are shown. Figure 3aA semiconductor package 200 is shown having a shielding layer 202. As described above with respect to the shielding layer 150, the shielding layer 202 is formed on the encapsulant 140, except that the shielding layer is selectively formed only on a portion of the semiconductor package 200. The shielding layer 202 is formed on the electronic device 130a, but not on the electronic devices 130b and 130c. A portion of the encapsulant 140 remains free and exposed from the shielding layer 202. The shielding layer 202 is selectively formed using a masking layer to remove a portion of the shielding layer, or is formed by inkjet printing only on a desired portion of the package 200.

[0036] Figure 3a A portion of the conductive layer 122 is shown extending laterally to the left edge of the substrate 120 and thereby electrically connected to the shielding layer 202. Any of the above or below embodiments may have the same features. The electrical connection may be used to ground the shielding layer 202 and improve shielding performance.

[0037] Figure 3b An embodiment of a package 210 is shown having only a portion of a substrate 120 disposed below an encapsulant 212. The encapsulant 212 is formed only on a portion of the substrate 120 by using a mold that separates the encapsulant from the rest of the substrate, or by etching the encapsulant after deposition. The shielding layer 214 is deposited only on the encapsulant 212 and not on the portion of the substrate 120 outside the encapsulant. A mask or cover is placed on the portion of the substrate 120 outside the encapsulant 212 to block the shielding layer 214 from being formed thereon. In another embodiment, laser ablation is used to remove the shielding layer. The shielding layer 214 can also be inkjet printed on the encapsulant 214 to control where the shielding layer is and is not formed.

[0038] Electrical components external to the encapsulant 212 and shielding layer 214, such as electrical component 130c, can be placed on the substrate 120 before the encapsulant 212, after the shielding layer 214 is formed, or between the encapsulant and the shielding layer. Any number and type of components can be disposed within the encapsulant 212 and outside the encapsulant 212. The conductive layer 122 extends to the right edge of the encapsulant 212 so that the shielding layer physically and electrically contacts the conductive layer, wherein the shielding layer extends to the top surface of the substrate 120.

[0039] Figure 3c A semiconductor package 220 is shown having a Figure 3a130a. The selective shielding in the encapsulant 224 and the additional conductive pillars or walls 222 disposed in the encapsulant 224. Before depositing the encapsulant 224, the pillars 222 may be formed or disposed on the substrate 120, or openings may be formed through the encapsulant for depositing or disposing the pillars 222 therein. The conductive pillars 222 may be a plurality of pillars periodically disposed around, for example, the electrical component 130a. In another embodiment, the conductive pillars 222 extend continuously around the selected component. The conductive pillars 222 may extend in a circuitous path around the desired component, or may contact the shielding layer 226 at the end of the pillar route. The pillars 222 provide EMI shielding in combination with the shielding layer 226. The shielding layer 226 completely covers the area surrounded by the pillars 222, so that the combination provides continuous shielding around all sides and the top of the electrical component 130a. The conductive layer 122 extends below the conductive pillars 222 and directly physically contacts the conductive pillars 222 to improve the grounding of the shielding layer.

[0040] Figure 3d Semiconductor package 230 is shown having conductive posts 232 formed through encapsulant 234 in a similar manner as posts 222. As described above with respect to package 210, encapsulant 234 and shielding layer 236 are formed only on a portion of substrate 120. Electrical component 130c remains outside of encapsulant 234 and shielding layer 236. Posts 232 provide lateral EMI protection between electrical components 130a and 130b.

[0041] Figure 4a and 4b Integration of the above-described semiconductor packages and devices (eg, semiconductor package 152 ) into a larger electronic device 300 is shown. Figure 4a A partial cross-sectional view of a semiconductor package 152 mounted on a printed circuit board (PCB) or other substrate 302 as part of an electronic device 300 is shown. Bumps 142 are reflowed onto a conductive layer 304 of the PCB 302 to physically attach and electrically connect the semiconductor package 152 to the PCB. In other embodiments, heat pressing or other suitable attachment and connection methods are used. In some embodiments, an adhesive or underfill layer is used between the semiconductor package 152 and the PCB 302. The electrical components 130a-130c are electrically coupled to the conductive layer 304 through the bumps 142 and the substrate 120.

[0042] Figure 4b An electronic device 300 is shown having a chip carrier substrate or PCB 302 with a plurality of semiconductor packages disposed on a surface of PCB 302, including semiconductor package 152. Electronic device 300 may have one type of semiconductor package or multiple types of semiconductor packages, depending on the application.

[0043] The electronic device 300 may be a stand-alone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, the electronic device 300 may be a subcomponent of a larger system. For example, the electronic device 300 may be part of a tablet computer, a cellular phone, a digital camera, a communication system, or other electronic device. Alternatively, the electronic device 300 may be a graphics card, a network interface card, or other signal processing card that may be inserted into a computer. The semiconductor package may include a microprocessor, a memory, an ASIC, a logic circuit, an analog circuit, an RF circuit, a discrete device, or other semiconductor die or electrical components. Miniaturization and lightweighting are essential for the product to be accepted by the market. The distance between semiconductor devices may be reduced to achieve higher density. The PCB 302 may have a more irregular shape to conveniently fit into a more ergonomic and smaller device housing.

[0044] exist Figure 4b In the embodiment of the present invention, PCB 302 provides a general substrate for structural support and electrical interconnection of semiconductor packages disposed on the PCB. Conductive signal traces 304 are formed on the surface or within the layers of PCB 302 using evaporation, electroplating, chemical plating, screen printing or other suitable metal deposition processes. Signal traces 304 provide electrical communication between each of the semiconductor packages, mounted components and other external system components. Traces 304 also provide power and ground connections for each semiconductor package.

[0045] In some embodiments, the semiconductor device has two packaging levels. The first level of packaging is a technique for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second level of packaging involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device may have only a first level of packaging, where the die is mechanically and electrically disposed directly on the PCB.

[0046] For illustrative purposes, several types of first level packages are shown on PCB 302, including bond wire package 346 and flip chip 348. In addition, several types of second level packages are shown disposed on PCB 302, including ball grid array (BGA) 350, bump chip carrier (BCC) 352, land grid array (LGA) 356, multi-chip module (MCM) or SIP module 358, quad flat no-lead package (QFN) 360, quad flat package 362, and embedded wafer level ball grid array (eWLB) 364. In one embodiment, eWLB 364 is a fan-out wafer level package (Fo-WLP) or a fan-in wafer level package (Fi-WLP).

[0047] Depending on the system requirements, any combination of semiconductor packages configured with any combination of first and second level packaging types and other electrical components can be connected to PCB 302. In some embodiments, electronic device 300 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electronic devices and systems. Because semiconductor packages include complex functions, electronic devices can be manufactured using less expensive components and simplified manufacturing processes. The resulting devices are less likely to fail and are less expensive to manufacture, thereby reducing costs to the consumer.

[0048] While one or more embodiments of the present invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations may be made to those embodiments without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: providing a substrate; disposing an electrical component on a substrate; depositing sealants on electrical components; forming a shielding layer on the sealant, wherein the shielding layer comprises a plurality of graphene-coated metal spheres in a matrix; as well as The shielding layer is sintered by irradiating with intense pulsed light (IPL).

2. The method according to claim 1, further comprising: forming a conductive pillar on a substrate; as well as A shielding layer is formed on the conductive pillars. The method according to claim 1 , further comprising selectively forming a shielding layer.

4. The method of claim 1, further comprising disposing a second electrical component on the substrate, wherein the step of depositing the encapsulant leaves the second electrical component outside the encapsulant. 5 . The method of claim 1 , wherein the plurality of graphene-coated metal balls comprises a plurality of cores formed of copper or silver, and each of the plurality of cores comprises a graphene coating layer. The method according to claim 1 , further comprising forming the shielding layer by inkjet printing.

7. A method for manufacturing a semiconductor device, comprising: providing a substrate; disposing an electrical component on a substrate; depositing sealants on electrical components; forming a shielding layer on the sealant; as well as The shielding layer is sintered by irradiating with intense pulsed light (IPL).

8. The method according to claim 7, further comprising: forming a conductive pillar on a substrate; as well as A shielding layer is formed on the conductive pillars.

9. The method of claim 7, wherein the shielding layer comprises graphene.

10. The method of claim 7, further comprising forming the shielding layer by inkjet printing.

11. A semiconductor device comprising: substrate; an electrical component disposed on a substrate; sealants deposited on electrical components; as well as A shielding layer is formed on the encapsulant, wherein the shielding layer includes a plurality of graphene-coated metal balls. 12 . The semiconductor device according to claim 11 , further comprising a conductive pillar disposed on the substrate, wherein the conductive pillar extends from the substrate to the shielding layer.

13. The semiconductor device of claim 12, wherein the conductive pillar completely or partially surrounds the electrical component in a continuous path or as a plurality of discrete pillars.

14. The semiconductor device according to claim 11, wherein a portion of the sealant is exposed from the shielding layer. 15 . The semiconductor device of claim 11 , wherein the plurality of graphene-coated metal balls include a plurality of cores formed of copper or silver, and each of the plurality of cores includes a graphene coating layer.

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