Semiconductor device

Abstract

The invention relates to a semiconductor device structure and a method of manufacturing a semiconductor device. The method comprises the following steps: providing a first semiconductor substrate with a first main surface and an opposite second main surface, wherein a first metal layer is formed on the first main surface; providing a second semiconductor substrate having a first main surface and an opposing second main surface, where the second semiconductor substrate includes a plurality of active device regions formed therein and a second metal layer formed on the first main surface connecting each of the plurality of active device regions; bonding the first metal layer of the first semiconductor substrate to the second metal layer of the second semiconductor substrate; and forming a device contact on the second main surface of the second semiconductor substrate for electrical connection to each of the plurality of active device regions.

Description

[0001] This application is a divisional application of a patent application with application number 2019101045464, application date February 1, 2019, and invention name “Semiconductor Device”. Technical Field

[0002] The present disclosure relates to a semiconductor device structure and a manufacturing method. Specifically, the present disclosure relates to a semiconductor device structure including a donor substrate and a bonded carrier substrate. Background Art

[0003] The chip-scale semiconductor package (CSP) is characterized in that it is a package that can be directly surface mounted. The CSP is arranged to have all external contacts / contacts on one surface of the package, so that the package can be mounted on a carrier (e.g., a printed circuit board). The CSP generally includes a diode and / or transistor device structure arranged vertically within the package, so that the dominant current flow within the device structure is inherently vertical. However, because the CSP is arranged to have contacts on one surface, the current must flow to another contact on the same side, so the vertical current flowing through the active area of ​​the device structure must change direction to the lateral direction, pass through the substrate, and then change the direction back to the vertical direction to reach the second contact. Due to the limited conductivity of the bulk semiconductor material, the current density in the body and the device structure and the contact will be uneven. The current density in each portion of the device structure closer to the second contact can be higher. In addition, current crowding occurs at the edge of each contact of each device structure. Therefore, the maximum allowed total current through each device structure and each contact will be smaller than the following situation: the second contact is placed on another surface of the semiconductor crystal; and the current through the body is always vertical; and therefore the current density within each device structure is in principle the same for the entire area of ​​the device structure.

[0004] Additionally, parasitic current paths may occur between device structures, which can affect performance. These issues are also particularly relevant for transient voltage suppression devices where localized heating can lead to device failure. Summary of the invention

[0005] According to one embodiment, a method for manufacturing a semiconductor device is provided, the method comprising: providing a first semiconductor substrate having a first main surface and an opposite second main surface, a first metal layer being formed on the first main surface; providing a second semiconductor substrate having a first main surface and an opposite second main surface, wherein the second semiconductor substrate comprises a plurality of active device regions formed therein and a second metal layer, the second metal layer being formed on the first main surface and connecting each of the plurality of active device regions; bonding the first metal layer of the first semiconductor substrate to the second metal layer of the second semiconductor substrate; and forming a device contact on the second main surface of the second semiconductor substrate for electrically connecting to each of the plurality of active device regions.

[0006] Optionally, the method may include: bonding the first metal layer of the first semiconductor substrate to the second metal layer of the second semiconductor substrate to form a metal layer disposed between the two semiconductor layers. Optionally, the first metal layer and the second metal layer may be gold or aluminum.

[0007] Optionally, the method may further include thinning the opposing second main surface of the second semiconductor substrate before bonding the first metal layer to the second metal layer.

[0008] Optionally, the method may further include: forming one or more trench regions extending from the first main surface of the second semiconductor substrate to the opposite second main surface. The method may further include: filling the trench regions with an insulating material.

[0009] Optionally, the second semiconductor substrate may be a silicon-on-insulator substrate. Optionally, the plurality of active device regions are bidirectional active device regions.

[0010] According to one embodiment, a semiconductor device is also provided, comprising: a first semiconductor substrate having a first main surface and an opposite second main surface, a first metal layer being formed on the first main surface; and a second semiconductor substrate having a first main surface and an opposite second main surface, wherein the second semiconductor substrate comprises a plurality of active device regions formed therein and a second metal layer, the second metal layer being formed on the first main surface and connecting each of the plurality of active device regions; wherein the first metal layer of the first semiconductor substrate is bonded to the second metal layer of the second semiconductor substrate; and a device contact is arranged on the second main surface of the second semiconductor substrate for electrical connection to each of the plurality of active device regions.

[0011] The first metal layer of the first semiconductor substrate may be bonded to the second metal layer of the second semiconductor substrate to form a metal layer disposed between the two semiconductor layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Thus, the manner in which the features of the present disclosure may be understood in detail will be described in more detail with reference to various embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments and should not be considered limiting of their scope. The accompanying drawings are intended to facilitate understanding of the present disclosure and are not necessarily drawn to scale. The advantages of the claimed subject matter will become apparent to those skilled in the art by reading this specification in conjunction with the accompanying drawings, in which like reference numerals are used to represent like elements, and in which:

[0013] Figure 1 A carrier substrate or wafer is shown including a metal contact layer formed thereon.

[0014] Figure 2 A donor substrate or wafer is shown, which includes active regions connected to metal contact layers formed thereon;

[0015] Figure 3a shows an active region structure of a back-to-back diode according to an example of an embodiment;

[0016] Figure 3b An active region structure of an open base transistor according to an example of an embodiment is shown;

[0017] Figure 4 shows a donor substrate bonded to a carrier substrate prior to wafer thinning;

[0018] Figure 5 shows a donor substrate bonded to a carrier substrate after wafer thinning;

[0019] Figure 6 is a semiconductor device formed of a donor substrate and a carrier substrate according to an embodiment;

[0020] as well as

[0021] Figure 7 A semiconductor device formed of a donor substrate and a carrier substrate according to an embodiment is shown. DETAILED DESCRIPTION

[0022] Reference Figures 1 to 6 An example method of forming a semiconductor device according to an embodiment is described. The process may be Figure 1Starting with the carrier wafer or first substrate 100 shown. A first metal conductive layer 102 may be formed on a first major surface of the carrier wafer or first substrate 100. The first metal layer 102 may be deposited on the first substrate 100 by any suitable process, such as evaporation or sputtering. The first metal layer 102 may be formed of, for example, aluminum, gold, titanium, tungsten, platinum, or alloys thereof. The first substrate 100 may be a semiconductor substrate such as a silicon substrate, and may be a doped substrate or an undoped substrate. Preferably, the first metal layer 102 forms an ohmic contact with the first substrate 100.

[0023] like Figure 2 As shown, a donor wafer or second substrate 104 is provided. One or more active semiconductor device regions 106 may be formed in the second substrate 104. A second metal conductive layer 108 may be formed on a first main surface of the second substrate 104, and the second metal layer 108 may be electrically connected to contact regions of the one or more semiconductor device regions 106 formed in the second substrate 104. The semiconductor device regions 106 may be formed in the second substrate 104 by diffusion and / or implantation, and refer to the following Figure 3a and Figure 3b Some examples of semiconductor device region structures are discussed.

[0024] refer to Figure 3a , showing a back-to-back diode structure. In this example, the active region 106 is formed in a lightly doped p- second substrate 104. In this example, each cathode of each active region 106 is formed by burying a highly doped n-type region (BN) followed by a deeply highly doped n-type (DN) region, thereby forming the cathode region of each diode. The anode region is formed in the substrate of the highly doped p+ region, and the anode contact is formed to the highly doped p+ region of the active region 106 using a second metal layer 108.

[0025] For this purpose, the back-to-back diode structure is an anode-anode connection structure and is referred to below Figure 6 The formation and arrangement of the cathode contact is discussed in more detail.

[0026] Figure 3b Another example of an example active structure 106 is shown. In this case, the active structure 106 is a so-called open base transistor formed in a lightly doped p- second substrate 104. In this example, the active area 106 is formed by a buried highly doped n-type region (BN) forming the emitter region followed by a p-well base region followed by a highly doped n+ collector region. A collector contact is formed to the highly doped n+ region of the active area 106 using a second metal layer 108. Since an open base device is a bidirectional device, the role of the emitter and collector will change depending on the polarity, only when the polarity is reversed the (floating) base will still be the base.

[0027] The embodiments of the present disclosure are not limited to Figure 3a or Figure 3b The device structures shown are shown, and the skilled person will clearly appreciate that any suitable device structure, combination of structures, or multiple structures may be arranged and implemented without departing from the concepts of the present disclosure. In all embodiments, the metal layer 108 may be connected to multiple device structures.

[0028] After forming the first metal layer 102 on the first substrate 100 and forming the active region 106 in the second substrate 104 and the second metal layer 108, the first substrate 100 and the second substrate 104 are bonded together. Figure 4 As shown, the first metal layer 102 is bonded to the second metal layer 108 .

[0029] In this regard, from an electrical point of view, the joined first metal layer 102 and second metal 108 can be considered as a multi-layer structure. In this way, the first metal layer 102 joined to the second metal layer 108 can be considered as a buried metal layer, i.e., buried between the first substrate 100 and the second substrate 104.

[0030] Examples of bonding techniques may include thermocompression bonding. The first metal layer 102 and the second metal layer 108 are brought into atomic contact by applying heat and force simultaneously. Individual atoms from the lattice of the first metal layer migrate to the lattice of the second metal layer based on lattice vibrations, and the atomic interactions cause the first metal layer to be bonded to the second metal layer. Alternatively, a metal-to-metal bonding layer such as a eutectic alloy layer may be formed as a bonding material. Other alternatives to the bonding layer may include simultaneous adhesive-metal bonding or simultaneous molten-metal bonding.

[0031] like Figure 5 As shown, after the first substrate 100 and the second substrate 104 are bonded together, the second substrate 104 on the main side opposite to the second metal layer 108 may be thinned to expose portions of each active region 106. Figure 3a or Figure 3b After each example presented, the second substrate 104 can be thinned by any suitable etching or grinding process to remove a portion of the second substrate 104, exposing the highly doped n+ region (BN). Removing a portion of the second substrate 104 allows contacts to be properly formed with the exposed regions of each active region 106.

[0032] exist Figure 6 1 , which shows the formation of appropriate contacts 110 on the active area 106. Prior to forming the contacts 110, an optional isolation layer 112 may be formed on the side of the second substrate 104 opposite the second metal layer 108.

[0033] Before the first substrate 100 is bonded to the second substrate 104, the active region 106 is formed in the second substrate 104. Therefore, before bonding, all high temperature diffusion processes required to form the active region 106 are completed on the second substrate 104. As a result, low melting point metals such as gold or aluminum can be used in the bonding process because the bonding metal does not diffuse outward. In addition, after the bonding of the first metal layer and the second metal layer to form the buried metal layer, high temperature processing of the device (i.e., in order to form various diffusion regions) is difficult. This will require a metal with a high melting point to withstand the temperature required to form the various diffusion regions, and may cause serious mechanical problems, such as wafer bending or degradation of the metal layer. It is therefore advantageous to perform all high temperature processes, such as diffusion processes, before the wafer is bonded.

[0034] Furthermore, the resistance of the joined metal layers 102 , 108 may be controlled by appropriate selection of the metal and / or metal thickness.

[0035] In with Figure 5 In an alternative process, the second substrate 104 on the main side opposite to the second metal layer 108 may be thinned to expose portions of the respective active regions 106 before the first metal layer 102 is bonded to the second metal layer 108. In addition, depending on the thickness or depth of the active regions 106 formed in the second substrate 104, the second substrate 104 may not need to be thinned or may be partially thinned to expose the respective active regions 106 so that suitable contacts 110 may be formed.

[0036] Optionally, the first substrate 100 may be thinned prior to further processing of the finished device 120. This may include partially thinning the first substrate 100 to reduce its thickness and / or locally thinning to facilitate singulation of the device from an array of such devices.

[0037] Figure 7 A semiconductor device 120 according to one embodiment is shown. The donor wafer or second substrate 104 may include at least one trench 116 extending from a first major surface of the second substrate 104 to an opposite second major surface and located between the active regions 106. The at least one trench 116 may be filled with an electrically insulating material (e.g., an oxide) and is used to isolate the active regions 106 to prevent parasitic currents from flowing through the second substrate 104 between the active regions.

[0038] The at least one trench 116 may be formed in the second substrate 104 while forming the active region 106. As shown, the trench 116 may also be arranged at the edge of the device 120 to prevent parasitic currents (e.g., leakage currents) from the edge of the device 120. In the case where the second device structure is not an active structure but is simply in contact with the bulk semiconductor material, the contact may be connected to the buried metal layer through the conductive trench to reduce the resistance between the contact and the buried metal layer. This may have the effect of reducing the on-resistance of the device.

[0039] In terms of operation and reference Figure 6 , which reflects Figure 3a A back-to-back diode arrangement or Figure 3b In the open base transistor arrangement, current can flow from one contact 110 through one of the active regions 106 and into the multi-layer metal layer formed by the first metal layer 102 and the second metal layer 108. The current then passes through the multi-layer metal and another active region 106 until another contact 110.

[0040] Since the multi-layer metal structure is formed by the first metal layer 102 and the second metal layer 108, the current distribution perpendicular to the surface is substantially uniform. In other words, the current density in each area is substantially the same over the entire area of ​​the device structure. The resistance of the multi-layer metal structure is very small, with a sheet resistance of 1-20 mΩ, compared to the current path of the bulk semiconductor with a sheet resistance of 200-1000 mOhm. As a result, unlike known arrangements, the current density at the inner and outer edges of the device will be substantially uniform.

[0041] In addition, for the same reason, the differential on-resistance is very small. The buried metal layer effectively shortens the bulk that is usually part of the current path. Therefore, the on-resistance of the device according to the embodiment is reduced by 180-990mOhm. In addition, because the silicon portion of the current path (i.e., the vertical path) is small, the current will only be transmitted from the top contact to the buried metal layer in the vertical direction because the silicon resistance of this path is small.

[0042] Furthermore, the introduction of multi-layer metal structure 114 provides improved heat dissipation from active region 106 of device 120 during operation. Specifically, heat generated during operation of device 120 will be conducted away from active region 106 through multi-layer metal structure, thereby increasing the current robustness of device 120.

[0043] In an alternative to the above embodiment, the donor wafer or second substrate 104 may be a SOI (silicon on insulator) wafer. After forming the active region 106 in the SOI wafer and forming the second metal conductive layer 108 on the first main surface, as described above with reference to Figure 4As described above, an SOI wafer may be bonded to the first substrate 100. The oxide layer of the SOI wafer may be used as an optional isolation layer 112, with appropriate contacts 110 formed therethrough to contact the active region 106, as described above with reference to FIG. Figure 6 discussed.

[0044] If the oxide layer of the SOI wafer is a buried oxide, the SOI wafer on the main surface opposite the second metal layer 108 can be thinned to expose the buried oxide. As described above, the buried oxide can be used as an optional isolation layer 112, and appropriate contacts can be formed therethrough to connect to the active area 106. Figure 7 As discussed, trench 116 may also be formed in the SOI wafer.

[0045] As mentioned above Figure 3a and 3b As mentioned, the skilled person will understand that the arrangement of the active layer is not limited to the examples of back-to-back diodes or open base transistors. Based on the above teachings, the skilled person will understand that the concept of the buried metal layer is applicable to different types of semiconductor device structures. For example, devices such as vertical MOS diodes, trench MOS transistors, insulated gate bipolar transistors (IGBTs) and / or vertical bipolar transistors or any combination of devices can be arranged as active region 106.

[0046] The above embodiments are particularly suitable for semiconductor devices used for transient voltage suppression (TVS), which may need to shunt excess current during operation when the transient voltage exceeds the avalanche breakdown potential of the device. TVS devices typically suppress all transient voltages higher than the breakdown voltage of the device, and because these transient voltages generate heat in the device, the buried metal layer formed by the first metal layer 102 and the second metal layer 108 improves the heat dissipation capability of the device while also reducing the on-resistance of the device. The device is improved due to the inclusion of additional heat conduction paths and current conduction paths.

[0047] Particular and preferred aspects of the invention are set out in the accompanying independent claims. Combinations of features from the dependent claims and / or the independent claim may be combined as appropriate and not just as set out in the claims.

[0048] The scope of the present disclosure includes any novel feature or combination of features disclosed explicitly or implicitly, or any generalization thereof, whether or not it relates to the claimed invention or mitigates any or all of the problems solved by the invention. The applicants hereby give notice that new claims may be formulated to such features during the prosecution of the present application or of any such further application derived therefrom. In particular, with reference to the appended claims, features of dependent claims may be combined with features of the independent claims, and features from separate independent claims may be combined in any appropriate manner and not merely in the specific combinations recited in the claims.

[0049] Features that are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features that are, for brevity, described in the context of a single embodiment may also be provided separately or in any suitable subcombination.

[0050] The term "comprising" does not exclude other elements or steps and the term "a" or "an" does not exclude a plurality. Reference signs in the claims should not be construed as limiting the scope of the claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: providing a first semiconductor substrate having a first main surface and an opposite second main surface, wherein a first metal layer is formed on the first main surface; providing a second semiconductor substrate having a first major surface and an opposite second major surface, wherein the second semiconductor substrate includes a plurality of active device regions formed therein and a continuous second metal layer, the second metal layer being formed on the first major surface and laterally spanning the entire width of the entire semiconductor device to connect each of the plurality of active device regions; directly bonding the first metal layer of the first semiconductor substrate to the second metal layer of the second semiconductor substrate to form a buried metal layer disposed between the two semiconductor layers, the buried metal layer being configured such that a current distribution perpendicular to a surface is substantially uniform and a current density in each region is substantially the same over the entire area of ​​the device; as well as A device contact is formed on the second main surface of the second semiconductor substrate for electrical connection to each of the plurality of active device regions. 2 . The method of claim 1 , further comprising bonding the first metal layer of the first semiconductor substrate to the second metal layer of the second semiconductor substrate using a gold bonding layer or an aluminum bonding layer. 3 . The method of claim 1 , further comprising thinning an opposing second major surface of the second semiconductor substrate before bonding the first metal layer to the second metal layer. 4 . The method of claim 1 , further comprising forming one or more trench regions extending from the first major surface to an opposing second major surface of the second semiconductor substrate. The method of claim 4 , further comprising filling the trench region with an insulating material.

6. The method according to claim 1, wherein: The second semiconductor substrate is a silicon-on-insulator substrate.

7. The method according to claim 1, wherein: The plurality of active device regions are bidirectional active device regions.

8. A semiconductor device comprising: A first semiconductor substrate having a first main surface and an opposite second main surface, wherein a first metal layer is formed on the first main surface; a second semiconductor substrate having a first major surface and an opposite second major surface, wherein the second semiconductor substrate includes a plurality of active device regions formed therein and a continuous second metal layer, the second metal layer being formed on the first major surface and laterally spanning across the entire width of the semiconductor device to connect each of the plurality of active device regions; wherein the first metal layer of the first semiconductor substrate is directly bonded to the second metal layer of the second semiconductor substrate to form a buried metal layer disposed between the two semiconductor layers, the buried metal layer being configured such that a current distribution perpendicular to a surface is substantially uniform and a current density in each region is substantially the same over the entire region of the device; as well as A plurality of device contacts are disposed on the second main surface of the second semiconductor substrate for electrically connecting to each of the plurality of active device regions.

9. The semiconductor device according to claim 8, wherein: The first metal layer and the second metal layer are gold or aluminum. 10 . The semiconductor device of claim 8 , further comprising one or more trench regions extending from the first main surface to an opposing second main surface of the second semiconductor substrate.

11. The semiconductor device according to claim 10, wherein: The trench region is filled with an insulating material.

12. The semiconductor device according to claim 8, wherein The second semiconductor substrate is a silicon-on-insulator substrate.

13. The semiconductor device according to claim 8, wherein: The active device region is a bidirectional active device region.

14. The semiconductor device according to claim 8, wherein: The buried metal layer has a sheet resistance of 1-20 mΩ.

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