Preparation process of SOI substrate for chip
By etching the gaps on the SOI substrate and filling the polymer, the problem of large Young's modulus of SOI substrates in the prior art is solved, and a SOI substrate preparation process with higher flexibility and greater amplitude is achieved. Improved device performance.
Patent Information
- Application Number
- CN202311222033.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-20
- Publication Date
- 2024-12-10
AI Technical Summary
The Young's modulus of existing SOI substrates is large, resulting in a smaller amplitude of the diaphragm or movable structure, limiting device performance.
The slit is formed by etching the top silicon on the SOI substrate and filling the slit with polymers patterned to connect the vibrating and fixing portions, increasing the flexibility and amplitude of the structure.
It improves the flexibility and amplitude of the SOI substrate, maximizes the device performance, and enhances the performance of the chip.
Smart Images
Figure CN119108335A_ABST
Abstract
Description
Technical Field
[0001] One or more embodiments of the present specification relate to the field of semiconductor process technology, and in particular, to a process for preparing an SOI substrate for a chip. Background Art
[0002] SOI (Silicon-On-Insulator) technology introduces a buried oxide layer between the top silicon and the back substrate. In the prior art, since SOI top silicon has a large Young's modulus, when used as the structural layer of piezoelectric actuators and transducers, it will cause the diaphragm or movable structure to have a small amplitude, limiting the performance of the device.
[0003] In summary, the present application now proposes a process for preparing a chip SOI substrate to solve the above-mentioned problems. Summary of the invention
[0004] The present invention aims to solve the problems raised in the background technology. The purpose of one or more embodiments of this specification is to propose a preparation process of an SOI substrate for a chip. The prepared SOI substrate has a high flexibility and a large amplitude, and can release the device performance to the greatest extent.
[0005] Based on the above purpose, one or more embodiments of the present specification provide a process for preparing an SOI substrate for a chip, comprising the following steps: preparing a substrate, the substrate comprising bottom silicon and top silicon connected by a buried oxide layer; etching the top silicon to produce a gap in the top silicon, the gap causing the top silicon to form a vibration part and a fixed part that are independent of each other from the inside to the outside; filling the gap with a polymer, and etching the polymer to pattern the polymer, the polymer being used to connect the vibration part and the fixed part; etching the bottom silicon and the buried oxide layer to form a space for the vibration part to vibrate.
[0006] According to the process for preparing a chip SOI substrate provided by an embodiment of the present invention, the polymer fills the gaps.
[0007] According to the process for preparing the SOI substrate for a chip proposed in an embodiment of the present invention, after filling with polymer, the polymer is etched to pattern the polymer to form a cantilever beam for connecting the vibration part and the fixed part.
[0008] According to the process for preparing a chip SOI substrate provided by an embodiment of the present invention, the gap in step S2 is ring-shaped.
[0009] According to the process for preparing a SOI substrate for a chip proposed in an embodiment of the present invention, the gap in step S2 is a U-shaped structure.
[0010] The beneficial effects of the present invention are described in detail below with reference to the embodiments and drawings of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] In order to more clearly illustrate one or more embodiments of the present specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only one or more embodiments of the present specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0012] Figure 1 A schematic diagram of step S1 of a process for preparing a chip SOI substrate according to an embodiment of the present invention;
[0013] Figure 2 A schematic diagram of step S2 of a process for preparing a chip SOI substrate according to an embodiment of the present invention;
[0014] Figure 3 A schematic diagram of step S3 of a process for preparing a chip SOI substrate according to an embodiment of the present invention;
[0015] FIG. 4 is a schematic diagram of step S4 of a process for preparing a chip SOI substrate according to an embodiment of the present invention.
[0016] In the figure numerals: 1. bottom silicon; 2. buried oxide layer; 3. top silicon; 31. fixed part; 32. vibration part; 4. gap; 5. polymer. DETAILED DESCRIPTION
[0017] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in conjunction with specific embodiments.
[0018] According to the following Figure 1 - Figure 4 describes the specific structure of a process for preparing a chip SOI substrate in an embodiment of the present invention.
[0019] Embodiment 1
[0020] The preparation process of the SOI substrate for a chip proposed in an embodiment of the present invention comprises the following steps:
[0021] S1, prepare a substrate, the substrate includes a bottom silicon 1 and a top silicon 3 connected by a buried oxide layer 2, such as Figure 1 shown.
[0022] S2, etching the top silicon 3, so that the top silicon 3 has a gap 4, the gap 4 is a circular ring structure, and the gap 4 makes the top silicon 3 form a vibration part 32 and a fixed part 31 which are independent of each other from the inside to the outside, such as Figure 2 As shown in a.
[0023] S3, growing polymer 5 in the gap 4, etching the polymer 5 to remove the excess part, so that the remaining polymer 5 fills the gap, which is used to connect the vibration part 32 and the fixed part 31, as shown in Figure 3 As shown in a.
[0024] S4, etching the bottom silicon layer 1 and the buried oxide layer 2 to form a space for the vibration part 32 to vibrate, as shown in FIG. 4 .
[0025] Embodiment 2
[0026] S1, prepare a substrate, the substrate includes a bottom silicon 1 and a top silicon 3 connected by a buried oxide layer 2, such as Figure 1 shown.
[0027] S2, etching the top silicon 3, so that the top silicon 3 has a gap 4, the gap 4 is a U-shaped structure, and the gap 4 makes the top silicon 3 form a vibration part 32 and a fixed part 31 which are independent of each other from the inside to the outside, such as Figure 2 As shown in b.
[0028] S3, growing a polymer 5 in the gap 4, and etching the polymer 5 to pattern the polymer 5, so as to form a cantilever beam for connecting the vibration part 32 and the fixed part 31, as shown in FIG. Figure 3 As shown in b.
[0029] S4, etching the bottom silicon layer 1 and the buried oxide layer 2 to form a space for the vibration part 32 to vibrate, as shown in FIG. 4 .
[0030] In the chip preparation process, after the upper electrode, PZT, and lower electrode are patterned, the original connection area of the top silicon is etched away during the etching process, and then polymers are grown and patterned to fill or create connection structures to improve structural flexibility and increase amplitude. The suspended structure in the middle is connected and supported by polymers or polymer patterned structures, and finally the bottom silicon and buried oxide layers are etched to complete device manufacturing.
[0031] Optionally, the polymer is one or a combination of PI (polyimide), parylene, polyparaxylene and PDMS (polydimethylsiloxane).
[0032] One or more embodiments of this specification are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification should be included in the scope of protection of this disclosure.
Claims
1. A process for preparing a SOI substrate for a chip, It is characterized in that The following steps are involved: Prepare a substrate, the substrate comprising bottom silicon (1) and top silicon (3) connected by a buried oxide layer (2); Etching the top silicon (3) to generate a gap (4) in the top silicon (3), wherein the gap (4) forms a vibration part (32) and a fixed part (31) which are independent of each other from the inside to the outside of the top silicon (3); Growing a polymer (5) in the gap (4), and etching the polymer (5) to pattern the polymer (5), wherein the polymer (5) is used to connect the vibration part (32) and the fixing part (31); The bottom silicon (1) and the buried oxide layer (2) are etched to form a space for the vibration part (32) to vibrate.
2. The process for preparing the SOI substrate for a chip according to claim 1, It is characterized in that The polymer (5) fills the gaps.
3. The process for preparing a chip SOI substrate according to claim 1, It is characterized in that After the polymer (5) is filled, the polymer (5) is etched to pattern the polymer (5) to form a cantilever beam for connecting the vibration part (32) and the fixed part (31).
4. A process for preparing a chip SOI substrate according to any one of claims 1 to 3, It is characterized in that The gap (4) is annular.
5. A process for preparing a chip SOI substrate according to any one of claims 1 to 3, It is characterized in that The gap (4) is a U-shaped structure.