Semiconductor device

Abstract

A semiconductor device includes a via pattern in a first interlayer insulating film and a wiring pattern extending in a first direction and on the first interlayer insulating film and the via pattern. The wiring pattern includes a lower wiring and an upper wiring on the lower wiring, where the lower wiring and the upper wiring are stacked in the second direction, where the lower wiring is between the via pattern and the upper wiring and on an upper surface of the via pattern, wherein a first portion of the lower wiring is on an upper surface of the via pattern and has a first thickness, and wherein a second portion of the lower wiring is on an upper surface of the first interlayer insulating film and has a second thickness.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including a wiring formed in a BEOL (back end of line) process. Background Art

[0002] In recent years, as the scaling down of semiconductor elements has been rapidly developed due to the development of electronic technology, semiconductor chips are expected to have higher integration and lower power consumption. In order to cope with the requirements of higher integration and lower power consumption of semiconductor chips, the feature size of semiconductor devices continues to decrease.

[0003] Since various contact forms are used for connection between wirings, the length of the contact may increase, and the contact resistance may increase accordingly. Summary of the invention

[0004] Aspects of the present disclosure provide a semiconductor device which can improve element performance and reliability by using a wiring pattern of a stack structure formed of metal.

[0005] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0006] According to one aspect of the present disclosure, a semiconductor device is provided, which includes a via pattern in a first interlayer insulating film and a wiring pattern extending in a first direction and on the first interlayer insulating film and the via pattern, wherein the wiring pattern includes a lower wiring and an upper wiring on the lower wiring, wherein the lower wiring and the upper wiring are stacked in a second direction, wherein the lower wiring is between the via pattern and the upper wiring and on an upper surface of the via pattern, wherein a first portion of the lower wiring is on the upper surface of the via pattern and has a first thickness, and wherein a second portion of the lower wiring is on the upper surface of the first interlayer insulating film and has a second thickness different from the first thickness.

[0007] According to another aspect of the present disclosure, a semiconductor device is provided, comprising: a via pattern in a first interlayer insulating film; a wiring pattern extending in a first direction and on the first interlayer insulating film and the via pattern, wherein the wiring pattern comprises a lower wiring and an upper wiring on the lower wiring, and wherein the lower wiring and the upper wiring are stacked in a second direction; and a second interlayer insulating film on the first interlayer insulating film, wherein the second interlayer insulating film comprises a wiring insulation pad extending along a side wall of the wiring pattern and an upper surface of the first interlayer insulating film, and wherein the second interlayer insulating film comprises a filling interlayer insulating film on the wiring insulation pad, wherein the upper wiring comprises an upper surface and a bottom surface opposite to each other in the second direction, wherein the upper wiring comprises a side wall in contact with an upper surface of the upper wiring and a bottom surface of the upper wiring, wherein the lower wiring is between an upper surface of the via pattern and a bottom surface of the upper wiring, wherein the lower wiring contacts the upper surface of the via pattern, and wherein the lower wiring does not extend along the side wall of the upper wiring.

[0008] According to another aspect of the present disclosure, a semiconductor device is provided, which includes a via pattern in a first interlayer insulating film and a wiring pattern extending in a first direction and on the first interlayer insulating film and the via pattern, wherein the wiring pattern includes a lower wiring and an upper wiring on the lower wiring, and wherein the lower wiring and the upper wiring are stacked in a second direction, wherein the upper wiring includes an upper surface and a bottom surface opposite to each other in the second direction, wherein the upper wiring includes a side wall connecting the upper surface of the upper wiring and the bottom surface of the upper wiring, wherein the lower wiring is between the upper surface of the via pattern and the bottom surface of the upper wiring, wherein the lower wiring contacts the upper surface of the via pattern, wherein the lower wiring includes a first portion extending along a portion of the side wall of the upper wiring and a second portion extending along the bottom surface of the upper wiring, and wherein the upper wiring overlaps with the uppermost surface of the lower wiring in the second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is an example layout diagram for illustrating a semiconductor device according to some embodiments.

[0010] Figure 2 is along Figure 1 A cross-sectional view taken along line AA.

[0011] Figure 3 is along Figure 1 A cross-sectional view taken along line BB.

[0012] Figure 4 yes Figure 3 Magnified view of portion P.

[0013] Figure 5 , Figure 6 and Figure 7is a diagram for explaining a semiconductor device according to some embodiments.

[0014] Figure 8 and Fig. 9 is a diagram of a semiconductor device according to some embodiments.

[0015] Fig.10 is a diagram of a semiconductor device according to some embodiments.

[0016] Fig.11 is a diagram of a semiconductor device according to some embodiments.

[0017] Fig.12 , Fig.13 and Fig.14 is a diagram of a semiconductor device according to some embodiments.

[0018] Fig.15 and Fig.16 is a diagram of a semiconductor device according to some embodiments.

[0019] Fig.17 and Fig.18 is a diagram of a semiconductor device according to some embodiments.

[0020] Fig.19 , Fig. 20 , Fig.21 and Fig. 22 is a diagram of a semiconductor device according to some embodiments.

[0021] Fig.23 is a diagram of a semiconductor device according to some embodiments.

[0022] Fig.24 and Fig.25 is a diagram of a semiconductor device according to some embodiments.

[0023] Fig.26 and Fig. 27 is a diagram of a semiconductor device according to some embodiments.

[0024] Fig.28 and Fig.29 is a diagram of a semiconductor device according to some embodiments.

[0025] Fig.30 is a diagram of a semiconductor device according to some embodiments.

[0026] Fig.31 is a diagram of a semiconductor device according to some embodiments.

[0027] Fig.32 , Fig.33 and Fig.34is a diagram of a semiconductor device according to some embodiments.

[0028] Fig.35 , Fig.36 and Fig.37 is a diagram of an intermediate stage in a method for fabricating a semiconductor device according to some embodiments.

[0029] Fig.38 , Fig.39 , Fig.40 , Fig.41 and Fig.42 is a diagram of an intermediate stage in a method for fabricating a semiconductor device according to some embodiments.

[0030] Fig.43 , Fig.44 , Fig.45 , Fig.46 and Fig.47 is a diagram of an intermediate stage in a method for fabricating a semiconductor device according to some embodiments.

[0031] Fig.48 , Fig.49 , Fig.50 and Fig.51 is a diagram of an intermediate stage in a method for fabricating a semiconductor device according to some embodiments.

[0032] Fig.52 and Fig.53 is a diagram of an intermediate stage in a method for fabricating a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0033] In order to clarify the present disclosure, parts not related to the description will be omitted, and the same elements or equivalents are represented by the same reference numerals throughout the specification. In addition, since the sizes and thicknesses of the constituent members shown in the drawings are arbitrarily given for better understanding and ease of description, the present disclosure is not limited to the sizes and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are excessively shown for better understanding and ease of description.

[0034] It will be understood that when an element such as a layer, film, region or substrate is referred to as "on" another element, it can be directly on the other element, or there can also be an intervening element. On the contrary, when an element is referred to as "directly on" another element, there is no intervening element. In addition, for ease of description, spatial relative terms such as "under ... ", "under ... ", "lower part", "on ... ", "upper part", etc., can be used herein to describe the relationship between an element or feature and another element or feature as shown in the figure. It will be understood that, in addition to the orientation depicted in the figure, spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the accompanying drawings is turned over, the element described as "under" or "under" other elements or features will be oriented to be "on" other elements or features. Therefore, the term "under ... " can cover both upper and lower orientations. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0035] In addition, unless explicitly described to the contrary, the word "comprise" and variations such as "comprises" or "comprises ... " will be understood to imply inclusion of the elements but not excluding any other elements. As used herein, the phrase "at least one of A, B and C" refers to the logic (A or B or C) using a non-exclusive logic or (OR), and should not be interpreted as meaning "at least one of A, at least one of B and at least one of C". As used herein, the singular forms "one" and "the" are intended to also include plural forms unless the context clearly indicates otherwise. It will be further understood that when used herein, the terms "comprise", "comprises ... ", "comprises" and / or "comprises ... " indicate the presence of the features, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, steps, operations, elements, parts and / or their groups. The term "and / or" includes any and all combinations of one or more associated listed items. The term "connection" can be used herein to refer to physical connections and / or electrical connections, and can refer to direct or indirect physical connections and / or electrical connections. Components or layers described with reference to “overlapping” in a particular direction may be at least partially blocked from each other when viewed along a line extending in the particular direction or in a plane perpendicular to the particular direction.

[0036] Although terms such as first and second are used in this specification to describe various elements or components, it goes without saying that these elements or components are not limited by these terms. These terms are only used to distinguish a single element or component from other elements or components. Therefore, it goes without saying that within the technical concept of the present disclosure, the first element or component mentioned below may be the second element or component.

[0037] Although the drawings of the semiconductor device according to some embodiments show, as examples, a fin transistor (FinFET) including a channel region in a fin pattern shape, a transistor including a nanowire or a nanosheet, an MBCFET TM (Multi-bridge channel field effect transistor) or vertical transistor (vertical FET), but the embodiments are not limited thereto. Of course, semiconductor devices according to some embodiments may include tunneling transistors (tunneling FETs) or three-dimensional (3D) transistors. Semiconductor devices according to some embodiments may include planar transistors. In addition, the technical concept of the present disclosure can be applied to transistors based on two-dimensional materials (FETs based on 2D materials) and their heterostructures.

[0038] In addition, the semiconductor device according to some embodiments may further include a bipolar junction transistor, a laterally diffused metal oxide semiconductor (LDMOS), and the like.

[0039] Figure 1 is an example layout diagram of a semiconductor device according to some embodiments. Figure 2 is along Figure 1 A cross-sectional view taken along line AA. Figure 3 is along Figure 1 A cross-sectional view taken along line BB. Figure 4 yes Figure 3 Magnified view of portion P.

[0040] Reference Figures 1 to 4 , a semiconductor device according to some embodiments may include a first conductive lower pattern 110 , a second conductive lower pattern 120 , a first upper wiring structure 210ST, and a second upper wiring structure 220ST.

[0041] The first conductive lower pattern 110 and the second conductive lower pattern 120 may each be disposed inside the first interlayer insulating film 150. The first conductive lower pattern 110 and the second conductive lower pattern 120 may each extend long in the first direction D1. The first conductive lower pattern 110 and the second conductive lower pattern 120 may be spaced apart from each other in the second direction D2.

[0042] The first conductive lower pattern 110 and the second conductive lower pattern 120 may each have a linear shape extending in the first direction D1. For example, the first direction D1 may be a longitudinal direction of the first conductive lower pattern 110 and the second conductive lower pattern 120, and the second direction D2 may be a width direction of the first conductive lower pattern 110 and the second conductive lower pattern 120. Here, the first direction D1 intersects the second direction D2 and the third direction D3. The second direction D2 intersects the third direction D3.

[0043] Although the first conductive lower pattern 110 and the second conductive lower pattern 120 are shown as being adjacent to each other in the second direction D2, embodiments are not limited thereto. In one variation, an additional conductive lower pattern may be disposed between the first conductive lower pattern 110 and the second conductive lower pattern 120. In addition, although the length of the first conductive lower pattern 110 in the first direction D1 is shown as being the same as the length of the second conductive lower pattern 120 in the first direction D1, embodiments are not limited thereto.

[0044] The first interlayer insulating film 150 may cover or overlap the gate electrode and source / drain of the transistor formed in the front end of line (FEOL) process. Alternatively, the gate electrode of the transistor may be disposed inside the first interlayer insulating film 150. Alternatively, the first interlayer insulating film 150 may be an interlayer insulating film formed in the back end of line (BEOL) process.

[0045] In other words, as an example, each of the first conductive lower pattern 110 and the second conductive lower pattern 120 may be a contact or contact wiring formed in a middle of the road (MOD) process. As another example, the first conductive lower pattern 110 and the second conductive lower pattern 120 may be a connection wiring formed in a BEOL process. As yet another example, the first conductive lower pattern 110 and the second conductive lower pattern 120 may be a gate electrode formed in a FEOL process.

[0046] In the following description, the first conductive lower pattern 110 and the second conductive lower pattern 120 will be described as connection wiring formed in a BEOL process. For example, the first conductive lower pattern 110 and the second conductive lower pattern 120 may be disposed on a first metal level.

[0047] The first interlayer insulating film 150 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. The low dielectric constant material may have a lower dielectric constant than silicon oxide. The low dielectric constant material may be, for example, silicon oxide with moderately high carbon and hydrogen, and may be a material such as SiCOH. On the other hand, since carbon is included in the insulating material, the dielectric constant of the insulating material may be reduced. However, in order to further reduce the dielectric constant of the insulating material, the insulating material may include a hole such as a cavity, in which a gas or air is filled in the insulating material.

[0048] Low dielectric constant materials may include, for example, but are not limited to, fluorinated tetraethylorthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethylorthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxydi-tert-butylsiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), TOSZ (Tonen SilaZen), FSG (fluoride silicate glass), polyimide nanofoam (such as polypropylene oxide), CDO (carbon-doped silicon oxide), OSG (organosilicate glass), SiLK, amorphous fluorinated carbon, silica aerogel, silica xerogel, mesoporous silica, or a combination thereof.

[0049] The first conductive lower pattern 110 and the second conductive lower pattern 120 may each include, for example, a lower wiring barrier film 110a and a lower wiring filling film 110b. The lower wiring filling film 110b may be disposed on the lower wiring barrier film 110a. The first conductive lower pattern 110 and the second conductive lower pattern 120 may each include a plurality of conductive films. The first conductive lower pattern 110 and the second conductive lower pattern 120 may each have a plurality of conductive film structures.

[0050] The lower wiring barrier film 110a may extend along the sidewalls of the lower wiring filling film 110b and the bottom surface of the lower wiring filling film 110b. In one variation, the lower wiring barrier film 110a may not be disposed on the sidewalls of the lower wiring filling film 110b. As another example, the lower wiring barrier film 110a may not be disposed on the bottom surface of the lower wiring filling film 110b.

[0051] The lower wiring barrier film 110a may include, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional material (2D material). The lower wiring barrier film 110a may include, for example, but not limited to, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium, nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), molybdenum (Mo), and at least one of a two-dimensional material.

[0052] The two-dimensional material (2D material) may include a 2D allotrope or a 2D compound, and may include, for example, but not limited to, at least one of graphene, boron nitride (BN), molybdenum sulfide, molybdenum selenide, tungsten sulfide, tungsten selenide, and tantalum sulfide. That is, since the above-mentioned 2D materials are listed only by way of example, the 2D materials that may be included in the semiconductor device of the present disclosure are not limited to the above-mentioned materials.

[0053] The lower wiring filling film 110b may include a metal or a conductive compound including a metal. The lower wiring filling film 110b may include, for example but not limited to, aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn), molybdenum (Mo), rhodium (Rh), iridium (Ir), RuAl, NiAl, NbB 2 、MoB 2 , TaB 2 、V 2 At least one of AlC and CrAlC. When the lower wiring filling film 110b includes copper (Cu), the lower wiring filling film 110b may include, for example, carbon (C), silver (Ag), cobalt (Co), tantalum (Ta), indium (In), tin (Sn), zinc (Zn), manganese (Mn), titanium (Ti), magnesium (Mg), chromium (Cr), germanium (Ge), strontium (Sr), platinum (Pt), magnesium (Mg), aluminum (Al) or zirconium (Zr).

[0054] The widths of the first conductive lower pattern 110 and the second conductive lower pattern 120 in the first direction D1 may decrease as they are away from the upper surface of the first interlayer insulating film 150. In addition, as the first conductive lower wiring 110 and the second conductive lower wiring 120 are away from the upper surface of the first interlayer insulating film 150, the widths of the first conductive lower wiring 110 and the second conductive lower wiring 120 in the second direction D2 may decrease.

[0055] In one variation, the widths of the first conductive lower pattern 110 and the second conductive lower pattern 120 in the first direction D1 may increase as they are away from the upper surface of the first interlayer insulating film 150. As the first conductive lower pattern 110 and the second conductive lower pattern 120 are away from the upper surface of the first interlayer insulating film 150, the widths of the first conductive lower pattern 110 and the second conductive lower pattern 120 in the second direction D2 may increase.

[0056] Although not shown, a via pattern connecting the first conductive lower pattern 110 and a conductive pattern disposed below the first conductive lower pattern 110 may be further provided. Similarly, a via pattern connecting the second conductive lower pattern 120 and a conductive pattern disposed below the second conductive lower pattern 120 may be further provided.

[0057] The second interlayer insulating film 160 may be disposed on the first conductive lower pattern 110, the second conductive lower pattern 120, and the first interlayer insulating film 150. The second interlayer insulating film 160 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0058] The first etch stopper film 155 may be disposed between the first interlayer insulating film 150 and the second interlayer insulating film 160. The first etch stopper film 155 may be disposed on the first conductive lower pattern 110, the second conductive lower pattern 120, and the first interlayer insulating film 150. The first etch stopper film 155 may include a material having an etching selectivity with respect to the second interlayer insulating film 160.

[0059] The third interlayer insulating film 170 may be disposed on the second interlayer insulating film 160. The third interlayer insulating film 170 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0060] In the semiconductor device according to some embodiments, the third interlayer insulating film 170 may be a single film.The third interlayer insulating film 170 may include, but is not limited to, silicon oxide.

[0061] The second etch stop film 165 may be disposed between the second interlayer insulating film 160 and the third interlayer insulating film 170. The second etch stop film 165 may be disposed on an upper surface 160US of the second interlayer insulating film. The upper surface 160US of the second interlayer insulating film may be a boundary surface between the second etch stop film 165 and the second interlayer insulating film 160. The second etch stop film 165 may include a material having an etching selectivity with respect to the second interlayer insulating film 160.

[0062] The first etch stop film 155 and the second etch stop film 165 may each include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), aluminum oxide (AlO), aluminum nitride (AlN), aluminum oxycarbide (AlOC), and combinations thereof. Although the first etch stop film 155 and the second etch stop film 165 are each shown as a single film, this is only for ease of description, and embodiments are not limited thereto.

[0063] In one modification, the first etch stopper film 155 may include a plurality of insulating films sequentially stacked on the first interlayer insulating film 150. The second etch stopper film 165 may include a plurality of insulating films sequentially stacked on the second interlayer insulating film 160.

[0064] The first upper wiring structure 210ST and the second upper wiring structure 220ST may be disposed on the first conductive lower pattern 110 and the second conductive lower pattern 120. The first upper wiring structure 210ST and the second upper wiring structure 220ST may each be disposed inside the first etch stopper film 155, the second interlayer insulating film 160, the second etch stopper film 165, and the third interlayer insulating film 170.

[0065] For example, the first upper wiring structure 210ST may be connected to the first conductive lower pattern 110. The second upper wiring structure 220ST may be connected to the second conductive lower pattern 120. The first upper wiring structure 210ST may include a first wiring pattern 210 and a first via pattern 215. The second upper wiring structure 220ST may include a second wiring pattern 220 and a second via pattern 225. The first wiring pattern 210 and the second wiring pattern 220 may be disposed at a second metal level higher than the first metal level.

[0066] The first wiring pattern 210 may extend in the second direction D2. The first via pattern 215 may be disposed between the first wiring pattern 210 and the first conductive lower pattern 110. The first wiring pattern 210 may be disposed on the first via pattern 215. The first via pattern 215 connects the first conductive lower pattern 110 and the first wiring pattern 210.

[0067] The second wiring pattern 220 may extend in the second direction D2. The second wiring pattern 220 may be spaced apart from the first wiring pattern 210 in the first direction D1. Although not shown, a second via pattern 225 may be disposed between the second wiring pattern 220 and the second conductive lower pattern 120. The second wiring pattern 220 may be disposed on the second via pattern 225. The second via pattern 225 connects the second conductive lower pattern 120 and the second wiring pattern 220.

[0068] The structure of the second upper wiring structure 220ST may be substantially the same as that of the first upper wiring structure 210ST. The following description may focus on the first wiring pattern 210 and the first via pattern 215 included in the first upper wiring structure 210ST. The content of the second wiring pattern 220 may be substantially the same as the description of the first wiring pattern 210 below. The content of the second via pattern 225 may be substantially the same as the description of the first via pattern 215 below.

[0069] The first via pattern 215 may be disposed on the first conductive lower pattern 110. The first via pattern 215 may be disposed inside the first etch stop film 155 and the second interlayer insulating film 160. The first via pattern 215 passes through the first etch stop film 155 or extends into the first etch stop film 155 and may be electrically connected to the first conductive lower pattern 110.

[0070] The first via pattern 215 may include an upper surface 215US and a bottom surface opposite to each other in the third direction D3 . The bottom surface of the first via pattern 215 faces the first conductive lower pattern 110 .

[0071] In the semiconductor device according to some embodiments, an upper surface 215US of the first via pattern may be lower than an upper surface 160US of the second interlayer insulating film based on an upper surface of the first conductive lower pattern 110. A distance between an upper surface of the first conductive lower pattern 110 and an upper surface 215US of the first via pattern may be smaller than a distance between an upper surface of the first conductive lower pattern 110 and an upper surface 160US of the second interlayer insulating film.

[0072] For example, the first via pattern 215 may have a single film structure. The first via pattern 215 may not be Figure 2 and Figure 3 The first via pattern 215 may include a multi-film structure including materials different from each other like the first conductive lower pattern 110. The first via pattern 215 may be formed of one conductive material. The first via pattern 215 may have a single conductive film structure.

[0073] The first via pattern 215 may include a metal. The first via pattern 215 may include, for example, one of tungsten (W), molybdenum (Mo), cobalt (Co), and ruthenium (Ru). For example, when the first via pattern 215 includes molybdenum (Mo), the first via pattern 215 may have a single film structure formed of molybdenum. Here, the single film structure formed of molybdenum does not mean a structure formed only of molybdenum. When the first via pattern 215 including molybdenum is formed, various impurities may flow into the first via pattern 215. That is, impurities may be included in the single film structure formed of molybdenum.

[0074] The first wiring pattern 210 may be disposed on the first via pattern 215 and the second interlayer insulating film 160. The first wiring pattern 210 is connected to an upper surface 215US of the first via pattern.

[0075] The first wiring pattern 210 may be disposed inside the second etch stopper film 165 and the third interlayer insulating film 170. A portion of the first wiring pattern 210 may enter the second interlayer insulating film 160. The first wiring pattern 210 may be in contact with the third interlayer insulating film 170. The first wiring pattern 210 may be in contact with the upper surface 160US of the second interlayer insulating film.

[0076] The first wiring pattern 210 may include a first lower metal wiring 210BM and a first upper metal wiring 210UM stacked in the third direction D3. The first lower metal wiring 210BM and the first upper metal wiring 210UM may each extend in the second direction D2.

[0077] The first lower metal wiring 210BM may be disposed between the first upper metal wiring 210UM and the first via pattern 215. The first lower metal wiring 210BM may be disposed on an upper surface 215US of the first via pattern and an upper surface 160US of the second interlayer insulating film.

[0078] The first lower metal wiring 210BM may be in contact with the upper surface 215US of the first via pattern. The first lower metal wiring 210BM may be in contact with the upper surface 160US of the second interlayer insulating film. Since the upper surface 215US of the first via pattern is lower than the upper surface 160US of the second interlayer insulating film in the third direction D3, a portion of the first lower metal wiring 210BM may enter the second interlayer insulating film 160 or extend into the second interlayer insulating film 160.

[0079] The first upper metal wiring 210UM may be disposed on the first lower metal wiring 210BM. The first upper metal wiring 210UM may be disposed inside the third interlayer insulating film 170 .

[0080] The first upper metal wiring 210UM includes an upper surface 210UM_US and a bottom surface 210UM_BS opposite to each other in the third direction D3. The bottom surface 210UM_BS of the first upper metal wiring may face the first via pattern 215. The first lower metal wiring 210BM may be disposed between the upper surface 215US of the first via pattern and the bottom surface 210UM_BS of the first upper metal wiring.

[0081] The width W12 of the bottom surface 210UM_BS of the first upper metal wiring in the first direction D1 may be different from the width W11 of the upper surface 210UM_US of the first upper metal wiring in the first direction D1. For example, the width W12 of the bottom surface 210UM_BS of the first upper metal wiring in the first direction D1 may be smaller than the width W11 of the upper surface 210UM_US of the first upper metal wiring in the first direction D1.

[0082] Although the upper surface 210UM_US of the first upper metal wiring is shown as a plane, this is only for convenience of explanation and embodiments are not limited thereto. In one variation, the upper surface 210UM_US of the first upper metal wiring may include a convex curved surface.

[0083] The first wiring pattern 210 may include a sidewall 210SW extending in the third direction D3. The sidewall 210SW of the first wiring pattern may be defined by the first lower metal wiring 210BM and the first upper metal wiring 210UM. The sidewall 210SW of the first wiring pattern may include a sidewall 210UM_S of the first upper metal wiring and a sidewall 210BM_S of the first lower metal wiring. The sidewall 210UM_S of the first upper metal wiring connects the bottom surface 210UM_BS of the first upper metal wiring and the upper surface 210UM_US of the first upper metal wiring.

[0084] In a semiconductor device according to some embodiments, the first lower metal wiring 210BM may extend along a bottom surface 210UM_BS of the first upper metal wiring. The first lower metal wiring 210BM does not extend along a sidewall 210UM_S of the first upper metal wiring.

[0085] The third interlayer insulating film 170 may be in contact with the first upper metal wiring 210UM. For example, the third interlayer insulating film 170 may be in contact with the sidewall 210UM_S of the first upper metal wiring. Although not shown, a metal oxide in an oxidized form of the metal contained in the first upper metal wiring 210UM may be provided along a boundary between the third interlayer insulating film 170 and the first upper metal wiring 210UM.

[0086] The first lower metal wiring 210BM and the first upper metal wiring 210UM may each have a single conductive film structure. The first lower metal wiring 210BM and the first upper metal wiring 210UM may each include a metal. The first lower metal wiring 210BM may include a metal different from the first upper metal wiring 210UM. The first lower metal wiring 210BM may include a metal different from the first via pattern 215 having a single conductive film structure.

[0087] The first lower metal wiring 210BM and the first upper metal wiring 210UM may each include, for example, one of tungsten (W), molybdenum (Mo), cobalt (Co), and ruthenium (Ru). As an example, the first lower metal wiring 210BM may include one of tungsten (W), cobalt (Co), and ruthenium (Ru), and the first upper metal wiring 210UM may include molybdenum (Mo), but the embodiment is not limited thereto.

[0088] In the semiconductor device according to some embodiments, the thickness t11 of the first lower metal wiring 210BM on the upper surface 215US of the first via pattern may be different from the thickness t12 of the first lower metal wiring 210BM on the upper surface 160US of the second interlayer insulating film. For example, the thickness t11 of the first lower metal wiring 210BM on the upper surface 215US of the first via pattern may be greater than the thickness t12 of the first lower metal wiring 210BM on the upper surface 160US of the second interlayer insulating film.

[0089] In other words, the first wiring pattern 210 may include a first portion 210P1 and a second portion 210P2. The first portion 210P1 of the first wiring pattern may overlap with the upper surface 215US of the first via pattern in the third direction D3. The second portion 210P2 of the first wiring pattern may not overlap with the upper surface 215US of the first via pattern in the third direction D3.

[0090] The thickness t11 of the first lower metal wiring 210BM in the first portion 210P1 of the first wiring pattern may be different from the thickness t12 of the first lower metal wiring 210BM in the second portion 210P2 of the first wiring pattern. The thickness t11 of the first lower metal wiring 210BM in the first portion 210P1 of the first wiring pattern may be greater than the thickness t12 of the first lower metal wiring 210BM in the second portion 210P2 of the first wiring pattern.

[0091] During the formation of the first lower metal wiring 210BM, the thickness of the first lower metal wiring 210BM may vary depending on which material the first lower metal wiring 210BM is formed on. Assume that the first lower metal wiring 210BM may include ruthenium (Ru). When forming the first lower metal wiring 210BM, the thickness of the ruthenium film formed on the upper surface 215US of the first via pattern may be different from the thickness of the ruthenium film formed on the upper surface 160US of the second interlayer insulating film.

[0092] Figures 5 to 7 is a diagram of a semiconductor device according to some embodiments. For ease of explanation, the description will focus on the use of Figures 1 to 4 The points described are different.

[0093] For reference, Figure 6 and Figure 7 yes Figure 5 A magnified view of section Q.

[0094] Reference Figures 5 to 7 , in the semiconductor device according to some embodiments, the first lower metal wiring 210BM may extend along the bottom surface 210UM_BS of the first upper metal wiring and the sidewall 210UM_S of the first upper metal wiring.

[0095] For example, the first lower metal wiring 210BM may extend upward to the upper surface 210UM_US of the first upper metal wiring. The sidewall 210SW of the first wiring pattern may be defined by the first lower metal wiring 210BM.

[0096] exist Figure 6 In the embodiment, a thickness t12 of the first lower metal wiring 210BM between a bottom surface 210UM_BS of the first upper metal wiring and an upper surface 160US of the second interlayer insulating film may be equal to a thickness t13 of the first lower metal wiring 210BM on a sidewall 210UM_S of the first upper metal wiring.

[0097] exist Figure 7 In the embodiment, a thickness t12 of the first lower metal wiring 210BM between a bottom surface 210UM_BS of the first upper metal wiring and an upper surface 160US of the second interlayer insulating film may be greater than a thickness t13 of the first lower metal wiring 210BM on a sidewall 210UM_S of the first upper metal wiring.

[0098] Figure 8 and Fig. 9 is a diagram of a semiconductor device according to some embodiments. Fig.10 is a diagram of a semiconductor device according to some embodiments. For ease of explanation, the description will focus on the use of Figures 1 to 4 The points described are different.

[0099] Reference Figure 8 and Fig. 9 In the semiconductor device according to some embodiments, the third interlayer insulating film 170 may include a wiring insulating liner 170LI and a filling interlayer insulating film 170FI.

[0100] The wiring insulation liner 170LI may be disposed on the second etch stop film 165. The wiring insulation liner 170LI may extend along the upper surface 160US of the second interlayer insulation film and the sidewall 210SW of the first wiring pattern. The wiring insulation liner 170LI may extend along the sidewall 210UM_S of the first upper metal wiring. The second etch stop film 165 may be disposed between the wiring insulation liner 170LI and the second interlayer insulation film 160.

[0101] The filling interlayer insulating film 170FI may be disposed on the wiring insulation liner 170LI. The filling interlayer insulating film 170FI may fill or be in a space defined by the wiring insulation liner 170LI.

[0102] The wiring insulation pad 170LI may include, for example, but not limited to, one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon carbon nitride (SiCN), and silicon oxycarbide (SiOC). The filling interlayer insulation film 170FI may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0103] Reference Fig.10 In the semiconductor device according to some embodiments, the second interlayer insulating film 160 may include a second lower interlayer insulating film 160B and a second upper interlayer insulating film 160U.

[0104] The second upper interlayer insulating film 160U may be disposed on the second lower interlayer insulating film 160B. The second upper interlayer insulating film 160U may be disposed between the second lower interlayer insulating film 160B and the second etch stop film 165. The second upper interlayer insulating film 160U may include an upper surface 160US of the second interlayer insulating film.

[0105] For example, the first lower metal wiring 210BM may be in contact with the second upper interlayer insulating film 160U.

[0106] The second lower interlayer insulating film 160B may include, for example, a low dielectric constant material having a dielectric constant smaller than that of silicon oxide. The second upper interlayer insulating film 160U may include, for example, at least one of silicon oxide and aluminum oxide.

[0107] Fig.11 is a diagram of a semiconductor device according to some embodiments. For ease of description, the following will mainly describe Figures 1 to 4 , Figure 8 and Fig. 9 The points described are different.

[0108] Reference Fig.11 , in the semiconductor device according to some embodiments, the third interlayer insulating film 170 may include an inter-wiring air gap 170AG.

[0109] The inter-wiring air gap 170AG may be disposed between the first and second wiring patterns 210 and 220 adjacent to each other in the first direction D1. For example, the filling interlayer insulating film 170FI may include the inter-wiring air gap 170AG.

[0110] Figure 12 to Figure 14 is a diagram for explaining a semiconductor device according to some embodiments. For ease of explanation, the description will focus on the use of Figures 1 to 4 The points described are different.

[0111] For reference, Fig.14 yes Fig.12 An enlarged view of portion R of FIG.

[0112] Reference Figure 12 to Figure 14 In the semiconductor device according to some embodiments, the distance between the upper surface of the first conductive lower pattern 110 and the upper surface 215US of the first via pattern may be substantially the same as the distance between the upper surface of the first conductive lower pattern 110 and the upper surface 160US of the second interlayer insulating film.

[0113] Based on the upper surface of the first conductive lower pattern 110 , an upper surface 215US of the first via pattern may be no lower than an upper surface 160US of the second interlayer insulating film.

[0114] For example, thickness t11 of first lower metal wiring 210BM on upper surface 215US of first via pattern may be the same as thickness t12 of first lower metal wiring 210BM on upper surface 160US of second interlayer insulating film. Here, "same thickness" means not only the case where the thickness is exactly the same at two locations being compared, but also a slight thickness difference that may occur due to process margin, etc.

[0115] In some embodiments, the second etch stop film ( Figure 2 and Figure 3 The upper surface 165 of the second interlayer insulating film is not disposed between the second interlayer insulating film 160 and the third interlayer insulating film 170. The third interlayer insulating film 170 may be in contact with the upper surface 160US of the second interlayer insulating film.

[0116] The third interlayer insulating film 170 may include a wiring insulating pad 170LI and a filling interlayer insulating film 170FI. The wiring insulating pad 170LI may extend along the upper surface 160US of the second interlayer insulating film and the sidewall 210SW of the first wiring pattern. The wiring insulating pad 170LI may contact the upper surface 160US of the second interlayer insulating film. The filling interlayer insulating film 170FI may be disposed on the wiring insulating pad 170LI.

[0117] In a variation, the filling interlayer insulating film 170FI may include an inter-wiring air gap 170AG, such as Fig.11 shown.

[0118] The width W13 of the first lower metal wiring 210BM in the first direction D1 may be the same as the width W12 of the bottom surface 210UM_BS of the first upper metal wiring in the first direction D1. For example, the width W13 of the first lower metal wiring 210BM in the first direction D1 may be the width of the first lower metal wiring 210BM bordering the first upper metal wiring 210UM or at least partially surrounding the first upper metal wiring 210UM. In other words, the width W13 of the first lower metal wiring 210BM in the first direction D1 may be the width of the boundary surface of the first lower metal wiring 210BM in contact with the bottom surface 210UM_BS of the first upper metal wiring.

[0119] A width W11 of the first upper metal wiring 210UM in the first direction D1 may be greater than a width W13 of the first lower metal wiring 210BM in the first direction D1.

[0120] First lower metal wiring 210BM may include a bottom surface facing first via pattern 215. Although the width of the bottom surface of first lower metal wiring 210BM in first direction D1 is shown to be equal to the width of upper surface 215US of first via pattern in first direction D1, embodiments are not limited thereto.

[0121] Fig.15 and Fig.16 is a diagram of a semiconductor device according to some embodiments. Fig.17 and Fig.18 is a diagram of a semiconductor device according to some embodiments. For ease of explanation, the description will focus on the use of Figure 12 to Figure 14 The points described are different.

[0122] For reference, Fig.16 and Fig.18 yes Fig.15 and Fig.17 An enlarged view of portion R of FIG.

[0123] Reference Fig.15 and Fig.16 , in the semiconductor device according to some embodiments, a width W11 of an upper surface 210UM_US of the first upper metal wiring in the first direction D1 may be smaller than a width W12 of a bottom surface 210UM_BS of the first upper metal wiring in the first direction D1.

[0124] A width W11 of the first upper metal wiring 210UM in the first direction D1 may be smaller than a width W13 of the first lower metal wiring 210BM in the first direction D1.

[0125] Although the width of the bottom surface of the first lower metal wiring 210BM in the first direction D1 is shown to be greater than the width of the upper surface 215US of the first via pattern in the first direction D1, embodiments are not limited thereto.

[0126] Reference Fig.17 and Fig.18 , in the semiconductor device according to some embodiments, a width W13 of the first lower metal wiring 210BM in the first direction D1 is smaller than a width W12 of a bottom surface 210UM_BS of the first upper metal wiring in the first direction D1.

[0127] The first lower metal wiring 210BM may be undercut or recessed under the first upper metal wiring 210UM. A portion of a bottom surface 210UM_BS of the first upper metal wiring may be in contact with the wiring insulation liner 170LI.

[0128] In such Fig.15 and Fig.16 In the illustrated first wiring pattern 210 , the first lower metal wiring 210BM may be undercut or recessed below the first upper metal wiring 210UM.

[0129] Figures 19 to 22 is a diagram of a semiconductor device according to some embodiments. For ease of explanation, the description will focus on the use of Figures 1 to 4 The points described are different.

[0130] For reference, Fig.21 and Fig. 22 yes Fig.19 An enlarged view of portion R of FIG.

[0131] Reference Figures 19 to 22 , in the semiconductor device according to some embodiments, the first lower metal wiring 210BM may extend along a portion of the sidewall 210UM_S of the first upper metal wiring.

[0132] The first lower metal wiring 210BM does not extend upward to the upper surface 210UM_US of the first upper metal wiring. A sidewall 210SW of the first wiring pattern may be defined by the first lower metal wiring 210BM and the first upper metal wiring 210UM.

[0133] The first upper metal wiring 210UM covers or overlaps the uppermost surface 210BM-UUS of the first lower metal wiring. The first upper metal wiring 210UM may be in contact with the uppermost surface 210BM-UUS of the first lower metal wiring.

[0134] The distance between the upper surface of the first conductive lower pattern 110 and the upper surface 215US of the first via pattern may be substantially equal to the distance between the upper surface of the first conductive lower pattern 110 and the upper surface 160US of the second interlayer insulating film. Based on the upper surface of the first conductive lower pattern 110, the upper surface 215US of the first via pattern may not be lower than the upper surface 160US of the second interlayer insulating film in the third direction.

[0135] For example, the thickness t11 of the first lower metal wiring 210BM on the upper surface 215US of the first via pattern may be the same as the thickness t12 of the first lower metal wiring 210BM on the upper surface 160US of the second interlayer insulating film.

[0136] exist Fig.21 In the embodiment, a thickness t11 of the first lower metal wiring 210BM between the bottom surface 210UM_BS of the first upper metal wiring and the upper surface 215US of the first via pattern may be greater than a thickness t13 of the first lower metal wiring 210BM on the sidewall 210UM_S of the first upper metal wiring.

[0137] exist Fig. 22 In the embodiment, a thickness t11 of the first lower metal wiring 210BM on the bottom surface 210UM_BS of the first upper metal wiring may be the same as a thickness t13 of the first lower metal wiring 210BM on the sidewall 210UM_S of the first upper metal wiring.

[0138] Fig.23 is a diagram of a semiconductor device according to some embodiments. For ease of description, the following will mainly describe Figures 19 to 22 The points described are different.

[0139] Reference Fig.23 In the semiconductor device according to some embodiments, the third interlayer insulating film 170 may include a wiring insulating liner 170LI and a filling interlayer insulating film 170FI.

[0140] The wiring insulation liner 170LI may extend along the upper surface 160US of the second interlayer insulation film and the sidewall 210SW of the first wiring pattern. The wiring insulation liner 170LI may contact the second etch stopper film 165. The filling interlayer insulation film 170FI may be disposed on the wiring insulation liner 170LI.

[0141] Fig.24 and Fig.25 is a diagram of a semiconductor device according to some embodiments. For ease of explanation, the description will focus on the use of Figures 1 to 4 The points described are different.

[0142] Reference Fig.24 and25 , in the semiconductor device according to some embodiments, a width W1 of the first wiring pattern 210 in the first direction D1 may be smaller than a width W2 of the second wiring pattern 220 in the first direction D1.

[0143] The first wiring pattern 210 will be described as an example. The width W1 of the first wiring pattern 210 in the first direction D1 may be the width of an upper surface of the first wiring pattern 210 in the first direction D1.

[0144] The first wiring pattern 210 may include a first lower metal wiring 210BM and a first upper metal wiring 210UM. The second wiring pattern 220 may include only the first upper metal wiring 210UM without including the first lower metal wiring 210BM. When the first wiring pattern 210 and the second wiring pattern 220 have different widths, the first wiring pattern 210 and the second wiring pattern 220 may have different metal stack structures from each other.

[0145] Fig.26 and Fig. 27 are diagrams of semiconductor devices according to some embodiments. For ease of explanation, the description will focus on the use of Figures 1 to 4 The points described are different.

[0146] Reference Fig.26 In the semiconductor device according to some embodiments, the first via pattern 215 may include a via barrier film 215 a and a via filling film 215 b .

[0147] The via filling film 215b may be disposed on the via barrier film 215a. The via barrier film 215a may extend along the sidewall and bottom surface of the via filling film 215b. The first via pattern 215 may have a plurality of conductive film structures. The upper surface 215 of the first via pattern may be defined by the via barrier film 215a and the via filling film 215b.

[0148] The description of materials that may be included in the via barrier film 215 a and the via filling film 215 b may be substantially the same as that of the lower wiring barrier film 110 a and the lower wiring filling film 110 b .

[0149] Reference Fig. 27 , in the semiconductor device according to some embodiments, the first conductive lower pattern 110 may have a single film structure.

[0150] For example, the first conductive lower pattern 110 may have a single conductive film structure. The first conductive lower pattern 110 may include, for example, one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, and a conductive metal carbonitride.

[0151] Fig.28 and Fig.29 are diagrams of semiconductor devices according to some embodiments. For ease of explanation, the description will focus on the use of Figures 1 to 4 The points described are different.

[0152] For reference, in Fig.28 and Fig.29 Although the structures of the first wiring pattern 210 and the first via pattern 215 are shown as Figure 2 and Figure 3 The structure of the first wiring pattern 210, the first via pattern 215 and the first conductive lower pattern 110 may be the same as that shown in FIG. Figures 1 to 27 One of the structures described.

[0153] Reference Fig.28 , the semiconductor device according to some embodiments may further include a third wiring pattern 310 and a third via pattern 315 .

[0154] The third etch stopper film 175, the fourth interlayer insulating film 180, the fourth etch stopper film 185, and the fifth interlayer insulating film 190 may be sequentially disposed on the third interlayer insulating film 170, the first wiring pattern 210, and the second wiring pattern 220. The third etch stopper film 175 may be disposed between the third interlayer insulating film 170 and the fourth interlayer insulating film 180. The fourth etch stopper film 185 may be disposed between the fourth interlayer insulating film 180 and the fifth interlayer insulating film 190.

[0155] The third via pattern 315 may be connected to the second wiring pattern 220 on the second wiring pattern 220. The third via pattern 315 may be disposed inside the third etch stopper film 175 and the fourth interlayer insulating film 180. In one modification, the third via pattern 315 may be connected to the first wiring pattern 210 on the first wiring pattern 210.

[0156] Taking the upper surface of the second wiring pattern 220 as a reference, the upper surface 315US of the third via pattern may be lower than the upper surface 180US of the fourth interlayer insulating film.

[0157] The third wiring pattern 310 may be disposed on the third via pattern 315 and the fourth interlayer insulating film 180 . The third wiring pattern 310 is connected to an upper surface 315US of the third via pattern. The third wiring pattern 310 may be disposed inside the fourth etch stopper film 185 and the fifth interlayer insulating film 190 .

[0158] The third wiring pattern 310 may include a second lower metal wiring 310BM and a second upper metal wiring 310UM stacked in the third direction D3. The second lower metal wiring 310BM and the second upper metal wiring 310UM may each extend in the first direction D1.

[0159] The description of the third wiring pattern 310 and the third via pattern 315 can be similar to that using Figures 1 to 4 Description of the first wiring pattern 210 and the first via pattern 215 described. Since the description of the first wiring pattern 210 and the first via pattern 215 can be applied to the third wiring pattern 310 and the third via pattern 315, a description thereof will not be provided below.

[0160] In addition, although the structures of the third wiring pattern 310 and the third via pattern 315 are shown as being the same as those using Figures 1 to 4 The structures of the first wiring pattern 210 and the first via pattern 215 described above are the same, but the embodiment is not limited thereto. In a variation, the structures of the third wiring pattern 310 and the third via pattern 315 may be the same as those of the first wiring pattern 210 and the first via pattern 215. Figures 5 to 25 One of the structures of the described first wiring pattern 210 and the first via pattern 215 is the same.

[0161] Reference Fig.29 , the semiconductor device according to some embodiments may further include a third upper wiring structure 310ST connected to the second wiring pattern 220 .

[0162] A third etch stopper film 175 and a fourth interlayer insulating film 180 may be sequentially disposed on the third interlayer insulating film 170 , the first wiring patterns 210 , and the second wiring patterns 220 .

[0163] The third upper wiring structure 310ST may include a wiring portion extending in the first direction D1 and a via portion connecting the wiring portion and the second wiring pattern 220 .

[0164] The third upper wiring structure 310ST may include an upper wiring barrier film 310a and an upper wiring filling film 310b. The upper wiring filling film 310b may be disposed on the upper wiring barrier film 310a. The via portion of the third upper wiring structure 310ST may include a portion of the upper wiring barrier film 310a and a portion of the upper wiring filling film 310b. The wiring portion of the third upper wiring structure 310ST may include a remaining portion of the upper wiring barrier film 310a and a remaining portion of the upper wiring filling film 310b.

[0165] The description of materials that may be included in the upper wiring barrier film 310 a and the upper wiring filling film 310 b may be substantially the same as that of the lower wiring barrier film 110 a and the lower wiring filling film 110 b .

[0166] In one modification, the third upper wiring structure 310ST may be connected to the first wiring pattern 210 on the first wiring pattern 210 .

[0167] Fig.30 is a diagram of a semiconductor device according to some embodiments.

[0168] For reference, Fig.30 An example diagram taken along the first gate electrode GE is shown. Fig.30 In the embodiment, the first gate electrode GE can be Figures 1 to 25 The fin pattern AF extends in the first direction D1 or may extend in the second direction D2. When the first gate electrode GE extends in the second direction D2, the fin pattern AF extends in the first direction D1 intersecting the first gate electrode GE.

[0169] Reference Fig.30 , a semiconductor device according to some embodiments may include a transistor TR disposed between the substrate 10 and the first via pattern 215 .

[0170] The substrate 10 may be a silicon substrate or a silicon on insulator (SOI). In contrast, the substrate 10 may include, but is not limited to, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0171] The transistor TR has a fin pattern AF, a first gate electrode GE on the fin pattern AF, and a first gate insulating film GI between the fin pattern AF and the first gate electrode GE.

[0172] Although not shown, the transistor TR may include source / drain patterns disposed on both sides of the first gate electrode GE.

[0173] The fin pattern AF may protrude or extend from the substrate 10. The fin pattern AF may extend in one direction. The fin pattern AF1 may be a portion of the substrate 10 and may include an epitaxial layer grown from the substrate 10. The fin pattern AF may include, for example, silicon or germanium as an elemental semiconductor material. In addition, the fin pattern AF may include a compound semiconductor and may include, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0174] The IV-IV compound semiconductor may include, for example, a binary compound or a ternary compound including at least two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound obtained by doping these elements with a group IV element. The III-V compound semiconductor may be, for example, at least one of a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) as group III elements with one of phosphorus (P), arsenic (As), and antimony (Sb) as group V elements.

[0175] The field insulating film 15 may be disposed on the substrate 10. The field insulating film 15 may be formed on a portion of a sidewall of the fin pattern AF. The fin pattern AF may protrude above an upper surface of the field insulating film 15. The field insulating film 15 may include, for example, an oxide film, a nitride film, an oxynitride film, or a combined film thereof.

[0176] The first gate electrode GE may be disposed on the fin pattern AF. The first gate electrode GE may extend in another direction intersecting with one direction in which the fin pattern AF extends. The first gate electrode GE may intersect with the fin pattern AF.

[0177] The first gate electrode GE may include, for example, at least one of metal, conductive metal nitride, conductive metal carbonitride, conductive metal carbide, metal silicide, a doped semiconductor material, conductive metal oxynitride, and conductive metal oxide.

[0178] The first gate insulating film GI may be disposed between the first gate electrode GE and the fin pattern AF and between the first gate electrode GE and the field insulating film 15. The first gate insulating film GI may include, for example, silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a dielectric constant greater than that of silicon oxide. The high dielectric constant material may include, for example, at least one of boron nitride, metal oxide, and metal silicon oxide.

[0179] The semiconductor device according to some embodiments may include an NC (Negative Capacitance) FET using a negative capacitor.For example, the first gate insulating film GI may include a ferroelectric material film having ferroelectric characteristics and a paraelectric material film having paraelectric characteristics.

[0180] The ferroelectric material film may have a negative capacitance, and the paraelectric material film may have a positive capacitance. For example, if two or more capacitors are connected in series and the capacitance of each capacitor has a positive value, the total capacitance is reduced from the capacitance of each individual capacitor. On the other hand, if at least one of the capacitances of the two or more capacitors connected in series has a negative value, the total capacitance may be greater than the absolute value of each individual capacitance while having a positive value.

[0181] When a ferroelectric material film having negative capacitance is connected in series with a paraelectric material film having positive capacitance, the total capacitance value of the ferroelectric material film and the paraelectric material film connected in series can be increased. By using the increased total capacitance value, a transistor including the ferroelectric material film can have a subthreshold swing (SS) of less than 60mV / decade at room temperature.

[0182] The ferroelectric material film may have ferroelectric properties. The ferroelectric material film may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, the hafnium zirconium oxide may be a material obtained by doping hafnium oxide with zirconium (Zr). As another example, the hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0183] The ferroelectric material film may also include doped dopants. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant included in the ferroelectric material film may vary depending on which type of ferroelectric material is included in the ferroelectric material film.

[0184] When the ferroelectric material film includes hafnium oxide, the dopant included in the ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0185] When the dopant is aluminum (Al), the ferroelectric material film may include 3 to 8 at % (atomic %) of aluminum. Here, the ratio of the dopant may be a ratio of the dopant to the sum of hafnium and the dopant.

[0186] When the dopant is silicon (Si), the ferroelectric material film may include 2 to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material film may include 2 to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may include 1 to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may include 50 to 80 at% zirconium.

[0187] The paraelectric material film may have paraelectric properties. The paraelectric material film may include, for example, at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide.

[0188] The ferroelectric material film and the paraelectric material film may include the same material. The ferroelectric material film has ferroelectric properties, but the paraelectric material film may not have ferroelectric properties. For example, when the ferroelectric material film and the paraelectric material film include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material film is different from the crystal structure of the hafnium oxide included in the paraelectric material film.

[0189] The ferroelectric material film may have a thickness that exhibits ferroelectric properties. The thickness of the ferroelectric material film may be, for example, 0.5 to 10 nm. Since the thickness that exhibits ferroelectric properties may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

[0190] As an example, the first gate insulating film GI may include a ferroelectric material film. As another example, the first gate insulating film GI may each include a plurality of ferroelectric material films spaced apart from each other. The first gate insulating film GI may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0191] The gate capping pattern GE_CAP may be disposed on the first gate electrode GE. In one variation, the gate capping pattern GE_CAP may not be disposed on the first gate electrode GE.

[0192] The first via pattern 215 and the first wiring pattern 210 may be disposed on the first gate electrode GE. Although the first via pattern 215 is shown as not connected to the first gate electrode GE, the present disclosure is not limited thereto. In one variation, the first via pattern 215 may be connected to the first gate electrode GE.

[0193] Unlike the example shown, the first conductive lower pattern ( Figure 2 and Figure 3 110) and a second conductive lower pattern 120 may be further disposed between the first via pattern 215 and the first gate electrode GE.

[0194] Since the description of the first via pattern 215 and the first wiring pattern 210 can be the same as that of the first via pattern 215 and the first wiring pattern 210, Figures 1 to 25 The descriptions are basically the same, so no description will be provided below.

[0195] Fig.31 is a diagram of a semiconductor device according to some embodiments. For ease of description, the following will mainly describe Fig.30 The points described are different.

[0196] Reference Fig.31 In a semiconductor device according to some embodiments, the transistor TR may include a nanosheet NS, a first gate electrode GE at least partially surrounding the nanosheet NS, and a first gate insulating film GI between the nanosheet NS and the first gate electrode GE.

[0197] The nanosheet NS may be disposed on the lower fin pattern BAF. The nanosheet NS may be disposed in the third direction ( Figure 2 The transistor TR is shown as including three nanosheets NS spaced apart in the third direction D3, but the embodiment is not limited thereto. It goes without saying that the number of nanosheets NS disposed on the lower fin pattern BAF in the third direction D3 may be greater than three or less than three.

[0198] The lower fin pattern BAF and the nanosheet NS may each include, for example, silicon or germanium, which is an elemental semiconductor material. The lower fin pattern BAF and the nanosheet NS may each include a compound semiconductor, and may include, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor. The lower fin pattern BAF and the nanosheet NS may include the same material or may include different materials.

[0199] Figure 32 to Figure 34 is a diagram of a semiconductor device according to some embodiments. For reference, Fig.32 is a top view of a semiconductor device according to some embodiments. Fig.33 is along Fig.32 A cross-sectional view taken along lines CC and DD. Fig.34 is along Fig.32 A cross-sectional view taken from EE.

[0200] Reference Figure 32 to Figure 34 , a logic cell LC may be provided on the substrate 10. The logic cell LC may refer to a logic element (eg, an inverter, a flip-flop, etc.) that performs a specific function. The logic cell LC may include vertical transistors (vertical FETs) constituting the logic element and wiring that connects the vertical transistors together.

[0201] The logic cell LC on the substrate 10 may include a first active region RX1 and a second active region RX2. For example, the first active region RX1 may be a PMOSFET region, and the second active region RX2 may be an NMOSFET region. The first active region RX1 and the second active region RX2 may be defined by a trench T_CH formed in an upper portion of the substrate 10. The first active region RX1 and the second active region RX2 may be spaced apart from each other in the first direction D1.

[0202] The first lower epitaxial pattern SPO1 may be provided on the first active region RX1, and the second lower epitaxial pattern SPO2 may be provided on the second active region RX2. From a planar viewpoint, the first lower epitaxial pattern SPO1 may overlap with the first active region RX1, and the second lower epitaxial pattern SPO2 may overlap with the second active region RX2. The first lower epitaxial pattern SPO1 and the second lower epitaxial pattern SPO2 may be epitaxial patterns formed by a selective epitaxial growth process. The first lower epitaxial pattern SPO1 may be provided in the first recessed region RS1 of the substrate 10, and the second lower epitaxial pattern SPO2 may be provided in the second recessed region RS2 of the substrate 10.

[0203] The first active pattern AP1 may be provided on the first active region RX1, and the second active pattern AP2 may be provided on the second active region RX2. Each of the first active pattern AP1 and the second active pattern AP2 may have a vertically protruding fin shape. From a plane viewpoint, each of the first active pattern AP1 and the second active pattern AP2 may have a bar shape extending in the first direction D1. The first active pattern AP1 may be arranged along the second direction D2, and the second active pattern AP2 may be arranged along the second direction D2.

[0204] Each first active pattern AP1 may include a first channel pattern CHP1 vertically protruding or extending from a first lower epitaxial pattern SPO1 and a first upper epitaxial pattern DOP1 on the first channel pattern CHP1. Each second active pattern AP2 may include a second channel pattern CHP2 vertically protruding or extending from a second lower epitaxial pattern SPO2 and a second upper epitaxial pattern DOP2 on the second channel pattern CHP2.

[0205] An element isolation film ST may be provided on the substrate 10 to fill the trench T_CH or in the trench T_CH. The element isolation film ST may cover or overlap upper surfaces of the first and second lower epitaxial patterns SPO1 and SPO2. The first and second active patterns AP1 and AP2 may protrude vertically onto the element isolation film ST.

[0206] A plurality of second gate electrodes 420 extending parallel to each other in the first direction D1 may be provided on the element isolation film ST. The second gate electrodes 420 may be arranged along the second direction D2. The second gate electrode 420 may at least partially surround the first channel pattern CHP1 of the first active pattern AP1, and may at least partially surround the second channel pattern CHP2 of the second active pattern AP2. For example, the first channel pattern CHP1 of the first active pattern AP1 may have first to fourth side walls SW1 to SW4. The first side wall SW1 and the second side wall SW2 may be opposite to each other in the second direction D2, and the third side wall SW3 and the fourth side wall SW4 may be opposite to each other in the first direction D1. The second gate electrode 420 may be provided on the first to fourth side walls SW1 to SW4. In other words, the second gate electrode 420 may surround the first to fourth side walls SW1 to SW4.

[0207] The second gate insulating film 430 may be interposed between the second gate electrode 420 and each of the first and second channel patterns CHP1 and CHP2. The second gate insulating film 430 may cover or overlap the bottom surface of the second gate electrode 420 and the inner wall of the second gate electrode 420. For example, the second gate insulating film 430 may directly cover or overlap the first to fourth side walls SW1 to SW4 of the first active pattern AP1.

[0208] The first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2 may protrude or extend vertically above the second gate electrode 420. In the third direction, the upper surface of the second gate electrode 420 may be lower than the bottom surface of each of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. In other words, each of the first active pattern AP1 and the second active pattern AP2 may have a structure that protrudes or extends vertically from the substrate 10 and penetrates the second gate electrode 420.

[0209] The semiconductor element according to the present embodiment may include a vertical transistor in which carriers move in a third direction D3. For example, when a voltage is applied to the second gate electrode 420 and the transistor is "on", carriers may move from the lower epitaxial patterns SOP1 and SOP2 through the channel patterns CHP1 and CHP2 to the upper epitaxial patterns DOP1 and DOP2. In the semiconductor device according to some embodiments, the second gate electrode 420 may completely surround the sidewalls SW1 to SW4 of the channel patterns CHP1 and CHP2. The transistor according to the present disclosure may be a three-dimensional field effect transistor (e.g., VFET) having a gate all-around structure. Since the gate surrounds the channel, the semiconductor element according to the present disclosure may have excellent electrical characteristics.

[0210] A spacer 440 covering or overlapping the second gate electrode 420 and the first and second active patterns AP1 and AP2 may be provided on the element isolation film ST. The spacer 440 may include a silicon nitride film or a silicon oxynitride film. The spacer 440 may include a lower spacer 440LS, an upper spacer 440US, and a gate spacer 440GS between the lower spacer 440LS and the upper spacer 440US.

[0211] The lower spacer 440LS may directly cover or overlap the upper surface of the element isolation film ST. The second gate electrode 420 may be spaced apart from the element isolation film ST in the third direction D3 by the lower spacer 440LS. The gate spacer 440GS may cover or overlap the upper surface and the outer sidewall of each second gate electrode 420. The upper spacer 440US may cover or overlap the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. However, the upper spacer 440US does not cover or overlap the upper surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2, and may expose the upper surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2.

[0212] A first portion 195BP of a lower interlayer insulating film may be provided on the spacer 440. An upper surface of the first portion 195BP of the lower interlayer insulating film may be substantially coplanar with upper surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. A second portion 195UP of the lower interlayer insulating film and the second and third interlayer insulating films 160 and 170 may be sequentially stacked on the first portion 195BP of the lower interlayer insulating film. The first portion 195BP of the lower interlayer insulating film and the second portion 195UP of the lower interlayer insulating film may be included in the lower interlayer insulating film 195. The second portion 195UP of the lower interlayer insulating film may cover or overlap upper surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2.

[0213] At least one first source / drain contact 470 may be provided, which extends into or penetrates the second portion 195UP of the lower interlayer insulating film and is connected to the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. At least one second source / drain contact 570 may be provided, which sequentially extends into or penetrates the lower interlayer insulating film 195, the lower spacer 440LS, and the element isolation film ST, and is connected to the first lower epitaxial pattern SPO1 and the second lower epitaxial pattern SPO2. A gate contact 480 may be provided, which sequentially extends into or penetrates the second portion 195UP of the lower interlayer insulating film, the first portion 195BP of the lower interlayer insulating film, and the gate spacer 440GS, and is connected to the second gate electrode 420.

[0214] The first etch stopper film 155 may be further disposed between the second portion 195UP of the lower interlayer insulating film and the second interlayer insulating film 160. The second etch stopper film 165 may be disposed between the second interlayer insulating film 160 and the third interlayer insulating film 170.

[0215] The first via pattern 215 and the first wiring pattern 210 may be provided on the first source / drain contact 470, the second source / drain contact 570, and the gate contact 480. The first via pattern 215 may be connected to the first source / drain contact 470, the second source / drain contact 570, and the gate contact 480.

[0216] In a variation, an additional wiring similar to the first conductive lower pattern 110 may be further disposed, for example, between the first source / drain contact 470 and the first via pattern 215 .

[0217] The detailed description of the first via pattern 215 and the first wiring pattern 210 may be the same as that described above using Figures 1 to 25 The descriptions are basically the same.

[0218] Figure 35 to Figure 37 is an intermediate stage diagram of a method for manufacturing a semiconductor device according to some embodiments. For reference, Figure 35 to Figure 37 Can be along Figure 1 AA cross-sectional view.

[0219] Reference Fig.35 , the first conductive lower pattern 110 may be formed in the first interlayer insulating film 150 .

[0220] A first etch stopper film 155 may be sequentially formed on the first interlayer insulating film 150 and the first conductive lower pattern 110. A second interlayer insulating film 160 may be formed on the first etch stopper film 155.

[0221] A via pattern hole may be formed in the first etch stopper film 155 and the second interlayer insulating film 160. The via pattern hole may expose a portion of the first conductive lower pattern 110. A first via pattern 215 may be formed in the via pattern hole. The first via pattern 215 may be formed in the second interlayer insulating film 160.

[0222] Subsequently, a second etch stopper film 165 may be formed along an upper surface 160US of the second interlayer insulating film. A third interlayer insulating film 170 may be formed on the second etch stopper film 165.

[0223] A wiring pattern groove 210t may be formed in the third interlayer insulating film 170 and the second etch stopper film 165. The wiring pattern groove 210t may penetrate the second etch stopper film 165 or extend into the second etch stopper film 165 and expose the first via pattern 215. The wiring pattern groove 210t may extend in the second direction D2.

[0224] Reference Fig.36 , a portion of the first via pattern 215 exposed by the wiring pattern trench 210t may be removed.

[0225] Therefore, an upper surface 215US of the first via pattern may be lowered. Based on the upper surface of the first conductive lower pattern 110, an upper surface 215US of the first via pattern may be lower than an upper surface 160US of the second interlayer insulating film.

[0226] Reference Fig.37 , a first lower metal wiring 210BM may be formed in the wiring pattern trench 210t.

[0227] The first lower metal wiring 210BM may partially fill the wiring pattern trench 210t or be in the wiring pattern trench 210t. The first lower metal wiring 210BM may make contact with an upper surface 215US of the first via pattern.

[0228] The thickness of the first lower metal wiring 210BM formed on the upper surface 215US of the first via pattern may be different from the thickness of the first lower metal wiring 210BM formed on the upper surface 160US of the second interlayer insulating film. For example, the first lower metal wiring 210BM may be formed using a deposition method in which the deposition thickness may vary depending on the type of material exposed in the portion in which the first lower metal wiring 210BM is deposited. That is, the thickness of the first lower metal wiring 210BM formed on the conductive material may be different from the thickness of the first lower metal wiring 210BM formed on the insulating material. In addition, the thickness of the deposited first lower metal wiring 210BM may vary depending on the type of insulating material.

[0229] Next, refer to Figure 2 , a first upper metal wiring 210UM may be formed on the first lower metal wiring 210BM. The first upper metal wiring 210UM may fill the remaining portion of the wiring pattern trench 210t. The first upper metal wiring 210UM may be formed using, for example, a bottom-up growth method. Thus, a first wiring pattern 210 including the first upper metal wiring 210UM and the first lower metal wiring 210BM may be formed.

[0230] Figures 38 to 42 is a diagram of an intermediate stage in a method for fabricating a semiconductor device according to some embodiments.

[0231] Reference Fig.38 , the first conductive lower pattern 110 may be formed in the first interlayer insulating film 150 .

[0232] A first etch stopper film 155 and a second interlayer insulating film 160 may be sequentially formed on the first interlayer insulating film 150. A first via pattern 215 may be formed in the first etch stopper film 155 and the second interlayer insulating film 160.

[0233] Subsequently, a second etch stopper film 165 and a sacrificial interlayer insulating film 170SC may be sequentially formed on the second interlayer insulating film 160. A wiring pattern groove 210t may be formed in the sacrificial interlayer insulating film 170SC and the second etch stopper film 165.

[0234] The sacrificial interlayer insulating film 170SC may include a material different from that of the second interlayer insulating film 160. For example, the second interlayer insulating film 160 may include silicon oxide, and the sacrificial interlayer insulating film 170SC may include silicon nitride, but the embodiment is not limited thereto.

[0235] Subsequently, a portion of the first via pattern 215 may be removed to reduce the height of the first via pattern 215. In the third direction, an upper surface 215US of the first via pattern may be lower than an upper surface 160US of the second interlayer insulating film.

[0236] Reference Fig.39 , a selective inhibition film 170IH may be formed along the sidewalls of the wiring pattern trench 210t and the upper surface of the sacrificial interlayer insulating film 170SC.

[0237] The selective inhibition film 170IH may not be formed on the upper surface 215US of the first via pattern and the upper surface 160US of the second interlayer insulating film. For example, the selective inhibition film 170IH may be selectively formed on the sacrificial interlayer insulating film 170SC.

[0238] The selective inhibition film 170IH includes an organic material. The selective inhibition film 170IH may prevent a conductive material from being deposited on a surface on which the selective inhibition film 170IH is formed.

[0239] Reference Fig.40 , the first lower metal wiring 210BM may be formed in the wiring pattern trench 210t in a state where the selective inhibition film 170IH is formed.

[0240] The first lower metal wiring 210BM may partially fill or be in the wiring pattern trench 210t. The thickness of the first lower metal wiring 210BM formed on the upper surface 215US of the first via pattern may be different from the thickness of the first lower metal wiring 210BM formed on the upper surface 160US of the second interlayer insulating film.

[0241] Reference Fig.40 and Fig.41 , the selective inhibition membrane 170IH can be removed.

[0242] Subsequently, a first upper metal wiring 210UM may be formed on the first lower metal wiring 210BM. The first wiring pattern 210 may be formed on the first via pattern 215 .

[0243] Reference Fig.41 and Fig.42 , the sacrificial interlayer insulating film 170SC can be removed.

[0244] The first wiring pattern 210 may protrude in the third direction D3 beyond the second etch stop film 165. A sidewall of the first upper metal wiring 210UM may be exposed.

[0245] Next, refer to Figure 8, a third interlayer insulating film 170 may be formed on the second etch stop film 165. The third interlayer insulating film 170 may cover or overlap the sidewalls of the first wiring pattern 210. The third interlayer insulating film 170 may include a wiring insulating liner 170LI and a filling interlayer insulating film 170FI. In a variation, the third interlayer insulating film 170 may be a single film, such as Figure 2 shown.

[0246] Figure 43 to Figure 47 is a diagram of an intermediate stage in a method for fabricating a semiconductor device according to some embodiments.

[0247] Reference Fig.43 , the first conductive lower pattern 110 may be formed in the first interlayer insulating film 150. The first etch stopper film 155 and the second interlayer insulating film 160 may be sequentially formed on the first interlayer insulating film 150. The first via pattern 215 may be formed in the first etch stopper film 155 and the second interlayer insulating film 160.

[0248] Subsequently, a lower metal wiring film 210BM_P may be formed on the second interlayer insulating film 160 and the first via pattern 215 . The lower metal wiring film 210BM_P may be formed along the upper surface 160US of the second interlayer insulating film. The lower metal wiring film 210BM_P is connected to the first via pattern 215 .

[0249] A sacrificial interlayer insulating film 170SC may be formed on the lower metal wiring film 210BM_P. For example, the sacrificial interlayer insulating film 170SC may include an insulating material.

[0250] Reference Fig.44 , a wiring pattern groove 210t may be formed in the sacrificial interlayer insulating film 170SC.

[0251] The wiring pattern groove 210t may expose the lower metal wiring film 210BM_P.

[0252] Reference Fig.44 and Fig.45 , a first upper metal wiring 210UM may be formed on the lower metal wiring film 210BM_P.

[0253] The first upper metal wiring 210UM may fill the wiring pattern trench 210t. The first upper metal wiring 210UM may be formed using, for example, a bottom-up growth method.

[0254] Reference Fig.45 and Fig.46 , the sacrificial interlayer insulating film 170SC may be removed to expose the sidewall of the first upper metal wiring 210UM.

[0255] The lower metal wiring film 210BM_P covered or overlapped by the sacrificial interlayer insulating film 170SC may be exposed.

[0256] Reference Fig.46 and Fig.47 , by using the first upper metal wiring 210UM as a mask, the lower metal wiring film 210BM_P that does not overlap with the first upper metal wiring 210UM in the third direction D3 can be removed.

[0257] The first lower metal wiring 210BM may be formed between the first upper metal wiring 210UM and the first via pattern 215 by patterning the lower metal wiring film 210BM_P. The first wiring pattern 210 may be formed on the first via pattern 215. While the first wiring pattern 210 is being formed, the second wiring pattern 220 including the first upper metal wiring 210UM and the first lower metal wiring 210BM may be formed on the second interlayer insulating film 160.

[0258] Next, a preliminary wiring insulation pad 170L_P may be formed along the upper surface 160 of the second interlayer insulation film, the sidewalls and upper surfaces of the first wiring patterns 210, and the sidewalls and upper surfaces of the second wiring patterns 220. A preliminary filling interlayer insulation film 170F_P may be formed on the preliminary wiring insulation pad 170L_P.

[0259] Subsequently, a portion of the preliminary filling interlayer insulating film 170F_P and a portion of the preliminary wiring insulating liner 170L_P may be removed using a planarization process. Upper surfaces of the first wiring patterns 210 and the second wiring patterns 220 may be exposed.

[0260] Figures 48 to 51 is an intermediate stage diagram of a method for manufacturing a semiconductor device according to some embodiments. For reference, Fig.48 It can be in Fig.43 The manufacturing process is then performed.

[0261] Reference Fig.48 , the first lower metal wiring 210BM and the sacrificial interlayer insulating pattern 170SC_P may be formed by patterning the lower metal wiring film 210BM_P and the sacrificial interlayer insulating film 170SC.

[0262] A first lower metal wiring 210BM and a sacrificial interlayer insulating pattern 170SC_P may be formed on the second interlayer insulating film 160 .

[0263] Reference Fig.49A preliminary wiring insulation pad 170L_P may be formed on an upper surface of the second interlayer insulating film 160 , a sidewall of the first lower metal wiring 210BM, and a sidewall and an upper surface of the sacrificial interlayer insulating pattern 170SC_P.

[0264] A preliminary filling interlayer insulating film 170F_P may be formed on the preliminary wiring insulating pad 170L_P.

[0265] Reference Fig.49 and Fig.50 , a portion of the preliminary filling interlayer insulating film 170F_P and a portion of the preliminary wiring insulating pad 170L_P may be removed using a planarization process.

[0266] Thus, the third interlayer insulating film 170 including the wiring insulating liner 170LI and the filling interlayer insulating film 170FI may be formed. After the planarization process is performed, the upper surface of the sacrificial interlayer insulating pattern 170SC_P may be exposed.

[0267] Reference Fig.50 and Fig.51 , the sacrificial interlayer insulating pattern 170SC_P may be removed to form a wiring pattern trench 210 t inside the third interlayer insulating film 170 .

[0268] An upper surface of the first lower metal wiring 210BM is exposed.

[0269] Subsequently, a first upper metal wiring 210UM may be formed in the wiring pattern trench 210t. The first upper metal wiring 210UM may fill the wiring pattern trench 210t or be in the wiring pattern trench 210t.

[0270] Fig.52 and Fig.53 is an intermediate stage diagram of a method for manufacturing a semiconductor device according to some embodiments. For reference, Fig.52 It can be in Fig.35 The manufacturing process is then performed.

[0271] Reference Fig.52 , a lower metal wiring film 210BM_P may be formed along the sidewall and bottom surface of the wiring pattern trench 210 t and the upper surface of the third interlayer insulating film 170 .

[0272] Then a barrier pattern 210_PI may be formed in the wiring pattern trench 210t. The barrier pattern 210_PI partially fills the wiring pattern trench 210t or is partially in the wiring pattern trench 210t. Portions of the lower metal wiring film 210BM_P not covered or overlapped by the barrier pattern 210_PI are exposed.

[0273] Reference Fig.52 and Fig.53 , a first lower metal wiring 210BM may be formed in the wiring pattern trench 210t by removing a portion of the lower metal wiring film 210BM_P.

[0274] The exposed lower metal wiring film 210BM_P may be removed by using the barrier pattern 210_PI as a mask. After forming the first lower metal wiring 210BM, the barrier pattern 210_PI may be removed.

[0275] Next, refer to Fig.19 , a first upper metal wiring 210UM may be formed on the first lower metal wiring 210BM. The first upper metal wiring 210UM may fill the remaining portion of the wiring pattern trench 210t or be in the remaining portion of the wiring pattern trench 210t.

[0276] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above-described embodiments and can be implemented in various different forms. A person skilled in the art of the present disclosure will be able to understand that the present disclosure can be implemented in other specific forms without changing the technical concept or basic features of the present disclosure. Therefore, it should be understood that the embodiments described above are not restrictive, but illustrative in all aspects.

[0277] This application claims the priority and all the benefits of Korean Patent Application No. 10-2023-0149144 filed in the Korean Intellectual Property Office on November 1, 2023 and Korean Patent Application No. 10-2023-0073486 filed in the Korean Intellectual Property Office on June 8, 2023, the contents of which are incorporated herein by reference in their entirety.

Claims

1. A semiconductor device, include: a via pattern in the first interlayer insulating film; as well as a wiring pattern extending in a first direction and on the first interlayer insulating film and the via pattern, wherein the wiring pattern includes a lower wiring and an upper wiring on the lower wiring, wherein the lower wiring and the upper wiring are stacked in a second direction, wherein the lower wiring is between the via pattern and the upper wiring and on an upper surface of the via pattern, wherein a first portion of the lower wiring is on the upper surface of the via pattern and has a first thickness, and The second portion of the lower wiring is on the upper surface of the first interlayer insulating film and has a second thickness different from the first thickness. 2 . The semiconductor device according to claim 1 , wherein the first thickness is greater than the second thickness.

3. The semiconductor device according to claim 1, in: The upper wiring includes a first metal including molybdenum (Mo), ruthenium (Ru) or tungsten (W), The lower wiring includes a second metal including ruthenium (Ru), cobalt (Co), or tungsten (W), and The first metal and the second metal are different.

4. The semiconductor device according to claim 1, further comprising: include: a second interlayer insulating film on the first interlayer insulating film, The upper wiring is in the second interlayer insulating film and contacts the second interlayer insulating film. 5 . The semiconductor device according to claim 1 , wherein in the second direction, the upper surface of the via pattern is lower than the upper surface of the first interlayer insulating film.

6. The semiconductor device according to claim 1, in: The upper wiring includes a bottom surface facing the via pattern and a side wall extending in the second direction, and The lower wiring extends along the bottom surface of the upper wiring and the sidewall of the upper wiring.

7. The semiconductor device according to claim 1, in: the first interlayer insulating film includes a first lower interlayer insulating film and a first upper interlayer insulating film on the first lower interlayer insulating film, The lower wiring contacts the first upper interlayer insulating film, The first upper interlayer insulating film includes silicon oxide, and The first lower interlayer insulating film includes a material having a dielectric constant smaller than that of silicon oxide.

8. The semiconductor device according to claim 1, further comprising a second interlayer insulating film on the first interlayer insulating film, wherein the second interlayer insulating film include: a wiring insulating pad extending along the upper surface of the first interlayer insulating film and the side wall of the wiring pattern, and A filling interlayer insulating film is formed on the wiring insulating pad.

9. A semiconductor device, include: a via pattern in the first interlayer insulating film; a wiring pattern extending in a first direction and on the first interlayer insulating film and the via pattern, wherein the wiring pattern includes a lower wiring and an upper wiring on the lower wiring, and wherein the lower wiring and the upper wiring are stacked in a second direction; as well as a second interlayer insulating film on the first interlayer insulating film, wherein the second interlayer insulating film includes a wiring insulating pad extending along a side wall of the wiring pattern and an upper surface of the first interlayer insulating film, and wherein the second interlayer insulating film includes a filling interlayer insulating film on the wiring insulating pad, wherein the upper wiring includes an upper surface and a bottom surface opposite to each other in the second direction, wherein the upper wiring includes a side wall, the side wall contacting the upper surface of the upper wiring and the bottom surface of the upper wiring, wherein the lower wiring is between the upper surface of the via pattern and the bottom surface of the upper wiring, wherein the lower wiring contacts the upper surface of the via pattern, and The lower wiring does not extend along the side wall of the upper wiring. 10 . The semiconductor device according to claim 9 , wherein a width of the upper surface of the upper wiring in the third direction is smaller than a width of the bottom surface of the upper wiring in the third direction. 11 . The semiconductor device according to claim 9 , wherein a width of the upper surface of the upper wiring in a third direction is greater than a width of the bottom surface of the upper wiring in the third direction. 12 . The semiconductor device according to claim 9 , wherein a width of the lower wiring in a third direction is smaller than a width of the bottom surface of the upper wiring in the third direction. 13 . The semiconductor device according to claim 9 , wherein a width of the lower wiring in a third direction is the same as a width of the bottom surface of the upper wiring in the third direction.

14. The semiconductor device according to claim 9, in: The upper wiring includes a first metal, and the first metal includes one of molybdenum (Mo), ruthenium (Ru), and tungsten (W). The lower wiring includes a second metal including one of ruthenium (Ru), cobalt (Co), and tungsten (W), and The first metal and the second metal are different.

15. The semiconductor device according to claim 9, wherein the filling interlayer insulating film defines an air gap. 16 . The semiconductor device according to claim 9 , wherein the wiring insulation pad contacts the upper surface of the first interlayer insulating film.

17. A semiconductor device, include: a via pattern in the first interlayer insulating film; as well as a wiring pattern extending in a first direction and on the first interlayer insulating film and the via pattern, wherein the wiring pattern includes a lower wiring and an upper wiring on the lower wiring, and wherein the lower wiring and the upper wiring are stacked in a second direction, wherein the upper wiring includes an upper surface and a bottom surface opposite to each other in the second direction, wherein the upper wiring includes a side wall connecting the upper surface of the upper wiring and the bottom surface of the upper wiring, wherein the lower wiring is between the upper surface of the via pattern and the bottom surface of the upper wiring, wherein the lower wiring contacts the upper surface of the via pattern, wherein the lower wiring includes a first portion extending along a portion of the side wall of the upper wiring and a second portion extending along the bottom surface of the upper wiring, and wherein the upper wiring overlaps with an uppermost surface of the lower wiring in the second direction. 18 . The semiconductor device according to claim 17 , wherein a thickness of the second portion is greater than a thickness of the first portion.

19. The semiconductor device according to claim 17, further comprising a second interlayer insulating film on the first interlayer insulating film, wherein the second interlayer insulating film include: a wiring insulating pad extending along an upper surface of the first interlayer insulating film and the side wall of the upper wiring, and A filling interlayer insulating film is formed on the wiring insulating pad.

20. The semiconductor device according to claim 17, in: The upper wiring includes a first metal including molybdenum (Mo), ruthenium (Ru) or tungsten (W), The lower wiring includes a second metal including ruthenium (Ru), cobalt (Co), or tungsten (W), and The first metal and the second metal are different.

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