Bonding structure, semiconductor device, and method of manufacturing semiconductor device

Abstract

The embodiment of the invention relates to a bonding structure, a semiconductor device and a method of manufacturing the semiconductor device. A bond structure for hybrid wafer bonding may include a plurality of bond pads and a bond insulating layer. The bond insulating layer may be configured to electrically isolate the bond pads from each other. The bond insulating layer may include at least one dielectric layer and a vertical expansion inducing layer disposed on the dielectric layer. The vertical expansion inducing layer includes a hardness greater than a hardness of the dielectric layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Application No. 10-2023-0073129 filed on June 7, 2023, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments generally relate to a bonding structure for hybrid wafer bonding, a semiconductor device including the bonding structure, and a method of manufacturing a semiconductor device. Background Art

[0004] Hybrid wafer bonding may be a three-dimensional stacking technology that directly bonds two wafers with integrated circuits.

[0005] Each wafer to be bonded may include a plurality of metal pads and a dielectric layer at its bonding interface, respectively. The dielectric layer of the wafer may be directly contacted by bonding force. The metal pads of the wafer may be directly contacted by thermal expansion using an annealing process. In order to allow the metal pads to fully thermally expand, the material of the dielectric layer around the metal pads, the annealing temperature, the size of the metal pads, etc. may be important. Summary of the invention

[0006] According to various embodiments, a bonding structure for hybrid wafer bonding may be provided. The bonding structure may include a plurality of bonding pads and a bonding insulation layer. The bonding insulation layer is configured to electrically isolate the bonding pads from each other. The bonding insulation layer includes at least one dielectric layer and at least one vertical expansion inducing layer on the dielectric layer. The vertical expansion inducing layer includes a hardness greater than a hardness of the dielectric layer.

[0007] According to various embodiments, a semiconductor device may be provided. The semiconductor device may include: a first bonding structure including a first bonding layer; and a second bonding structure including a second bonding layer bonded to the first bonding layer. At least one of the first bonding layer and the second bonding layer includes a plurality of bonding pads and a bonding insulating layer. The bonding insulating layer is arranged between the bonding pads. The bonding insulating layer includes an upper region adjacent to a bonding surface between the first bonding layer and the second bonding layer and a lower region below the upper region.

[0008] According to various embodiments, a semiconductor device may be provided. The semiconductor device may include a device layer and a bonding layer. The bonding layer is formed above the device layer. The bonding layer includes a bonding insulating layer and at least one bonding pad formed in the bonding insulating layer. The bonding insulating layer includes a plurality of dielectric layers stacked from the device layer toward a bonding surface. At least one of the dielectric layers adjacent to the bonding surface includes a first dielectric material, and the remaining dielectric layers include a second dielectric material, the second dielectric material including a hardness less than that of the first dielectric material.

[0009] According to various embodiments, a method for manufacturing a semiconductor device may be provided. In the method for manufacturing a semiconductor device, a first structure may be provided. The first structure may include a first bonding insulating layer and a plurality of first bonding pads. The first bonding insulating layer may include a first vertical expansion inducing layer. The first bonding pad may be formed in the first bonding insulating layer. A second structure may be provided. The second structure may include a second bonding insulating layer and a plurality of second bonding pads. The second bonding pad may be formed in the second bonding insulating layer. The first vertical expansion inducing layer of the first bonding insulating layer may be bonded to the second bonding insulating layer. The first bonding pad and the second bonding pad may be thermally expanded in a vertical direction by the first vertical expansion inducing layer to hybrid bond the first bonding pad to the second bonding pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the subject matter of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1A , Figure 1B and Figure 1C is a cross-sectional view illustrating a method of manufacturing a semiconductor device using a comparative example of a hybrid wafer bonding process;

[0012] Figure 2A is a cross-sectional view illustrating bonding structures A and B including a metal pad having a recess according to an embodiment;

[0013] Figure 2B is a cross-sectional view illustrating a semiconductor device having a disconnection according to an embodiment;

[0014] Figure 3A , Figure 3B , Figure 3C and Figure 3D are cross-sectional views illustrating various examples of first bonding structures according to various embodiments;

[0015] Figure 4 is a cross-sectional view illustrating a first engagement structure including a lower structure according to various embodiments;

[0016] Figure 5A , Figure 5B , Figure 5C and Figure 5D are cross-sectional views illustrating various embodiments of a semiconductor device including a second bonding structure and a third bonding structure having different structures according to various embodiments;

[0017] Fig. 6A , Figure 6B , Figure 6C and Fig.6D are cross-sectional views illustrating various embodiments of a semiconductor device including a second bonding structure and a fourth bonding structure according to various embodiments;

[0018] Figure 7 is a flow chart for illustrating a method of manufacturing a semiconductor device according to various embodiments;

[0019] Fig. 8A , Figure 8B , Figure 8C , Fig.8D and Fig. 8E is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to various embodiments;

[0020] Fig. 9A , Fig. 9B and Fig. 9C is a cross-sectional view illustrating a hybrid bonding method of a lower bonding structure and an upper bonding structure according to an embodiment; and

[0021] Fig.10 is a cross-sectional view illustrating a semiconductor memory device including a hybrid bonded wafer according to various embodiments. DETAILED DESCRIPTION

[0022] Various embodiments will be described in more detail with reference to the accompanying drawings. The accompanying drawings are schematic illustrations of various embodiments (and intermediate structures). In this way, due to reasons such as manufacturing technology and / or tolerances, the configuration and shape changes shown in the drawings are predictable. Therefore, the described embodiments should not be interpreted as being limited to the specific configuration and shape illustrated herein, but may include deviations from the configuration and shape of the spirit and scope of the present application as defined by the appended claims. It should be understood that when an element or layer, etc. is referred to as "on" another element or layer, etc., "connected to" another element or layer, etc., or "coupled to" another element or layer, etc., it can be directly on the other element or layer, etc., connected to the other element or layer, etc., or coupled to the other element or layer, etc., or there may be an intermediate element or layer, etc. In contrast, when an element or layer, etc. is referred to as "directly on another element or layer, etc.," "directly connected to" another element or layer, etc., or "directly coupled to" another element or layer, etc., there is no intermediate element or layer, etc. The same reference numerals throughout the text refer to the same elements. It should be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish an element from another element, and are not used to limit the element itself or to mean a specific sequence. For ease of description, spatial relative terms such as "below", "below", "below", "lower", "above", "upper", etc. can be used herein to describe the relationship between an element or feature as shown in the figure and (multiple) other elements or features. It should be understood that, in addition to the orientation depicted in the figure, spatially related terms are also intended to cover the different orientations of the device in use or operation. For example, if the device in the figure is flipped, the element described as "below" or "below" or "below" in other elements or features will be oriented to "above" other elements or features. Therefore, the example of the term "below" can cover the orientation above and below. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein are interpreted accordingly.

[0023] As used herein, the term "substrate" refers to a material to which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0024] As used herein, the term "layer" refers to a material portion including an area with a certain thickness. The layer can extend over the entire lower or upper structure, or can have a range smaller than the range of the lower or upper structure. In addition, the layer can be a region of a homogeneous or inhomogeneous continuous structure, which has a thickness smaller than the thickness of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure or between any pair of horizontal planes at the top surface and the bottom surface of the continuous structure. The layer can extend horizontally, vertically and / or along a tapered surface. The substrate can be a layer, one or more layers can be included therein, and / or one or more layers can be thereon, above and / or below it. The layer can include multiple layers. For example, the interconnect layer can include one or more conductors and contact layers (forming interconnect lines and / or through-hole contacts therein) and one or more dielectric layers.

[0025] As used herein, the term "approximately" indicates a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "approximately" may indicate a value of a given quantity that varies within a range of, for example, 10% to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0026] As used herein, a "wafer" is a piece of semiconductor material in and / or on which semiconductor devices are built, and which may undergo various manufacturing processes before being separated into die.

[0027] According to various embodiments of the present disclosure, a semiconductor device including a bonding structure is provided, the bonding structure including a bonding insulating layer and at least one pad arranged in the bonding insulating layer. The bonding insulating layer may include a vertical expansion inducing layer as a part of the bonding insulating layer. The vertical expansion inducing layer may occupy 40% to 90% of the bonding insulating layer. Compared with other materials constituting the bonding insulating layer, the vertical expansion inducing layer may have relatively high strength and hardness. For example, the vertical expansion inducing layer may include at least one of nitrogen and carbon. The vertical expansion inducing layer may generate interfacial stress so that the bonding pad may thermally expand in the vertical direction.

[0028] Furthermore, the vertical expansion inducing layer may be formed in at least one of an upper region, a middle region, or a lower region of the bonding insulating layer.

[0029] Furthermore, when the joined structures having the vertical expansion inducing layers are hybrid-joined, the joined structures may be joined such that the vertical expansion inducing layers face each other.

[0030] According to various embodiments, a bonding structure for hybrid wafer bonding may be provided. The bonding structure may include a multilayer dielectric layer and a metal pad. The multilayer dielectric layer may include an oxide layer and a nitride layer. The metal pad may be arranged in the multilayer dielectric layer. The volume ratio of the nitride layer relative to the total volume of the multilayer dielectric layer may be about 40% to about 90%.

[0031] According to various embodiments, a semiconductor device may be provided. The semiconductor device may include a lower bonding structure and an upper bonding structure. The lower bonding structure may include a lower dielectric layer and a lower metal pad in the lower dielectric layer. The upper bonding structure may include an upper dielectric layer and an upper metal pad in the upper dielectric layer. The upper bonding structure may be bonded to the lower bonding structure, wherein an upper surface of the lower metal pad faces an upper surface of the upper metal pad. At least one of the lower dielectric layer and the upper dielectric layer may include a multilayer dielectric layer. The multilayer dielectric layer may include an oxide layer and a nitride layer. The volume ratio of the nitride layer relative to the total volume of the multilayer dielectric layer may be about 40% to about 90%.

[0032] In various embodiments, the multilayer dielectric layer may include a silicon nitride layer (SiN), a silicon oxide layer (SiO2), and a silicon carbonitride layer (SiCN) stacked sequentially. The volume ratio of the silicon nitride layer and the silicon carbonitride layer relative to the total volume of the multilayer dielectric layer may be about 50% to about 70%. The volume ratio of the silicon oxide layer relative to the total volume of the multilayer dielectric layer may be about 30% to about 50%.

[0033] According to various embodiments, a method for manufacturing a semiconductor device may be provided. In the method for manufacturing a semiconductor device, a lower metal layer may be formed on a lower dielectric layer having a first opening. An upper metal layer may be formed on an upper dielectric layer having a second opening. The lower metal layer may be partially removed to form a lower bonding structure. The lower bonding structure may include an exposed lower metal pad above the first opening and an exposed upper surface of the lower dielectric layer. The upper metal layer may be partially removed to form an upper bonding structure. The upper bonding structure may include an exposed upper metal pad above the second opening and an exposed upper surface of the upper dielectric layer. The upper bonding structure may be bonded to the lower bonding structure, wherein the upper surface of the lower metal pad faces the upper surface of the upper metal pad. The lower dielectric layer may be bonded to the upper dielectric layer to form a bonded stacking structure. The bonded stacking structure may be heated to bond the lower metal pad to the upper metal pad. At least one of the lower dielectric layer and the upper dielectric layer may include a multilayer dielectric layer. The multi-layer dielectric layer may include an oxide layer and a nitride layer. A volume ratio of the nitride layer relative to a total volume of the multi-layer dielectric layer may be about 40% to about 90%.

[0034] According to various embodiments, a bonding structure for hybrid wafer bonding may be provided. The bonding structure may include a plurality of bonding pads and a bonding insulation layer. The bonding insulation layer may be configured to electrically isolate the bonding pads from each other. The bonding insulation layer may include at least one dielectric layer and a vertical expansion inducing layer arranged on the dielectric layer. The vertical expansion inducing layer may have a hardness higher than that of the dielectric layer.

[0035] According to various embodiments, a semiconductor device may be provided. The semiconductor device may include a first structure and a second structure. The first structure may include a first bonding layer. The second structure may include a second bonding layer bonded to the first bonding layer. At least one of the first bonding layer and the second bonding layer may include a plurality of bonding pads and a bonding insulating layer inserted between the bonding pads. The bonding insulating layer may include an upper region adjacent to a bonding surface between the first bonding layer and the second bonding layer and a lower region positioned below the upper region. The interface stress between the upper region in the bonding insulating layer and the bonding pad may be higher than the interface stress between the lower region in the bonding insulating layer and the bonding pad.

[0036] According to various embodiments, a semiconductor device may be provided. The semiconductor device may include a device layer, a bonding insulating layer and a bonding layer. The bonding insulating layer may be formed on at least one of the surfaces of the device layer. The bonding insulating layer may include a plurality of dielectric layers stacked from the surface of the device layer to the bonding surface. The bonding layer may include a plurality of bonding pads inserted between the plurality of bonding insulating layers. At least one of the dielectric layers adjacent to the bonding surface may include a first dielectric material. The remaining dielectric layer may include a second dielectric material having a hardness lower than that of the first dielectric material.

[0037] Figures 1A to 1C is a cross-sectional view illustrating a method of manufacturing a semiconductor device using a comparative example of a hybrid wafer bonding process. Figure 2A is a cross-sectional view illustrating a bonding structure metal pad having a recess according to an embodiment, and Figure 2B is a cross-sectional view illustrating a semiconductor device having a disconnection according to an embodiment.

[0038] See also Figure 1A In a comparative example of a hybrid wafer bonding process, a first stack structure 30 and a second stack structure 40 may be prepared.

[0039] The first stacked structure 30 may include an upper dielectric layer 31 as a bonding insulating layer and a metal layer 33 in the upper dielectric layer 31. For example, the upper dielectric layer 31 and the metal layer 33 may be formed over the first substrate S1. The first stacked structure 30 may also include at least one interlayer insulating film 35 and at least one conductive pattern 37 in the interlayer insulating film 35. For example, the metal layer 33 may be electrically connected to the conductive pattern 37.

[0040] The first stack structure 30 may be formed through the following process.

[0041] An interlayer insulating film 35 may be formed over the first substrate S1. The interlayer insulating film 35 may be etched. Then a conductive pattern 37 may be formed in a portion where the interlayer insulating film 35 is etched. An upper dielectric layer 31 may be formed over the interlayer insulating film 35. The upper dielectric layer 31 may be etched to form at least one opening. A metal material may be formed on the upper dielectric layer 31 to fill the opening to form a metal layer 33.

[0042] The second stacked structure 40 may include an upper dielectric layer 41 as a bonding insulating layer, a metal layer 43, at least one interlayer insulating film 45, and at least one conductive pattern 47. The upper dielectric layer 41 may be formed on the second substrate S2. The conductive pattern 47 may be electrically connected to the metal layer 43. For example, the second stacked structure 40 may be formed by a process substantially the same as that used to form the first stacked structure 30.

[0043] See also Figure 1B , Figure 1A Each of the metal layers 33 and 43 can be polished by a chemical mechanical polishing (CMP) process until the upper dielectric layers 31 and 41 are exposed to form a first bonding structure 30a having a first metal pad 33a and a second bonding structure 40a having a second metal pad 43a. Here, the first metal pad 33a and the second metal pad 43a can correspond to bonding pads. Here, the first metal pad 33a and the second metal pad 43a can be understood as bonding pads for each of the first bonding structure 30a and the second bonding structure 40a. In addition, the upper dielectric layers 31 and 41 can be understood as bonding insulation layers for each of the first bonding structure 30a and the second bonding structure 40a.

[0044] See also Figure 1C, the second bonding structure 40a may be arranged above the first bonding structure 30a so that the first metal pad 33a and the second metal pad 43a face each other. The upper dielectric layers 31 and 41 may be bonded to each other. The bonded upper dielectric layers 31 and 41 may be annealed to bond the first metal pad 33a and the second metal pad 43a, thereby forming a semiconductor device including the hybrid-bonded first bonding structure 30a and the second bonding structure 40a.

[0045] However, when each of the metal layers 33 and 43 is polished by the CMP process, each of the metal layers 33 and 43 may be partially over-polished due to the material property difference between the upper dielectric layers 31 and 41 and the metal layers 33 and 43. Figure 2A As shown in FIG. 4 , recesses appear at the upper surfaces of the first metal pad 33 a and the second metal pad 43 a .

[0046] See also Figure 2B , the first metal pad 33a and the second metal pad 43a having the depression may not be sufficiently expanded during the annealing process. When the first metal pad 33a and the second metal pad 43a may not be sufficiently expanded, disconnection may be generated at the first metal pad 33a and the second metal pad 43a, thereby reducing the productivity of the semiconductor device.

[0047] In particular, the first structure 30a and the second structure 40a should be electrically connected to each other through a hybrid wafer bonding process. In the hybrid bonding process, the upper dielectric layer 31 and the upper dielectric layer 41 can be directly bonded to each other. The bonding between the upper dielectric layers 31 and 41 can be induced by heating at room temperature or low temperature. At the same time, under the bonding conditions of the upper dielectric layers 31 and 41, the first metal pad 33a and the second metal pad 43a may not be bonded. Therefore, the interface between the first metal pad 33a and the second metal pad 43a may not be electrically connected to each other. The first metal pad 33a and the second metal pad 43a may be annealed at a temperature of about 100°C to about 300°C to bond the first metal pad 33a and the second metal pad 43a to each other.

[0048] The heated first metal pad 33a and the second metal pad 43a may expand upward through the annealing process so that the first metal pad 33a and the second metal pad 43a may contact each other. Sufficient stress may be applied to the first metal pad 33a and the second metal pad 43a to bond the first metal pad 33a and the second metal pad 43a to each other. After cooling the bonded first metal pad 33a and the second metal pad 43a, the first metal pad 33a and the second metal pad 43a may not be separated from each other. Therefore, the electrical bonding between the first metal pad 33a and the second metal pad 43a may be maintained. The first metal pad 33a and the second metal pad 43a may have a higher thermal expansion coefficient than the thermal expansion coefficient of the upper dielectric layers 31 and 41. Therefore, in an embodiment, when the first bonding structure 30a and the second bonding structure 40a can be heated by an annealing process, the upper dielectric layers 31 and 41 located on the sides of the first metal pad 33a and the second metal pad 43a can prevent or reduce the thermal expansion of the first metal pad 33a and the second metal pad 43a along the lateral direction and generate interface stress, thereby applying interface stress to the first metal pad 33a and the second metal pad 43a.

[0049] If the first metal pad 33a and the second metal pad 43a are not sufficiently thermally expanded, the first metal pad 33a and the second metal pad 43a may be disconnected. In particular, when a depression may be generated at the first metal pad 33a and the second metal pad 43a, although the first metal pad 33a and the second metal pad 43a may be sufficiently heated by the annealing process, the first metal pad 33a and the second metal pad 43a may be disconnected. The amount of deformation caused by the thermal expansion in the first metal pad 33a and the second metal pad 43a caused by the annealing process may be affected by the Young's modulus of the upper dielectric layers 31 and 41 adjacent to the first metal pad 33a and the second metal pad 43a. In particular, when the first metal pad 33a and the second metal pad 43a may be thermally expanded, the thermal expansion of the first metal pad 33a and the second metal pad 43a may be induced by the hard upper dielectric layers 31 and 41. Therefore, for some embodiments, the bonding structures 100 a , 100 b , 100 c , and 100 d for hybrid wafer bonding according to various embodiments may include a dielectric layer around a metal pad.

[0050] In an embodiment, the dielectric layer as a bonding insulating layer may include a dielectric material having a strength and hardness higher than that of a silicon oxide layer generally used as a bonding insulating layer. When the metal pad is annealed, the dielectric material may apply sufficient stress to the metal pad based on the material difference between the dielectric material and the metal pad. Therefore, the metal pad may thermally expand toward the bonding surface (e.g., in the vertical direction) based on sufficient stress.

[0051] Hereinafter, a bonding structure for hybrid wafer bonding according to various embodiments (hereinafter, referred to as a first bonding structure) may be explained in detail.

[0052] FIG. 3A to FIG. 3D are cross-sectional views illustrating various examples of first bonding structures according to various embodiments.

[0053] See also FIG. 3A to FIG. 3D , the first bonding structures 100a, 100b, 100c, and 100d may include first multi-layer dielectric layers 110a, 110b, 110c, and 110d and a first metal pad 130. Therefore, in the hybrid bonding process, the first bonding structures 100a, 100b, 100c, and 100d may be bonded to each other without disconnection at interfaces between the first bonding structures 100a, 100b, 100c, and 100d.

[0054] A first metal pad 130 may be formed in at least one of the first multi-layer dielectric layers 110a, 110b, 110c, and 110d. The first metal pad 130 may include a material that thermally expands at a high temperature of 250° C. or more through an annealing process. For example, the first metal pad 130 may include copper, aluminum, tungsten, a combination thereof, or the like. In various embodiments, the first metal pad 130 may include copper.

[0055] At least one of the first multi-layer dielectric layers 110 a , 110 b , 110 c , and 110 d may include at least one oxide layer and at least one nitride layer.

[0056] For example, the first multi-layer dielectric layers 110 a , 110 b , 110 c , and 110 d may correspond to a bonding insulating layer.

[0057] For a more detailed explanation, see Figure 3A , the first bonding structure 100 a may include a first multi-layer dielectric layer 110 a and a first metal pad 130 in the first multi-layer dielectric layer 110 a .

[0058] For example, the first multi-layer dielectric layer 110 a may include a first oxide layer 111 and a first nitride layer 113 .

[0059] In an embodiment, first oxide layer 111 may buffer stress generated from first metal pad 130. In addition, first oxide layer 111 may prevent or alleviate deformation of first metal pad 130 during an annealing process.

[0060] In an embodiment, the first nitride layer 113 may include a dielectric material having a modulus higher than that of the first oxide layer 111. In other words, the nitride material may include a strength higher than that of the oxide material and a hardness higher than that of the oxide material. Therefore, in an embodiment, during the annealing process, the first nitride layer 113 may prevent or mitigate thermal expansion of the first metal pad 130 in a lateral direction (or horizontal direction). In addition, the first nitride layer 113 may induce thermal expansion of the first metal pad 130 in a vertical direction perpendicular to the lateral direction.

[0061] The first nitride layer 113 may occupy 40% to 90% of the first multilayer dielectric layer 110a. For example, the volume ratio of the first nitride layer 113 relative to the total volume of the first multilayer dielectric layer 110a may be about 40% to about 90%. In addition, the volume ratio of the first oxide layer 111 relative to the total volume of the first multilayer dielectric layer 110a may be about 10% to about 60%. In this embodiment, "volume" may be interpreted as a term including thickness.

[0062] When the volume ratio of the first nitride layer 113 relative to the total volume of the first multi-layer dielectric layer 110 may be lower than about 40%, the first metal pad 130 may not be sufficiently thermally expanded in the vertical direction, thereby causing disconnection. In contrast, when the volume ratio of the first nitride layer 113 relative to the total volume of the first multi-layer dielectric layer 110 may be higher than about 90%, the first metal pad 130 may be excessively thermally expanded in the vertical direction, so that the first metal pad 130 expands into an abnormal shape in the first multi-layer dielectric layer 110. In particular, the volume ratio of the first nitride layer 113 relative to the total volume of the first multi-layer dielectric layer 110 may be about 40% to about 90%, more specifically 50% to about 60%.

[0063] The first nitride layer 113 may be formed on the first oxide layer 111. Alternatively, the first oxide layer 111 may be formed on the first nitride layer 113. Positions of the first oxide layer 111 and the first nitride layer 113 in the first multi-layer dielectric layer 110a may vary according to the design of the semiconductor device.

[0064] The first oxide layer 111 may include silicon oxide (SiO2). The first nitride layer 113 may include at least one of nitrogen and carbon. For example, the first nitride layer 113 may include at least one of silicon nitride (SiN), silicon carbonitride (SiCN), and silicon oxynitride (SiON). Hereinafter, the oxide layer 111 will be understood as a silicon oxide layer.

[0065] like Figure 3AAs shown in FIG. 1 , the first multi-layer dielectric layer 110 a may include a single first oxide layer 111 and a single first nitride layer 113 , but is not limited thereto.

[0066] See also Figure 3B , the first multi-layer dielectric layer 110b of the first bonding structure 100b may include a first nitride layer 113-1, a first oxide layer 111, and a second nitride layer 113-2 that are sequentially stacked. The volume ratio of the first nitride layer 113-1 and the second nitride layer 113-2 relative to the total volume of the first multi-layer dielectric layer 110b may be about 40% to about 90%. The volume ratio of the first oxide layer 111 relative to the total volume of the first multi-layer dielectric layer 110b may be about 10% to about 60%.

[0067] The first nitride layer 113-1 and the second nitride layer 113-2 may include nitrides having the same composition or different compositions. The first nitride layer 113-1 and the second nitride layer 113-2 may have the same volume ratio or different volume ratios. That is, the first nitride layer 113-1 and the second nitride layer 113-2 may have the same thickness or different thicknesses.

[0068] Alternatively, at least one of the first oxide layers 111 and the nitride layers 113 may be alternately stacked to form the first multi-layer dielectric layer 110 a or 110 b as a bonding insulating layer.

[0069] See also Figure 3C The first multi-layer dielectric layer 110c of the first bonding structure 100c may include a first silicon nitride layer 113a, a first silicon oxide layer 111a, and a first silicon carbonitride layer 113b stacked sequentially. For example, the first silicon carbonitride layer 113b may have greater strength and hardness than the first silicon oxide layer 111a.

[0070] In an embodiment, the first silicon nitride layer 113 a and the first silicon carbonitride layer 113 b may correspond to vertical expansion inducing layers of the first multi-layer dielectric layer 110 c .

[0071] The volume ratio of the first silicon nitride layer 113a and the first silicon carbonitride layer 113b relative to the total volume of the first multi-layer dielectric layer 110c may be about 40% to about 90%, in particular, about 50% to about 70%. The volume ratio of the first silicon oxide layer 111a relative to the total volume of the first multi-layer dielectric layer 110c may be about 10% to about 60%. The first silicon nitride layer 113a and the first silicon carbonitride layer 113b in the first multi-layer dielectric layer 110c may be within the category of the nitride layer 113. The first silicon oxide layer 111a may be within the category of the oxide layer 111.

[0072] See also Figure 3D, the first multilayer dielectric layer 110d of the first bonding structure 100d may include a plurality of silicon nitride layers and a plurality of silicon oxide layers alternately stacked. For example, the nitride layer may be located in the uppermost layer and the lowermost layer of the first multilayer dielectric layer 110d. For example, the nitride layer may include at least one of a silicon nitride layer and a silicon carbonitride layer. In an embodiment, the first multilayer dielectric layer 110d may include a first silicon nitride layer 113a-1, a first silicon oxide layer 111a-1, a second silicon nitride layer 113a-2, a second silicon oxide layer 111a-2, and a first silicon carbonitride layer 113b stacked in sequence.

[0073] Alternatively, the first silicon nitride layer 113a-1 and the first silicon oxide layer 111a-1 may be alternately stacked at least twice to form the first multi-layer dielectric layer 110d. The first silicon carbonitride layer 113b may be stacked on the uppermost layer in the first bonding structure 100d.

[0074] The volume ratio of the first silicon nitride layers 113a-1 and 113a-2 and the first silicon carbonitride layer 113b to the total volume of the first multilayer dielectric layer 110d may be about 40% to about 90%, specifically about 50% to about 70%, and more specifically about 50% to about 60%. The volume ratio of the first silicon oxide layer 111a-1 and the second silicon oxide layer 111a-2 to the total volume of the first multilayer dielectric layer 110d may be about 10% to about 60%. The first silicon nitride layer 113a-1 and the first silicon carbonitride layer 113b in the first multilayer dielectric layer 110d may be within the category of nitride layers. The first silicon oxide layer 111a-1 may be within the category of oxide layers.

[0075] In an embodiment, in the first bonding structures 100a, 100b, 100c, and 100d, the (multiple) first nitride layers 113 may have a strength modulus greater than that of the (multiple) first oxide layers 111 to prevent or mitigate thermal expansion of the metal pad 130 along the lateral direction during the annealing process, so that the metal pad 130 can be sufficiently thermally expanded in the vertical direction to promote the bonding of the first metal pad 130 in the hybrid bonding process. The volume ratio of the nitride layer 113 relative to the total volume of the dielectric layer may be about 40% to about 90%. The nitride layer 113 may include silicon nitride. Alternatively, the nitride layer 113 may include silicon nitride and silicon carbonitride. The oxide layer 111 may include silicon oxide.

[0076] The density and strength modulus of first silicon carbon nitride layer 113b may be greater than those of silicon oxide layer 111 to improve thermal expansion of first metal pad 130. In addition, in an embodiment, silicon carbon nitride layer 113b may have good thermal stability, high bonding strength, and metal diffusion barrier properties, so that first silicon carbon nitride layer 113b may be used as a material for directly bonding dielectric layers to each other. Therefore, silicon carbon nitride layer 113b may be the uppermost layer of first bonding structures 100c and 100d.

[0077] In an embodiment, since the deposition rate of silicon oxide layer 111 may be greater than the deposition rate of nitride layer 113, silicon oxide layer 111 having a set thickness is required to reduce the time for forming the dielectric layer. Although oxide layer 111 has a lower strength than that of nitride layer 113 and a lower hardness than that of nitride layer 113, oxide layer 111 may define a space in which metal pad 130 will be formed. In addition, when metal pad 130 is annealed, oxide layer 111 may relieve and buffer stress between metal pad 130, silicon nitride layer 113a, and silicon carbonitride layer 113b.

[0078] The first bonding structures 100 a , 100 b , 100 c , and 100 d may form a structure configured to bond metal pads to each other at interfaces without disconnection in a hybrid wafer bonding process.

[0079] The volume ratio(s) may be adjusted by changing the thickness of the first oxide layer 111 and the first nitride layer 113 .

[0080] For example, see Figure 3A , when the thickness T of the first multilayer structure 110a corresponding to the bonding insulating layer may be about When the thickness T2 of the first nitride layer 113 is about to about And the thickness T1 of the first oxide layer 111 may be about to about Therefore, the volume ratio of the nitride layer 113 to the total volume of the first multilayer structure 110a may be about 40% to about 90%. The volume ratio of the first oxide layer 111 to the total volume of the first multilayer structure 110a may be about 10% to about 60%. In various embodiments, volume may be understood as thickness or content.

[0081] In other words, see Figure 3C , when the thickness T of the first multilayer structure 110c may be about When the thickness T21 of the first silicon nitride layer 113a and the thickness T22 of the first silicon carbonitride layer 113b are equal to or greater than about 100 mm, the total thickness T20 of the first silicon nitride layer 113a and the thickness T22 of the first silicon carbonitride layer 113b may be approximately to about And the thickness T1 of the first oxide layer 111a may be about to about

[0082] See also Figure 3D , when the thickness T of the first multilayer structure 110d may be about When the thickness T21 of the first silicon nitride layers 113a-1 and 113a-2 and the thickness T22 of the first silicon carbonitride layer 113b are both greater than 100 mm, the total thickness T20a of the first silicon nitride layers 113a-1 and 113a-2 and the thickness T22 of the first silicon carbonitride layer 113b may be approximately to about And the thickness T11 of the first oxide layers 111a-1 and 111a-2 may be about to about

[0083] Figure 4 is a cross-sectional view illustrating a first bonding structure including a lower structure according to various embodiments.

[0084] See also Figure 4 , the first bonding structure 100a may include a first multilayer dielectric layer 110a, a first metal pad 130, and a lower structure ST1. The first multilayer dielectric layer 110a may be formed on the lower structure ST1. The lower structure ST1 may include a substrate 101, at least one insulating layer 150, and at least one conductive pattern 170. The insulating layer 150 may be interposed between the first multilayer dielectric layer 110a and the substrate 101. The conductive pattern 170 may be formed in the insulating layer 150. For example, the conductive pattern 170 may be electrically connected to the first metal pad 130. In an embodiment, the substrate 101 may be removed.

[0085] FIG. 5A to FIG. 5D are cross-sectional views illustrating various examples of semiconductor devices including second and third bonding structures having different structures according to various embodiments.

[0086] See also FIG. 5A to FIG. 5D The semiconductor devices 10 a , 10 b , 10 c , and 10 d may include a second bonding structure 200 a , 200 b , 200 c , or 200 d and a third bonding structure 300 .

[0087] Any one of the second bonding structure 200a, 200b, 200c, or 200d and the third bonding structure 300 may have the same FIG. 3A to FIG. 3D The structures of the first bonding structures 100a, 100b, 100c and 100d shown in FIG. 1 are substantially the same structure.

[0088] In the semiconductor devices 10a, 10b, 10c and 10d, the second bonding structure 200a, 200b, 200c or 200d may include a second multilayer dielectric layer 210a, 210b, 210c or 210d and a second metal pad 230. The second metal pad 230 may be formed in the second multilayer dielectric layer 210a, 210b, 210c or 210d. For example, the second multilayer dielectric layer 210a, 210b, 210c or 210d may correspond to the bonding insulation layer of the second bonding structure 200a, 200b, 200c or 200d. The third bonding structure 300 may include a third dielectric layer 310 and a third metal pad 330. The third metal pad 330 may be formed in the third dielectric layer 310. The third dielectric layer may be a bonding insulation layer of the third bonding structure 300. The second bonding structure 200 and the third bonding structure 300 may have different structures. The second bonding structure 200 and the third bonding structure 300 may be hybrid-bonded to contact the second multi-layer dielectric layer 210 a , 210 b , 210 c , or 210 d and the third dielectric layer 310 .

[0089] See also Figure 5A , the second multilayer dielectric layer 210a of the semiconductor device 10a may include at least one oxide layer 211 and at least one nitride layer 213. Since the strength and hardness of the nitride layer 213 are higher than the strength and hardness of the oxide layer 211, the nitride layer 213 may apply greater stress to the second metal pad 230 than the oxide layer 211. Therefore, the nitride layer 213 may induce thermal expansion of the second metal pad 230 toward the third metal pad 330 (e.g., in a vertical direction). For example, the oxide layer 211 may be positioned in a lower region of the second multilayer dielectric layer 210a. The nitride layer 213 may be positioned in an upper region of the second multilayer dielectric layer 210a. The upper surface of the nitride layer 213 may be a bonding surface bonded to the third bonding structure 300. The interface stress between the nitride layer 213 positioned in the upper region of the second multilayer dielectric layer 210a and the second metal pad 230 corresponding to the bonding pad may be greater than the interface stress between the oxide layer 211 positioned in the lower region of the second multilayer dielectric layer 210a and the second metal pad 230. For reference, a portion of each of the multilayer dielectric layers adjacent to the bonding surface will be referred to as an upper region, and a portion of each of the multilayer dielectric layers separated from the bonding surface will be referred to as a lower region. The middle region of the multilayer dielectric layer may be positioned between the lower region and the upper region.

[0090] The volume ratio of the nitride layer 213 to the total volume of the second multi-layer dielectric layer 210a may be about 40% to about 90%, particularly 50% to about 70%, and more particularly 50% to about 60%. The volume ratio of the oxide layer 211 to the total volume of the second multi-layer dielectric layer 210a may be about 10% to about 60%. For example, the thickness of the upper region including the nitride layer 213 is greater than the thickness of the lower region including the oxide layer 211.

[0091] See also Figure 5B , the second multilayer dielectric layer 210b of the semiconductor device 10b may include a first nitride layer 213-1, an oxide layer 211, and a second nitride layer 213-2. Here, the first nitride layer 213-1 and the second nitride layer 213-2 may be vertical expansion inducing layers for inducing thermal expansion of the second metal pad 230 in a vertical direction. The volume ratio of the first nitride layer 213-1 and the second nitride layer 213-2 relative to the total volume of the second multilayer dielectric layer 210b may be about 40% to about 90%, particularly 50% to about 70%, and more particularly 50% to about 60%. The volume ratio of the oxide layer 211 relative to the total volume of the second multilayer dielectric layer 210b may be about 10% to about 60%.

[0092] For example, the volume ratio of the first nitride layer 213-1 to the second nitride layer 213-2 may be about 0.5:1.5 to about 1.5:0.5. The volume ratio may be formed by controlling the thickness of the first nitride layer 213-1 to the second nitride layer 213-2. For example, when the thickness of the first nitride layer 213-1 may be about When the second nitride layer 213-2 has a thickness of about to about For example, the second multilayer dielectric layer 210b of the semiconductor device 10b may include a first oxide layer, a nitride layer (or a carbon material), and a second oxide layer stacked in sequence. For example, the second oxide layer may be directly bonded to the third dielectric layer 310. Here, the volume ratio of the nitride layer to the total volume of the second multilayer dielectric layer 210b may be about 40% to about 90%, particularly about 50% to about 70%, and more particularly about 50% to about 60%.

[0093] See also Figure 5C, the second multilayer dielectric layer 210c of the semiconductor device 10c may include a silicon nitride layer 213a, a silicon oxide layer 211a, and a silicon carbonitride layer 213b stacked in sequence. For example, the silicon nitride layer 213a may be positioned in the lower region of the second multilayer dielectric layer 210c. The silicon oxide layer 211a may be positioned in the middle region of the second multilayer dielectric layer 210c, and the silicon carbonitride layer 213b may be positioned in the upper region of the second multilayer dielectric layer 210c. In this embodiment, the silicon nitride layer 213a and the silicon carbonitride layer 213b may be vertical expansion inducing layers for inducing thermal expansion of the second metal pad 230 in the vertical direction. The volume ratio of the silicon nitride layer 213a and the silicon carbonitride layer 213b relative to the total volume of the second multilayer dielectric layer 210c may be about 40% to about 90%, particularly 50% to about 70%, and more particularly 50% to about 60%. A volume ratio of the oxide layer 211 a with respect to the total volume of the second multi-layer dielectric layer 210 c may be about 10% to about 60%.

[0094] In addition, the volume ratio of the silicon nitride layer 213a and the silicon carbonitride layer 213b can be about 0.5:1.5 to about 1.5:0.5. The volume ratio can be controlled by the thickness of the silicon nitride layer 213a and the silicon carbonitride layer 213b. For example, when the thickness of the silicon nitride layer 213a can be about When the silicon carbonitride layer 213b has a thickness of about to about Thickness.

[0095] For example, when the second multi-layer dielectric layer 210c has about When the thickness is , the total thickness of the silicon nitride layer 213a and the silicon carbonitride layer 213b may be about to about The thickness of the oxide layer 211 is 200 nm to provide a volume ratio of about 40% to about 90% for the nitride layers 213a and 213b and a volume ratio of about 10% to about 60% for the oxide layer 211.

[0096] See also Figure 5D, the second multilayer dielectric layer 210d of the semiconductor device 10d may include vertical expansion inducing layers 2130 and buffer layers 2110 that are alternately stacked. For example, the vertical expansion inducing layer 2130 may be located at the lower region and the upper region of the second multilayer dielectric layer 210d. The vertical expansion inducing layer 2130 may include at least one of a silicon nitride layer 213a and a silicon carbonitride layer 213b. For example, the silicon nitride layer 213a may be positioned in the lower region (e.g., the lowermost layer) of the second multilayer dielectric layer 210d, and the silicon carbonitride layer 213b may be positioned in the upper region (e.g., the uppermost layer) of the second multilayer dielectric layer 210d to contact the third bonding structure 300. Therefore, the silicon nitride layer 213a and the silicon carbonitride layer 213b may induce thermal expansion of the second metal pad 230 in the vertical direction. Here, the buffer layer 2110 may include a silicon oxide layer to relieve the stress of the metal pad 230. In certain embodiments, a silicon oxide layer (not shown) may be disposed on the uppermost surface of the second multi-layer dielectric layer 210 a , 210 b , 210 c , or 210 d hybrid-bonded with the third dielectric layer 310 .

[0097] The volume ratio of the vertical expansion inducing layer 2130 including the silicon nitride layer 213a and the silicon carbonitride layer 213b to the total volume of the second multi-layer dielectric layer 210d may be about 40% to about 90%, particularly 50% to about 70%, and more particularly 50% to about 60%. The volume ratio of the (multiple) buffer layers 2110 to the total volume of the second multi-layer dielectric layer 210d may be about 10% to about 60%.

[0098] In addition, a volume ratio of the silicon nitride layer 213 a to the silicon carbonitride layer 213 b may be about 0.5:1.5 to about 1.5:0.5.

[0099] See also FIG. 5A to FIG. 5D , the third bonding structure 300 of the semiconductor devices 10 a , 10 b , 10 c , and 10 d may include a third dielectric layer 310 and a third metal pad 330 disposed in the third dielectric layer 310 .

[0100] The third dielectric layer 310 may include a dielectric material bonded to the second multilayer dielectric layers 210a, 210b, 210c, and 210d. The dielectric material of the third dielectric layer 310 may include at least one of silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbide, and silicon oxynitride carbide.

[0101] The third metal pad 330 may be formed in the third dielectric layer 310 using the metal bonded to the second metal pad 230 .

[0102] therefore, FIG. 5A to FIG. 5DThe second engaging structure 200 may be shown positioned below the third engaging structure 300. Alternatively, the positions of the second engaging structure 200 and the third engaging structure 300 may be reversed.

[0103] In addition, FIG. 5A to FIG. 5D In the embodiment, the second metal pad 230 and the third metal pad 330 may have different cross-sectional shapes, but are not limited thereto. For example, the second metal pad 230 and the third metal pad 330 may have the same cross-sectional shape. In particular, different cross-sectional shapes may be provided for the second metal pad 230 and the third metal pad 330 to ensure a bonding margin between the second metal pad 230 and the third metal pad 330.

[0104] In an embodiment, the semiconductor devices 10 a , 10 b , 10 c , and 10 d may form a bonding structure at an interface without disconnection through a hybrid bonding process.

[0105] FIG. 6A to FIG. 6D are cross-sectional views illustrating various examples of semiconductor devices including a second bonding structure and a fourth bonding structure according to various embodiments.

[0106] See also FIG. 6A to FIG. 6D , the semiconductor devices 10e, 10f, 10g, and 10h of various embodiments may include second bonding structures 200a, 200b, 200c, and 200d and fourth bonding structures 400a, 400b, 400c, and 400d.

[0107] The second bonding structures 200a, 200b, 200c, and 200d may include a second multi-layer dielectric layer 210a, 210b, 210c, or 210d and at least one second metal pad 230 in the second multi-layer dielectric layer 210, as mentioned above. The fourth bonding structures 400a, 400b, 400c, and 400d may include a fourth multi-layer dielectric layer 410a, 410b, 410c, or 410d and at least one fourth metal pad 430 in the fourth multi-layer dielectric layer 410a, 410b, 410c, or 410d.

[0108] See also Fig. 6A , the semiconductor device 10e may include a fourth bonding structure 400a. The fourth bonding structure 400a may include at least one oxide layer 411 and at least one nitride layer 413 as a vertical expansion inducing layer. For example, see Fig. 6A , the fourth bonding structure 400 a may be bonded to the second bonding structure 200 a including the second multi-layer dielectric layer 210 a .

[0109] As described above, the second multi-layer dielectric layer 210a may include an oxide layer 211 and a nitride layer 213. The fourth multi-layer dielectric layer 410a may include an oxide layer 411 and a nitride layer 413.

[0110] The volume ratio of the nitride layer 213 to the total volume of the second multi-layer dielectric layer 210a may be about 40% to about 90%, specifically about 50% to about 70%, more specifically about 60% to about 70%. The volume ratio of the fourth nitride layer 413 to the total volume of the fourth multi-layer dielectric layer 410a may be about 40% to about 90%, specifically about 50% to about 70%, more specifically about 60% to about 70%.

[0111] For example, the second bonding structure 200a and the fourth bonding structure 400a may have the same structure. The second bonding structure 200a and the fourth bonding structure 400a may be hybrid-bonded such that the nitride layer 213 of the second multilayer dielectric layer 210a faces the nitride layer 413 of the fourth multilayer dielectric layer 410a.

[0112] See also Figure 6B The second multilayer dielectric layer 210b of the semiconductor device 10f may include a first nitride layer 213-1, an oxide layer 211, and a second nitride layer 213-2. The fourth multilayer dielectric layer 410b may include a first nitride layer 413-1, an oxide layer 411, and a second nitride layer 413-2.

[0113] The volume ratio of the first nitride layer 213-1 and the second nitride layer 213-2 to the total volume of the second multilayer dielectric layer 210b may be about 40% to about 90%, specifically 50% to about 70%, more specifically 60% to about 70%. The total volume ratio of the first nitride layer 413-1 and the second nitride layer 413-2 to the total volume of the fourth multilayer dielectric layer 410b may be about 40% to about 90%, specifically 50% to about 70%, more specifically 60% to about 70%.

[0114] In addition, by controlling the thicknesses of the nitride layers 213-1 and 213-2 and the nitride layers 413-1 and 413-2, each of the volume ratios of the nitride layers 213-1 and 213-2 in the second multilayer dielectric layer 210b and the volume ratios of the nitride layers 413-1 and 413-2 in the fourth multilayer dielectric layer 410b can be approximately 0.5:1.5 to approximately 1.5:0.5.

[0115] See also Figure 6C, the second multilayer dielectric layer 210c may include a silicon nitride layer 213a, a silicon oxide layer 211a, and a silicon carbonitride layer 213b stacked in sequence. The fourth multilayer dielectric layer 410c may include a silicon carbonitride layer 413b, a silicon oxide layer 411a, and a silicon nitride layer 413a stacked in sequence. For example, the fourth bonding structure 400c may be bonded to the second bonding structure 200c so that the silicon carbonitride layer 213b of the second multilayer dielectric layer 210c and the silicon carbonitride layer 413b of the fourth multilayer dielectric layer 410c face each other.

[0116] The volume ratio of the silicon nitride layer 213a and the silicon carbonitride layer 213b to the total volume of the second multilayer dielectric layer 210c may be about 40% to about 90%, specifically 50% to about 70%, more specifically 50% to about 60%. The volume ratio of the silicon nitride layer 413a and the silicon carbonitride layer 413b to the total volume of the fourth multilayer dielectric layer 410c may be about 40% to about 90%, specifically 50% to about 70%, more specifically 50% to about 60%. The volume ratio of the silicon oxide layer 211a to the total volume of the second multilayer dielectric layer 210c and the volume ratio of the silicon oxide layer 411a to the total volume of the fourth multilayer dielectric layer 410c may be about 10% to about 60%.

[0117] See also Fig.6D , the second multilayer dielectric layer 210d may include silicon nitride layers 213a and oxide layers 211 alternately stacked at least twice. In addition, the second multilayer dielectric layer 210d may include silicon carbonitride layers 213b formed on the upper surface of the second multilayer dielectric layer 210d. The fourth multilayer dielectric layer 410d may include silicon nitride layers 413 and oxide layers 411 alternately stacked at least twice. In addition, the fourth multilayer dielectric layer 410d may include silicon carbonitride layers 413b formed on the lower surface of the fourth multilayer dielectric layer 410d.

[0118] The volume ratio of silicon nitride layer 213a and silicon carbonitride layer 413b to the total volume of fourth multilayer dielectric layer 410d may be about 40% to about 90%. The volume ratio of oxide layer 411 to the total volume of fourth multilayer dielectric layer 410c may be about 10% to about 60%.

[0119] The semiconductor devices 10e, 10f, 10g, and 10h can form a bonding structure at the interface without disconnection through a hybrid bonding process.

[0120] In semiconductor devices 10a, 10b, 10c, 10d, 10e, 10f, 10g and 10h, the oxide layer may have the lowest strength modulus. Therefore, in an embodiment, when the metal pad is thermally expanded, the oxide layer may play a buffering role to prevent or alleviate excessive deformation of the metal pad. The oxide layer may include a silicon oxide layer. The nitride layer may have a high strength modulus. Therefore, in an embodiment, when the metal pad is thermally expanded, the nitride layer may prevent or alleviate the thermal expansion of the metal pad in the lateral direction. The nitride layer may induce thermal expansion of the metal pad along the vertical direction. In particular, the silicon carbonitride layer may have a strength modulus between the strength modulus of the silicon oxide layer and the strength modulus of the silicon nitride layer. The silicon carbonitride layer may have high thermal stability, high bonding strength and metal expansion barrier properties, so that the silicon carbonitride layer can be used as a material for directly bonding wafers to each other.

[0121] In particular, in an embodiment, when dielectric layers corresponding to bonding insulating layers are bonded to each other, vertical expansion inducing layers such as silicon nitride layers and silicon carbonitride layers may induce strong bonding through non-metal at a temperature lower than 250°C, compared to when silicon oxide layers may be bonded to each other.

[0122] Therefore, in an embodiment, in the semiconductor devices 10a, 10b, 10c, 10d, 10e, 10f, 10g, and 10h, the nitride layer may have a strength modulus higher than that of the oxide layer to prevent or mitigate thermal expansion of the metal pad in the lateral direction. In contrast, the nitride layer may induce thermal expansion of the metal pad along the vertical direction in the hybrid wafer bonding process to facilitate bonding of the metal pad. In an embodiment, the oxide layer may buffer the stress applied to the metal pad by the annealing process to prevent or mitigate excessive deformation of the metal pad.

[0123] Therefore, in the semiconductor devices 10a, 10b, 10c, 10d, 10e, 10f, 10g, and 10h, the volume ratio of the nitride layer in the bonding structure relative to the total volume of the multilayer dielectric layer may be about 40% to about 90%. As a result, in an embodiment, disconnection may not be generated at the bonding surface between the metal pads, so that the semiconductor devices 10a, 10b, 10c, 10d, 10e, 10f, 10g, and 10h may have improved electrical characteristics.

[0124] exist FIG. 6A to FIG. 6D In the embodiment, the second metal pad 230 and the fourth metal pad 430 may have different cross-sectional shapes, but are not limited thereto. The second metal pad 230 and the fourth metal pad may have the same cross-sectional shape. In particular, different cross-sectional shapes may be provided for the second metal pad 230 and the fourth metal pad 330 to ensure a bonding margin between the second metal pad 230 and the fourth metal pad 330.

[0125] Figure 7 is a flowchart for illustrating a method of manufacturing a semiconductor device according to various embodiments. FIG. 8A to FIG. 8E is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to various embodiments.

[0126] See also Figure 7 and Fig. 8A In step S100, a first bonding insulating layer LD may be formed on the first substrate W1. The first bonding insulating layer LD may include at least one vertical expansion inducing layer SN1, CN1 and at least one buffer layer SO1. As mentioned above, the vertical expansion inducing layers SN1, CN1 and the buffer layer SO1 may include a dielectric material. The vertical expansion inducing layers SN1, CN1 may be denser and harder than the buffer layer SO1. For example, the vertical expansion inducing layer SN1 may be a silicon nitride layer, and the vertical expansion inducing layer CN1 may be a silicon carbonitride layer. The buffer layer SO1 may be a silicon oxide layer. The first substrate W1 may have a plurality of semiconductor circuit patterns (not shown). Alternatively, the first substrate W1 may be a bare silicon substrate.

[0127] See also Figure 7 and Figure 8B In step S200, at least one first metal pad MP1 may be formed in the first bonding insulating layer LD. In more detail, the first bonding insulating layer LD may be etched to form at least one first opening (not shown). A metal layer (e.g., a copper (Cu) layer) may be formed to fill the first opening. The metal layer may be planarized to form at least one first metal pad MP1, thereby forming a first bonding structure BDS1.

[0128] See also Figure 7 and Figure 8C In step S300, a second bonding insulating layer UD may be formed on the second substrate W2. Similar to the first bonding insulating layer LD, the second bonding insulating layer UD may include at least one vertical expansion inducing layer SN2, CN2 and at least one buffer layer SO2. The second substrate W2 may have a plurality of semiconductor circuit patterns (not shown). Alternatively, the second substrate W2 may be a bare silicon substrate.

[0129] See also Figure 7 and Fig.8D In step S400, at least one second metal pad MP2 may be formed in the second bonding insulating layer UD. In more detail, the second bonding insulating layer UD may be etched to form at least one second opening (not shown). A metal layer (e.g., a copper (Cu) layer) may be formed to fill the second opening. The metal layer may be planarized to form at least one second metal pad MP2, thereby forming a second bonding structure BDS2.

[0130] See also Figure 7 and Fig. 8E In step S500, the second bonding structure BDS2 may be stacked on the first bonding structure BDS1 so that the first metal pad MP1 and the second metal pad MP2 face each other. The first bonding insulation layer LD and the second bonding insulation layer UD may be bonded to each other to apply physical force. Then, the first metal pad MP1 and the second metal pad MP2 may be hybrid-bonded by an annealing process to form a bonding stack structure BSS.

[0131] In various embodiments, the first bonding structure BDS1 and the second bonding structure BDS2 may include any one of the first to fourth bonding structures 100, 200, 300, and 400. In addition, the first bonding structure BDS1 and the second bonding structure BDS2 may have the same structure or different structures.

[0132] 9A to 9C is a cross-sectional view illustrating a hybrid bonding method of a lower bonding structure and an upper bonding structure according to an embodiment.

[0133] See also Fig. 9A , the hybrid bonding device may include a lower vacuum chuck VC1 and an upper vacuum chuck VC2. To form a bonded stack structure, a first bonded structure BDS1 may be loaded above the lower vacuum chuck VC1. The first bonded structure BSD1 may be fixed using vacuum. The upper vacuum chuck VC2 may fix and pick up the second bonded structure BSD2.

[0134] See also Fig. 9B and Fig. 8E , the second bonding structure BDS2 can be arranged on the first bonding structure BDS1 using the upper vacuum suction cup VC2. The vacuum state in the upper center area of ​​the second bonding structure BDS2 can be released. The vacuum state in the outer area of ​​the upper vacuum suction cup VC2 can be maintained. The center area of ​​the second bonding structure BDS2 can be brought into contact with the center area of ​​the first bonding structure BDS1 using a tip. The vacuum of the upper vacuum suction cup VC2 can then be released to bring the second bonding structure BDS2 into contact with the upper surface of the first bonding structure BSD1. The first bonding insulating layer LD of the first bonding structure BDS1 and the second bonding insulating layer UD of the second bonding structure BDS2 can be mixed and bonded to each other. The bonding between the first bonding insulating layer LD and the second bonding insulating layer UD can be induced by heating at room temperature or a relatively low temperature. The interface of the first metal pad MP1 may not be separated from the interface of the second metal pad MP2.

[0135] See also Fig. 9C and Fig. 8EThe first bonding structure BSD1 and the second bonding structure BSD2 may be annealed at about 100° C. to about 300° C. for about 0.1 hour to about 3 hours. Then, the metal pads MP1 and MP2 may be thermally expanded to bond the metal pads MP1 and MP2 to each other, thereby forming a bonding stack structure BSS.

[0136] Fig.10 is a cross-sectional view illustrating a semiconductor memory device implemented by a semiconductor device according to various embodiments.

[0137] See also Fig.10 The semiconductor device 1000 of various embodiments may include a first semiconductor structure SEM1 and a second semiconductor structure SEM2 , the first semiconductor structure SEM1 including a first bonding structure BDS1 , and the second semiconductor structure SEM2 including a second bonding structure BDS2 .

[0138] The first semiconductor structure SEM1 may include a plurality of peripheral circuits PC. A first bonding structure BDS1 may be formed on the plurality of peripheral circuits PC. The first metal pads MP1 of the first bonding structure BDS1 may be electrically coupled to the plurality of peripheral circuits PC, respectively. For example, the plurality of peripheral circuits PC may correspond to a device layer of the first semiconductor structure SEM1.

[0139] The second semiconductor structure SEM2 may include a memory cell array MCA. The memory cell array MCA may include a plurality of memory cells. A second bonding structure BDS2 may be formed on the memory cell array MCA. The second metal pads MP2 of the second bonding structure BDS2 may be electrically coupled to the plurality of memory cells, respectively. For example, the memory cell array MCA may correspond to a device layer of the second semiconductor structure SEM2.

[0140] The first bonding structure BDS1 of the first semiconductor structure SEM1 may be hybrid-bonded to the second bonding structure BDS2 of the second semiconductor structure SEM2. Thus, the plurality of peripheral circuits PC may be electrically coupled to the plurality of memory cells.

[0141] The above embodiments are intended to illustrate rather than limit the description. Various alternatives and equivalents are possible. The description is not limited to the embodiments described herein. These embodiments are also not limited to any particular type of semiconductor device.

Claims

1. A bonding structure comprising: a plurality of bonding pads; as well as a bonding insulating layer configured to electrically isolate the bonding pads from each other, the bonding insulating layer comprising at least one dielectric layer and at least one vertical expansion inducing layer over the dielectric layer, Wherein the vertical expansion inducing layer comprises a hardness greater than a hardness of the dielectric layer. 2 . The bonded structure of claim 1 , further comprising an additional vertical expansion inducing layer located below the dielectric layer. 3 . The bonding structure according to claim 2 , wherein a total thickness of the vertical expansion inducing layer and the additional vertical expansion inducing layer corresponds to 40% to 90% of a thickness of the bonding insulating layer. 4 . The bonding structure according to claim 2 , wherein at least one of the vertical expansion inducing layer and the additional vertical expansion inducing layer comprises at least one of nitrogen and carbon. 5 . The bonding structure according to claim 4 , wherein at least one of the vertical expansion inducing layer and the additional vertical expansion inducing layer comprises at least one of a silicon nitride layer and a silicon carbonitride layer.

6. A semiconductor device comprising: a first bonding structure, the first bonding structure comprising a first bonding layer; as well as a second bonding structure comprising a second bonding layer bonded to the first bonding layer, At least one of the first bonding layer and the second bonding layer comprises: a plurality of bonding pads; as well as a bonding insulating layer disposed between the plurality of bonding pads, the bonding insulating layer including an upper region adjacent to a bonding surface between the first bonding layer and the second bonding layer and a lower region below the upper region, and The interface stress between the upper region of the bonding insulation layer and the bonding pad is greater than the interface stress between the lower region of the bonding insulation layer and the bonding pad.

7. The semiconductor device of claim 6, wherein the upper region of the bonding insulating layer comprises at least one first dielectric material, the lower region of the bonding insulating layer comprises at least one second dielectric material, and the first dielectric material comprises a hardness greater than a hardness of the second dielectric material.

8. The semiconductor device according to claim 7, wherein the bonding insulating layer further comprises a dielectric layer located below the lower region, The dielectric layer includes a third dielectric material, the third dielectric material including a hardness greater than a hardness of the second dielectric material. 9 . The semiconductor device of claim 8 , wherein at least one of the first dielectric material and the third dielectric material comprises at least one of silicon nitride and silicon carbonitride.

10. The semiconductor device according to claim 6, wherein a thickness of the upper region of the bonding insulating layer is greater than a thickness of the lower region of the bonding insulating layer, and The upper region of the bonding insulating layer includes at least one of silicon nitride, silicon nitride oxide, and silicon carbide, and the lower region of the bonding insulating layer includes silicon oxide.

11. A semiconductor device comprising: Equipment layer; as well as a bonding structure formed over the device layer, the bonding structure comprising a bonding insulating layer and at least one bonding pad formed in the bonding insulating layer, wherein the bonding insulating layer comprises a plurality of dielectric layers stacked from the device layer toward the bonding surface, At least one dielectric layer of the plurality of dielectric layers adjacent to the bonding surface comprises a first dielectric material, and the remaining dielectric layers comprise a second dielectric material having a hardness less than that of the first dielectric material. 12 . The semiconductor device according to claim 11 , wherein a volume ratio of the first dielectric material in the bonding insulating layer is greater than a volume ratio of the second dielectric material in the bonding insulating layer. 13 . The semiconductor device according to claim 11 , wherein a thickness of the first dielectric material is 40% to 90% of a thickness of the bonding insulating layer.

14. The semiconductor device of claim 11, wherein the first dielectric material comprises at least one of nitrogen and carbon.

15. A method for manufacturing a semiconductor device, the method comprising: providing a first bonding structure, the first bonding structure comprising a first bonding insulating layer and at least one first bonding pad in the first bonding insulating layer; providing a second bonding structure, the second bonding structure comprising a second bonding insulating layer and at least one second bonding pad in the second bonding insulating layer; bonding the first bonding structure and the second bonding structure so that the first bonding insulating layer contacts the second bonding insulating layer; as well as thermally expanding the first bonding pad and the second bonding pad in a vertical direction to hybrid-bond the first bonding pad to the second bonding pad, Wherein providing the first bonding structure comprises: forming at least one first buffer layer; forming at least one first vertical expansion inducing layer over the first buffer layer, the first vertical expansion inducing layer comprising a hardness higher than that of the first buffer layer; and The first bonding pad is formed through the first vertical expansion inducing layer and the first buffer layer.

16. The method of claim 15, wherein the first vertical expansion inducing layer is positioned in contact with the second engagement structure.

17. The method of claim 15, wherein providing the second engagement structure comprises: forming at least one second buffer layer; forming at least one second vertical expansion inducing layer over the second buffer layer, the second vertical expansion inducing layer comprising a hardness higher than that of the second buffer layer; and forming the second bonding pad through the second vertical expansion inducing layer and the second buffer layer, Wherein when the first bonding structure is hybrid-bonded to the second bonding structure, the second vertical expansion inducing layer directly contacts the first vertical expansion inducing layer. 18 . The method of claim 17 , wherein at least one of the first vertical expansion inducing layer and the second vertical expansion inducing layer comprises at least one of nitrogen and carbon.

19. The method according to claim 18, wherein the first vertical expansion inducing layer is formed to have a first thickness corresponding to 40% to 90% of a thickness of the first bonding insulating layer, and The second vertical expansion inducing layer is formed to have a thickness corresponding to 40% to 90% of a thickness of the second joining insulating layer.

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