Package and method of manufacturing semiconductor device

Abstract

In one embodiment, a package includes a first die over and bonded to a first side of a second die, where the second die includes: a first substrate; a first interconnect structure over the first substrate; a seal ring disposed within the first interconnect structure; a first dummy through substrate via (TSV) extending through an edge region of the first substrate of the second die and in physical contact with the sealing ring; and a functional TSV extending through a central region of the first substrate of the second die. The embodiment of the invention also relates to a method for manufacturing the semiconductor device.

Description

Technical Field

[0001] Embodiments of the present application relate to packages and methods of manufacturing semiconductor devices. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices, as examples. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive material layers over a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon. Tens or hundreds of integrated circuits are typically manufactured on a single semiconductor wafer. Individual dies are separated by sawing the integrated circuits along the scribe lines. The individual dies are then individually packaged, for example, in a multi-chip module or other type of package.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.) by continually reducing minimum feature size, which allows more components to be integrated into a given area. Summary of the invention

[0004] Some embodiments of the present application provide a package, comprising: a first die, located above a first side of a second die and bonded to the first side of the second die, wherein the second die comprises: a first substrate; a first interconnect structure, located above the first substrate; a sealing ring, disposed within the first interconnect structure; a first dummy substrate through via (TSV), extending through an edge region of the first substrate of the second die and in physical contact with the sealing ring; and a functional substrate through via, extending through a central region of the first substrate of the second die.

[0005] Some other embodiments of the present application provide a package, comprising: a first die, comprising: a first substrate; a first interconnect structure, located on the first substrate; a first sealing ring, arranged in the first interconnect structure; and a first dummy substrate through hole (TSV), extending through an edge area of ​​the first substrate of the first die, wherein the first dummy substrate through hole overlaps with the first sealing ring; and a second die, arranged below the first die, the first die being bonded to a first side of the second die, the second die comprising: a second substrate; a functional substrate through hole, extending through a central area of ​​the second substrate of the second die; a second interconnect structure, located on the second substrate; a second sealing ring, arranged in the second interconnect structure; and a second dummy substrate through hole, extending through an edge area of ​​the second substrate of the second die, wherein the second dummy substrate through hole is arranged to be located around the functional substrate through hole.

[0006] Still other embodiments of the present application provide a method for manufacturing a semiconductor device, the method comprising: forming a top die, wherein forming the top die comprises: forming a device layer on the front side of a substrate; forming a first dummy substrate through hole (TSV) extending through the device layer and an edge region of the substrate; forming a functional substrate through hole extending through the device layer and a central region of the substrate, wherein the first dummy substrate through hole is arranged around the functional substrate through hole; and forming an interconnect structure above the front side of the substrate, wherein forming the interconnect structure comprises forming a sealing ring that overlaps with and is in physical contact with the first dummy substrate through hole; and bonding the top die to a bottom die, wherein bonding the top die to the bottom die comprises bonding a first bonding pad of the top die to a second bonding pad of the bottom die. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1A to Figure 2 Cross-sectional and top views of intermediate steps during a process for forming a semiconductor die are shown in accordance with some embodiments.

[0009] Figures 3 to 6 Cross-sectional and top views of intermediate steps during a process for forming a semiconductor die are shown according to other embodiments.

[0010] Figures 7 to 9 Cross-sectional views of intermediate steps during a process for forming an integrated chip package are shown in accordance with some embodiments.

[0011] Fig. 10A and Fig. 10B Cross-sectional and top views of intermediate steps during a process for forming a semiconductor die are shown in accordance with some embodiments.

[0012] Fig.11A and Fig. 11B Cross-sectional and top views of intermediate steps during a process for forming a semiconductor die are shown in accordance with some embodiments.

[0013] Figures 12 to 16 Cross-sectional and top views of intermediate steps during a process for forming a semiconductor die are shown according to other embodiments.

[0014] Figures 17 to 21Cross-sectional views of intermediate steps during a process for forming an integrated chip package are shown in accordance with some embodiments.

[0015] Fig. 22 Cross-sectional views of intermediate steps during a process for forming an integrated chip package according to other embodiments are shown. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0017] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0018] Various embodiments provide methods suitable for forming 3D integrated chip (3DIC) packages (such as integrated chip system (SoIC) packages). Forming an integrated chip package includes bonding a semiconductor die (e.g., a top die) to a semiconductor wafer (e.g., a bottom die). The top die may include a pseudo substrate through hole (TSV) disposed at a peripheral region (also referred to as an edge region) of the top die. The semiconductor wafer may also include a pseudo substrate through hole (TSV) disposed at a peripheral region (also referred to as an edge region) of the semiconductor wafer. For example, the pseudo TSV may be uniformly distributed in the top die along the edge region of the top die. The pseudo TSV may also be uniformly distributed in the semiconductor wafer along the edge region of the semiconductor wafer. The pseudo TSV includes a metal and is used to increase the metal density of the edge region of the top die, and reduce the difference between the metal density of the edge region of the top die and the metal density of the center region of the top die. Advantageous features of one or more embodiments disclosed herein may include reducing the difference between the coefficient of thermal expansion (CTE) of the edge region of the top die and the coefficient of thermal expansion (CTE) of the center region of the top die. This allows to reduce the thermal stress generated in the top die, and therefore, there is a risk of reduced warping of the top die. This ensures that the edge region of the top die does not bend upward (also referred to as tilting) away from the top surface of the semiconductor wafer, and allows sufficient physical contact between the bonding pads of the edge region of the top die and the corresponding bonding pads of the semiconductor wafer. In this way, the bonding between the top die and the semiconductor wafer is improved, and device reliability is enhanced. In addition, preventing the edge region of the top die from tilting upward away from the top surface of the semiconductor wafer reduces the risk of forming a gap between the top die and the semiconductor wafer. Therefore, the risk of chemical damage or moisture damage to the exposed surfaces of the top die and the semiconductor wafer located in the gap during the processing steps subsequently implemented is reduced.

[0019] Figures 1A to 9 Cross-sectional views of intermediate steps during a process for forming an integrated chip package 10 are shown, in accordance with some embodiments. FIG. 10A to FIG. 21 2 shows a cross-sectional view of an intermediate step during a process for forming an integrated chip package 20 according to some embodiments. Figure 1A and Figure 1B , a semiconductor die 150 is shown. Figure 1A A cross-sectional view of semiconductor die 150 is shown. Figure 1BA top view of a semiconductor die 150 is shown. The semiconductor die 150 may be referred to as a top die subsequently. The semiconductor die 150 may be a logic die (e.g., an application processor (AP), a central processing unit, a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a hybrid memory cube (HBC), a static random access memory (SRAM) die, a wide input / output (wide IO) memory die, a magnetoresistive random access memory (mRAM) die, a resistive random access memory (rRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front end (AFE) die), a biomedical die, etc. The semiconductor die 150 may also be a system-on-chip (SoC) die, etc. The semiconductor die 150 may include a substrate 117 (e.g., a semiconductor substrate), an interconnect structure 119 disposed on the substrate 117, a dielectric layer 120 disposed on the interconnect structure 119, a bonding layer 121 disposed on the dielectric layer 120, and a bonding pad 123 disposed in the bonding layer 121 and exposed at a front side of the semiconductor die 150. The side of the semiconductor die 150 including the exposed bonding pad 123 and the bonding layer 121 may also be subsequently referred to as a front side of the semiconductor die 150. The side of the semiconductor die 150 including the exposed backside surface of the substrate 117 may also be subsequently referred to as a backside of the semiconductor die 150.

[0020] The substrate 117 of the semiconductor die 150 may include a crystalline silicon wafer. The substrate 117 may include various doped regions depending on the design requirements (e.g., a p-type substrate or an n-type substrate). In some embodiments, the doped regions may be doped with p-type or n-type dopants. The doped regions may be doped with: p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and / or combinations thereof. The doped regions may be configured for n-type fin field effect transistors (FinFETs) and / or p-type FinFETs. In some optional embodiments, the substrate 117 may include an active layer of a semiconductor on insulator (SOI) substrate. The substrate 117 may include: other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

[0021] Active and / or passive devices, such as transistors, diodes, capacitors, resistors, etc., may be formed in and / or on the substrate 117. For example, these active and / or passive devices may be formed in the front end of line (FEOL) layer 118 of the substrate 117 (later formed in Figures 2 to 4A 117). The devices may be interconnected by an interconnect structure 119. The interconnect structure 119 electrically connects the devices on the substrate 117 to form one or more integrated circuits. The interconnect structure 119 may include one or more dielectric layers (e.g., one or more interlayer dielectric (ILD) layers, intermetallic dielectric (IMD) layers, etc.) and a metallization pattern 126 (which may also be referred to as interconnect wiring) embedded in the one or more dielectric layers. The material of the one or more dielectric layers may include silicon oxide (SiO x , where x>0), silicon nitride (SiN x , where x>0), silicon oxynitride (SiO x N y , where x>0 and y>0) or other suitable dielectric materials. The metallization pattern 126 may include metal wiring. For example, the metallization pattern 126 may include copper wiring, copper pads, aluminum pads, or a combination thereof formed by one or more single damascene processes, dual damascene processes, etc. In addition, the interconnect structure 119 may include a sealing ring 128, and the sealing ring 128 includes copper, aluminum, etc. The sealing ring 128 may be formed simultaneously with the metallization pattern 126 and use the same process and materials used to form the metallization pattern 126. The sealing ring 128 (in Figure 1B 1 (shown in dashed lines in FIG. 1 ) is disposed within the interconnect structure 119 and adjacent to an edge of the semiconductor die 150 (eg, near the periphery) and surrounds the metallization pattern 126 within the interconnect structure 119 .

[0022] Semiconductor die 150 also includes functional through substrate vias (TSVs) 112 that can be electrically connected to metallization patterns 126 in interconnect structure 119. TSVs 112 can extend through substrate 117 and can be disposed in a central region of semiconductor die 150 (e.g., as shown in FIG. Figure 1B 1). In an embodiment, TSV 112 may also extend partially or completely through the interconnect structure to electrically connect to metallization pattern 126. In addition, semiconductor die 150 includes dummy through substrate vias (TSVs) 111 extending through substrate 117. Dummy TSVs 111 may also extend partially or completely through interconnect structure 119. In an embodiment, dummy TSVs 111 may not be used for functional electrical or interconnect purposes. Dummy TSVs 111 may be uniformly distributed within semiconductor die 150 along an edge region of semiconductor die 150. In an embodiment, dummy TSVs 111 may be arranged along seal ring 128 (at Figure 1B111) are arranged so that each dummy TSV 111 overlaps with the seal ring 128. For example, the dummy TSV 111 is arranged on the seal ring 128 (for example, Figure 1A ) may be uniformly distributed (e.g., arranged at regular intervals) over and along the seal ring 128, wherein the bottom surface of the dummy TSV 111 is in physical contact with the seal ring 128. In other embodiments, a single dummy TSV 111 is uniformly distributed (e.g., arranged at regular intervals) over and along the seal ring 128, wherein the bottom surface of the dummy TSV 111 is in physical contact with the seal ring 128. The dummy TSV 111 may be arranged adjacent to an edge of the semiconductor die 150 (e.g., near the periphery), wherein the dummy TSV 111 is arranged around the TSV 112, and the TSV 112 may be arranged in a central region of the semiconductor die 150. In addition, the seal ring 128 within the interconnect structure 119 is arranged adjacent to an edge of the semiconductor die 150 (e.g., near the periphery), wherein the seal ring 128 surrounds the metallization pattern 126. Dummy TSVs 111 and TSVs 112 may include copper, tungsten, aluminum, silver, gold, combinations thereof, etc. TSVs 112 provide electrical connections from the back side of substrate 117 to the front side of substrate 117 .

[0023] Further references Figure 1A and Figure 1B , a dielectric layer 120 may be disposed on the interconnect structure 119. The dielectric layer 120 may include silicon oxide, silicon nitride, etc., and may be formed using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, etc. In an embodiment, the dielectric layer 120 may include two or more dielectric sublayers. The semiconductor die 150 may also include one or more contact pads 124 that are made to be externally connected to the devices in and / or on the interconnect structure 119, the metallization pattern 126, and the substrate 117. One or more contact pads 124 may be embedded in the dielectric layer 120. To form the contact pads 124, an opening for the contact pads 124 is first formed in the dielectric layer 120 using acceptable photolithography and etching techniques. A deposition process such as sputtering, evaporation, CVD, plasma enhanced chemical vapor deposition (PECVD), a plating process, an electroless plating process, a combination thereof, etc. may then be used to form a conductive material in the opening. The conductive material may include copper, aluminum, or another conductive material.

[0024] A bond pad via (BPV) 130 may also be formed to extend through the dielectric layer 120. The BPV 130 may be formed by first forming a first opening and a second opening in the dielectric layer 120 by, for example, etching, etc. The first opening may expose a surface of the seal ring 128 or a surface of a corresponding contact pad 125 (if present) (which may then be exposed in the subsequent Figure 2), and the second opening may expose the surface of the metallization pattern 126 (e.g., the surface of the contact pad). A conductive material is then deposited in the first opening and the second opening. The conductive material may be formed by an electrochemical plating process, CVD, ALD, PVD, a combination thereof, or the like. Examples of conductive materials are copper, aluminum, silver, gold, a combination thereof, or the like. Excess conductive material may be removed from the front side of the semiconductor die 150 by, for example, chemical mechanical polishing. The remaining conductive material in the first opening forms a first BPV 130 that is in physical contact with the seal ring 128 or the corresponding contact pad 125 (if present). The remaining conductive material in the second opening forms a second BPV 130 that is in physical and electrical contact with the metallization pattern 126. In an embodiment, the first BPV 130 may be optional and not formed, and only the second BPV 130 is formed.

[0025] The bonding layer 121 is disposed on the dielectric layer 120 and may include a dielectric layer. The bonding pads 123 (e.g., first bonding pads 123 and second bonding pads 123) are embedded in the bonding layer 121, wherein the second bonding pads 123 allow electrical connections to be made to the metallization pattern 126 of the interconnect structure 119, the TSV 112, the contact pads 124, and the devices in or on the substrate 117 through the second BPV 130 extending through the dielectric layer 120. The first bonding pads 123 may be connected to the substrate 117 through the first BPV 130, the contact pads 125 (later in FIG. Figure 2 1) and the sealing ring 128 are electrically connected to the dummy TSV 111. The first bonding pad 123 and the first BPV 130 are optional and may not exist in some embodiments. The material of the bonding layer 121 may be silicon oxide (SiO x , where x>0), silicon nitride (SiN x , where x>0), silicon oxynitride (SiO x N y , where x>0 and y>0), tetraethyl orthosilicate (TEOS) or other suitable dielectric materials, and the bonding pad 123 may include a conductive pad (e.g., a copper pad), a conductive via (e.g., a copper via), or a combination thereof. The bonding layer 121 may be formed by: depositing a dielectric material on the dielectric layer 120 and the BPV 130 using a CVD process (e.g., a plasma enhanced CVD process or other suitable process); patterning the dielectric material to form a bonding layer 121 including an opening or a hole; and filling the opening or hole defined in the bonding layer 121 with a conductive material to form a bonding pad 123 embedded in the bonding layer 121.

[0026] Figure 2 It shows that according to the embodiment Figure 1A132 of the semiconductor die 150 shown in FIG. 13. To form the semiconductor die 150, a FEOL layer 118 is first formed in and / or on the front side of the substrate 117. The side of the substrate 117 opposite the front side of the substrate may be referred to as the back side of the substrate 117. The FEOL layer 118 includes active and / or passive devices, such as transistors, diodes, capacitors, resistors, etc. After the FEOL layer 118 is formed, the dummy TSVs 111 and TSVs 112 are then formed to extend completely through the substrate 117 (e.g., including the FEOL layer 118). The dummy TSVs 111 and TSVs 112 may be formed by first forming openings in the front side of the substrate 117 that partially extend through the substrate 117 (e.g., including the FEOL layer 118) by, for example, etching, milling, laser techniques, combinations thereof, etc. A thin barrier layer (not shown) may be conformally deposited in the opening, such as by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, combinations thereof, and the like. The barrier layer may include a nitride or oxynitride, such as titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, combinations thereof, and the like. A conductive material is deposited over the thin barrier layer and in the opening. The conductive material may be formed by an electrochemical plating process, CVD, ALD, PVD, combinations thereof, and the like. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, combinations thereof, and the like. Excess conductive material and barrier layer may be removed from the front side of the substrate 117 by, for example, chemical mechanical polishing. Therefore, in some embodiments, the pseudo TSV 111 and TSV 112 may include a conductive material and a thin barrier layer between the conductive material and the substrate 117. In a subsequent processing step, the back side of the substrate 117 may be thinned to expose the pseudo TSV 111 and TSV 112. After thinning, TSV 112 provides an electrical connection from the back side of substrate 117 to the front side of substrate 117. Dummy TSV 111 may be evenly distributed in substrate 117 along the edge region of semiconductor die 150, while TSV 112 is disposed in substrate 117 in the center region of semiconductor die 150. Figure 1A , Figure 1B and Figure 2 As seen in FIG. 1 , dummy TSVs 111 are disposed adjacent to an edge of semiconductor die 150 (eg, near a periphery) and are disposed around TSVs 112 .

[0027] After forming the dummy TSV 111 and the TSV 112, an interconnect structure 119 is then formed on the front side of the substrate 117. The interconnect structure 119 may include one or more dielectric layers (e.g., one or more interlayer dielectric (ILD) layers, intermetallic dielectric (IMD) layers, etc.) and a metallization pattern 126 embedded in the one or more dielectric layers. The material of the one or more dielectric layers may include silicon oxide (SiO2) formed using a CVD process, an ALD process, etc. x , where x>0), silicon nitride (SiN x , where x>0), silicon oxynitride (SiO x N y , where x>0 and y>0) or other suitable dielectric materials. Each dielectric layer can be patterned using acceptable photolithography and etching techniques to form openings corresponding to the desired pattern for the metallization pattern 126, which will be formed to extend along the main surface of the dielectric layer and extend through the dielectric layer. Then, a conductive material is formed in the opening of the dielectric layer using, for example, a PVD process, electroplating, chemical plating, a combination thereof, etc. to form the metallization pattern 126. The conductive material may include metals such as copper, titanium, tungsten, aluminum, a combination thereof, etc. The metallization pattern 126 is used to electrically connect the devices in the TSV 112 and the FEOL layer 118 to the contact pads 124, the bond pad through-vias (BPVs) 130, and the bond pads 123 that are subsequently formed.

[0028] The interconnect structure 119 also includes a seal ring 128. The seal ring 128 can be formed in the interconnect structure 119 at the same time as the metallization pattern 126, and using the same process and materials used to form the metallization pattern 126. The seal ring 128 is disposed within the interconnect structure 119 and adjacent to the edge of the semiconductor die 150 (e.g., near the periphery), and surrounds the metallization pattern 126 within the interconnect structure 119. The seal ring 128 extends vertically through one or more dielectric layers of the interconnect structure 119 to physically contact the dummy TSVs 111 arranged along the seal ring 128 (as previously described). Figure 1B ). Thus, when semiconductor die 150 is oriented in such a manner that substrate 117 is disposed vertically above interconnect structure 119, each dummy TSV 111 overlaps seal ring 128. In an embodiment, width W1 of seal ring 128 may vary along the vertical height of seal ring 128.

[0029] After forming the interconnect structure 119, a first portion of the contact pad 125 is formed in one or more dielectric layers of the interconnect structure 119. To form the first portion of the contact pad 125, a first opening is first formed in one or more dielectric layers of the interconnect structure 119 using acceptable photolithography and etching techniques. The first opening exposes the surface of the seal ring 128. A deposition process such as sputtering, evaporation, CVD, plasma enhanced chemical vapor deposition (PECVD), a plating process, an electroless plating process, etc. may then be used to form a conductive material in the first opening. The conductive material may include copper, aluminum, or another conductive material. A planarization process is then performed to remove an excess portion of the conductive material, and the remaining conductive material in the first opening forms the first portion of the contact pad 125. In this way, the first portion of each contact pad 125 is embedded in one or more dielectric layers of the interconnect structure 119.

[0030] Then, the dielectric layer 120 (previously Figure 1A and Figure 1B 1 and 12. The first portion of the contact pad 125 is formed on the interconnect structure 119 and the first portion of the contact pad 125. Then the second portion of the contact pad 125 is formed in the dielectric layer 120, so that each second portion of the contact pad 125 is in physical contact with the corresponding first portion of the contact pad 125. In this way, each second portion of the contact pad 125 is embedded in the dielectric layer 120. In order to form the second portion of the contact pad 125, a second opening is first formed in the dielectric layer 120 using acceptable photolithography and etching techniques. The second opening exposes the surface of the corresponding first portion of the contact pad 125. Then a deposition process such as sputtering, evaporation, CVD, plasma enhanced chemical vapor deposition (PECVD), plating process, chemical plating process, etc. can be used to form a conductive material in the second opening. The conductive material may include copper, aluminum, or another conductive material. Then a planarization process is performed to remove an excess portion of the conductive material, and the remaining conductive material in the second opening forms the second portion of the contact pad 125. The second portion of each contact pad 125 may have a width greater than its corresponding first portion of the contact pad 125. Each contact pad 125 is in physical contact with the seal ring 128. When the semiconductor die 150 is oriented in such a manner that the substrate 117 is disposed vertically above the interconnect structure 119, each dummy TSV 111 overlaps with a corresponding contact pad 125. In addition, one or more contact pads 124 (previously Figure 1A and Figure 1B ) may also be formed in the dielectric layer 120.

[0031] After forming contact pad 124, contact pad 125 and dielectric layer 120, BPV 130 (previously Figure 1A and Figure 1B) to extend through the dielectric layer 120. Each of the first BPVs 130 may be in physical contact with a corresponding contact pad 125, and each of the second BPVs 130 may be in physical contact with a surface of the metallization pattern 126 (eg, a surface of a contact pad).

[0032] After forming the BPV 130, the bonding layer 121 and the bonding pad 123 (previously Figure 1A and Figure 1B 1) is formed over the dielectric layer 120 and the BPV 130. The bonding pads 123 (e.g., the first bonding pad 123 and the second bonding pad 123) are embedded in the bonding layer 121, wherein the second bonding pad 123 allows electrical connection to be made to the metallization pattern 126 of the interconnect structure 119, the TSV 112, the contact pad 124, and the device in or on the substrate 117 through the second BPV 130 extending through the dielectric layer 120. The first bonding pad 123 can be electrically connected to the dummy TSV 111 through the first BPV 130, the contact pad 125, and the sealing ring 128.

[0033] Advantages may be achieved due to forming a semiconductor die 150 including dummy TSVs 111 distributed within the semiconductor die 150 along an edge region of the semiconductor die 150. The dummy TSVs 111 may be arranged along the seal ring 128 such that each dummy TSV 111 overlaps and is in physical contact with the seal ring 128. The dummy TSVs 111 may be disposed over and along the seal ring 128 at regular intervals (e.g., uniformly distributed) or irregular intervals (e.g., non-uniformly distributed), wherein the dummy TSVs 111 are disposed around the TSVs 112 disposed within a central region of the semiconductor die 150. These advantages include: increasing the metal density of the edge region of the semiconductor die 150; and reducing the difference between the metal density of the edge region of the semiconductor die 150 and the metal density of the central region of the semiconductor die 150. This allows for a reduction in the difference between the coefficient of thermal expansion (CTE) of the edge region of the semiconductor die 150 and the coefficient of thermal expansion (CTE) of the central region of the semiconductor die 150. This results in reduced thermal stress generated within semiconductor die 150 and further results in reduced risk of warping of semiconductor die 150. This ensures that edge regions of semiconductor die 150 do not bend upward (also referred to as tilt) away from wafer 200 (which is subsequently Figure 7200) is bonded to the top surface of the wafer 200, and allows sufficient physical contact between the bonding pads 123 on the edge region of the semiconductor die 150 and the corresponding bonding pads 223 on the wafer 200. In this way, the bonding between the semiconductor die 150 and the wafer 200 is improved, and the device reliability is enhanced. In addition, preventing the edge region of the semiconductor die 150 from tilting upward away from the top surface of the wafer 200 reduces the risk of forming a gap between the semiconductor die 150 and the wafer 200. Therefore, the risk of chemical damage or moisture damage to the exposed surfaces of the semiconductor die 150 and the wafer 200 located within the gap during the processing steps that are subsequently performed is reduced.

[0034] Figure 3 According to an alternative embodiment, Figure 1A 1. Unless otherwise specified, the same reference numerals in this embodiment (and the embodiments discussed subsequently) refer to semiconductor die 150 formed by the same process. Figure 1A to Figure 2 Therefore, the process steps and applicable materials may not be repeated herein.

[0035] Figure 3 The semiconductor die 150 shown in the embodiment is Figure 2 The semiconductor die 150 shown in the embodiment is different in that when forming Figure 3 In the semiconductor die 150 shown in the embodiment of FIG. 1 , the dummy TSV 111 is first formed to partially extend through the substrate 117 before the FEOL layer 118 is formed in and / or on the front side of the substrate 117. The TSV 112 may be formed after the FEOL layer 118 is formed in and / or on the front side of the substrate 117, as previously described. Figure 2 Described in .

[0036] The side of the substrate 117 opposite to the front side of the substrate may be referred to as the back side of the substrate 117. The pseudo TSV 111 is formed to extend partially through the substrate 117. The pseudo TSV 111 may be formed by first forming an opening extending partially through the substrate 117 in the back side of the substrate 117 by, for example, etching, milling, laser technology, combinations thereof, etc. A thin barrier layer (not shown) may be conformally deposited in the opening, such as by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, combinations thereof, etc. The barrier layer may include a nitride or oxynitride, such as titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, combinations thereof, etc. A conductive material is deposited over the thin barrier layer and in the opening. The conductive material may be formed by an electrochemical plating process, CVD, ALD, PVD, combinations thereof, etc. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, combinations thereof, etc. Excess conductive material and the barrier layer may be removed from the back side of the substrate 117 by, for example, chemical mechanical polishing. Thus, in some embodiments, the dummy TSV 111 may include a conductive material and a thin barrier layer between the conductive material and the substrate 117. After forming the dummy TSV 111, a FEOL layer 118 may be formed in and / or on the front side of the substrate 117.

[0037] After forming the FEOL layer 118 and the dummy TSV 111, the TSV 112 may be formed, as previously described. Figure 2 The dummy TSVs 111 may be uniformly distributed in the substrate 117 along the edge region of the semiconductor die 150, while the TSVs 112 are disposed in the substrate 117 in the center region of the semiconductor die 150. In this manner, Figure 1A , Figure 1B and Figure 3 As seen in FIG. 1 , dummy TSV 111 is disposed adjacent to an edge of semiconductor die 150 (eg, near the periphery) and is disposed around TSV 112. After forming TSV 112, interconnect structure 119 (eg, including seal ring 128 and metallization pattern 126) is formed, as previously described in Figure 1A , Figure 1B and Figure 2 In addition, after forming the interconnect structure 119, a dielectric layer 120, one or more contact pads 124, a contact pad 125, and a BPV 130 are formed, as previously described in Figure 1A , Figure 1B and Figure 2 In addition, after forming the dielectric layer 120, one or more contact pads 124, contact pads 125, and BPV 130, a bonding layer 121 and bonding pads 123 are formed over the dielectric layer 120 and BPV 130, as previously described in Figure 1A , Figure 1B and Figure 2 In an embodiment, each dummy TSV 111 may be electrically connected to a seal ring 128, a corresponding contact pad 125, a corresponding first BPV 130, and a corresponding first bonding pad 123 through a conductive plug 115 formed in a FEOL layer 118. In other embodiments, the dummy TSV 111 may be electrically isolated from the seal ring 128, the contact pad 125, the first BPV 130, and the first bonding pad 123. In an embodiment, the first bonding pad 123 and the first BPV 130 are optional and may not be formed.

[0038] Figure 4A According to an alternative embodiment, Figure 1A 1 . Edge region 132 of semiconductor die 150 is shown in FIG. Figure 4B The semiconductor die 150 is shown along Figure 4A Unless otherwise specified, the same reference numerals in this embodiment (and the embodiments discussed subsequently) refer to the same process. Figure 1A to Figure 2 Therefore, the process steps and applicable materials may not be repeated herein.

[0039] Figure 4A The semiconductor die 150 shown in the embodiment is Figure 2 The semiconductor die 150 shown in the embodiment is different in that when forming Figure 4A In the semiconductor die 150 shown in the embodiment of FIG. 1 , the dummy TSV 111 is formed after forming the FEOL layer 118, TSV 112, and interconnect structure 119 (e.g., including seal ring 128 and metallization pattern 126) in and / or on the front side of the substrate 117. First, the FEOL layer 118 is formed in and / or on the front side of the substrate 117, as previously described. Figure 1A , Figure 1B and Figure 2 After the FEOL layer 118 has been formed in and / or on the front side of the substrate 117, the TSV 112 may then be formed, as previously described in Figure 1A , Figure 1B and Figure 2 Described in .

[0040] After TSV 112 has been formed, interconnect structure 119 (including seal ring 128 and metallization pattern 126) is then formed, as previously described in Figure 1A , Figure 1B and Figure 2 The sealing ring 128 may be formed to have intermittent gaps in its structure, such as Figure 4BEach gap in the seal ring 128 structure is disposed between adjacent portions of the seal ring 128 , and the gap is filled with a dielectric material of one or more dielectric layers of the interconnect structure 119 .

[0041] The dummy TSVs 111 are then formed to extend through the substrate 117 (including the FEOL layer 118) and partially through the interconnect structure 119. Each dummy TSV 111 may extend through a corresponding gap between adjacent portions of the seal ring 128 (e.g., through dielectric material of one or more dielectric layers of the interconnect structure 119 disposed within the corresponding gap), such as Figure 4B . The pseudo TSV 111 can be formed by first forming an opening extending through the substrate 117 and partially through the interconnect structure 119 (e.g., through the dielectric layer of the interconnect structure 119) in the back side of the substrate 117 by, for example, etching, milling, laser technology, combinations thereof, etc. A thin barrier layer (not shown in the figure) can be conformally deposited in the opening, such as by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, combinations thereof, etc. The barrier layer can include a nitride or oxynitride, such as titanium nitride, titanium oxynitride, tantalum nitride, tungsten oxynitride, combinations thereof, etc. A conductive material is deposited over the thin barrier layer and in the opening. The conductive material can be formed by an electrochemical plating process, CVD, ALD, PVD, combinations thereof, etc. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, combinations thereof, etc. Excess conductive material and barrier layer can be removed from the back side of the substrate 117 by, for example, chemical mechanical polishing. Therefore, in some embodiments, dummy TSV 111 may include a conductive material and a thin barrier layer between the conductive material and substrate 117. Dummy TSV 111 may also include a conductive material and a thin barrier layer between the conductive material and a dielectric layer of interconnect structure 119. Dummy TSV 111 may be uniformly distributed within substrate 117 and interconnect structure 119 along an edge region of semiconductor die 150, while TSV 112 is disposed within substrate 117 in a central region of semiconductor die 150. In this manner, as shown in FIG. Figure 1A , Figure 1B , Figure 4A and Figure 4B As seen in FIG. 1 , dummy TSVs 111 are disposed adjacent to an edge of semiconductor die 150 (eg, near a periphery) and are disposed around TSVs 112 .

[0042] After forming the pseudo TSV 111, the first portion of the contact pad 125 is formed in one or more dielectric layers of the interconnect structure 119. In order to form the first portion of the contact pad 125, a first opening is first formed in one or more dielectric layers of the interconnect structure 119 using acceptable photolithography and etching techniques. The first opening exposes the surface of the pseudo TSV 111. Then a deposition process such as sputtering, evaporation, CVD, plasma enhanced chemical vapor deposition (PECVD), plating process, chemical plating process, etc. can be used to form a conductive material in the first opening. The conductive material may include copper, aluminum, or another conductive material. A planarization process is then performed to remove an excess portion of the conductive material, and the remaining conductive material in the first opening forms the first portion of the contact pad 125. In this way, the first portion of each contact pad 125 is embedded in one or more dielectric layers of the interconnect structure 119.

[0043] After the dummy TSV 111 and the first portion of the contact pad 125 have been formed, the dielectric layer 120, one or more contact pads 124, the second portion of the contact pad 125, and the BPV 130 are formed, as previously described in Figure 1A , Figure 1B and Figure 2 Each dummy TSV 111 may be in physical contact with a corresponding contact pad 125. In addition, after forming the dielectric layer 120, one or more contact pads 124, a second portion of the contact pad 125, and the BPV 130, a bonding layer 121 and a bonding pad 123 are formed over the dielectric layer 120 and the BPV 130, as previously described in Figure 1A , Figure 1B and Figure 2 . In an embodiment, each pseudo TSV 111 may be electrically connected to a corresponding contact pad 125, a corresponding first BPV 130, and a corresponding first bonding pad 123. In addition, each pseudo TSV is electrically isolated from the seal ring 128. In an embodiment, the first bonding pad 123 and the first BPV 130 are optional and may not be formed. When the semiconductor die 150 is oriented in such a manner that the substrate 117 is disposed vertically above the interconnect structure 119, each pseudo TSV 111 is in physical contact with and overlaps with the corresponding contact pad 125.

[0044] Figure 5 and Figure 6 A top view of a semiconductor die 150 according to an alternative embodiment is shown. Unless otherwise specified, like reference numerals in this embodiment (and subsequently discussed embodiments) denote semiconductor die 150 formed by the same process. Figures 1A to 4B Therefore, the process steps and applicable materials may not be repeated herein.

[0045] TSVs 112 may extend through substrate 117 and may be disposed in a central region of semiconductor die 150 (eg, as shown in FIG. 1 ). Figure 5 and Figure 6 119 to electrically connect to the metallization pattern 126. In addition, the semiconductor die 150 includes a dummy TSV 111 extending through the substrate 117. The dummy TSV 111 may also extend partially or completely through the interconnect structure 119. The dummy TSV 111 may be distributed within the semiconductor die 150 along an edge region of the semiconductor die 150. In an embodiment, the dummy TSV 111 may be distributed along the seal ring 128 (at Figure 5 and Figure 6 The pseudo TSVs 111 are arranged in a manner such that each pseudo TSV 111 overlaps with the sealing ring 128 and is in physical contact with the sealing ring 128. The clusters of pseudo TSVs 111 may be arranged to overlap with the corner regions of the sealing ring 128, such that the concentration of pseudo TSVs 111 along the corner regions of the sealing ring 128 is higher than that of other regions of the sealing ring 128. In addition, the semiconductor die 150 may also include pseudo TSVs 113, which are formed using a similar process and similar materials as the pseudo TSVs 111. The pseudo TSVs 113 may be arranged adjacent to the corner regions of the sealing ring 128, such that when viewed in a top view, the pseudo TSVs 113 are arranged within the inner perimeter of the sealing ring 128. Therefore, the pseudo TSVs 113 are not in physical contact with the sealing ring 128, and do not overlap with the sealing ring 128. In an embodiment, a single pseudo TSV 113 is arranged adjacent to each corner region of the sealing ring 128, such as Figure 5 In an embodiment, a cluster of dummy TSVs 113 (eg, more than one dummy TSV 113) is disposed adjacent to each corresponding corner region of the seal ring 128, as shown in FIG. Figure 6 as shown in .

[0046] exist Figure 7, semiconductor wafer 200 is bonded to semiconductor die 150. Wafer 200 may also be subsequently referred to as a bottom die. The materials and formation processes of components in wafer 200 can be found by referring to similar components in semiconductor die 150, where similar components in semiconductor die 150 start with the number "1", which corresponds to components in wafer 200 and has a reference number starting with the number "2". For example, wafer 200 may include a substrate 217 on which devices (e.g., transistors, capacitors, diodes, resistors, etc.) are formed and an interconnect structure 219. The interconnect structure 219 electrically connects the devices on substrate 217 to form one or more integrated circuits. The interconnect structure 219 includes one or more dielectric layers (e.g., one or more interlayer dielectric (ILD) layers, intermetallic dielectric (IMD) layers, etc.) and a metallization pattern 226 embedded in the one or more dielectric layers (which may also be subsequently referred to as interconnect wiring). In an embodiment, the interconnect structure 219 may or may not include a sealing ring ( Figure 7 The sealing ring is similar to that previously shown in Figures 1A to 6 The sealing ring 128 described in .

[0047] A dielectric layer 220 is disposed on the interconnect structure 219, a bonding layer 221 is disposed on the dielectric layer 220, and a bonding pad 223 is disposed in the bonding layer 221. The side of the wafer 200 including the bonding pad 223 and the bonding layer 221 may also be subsequently referred to as the front side of the wafer 200. The side of the wafer 200 including the exposed backside surface of the substrate 217 may also be subsequently referred to as the backside of the wafer 200. A bond pad via (BPV) 230 may extend through the dielectric layer 220, and the bonding pad 223 allows connections to be made to the interconnect structure 219 (e.g., metallization pattern 226) and devices on the substrate 217 through the BPV 230. One or more contact pads 224 may also be embedded within the dielectric layer 220 for making external connections to devices in and / or on the interconnect structure 219, the metallization pattern 226, and the substrate 217.

[0048] Still reference Figure 7, the semiconductor die 150 is bonded to the wafer 200, for example, in a hybrid bonding configuration. The semiconductor die 150 is disposed face-down and bonded to the wafer 200 such that the front side of the semiconductor die 150 is bonded to the front side of the wafer 200. The semiconductor die 150 is bonded to the bonding layer 221 on the front side of the wafer 200 and the bonding pads 223 in the bonding layer 221. For example, the bonding layer 121 of the semiconductor die 150 may be directly bonded to the bonding layer 221 of the wafer 200, and the bonding pads 123 of the semiconductor die 150 may be directly bonded to the bonding pads 223 of the wafer 200. In an embodiment, the bonding between the bonding layer 121 and the bonding layer 221 may be an oxide-to-oxide bonding, etc. The hybrid bonding process also directly bonds the bonding pads 123 of the semiconductor die 150 to the bonding pads 223 of the wafer 200 by direct metal-to-metal bonding. Thus, electrical connection between semiconductor die 150 and wafer 200 is provided by the physical connection of bond pad 123 to bond pad 223 .

[0049] As an example, the hybrid bonding process begins by aligning the semiconductor die 150 with the wafer 200, for example, by applying a surface treatment to one or more of the bonding layer 121 or the bonding layer 221. The surface treatment may include a plasma treatment. The plasma treatment may be implemented in a vacuum environment. After the plasma treatment, the surface treatment may also include a cleaning process (e.g., rinsing with deionized water, etc.) that may be applied to one or more of the bonding layer 121 or the bonding layer 221. Then, the hybrid bonding process may continue to align the bonding pad 123 with the bonding pad 223. Next, the semiconductor die 150 is contacted with the wafer 200, which may be at room temperature (e.g., between about 21° C. and about 25° C.). The hybrid bonding process continues with annealing, for example, at a temperature between about 150° C. and about 400° C. for a duration between about 0.5 hours and about 3 hours, so that the metal (e.g., copper) in the bonding pad 123 and the metal (e.g., copper) of the bonding pad 223 diffuse into each other, and thus form a direct metal-to-metal bond.

[0050] exist Figure 8In the embodiment, an insulating material 134 (also referred to as a gap filling material or a sealant) is formed over the semiconductor die 150 and the wafer 200 to seal the semiconductor die 150. According to some embodiments, the insulating material 134 may be an oxide (e.g., silicon dioxide), etc. The insulating material 134 may be formed by spin coating, high-density CVD, etc. After forming the insulating material 134, a planarization process may be performed to remove excess material of the insulating material 134 located above the semiconductor die 150 to expose the top surfaces of the substrate 117, the pseudo TSV 111, and the TSV 112. After the planarization process, the top surfaces of the substrate 117, the pseudo TSV 111, and the TSV 112 may be flush with the top surface of the insulating material 134 (within process variations). The planarization process may be a grinding process, a chemical mechanical polishing (CMP) process, etc. However, any suitable planarization process may be utilized.

[0051] exist Fig. 9 middle, Figure 8 The structure shown in FIG. 1 is shown as being flipped, wherein a dielectric layer 260 is formed on the bottom surface of the integrated chip package 10, such as on the exposed surfaces of the substrate 117, the dummy TSV 111, and the TSV 112. The dielectric layer 260 is also formed on the insulating material 134. In an embodiment, the dielectric layer 260 may include silicon oxide, silicon nitride, silicon oxynitride, a polymer, etc., and may be deposited by PVD, CVD, ALD, etc. Then, the dielectric layer 260 is patterned. The patterning forms an opening that exposes portions of the substrate 117 and the TSV 112 of the semiconductor die 150. The patterning may be performed by acceptable photolithography and etching techniques.

[0052] Then form metallization pattern 262.Metallization pattern 262 includes conductive elements extending along the main surface of dielectric layer 260 and extending through dielectric layer 260 to be physically and electrically coupled to TSV 112 of semiconductor die 150.As an example of forming metallization pattern 262, a seed layer is formed above dielectric layer 260 and in an opening extending through dielectric layer 260.In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials.In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer.The seed layer can be formed using, for example, PVD, etc. Then form and pattern photoresist on the seed layer.The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning.The pattern of the photoresist corresponds to metallization pattern 262.Patterning forms an opening through the photoresist to expose the seed layer.Then form a conductive material in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating, such as electroplating or chemical plating. The conductive material may include metals such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive material and the lower portion of the seed layer forms the metallization pattern 262. The photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet etching or dry etching.

[0053] After forming the dielectric layer 260 and the metallization pattern 262, a dielectric layer 264 is formed on the dielectric layer 260 and the metallization pattern 262. The dielectric layer 264 may be formed using similar processes and similar materials as those used during the formation of the dielectric layer 260. A metallization pattern 265 is then formed in the dielectric layer 264. The metallization pattern 265 may be formed using similar processes and similar materials as those used during the formation of the metallization pattern 262.

[0054] After forming the dielectric layer 264 and the metallization pattern 265, a dielectric layer 266 is formed on the dielectric layer 264 and the metallization pattern 265. The dielectric layer 266 may include a polymer such as polybenzoxazole (PBO), polyimide (PI), etc. In an embodiment, the dielectric layer 266 may include silicon oxide, silicon nitride, silicon oxynitride, etc. The dielectric layer 266 may be formed using spin coating, lamination, PVD, CVD, ALD, etc. The contact pad 268 may be embedded in the dielectric layer 266. To form the contact pad 268, an opening for the contact pad 268 is first formed in the first sublayer of the dielectric layer 266 using acceptable photolithography and etching techniques. Then, a deposition process such as sputtering, evaporation, CVD, plasma enhanced chemical vapor deposition (PECVD), a plating process, an electroless plating process, a combination thereof, etc. may be used to form a conductive material in the opening. The conductive material may include copper, aluminum, or another conductive material. A planarization process is then performed to remove excess conductive material from the surface of the first sub-layer of dielectric layer 266. A second sub-layer of dielectric layer 266 is then formed on the first sub-layer of dielectric layer 266 and contact pads 268. Contact pads 268 may be electrically connected to TSVs 112 through metallization patterns 265 and 262.

[0055] After forming contact pad 268 and dielectric layer 266, a first opening is formed in dielectric layer 266 to expose the surface of contact pad 268. The first opening can be formed using an acceptable etching technique. After forming the first opening, a dielectric layer 270 is formed on dielectric layer 266 and in the first opening. For example, dielectric layer 270 can be formed on the sidewalls in the first opening and on the exposed surface of contact pad 268 located within the first opening. Dielectric layer 270 can include a polymer, such as polyimide (PI) or the like. Dielectric layer 270 can be formed using spin coating, lamination, or the like.

[0056] After forming the dielectric layer 270, the lateral portion of the dielectric layer 270 located within the first opening is removed to re-expose the contact pad 268. The lateral portion of the dielectric layer 270 can be removed using an acceptable etching technique. After removing the lateral portion of the dielectric layer 270, the remaining portion of the dielectric layer 270 is still disposed on the sidewalls of each of the first openings.

[0057] Further references Fig. 9, an under bump metal (UBM) 272 is formed in the first opening for external connection to the contact pad 268. The UBM 272 has a bump portion located on and extending along the main surface of the dielectric layer 270, and has a through-hole portion extending through the dielectric layer 270 and the dielectric layer 266 to physically and electrically couple the contact pad 268. Therefore, the UBM 272 is electrically coupled to the TSV 112 and the metallization pattern 126 of the semiconductor die 150. In addition, the UBM 272 is also electrically connected to the metallization pattern 226 and the contact pad 224 of the wafer 200 through the BPV 130, the BPV 230, the bonding pad 123, and the bonding pad 223. The UBM 272 can be formed of the same material as the metallization patterns 126 and 226.

[0058] After forming UBM 272, conductive connector 274 is formed on UBM 272. Conductive connector 274 can be ball grid array (BGA) connector, solder ball, metal column, controlled collapse chip connection (C4) bump, micro bump, bump formed by chemical nickel plating-chemical palladium plating-immersion gold technology (ENEPIG), etc. Conductive connector 274 can include conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or their combination. In some embodiments, conductive connector 274 is formed by initially forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, reflow can be implemented to shape the material into a desired bump shape. Conductive connector 274 can be used to couple and electrically connect the integrated chip package 10 to other external devices, such as, for example, a packaging substrate, etc.

[0059] FIG. 10A to FIG. 21 1 shows a cross-sectional view of an intermediate step during a process for forming an integrated chip package 20 according to an alternative embodiment. Unless otherwise specified, like reference numerals in this embodiment (and subsequently discussed embodiments) denote components formed by the same process. Figures 1A to 9 Therefore, the process steps and applicable materials may not be repeated herein.

[0060] exist Fig. 10A and Fig. 10B , a semiconductor die 250 is shown. Fig. 10A A cross-sectional view of semiconductor die 250 is shown. Fig. 10B 2 shows a top view of a semiconductor die 250. The semiconductor die 250 may be similar to that previously described in Figures 1A to 9, except that semiconductor die 250 does not include functional TSVs 112 extending through substrate 117 of semiconductor die 250. Dummy TSVs 111 may be disposed adjacent to an edge of semiconductor die 250 (e.g., near a periphery) and may overlap and physically contact seal ring 128, as previously described in Figures 1A to 9 However, Fig. 10B As shown in FIG. 2 , no TSVs 112 are disposed within the central region of semiconductor die 250 .

[0061] Fig.11A and Fig. 11B Semiconductor die 350 is shown. Semiconductor die 350 may also be subsequently referred to as a bottom die. Materials and formation processes of components in semiconductor die 350 may be found by referring to similar components in semiconductor die 150, where similar components in semiconductor die 150 begin with the number "1", which corresponds to components in semiconductor die 350 and has a reference number beginning with the number "3". For example, semiconductor die 350 may include a substrate 317 on which devices (e.g., transistors, capacitors, diodes, resistors, etc.) are formed and an interconnect structure 319 on substrate 317. Interconnect structure 319 electrically connects the devices on substrate 317 to form one or more integrated circuits. Interconnect structure 319 includes one or more dielectric layers (e.g., one or more interlayer dielectric (ILD) layers, intermetallic dielectric (IMD) layers, etc.) and a metallization pattern 326 (which may also be subsequently referred to as interconnect wiring) embedded in the one or more dielectric layers. In an embodiment, interconnect structure 319 may include a sealing ring 328 (in Fig. 11B The sealing ring 328 is disposed within the interconnect structure 319 and adjacent to an edge of the semiconductor die 350 (eg, close to the periphery), and the sealing ring 328 surrounds the metallization pattern 326 within the interconnect structure 319.

[0062] Semiconductor die 350 also includes functional TSVs 312 that can be electrically connected to metallization patterns 326 in interconnect structure 319. TSVs 312 can extend through substrate 317 and can be disposed in a central region of semiconductor die 350 (eg, as shown in FIG. 1 ). Fig. 11B 312 may also extend partially or completely through the interconnect structure 319 to electrically connect to the metallization pattern 326. In addition, the semiconductor die 350 includes a dummy TSV 311 extending through the substrate 317. The dummy TSV 311 may also extend partially or completely through the interconnect structure 319. The dummy TSV 311 may be evenly distributed within the semiconductor die 350 along the edge region of the semiconductor die 350. In an embodiment, the dummy TSV 311 may be arranged along the seal ring 328 (at Fig. 11B311) are arranged so that each dummy TSV 311 overlaps with the seal ring 328. For example, the dummy TSV 311 is arranged on the seal ring 328 (for example, Fig.11A ) may be uniformly distributed (e.g., arranged at regular intervals) over and along the sealing ring 328, wherein the bottom surface of the pseudo TSV 311 is in physical contact with the sealing ring 328. In other embodiments, a single pseudo TSV 311 is uniformly distributed (e.g., arranged at regular intervals) over and along the sealing ring 328, wherein the bottom surface of the pseudo TSV 311 is in physical contact with the sealing ring 328. The pseudo TSV 311 may be arranged adjacent to the edge of the semiconductor die 350 (e.g., near the periphery), wherein the pseudo TSV 311 is arranged to be located around the TSV 312, and the TSV 312 is arranged in the central area of ​​the semiconductor die 350. The pseudo TSV 311 and the TSV 312 may include copper, tungsten, aluminum, silver, gold, combinations thereof, and the like. The TSV 312 provides an electrical connection from the back side of the substrate 317 to the front side of the substrate 317.

[0063] The dielectric layer 320 is disposed on the interconnect structure 319. The side of the semiconductor die 350 including the dielectric layer 320 may also be subsequently referred to as the front side of the semiconductor die 350. The side of the semiconductor die 350 including the exposed backside surface of the substrate 317 may also be subsequently referred to as the backside of the semiconductor die 350. One or more contact pads 324 may also be embedded within the dielectric layer 320 to make external connections to devices in and / or on the interconnect structure 319, the metallization pattern 326, and the substrate 317.

[0064] Fig.12 It shows that according to the embodiment Fig. 10A Edge region 232 of semiconductor die 250 is shown in FIG. Fig.12 It is also shown that Fig.11A 3. The edge region 332 of the semiconductor die 350 is shown in FIG. Unless otherwise specified, the same reference numerals for the semiconductor die 250 in this embodiment (and the embodiments discussed later) indicate that the semiconductor die 250 is formed by the same process. Figure 2 350 (e.g., describing the formation of semiconductor die 150). Therefore, process steps and applicable materials may not be repeated herein. In addition, unless otherwise specified, the materials and formation processes of the components in semiconductor die 350 shown in this embodiment (and the embodiments discussed subsequently) can be referred to by reference. Figure 2 Similar components in semiconductor die 150 may be found, where similar components in semiconductor die 150 begin with the number “1” and correspond to components in semiconductor die 350 and have reference numbers beginning with the number “3”.

[0065] like Fig. 10A and Fig.12 As shown in the corresponding edge region 232 of FIG. 1 , the process of forming semiconductor die 250 is similar to the process of forming semiconductor die 150 (previously described in Figure 2 117) in that when forming the semiconductor die 250, the TSV 112 is not formed to extend through the substrate 117. Instead, only the dummy TSV 111 is formed to extend completely through the substrate 117 (e.g., including the FEOL layer 118). In addition, the contact pad 125 and the first BPV 130 are not formed in the dielectric layer 120. However, the second BPV 130 is formed to be in physical contact with the surface of the metallization pattern 126 (e.g., the surface of the contact pad), as previously described in Figure 1A to Figure 2 Described in .

[0066] In addition, if Fig.11A and Fig.12 As shown in the corresponding edge region 332 of FIG. 1 , the process of forming semiconductor die 350 is similar to the process of forming semiconductor die 150 (previously described in Figure 2 ) is that when forming semiconductor die 350, contact pad 125 and BPV 130 (previously described in Figure 1A to Figure 2 ) is not formed in the dielectric layer 320.

[0067] Advantages may be achieved due to the formation of a semiconductor die 250 including pseudo TSVs 111 distributed within the semiconductor die 250 along an edge region of the semiconductor die 250. The pseudo TSVs 111 may be arranged along the seal ring 128 such that each pseudo TSV 111 overlaps with and is in physical contact with the seal ring 128. The pseudo TSVs 111 may be disposed over and along the seal ring 128 at regular intervals (e.g., uniformly distributed) or irregular intervals (e.g., non-uniformly distributed). In addition, the semiconductor die 350 is formed to include pseudo TSVs 311 distributed within the semiconductor die 350 along an edge region of the semiconductor die 350. The pseudo TSVs 311 may be arranged along the seal ring 328 such that each pseudo TSV 311 overlaps with and is in physical contact with the seal ring 328. The dummy TSVs 311 may be disposed over and along the seal ring 328 at regular intervals (e.g., uniformly distributed) or irregular intervals (e.g., non-uniformly distributed), wherein the dummy TSVs 311 are disposed around the TSVs 312 disposed within the central region of the semiconductor die 350. These advantages include: increasing the metal density of the edge region of the semiconductor die 250; and reducing the difference between the metal density of the edge region of the semiconductor die 250 and the metal density of the central region of the semiconductor die 250. This allows the difference between the coefficient of thermal expansion (CTE) of the edge region of the semiconductor die 250 and the coefficient of thermal expansion (CTE) of the central region of the semiconductor die 250 to be reduced. In addition, the metal density of the edge region of the semiconductor die 350 is increased, and therefore, the difference between the metal density of the edge region of the semiconductor die 350 and the metal density of the central region of the semiconductor die 350 is reduced. This allows the difference between the coefficient of thermal expansion (CTE) of the edge region of the semiconductor die 350 and the coefficient of thermal expansion (CTE) of the central region of the semiconductor die 350 to be reduced. This results in reduced thermal stress generated within each of semiconductor die 250 and semiconductor die 350, and further results in reduced risk of warping of semiconductor die 250 and semiconductor die 350. This ensures that the bottom surface of the edge region of semiconductor die 250 and the top surface of the edge region of semiconductor die 350 are not deformed after semiconductor die 250 is bonded to semiconductor die 350 (and subsequently after the bonding). Fig.18350) do not bend (also referred to as tilt) away from each other, and allow sufficient physical contact between the bonding pads 123 on the edge region of the semiconductor die 250 and the corresponding bonding pads 323 on the semiconductor die 350. In this way, the bonding between the semiconductor die 250 and the semiconductor die 350 is improved, and the device reliability is enhanced. In addition, preventing the edge region of the semiconductor die 250 from tilting upward away from the top surface of the semiconductor die 350 reduces the risk of a gap forming between the semiconductor die 250 and the semiconductor die 350. Therefore, the risk of chemical damage or moisture damage to the exposed surfaces of the semiconductor die 250 and the semiconductor die 350 located within the gap during the processing steps that are subsequently performed is reduced.

[0068] Fig.13 According to an alternative embodiment, Fig. 10A Edge region 232 of semiconductor die 250 is shown in FIG. Fig.13 Also shown is a diagram according to an alternative embodiment. Fig.11A 3. The edge region 332 of the semiconductor die 350 is shown in FIG. Unless otherwise specified, the same reference numerals for the semiconductor die 250 in this embodiment (and the embodiments discussed later) indicate that the semiconductor die 250 is formed by the same process. Fig.12 The same components in the embodiment shown in FIG. 1 (e.g., describing the formation of semiconductor die 250) are used. Therefore, the process steps and applicable materials may not be repeated herein. In addition, unless otherwise specified, the same reference numerals for semiconductor die 350 in this embodiment (and the embodiments discussed later) indicate that the semiconductor die 350 is formed by the same process. Fig.12 3. The same components in the embodiment shown in FIG. 3 (eg, describing the formation of semiconductor die 350) may be used. Therefore, process steps and applicable materials may not be repeated herein.

[0069] like Fig. 10A and Fig.13 As shown in the corresponding edge region 232, Fig.13 The process of forming the semiconductor die 250 shown in the embodiment is similar to that previously described in Fig.12 The process for semiconductor die 250 described in the above is different in that when forming Fig.13 When the semiconductor die 250 is shown in the embodiment shown in FIG. 1 , the dummy TSVs 111 are first formed to partially extend through the substrate 117 before the FEOL layer 118 is formed in and / or on the front side of the substrate 117. In an embodiment, each dummy TSV 111 may be electrically connected to the seal ring 128 through a conductive plug 115 formed in the FEOL layer 118. The formation of the dummy TSVs 111, the interconnect structure 119, the dielectric layer 120, and the second BPV 130 of the semiconductor die 250 are respectively performed using the same method as for Figure 3The formation of the dummy TSV 111 , the interconnect structure 119 , the dielectric layer 120 , and the second BPV 130 of the semiconductor die 150 is accomplished with similar materials and similar processes as described above.

[0070] In addition, if Fig.11A and Fig.13 As shown in the corresponding edge region 332, Fig.13 The process of forming the semiconductor die 350 shown in the embodiment is similar to that previously described in Fig.12 The process for semiconductor die 350 described in the above is different in that when forming Fig.13 When semiconductor die 350 is shown in the embodiment of FIG. 1 , dummy TSVs 311 are first formed to partially extend through substrate 317 before FEOL layer 318 is formed in and / or on the front side of substrate 317. TSVs 312 may then be formed after FEOL layer 318 is formed in and / or on the front side of substrate 317. In an embodiment, each dummy TSV 311 may be electrically connected to seal ring 328 via a conductive plug 315 formed in FEOL layer 318. The formation of dummy TSVs 311, TSVs 312, interconnect structures 319, and dielectric layers 320 of semiconductor die 350 may be performed using the same techniques as those described for FIG. Figure 3 The formation of dummy TSV 111 , TSV 112 , interconnect structure 119 , and dielectric layer 120 of semiconductor die 150 may be accomplished using similar materials and similar processes as described above.

[0071] Fig.14A According to an alternative embodiment, Fig. 10A Edge region 232 of semiconductor die 250 is shown in FIG. Fig.14A Also shown is a diagram according to an alternative embodiment. Fig.11A 3. Edge region 332 of semiconductor die 350 is shown in FIG. Fig. 14B The semiconductor die 250 / 350 is shown along Fig.14A Unless otherwise specified, the same reference numerals for semiconductor die 250 in this embodiment (and the embodiments discussed subsequently) denote semiconductor die 250 formed by the same process. Fig.12 The same components in the embodiment shown in FIG. 1 (e.g., describing the formation of semiconductor die 250) are used. Therefore, the process steps and applicable materials may not be repeated herein. In addition, unless otherwise specified, the same reference numerals for semiconductor die 350 in this embodiment (and the embodiments discussed later) indicate that the semiconductor die 350 is formed by the same process. Fig.12 3. The same components in the embodiment shown in FIG. 3 (eg, describing the formation of semiconductor die 350) may be used. Therefore, process steps and applicable materials may not be repeated herein.

[0072] like Fig. 10A and Fig.14A As shown in the corresponding edge region 232, Fig.14A The process of forming the semiconductor die 250 shown in the embodiment is similar to that previously described in Fig.12 The process for semiconductor die 250 described in the above is different in that when forming Fig.14A In the semiconductor die 250 shown in the embodiment of the present invention, the dummy TSV 111 is formed after the FEOL layer 118 and the interconnect structure 119 (e.g., including the seal ring 128 and the metallization pattern 126) are formed in and / or on the front side of the substrate 117. The FEOL layer 118 is first formed in and / or on the front side of the substrate 117. After the FEOL layer 118 has been formed in and / or on the front side of the substrate 117, the interconnect structure 119 (including the seal ring 128 and the metallization pattern 126) is then formed. The seal ring 128 can be formed to have a discontinuous gap in its structure, such as Fig. 14B Each gap in the seal ring 128 structure is disposed between adjacent portions of the seal ring 128 , and the gap is filled with a dielectric material of one or more dielectric layers of the interconnect structure 119 .

[0073] The dummy TSVs 111 are then formed to extend through the substrate 117 (including the FEOL layer 118) and partially through the interconnect structure 119. Each dummy TSV 111 may extend through a corresponding gap between adjacent portions of the seal ring 128 (e.g., through dielectric material of one or more dielectric layers of the interconnect structure 119 disposed within the corresponding gap), such as Fig. 14B The formation of the dummy TSV 111, the interconnect structure 119 (eg, including the metallization pattern 126 and the seal ring 128), the dielectric layer 120, and the second BPV 130 of the semiconductor die 250 are respectively performed using Figure 4A and Figure 4B The formation of the dummy TSV 111 , the interconnect structure 119 (eg, including the metallization pattern 126 and the seal ring 128 ), the dielectric layer 120 , and the second BPV 130 of the semiconductor die 150 may be accomplished using similar materials and similar processes as described above.

[0074] In addition, if Fig.11A and Fig.14A As shown in the corresponding edge region 332, Fig.14A The process of forming the semiconductor die 350 shown in the embodiment is similar to that previously described in Fig.12 The process for semiconductor die 350 described in the above is different in that when forming Fig.14AIn the semiconductor die 350 shown in the embodiment of FIG. 1 , the dummy TSV 311 is formed after the FEOL layer 318, TSV 312, and interconnect structure 319 (e.g., including seal ring 328 and metallization pattern 326) are formed in and / or on the front side of substrate 317. FEOL layer 318 is first formed in and / or on the front side of substrate 317. After FEOL layer 318 has been formed in and / or on the front side of substrate 317, TSV 312 is then formed using the same method as previously described for Figure 1A , Figure 1B and Figure 2 After forming TSV 312, interconnect structure 319 (including sealing ring 328 and metallization pattern 326) is then formed. Seal ring 328 can be formed to have a discontinuous gap in its structure, such as Fig. 14B Each gap in the seal ring 328 structure is disposed between adjacent portions of the seal ring 328 , and the gap is filled with dielectric material of one or more dielectric layers of the interconnect structure 319 .

[0075] Dummy TSVs 311 are then formed to extend through substrate 317 (including FEOL layer 318) and partially through interconnect structure 319. Each dummy TSV 311 may extend through a corresponding gap between adjacent portions of seal ring 328 (e.g., through dielectric material of one or more dielectric layers of interconnect structure 319 disposed within the corresponding gap), such as Fig. 14B The formation of the dummy TSV 311, the interconnect structure 319 (eg, including the metallization pattern 326 and the seal ring 328), and the dielectric layer 320 of the semiconductor die 350 are respectively performed using the same method as for Figure 4A and Figure 4B The formation of the dummy TSV 111 , the interconnect structure 119 (eg, including the metallization pattern 126 and the seal ring 128 ), and the dielectric layer 120 of the semiconductor die 150 may be accomplished using similar materials and similar processes as described above.

[0076] Fig.15 The previously described embodiment according to an alternative embodiment is shown Fig. 10A and Fig. 10B 2 is a top view of a semiconductor die 250 shown in FIG. Unless otherwise specified, the same reference numerals in this embodiment (and the embodiments discussed subsequently) denote semiconductor die 250 formed by the same process. Fig. 10A and Fig. 10B Therefore, the process steps and applicable materials may not be repeated herein.

[0077] Semiconductor die 250 includes dummy TSVs 111 extending through substrate 117. Dummy TSVs 111 may also extend partially or completely through interconnect structure 119. Dummy TSVs 111 may be distributed within semiconductor die 250 along an edge region of semiconductor die 250. In an embodiment, dummy TSVs 111 may be disposed along seal ring 128 (at Fig.15 The pseudo TSV 111 is arranged in a manner such that each pseudo TSV 111 overlaps with the sealing ring 128 and is in physical contact with the sealing ring 128. The cluster of pseudo TSVs 111 may be arranged to overlap with the corner regions of the sealing ring 128, so that the concentration of pseudo TSVs 111 along the corner regions of the sealing ring 128 is higher than other regions of the sealing ring 128. In addition, the semiconductor die 250 may also include pseudo TSVs 113, which are formed using a similar process and similar materials to the pseudo TSVs 111. The pseudo TSVs 113 may be arranged adjacent to the corner regions of the sealing ring 128, so that when viewed in a top view, the pseudo TSVs 113 are arranged within the inner perimeter of the sealing ring 128. Therefore, the pseudo TSVs 113 are not in physical contact with the sealing ring 128, and do not overlap with the sealing ring 128. In an embodiment, a single pseudo TSV 113 is arranged adjacent to each corner region of the sealing ring 128. In an embodiment, a cluster of dummy TSVs 113 (eg, more than one dummy TSV 113) is disposed adjacent to each corner region of the seal ring 128, such as Fig.15 as shown in .

[0078] Fig.16 The previously described embodiment according to an alternative embodiment is shown Fig.11A and Fig. 11B 3. Unless otherwise specified, the same reference numerals in this embodiment (and the embodiments discussed subsequently) refer to semiconductor die 350 formed by the same process. Fig.11A and Fig. 11B Therefore, the process steps and applicable materials may not be repeated herein.

[0079] TSV 312 may extend through substrate 317 and may be disposed in a central region of semiconductor die 350 (eg, as shown in FIG. 1 ). Fig.16 312 may also extend partially or completely through the interconnect structure 319 to electrically connect to the metallization pattern 326. In addition, the semiconductor die 350 includes a dummy TSV 311 extending through the substrate 317. The dummy TSV 311 may also extend partially or completely through the interconnect structure 319. The dummy TSV 311 may be distributed within the semiconductor die 350 along the edge region of the semiconductor die 350. In an embodiment, the dummy TSV 311 may be distributed along the seal ring 328 (at Fig.16The pseudo TSV 311 is arranged in a manner such that each pseudo TSV 311 overlaps with the sealing ring 328 and is in physical contact with the sealing ring 328. The cluster of pseudo TSVs 311 may be arranged to overlap with the corner regions of the sealing ring 328, so that the concentration of pseudo TSVs 311 along the corner regions of the sealing ring 328 is higher than other regions of the sealing ring 328. In addition, the semiconductor die 350 may also include pseudo TSVs 313, which are formed using a similar process and similar materials to the pseudo TSVs 311. The pseudo TSVs 313 may be arranged adjacent to the corner regions of the sealing ring 328, so that when viewed in a top view, the pseudo TSVs 313 are arranged within the inner perimeter of the sealing ring 328. Therefore, the pseudo TSVs 313 are not in physical contact with the sealing ring 328, and do not overlap with the sealing ring 328. In an embodiment, a single pseudo TSV 313 is arranged adjacent to each corner region of the sealing ring 328. In an embodiment, a cluster of dummy TSVs 313 (eg, more than one dummy TSV 313) is disposed adjacent to each respective corner region of the seal ring 328, such as Fig.16 As shown in , dummy TSV 311 and dummy TSV 313 are disposed around TSV 312 , and TSV 312 may be disposed in a central region of semiconductor die 350 .

[0080] exist Fig.17 , a carrier substrate 352 is bonded to the front side of the semiconductor die 350 (e.g., the surface of the dielectric layer 320). The semiconductor die 350 may also be subsequently referred to as a bottom die. The carrier substrate 352 may include a bulk substrate (e.g., a semiconductor substrate) or a wafer, and may be formed of a material such as silicon, ceramic, glass, etc. The carrier substrate 352 is bonded to the dielectric layer 320 of the semiconductor die 350 using a suitable technique such as fusion bonding. For example, in various embodiments, the carrier substrate 352 may be bonded to the semiconductor die 350 using a bonding layer 354 on the surface of the carrier substrate 352. In some embodiments, the bonding layer 354 may include silicon oxide formed on the surface of the carrier substrate 352 by a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. In other embodiments, the bonding layer 354 may be formed by thermal oxidation of the silicon surface on the carrier substrate 352. The dielectric layer 320 may include silicon oxide, etc.

[0081] Before bonding, the bonding layer 354 may be subjected to surface treatment. The surface treatment may include plasma treatment. The plasma treatment may be implemented in a vacuum environment. After the plasma treatment, the surface treatment may also include a cleaning process (e.g., rinsing with deionized water, etc.) that may be applied to the bonding layer 354. Then, the carrier substrate 352 is aligned with the semiconductor die 350, and the two are pressed against each other at a temperature between, for example, about 21 degrees and about 25 degrees, so that the carrier substrate 352 is in contact with and bonded to the semiconductor die 350. The bonding process may be enhanced by a subsequent annealing step. For example, this may be accomplished by heating the semiconductor die 350 and the carrier substrate 352 to a temperature in the range of 140°C to 500°C.

[0082] After the carrier substrate 352 is bonded to the semiconductor die 350, an insulating material 356 (also referred to as a sealant) is formed over the semiconductor die 350 and the carrier substrate 352 to seal the semiconductor die 350. According to some embodiments, the insulating material 356 may be an oxide (e.g., silicon dioxide), etc. The insulating material 356 may be formed by spin coating, high-density CVD, etc. After the insulating material 356 is formed, a planarization process may be performed to remove excess material of the insulating material 356 located above the semiconductor die 350 to expose the top surfaces of the substrate 317, the pseudo TSV 311, and the TSV 312. After the planarization process, the top surfaces of the substrate 317, the pseudo TSV 311, and the TSV 312 may be flush with the top surface of the insulating material 356 (within process variations). The planarization process may be a grinding process, a chemical mechanical polishing (CMP) process, etc. However, any suitable planarization process may be utilized.

[0083] After the planarization process, a bonding layer 321 is formed on the top surface of the semiconductor die 350 (e.g., the top surface of the substrate 317, TSV 312, and dummy TSV 311) and the insulating material 356. A bonding pad 323 is embedded in the bonding layer 321, wherein the bonding pad 323 is in physical contact with the TSV 312 and allows electrical connections to be made through the TSV 312 to the contact pad 324, the metallization pattern 326 of the interconnect structure 319, and the device in or on the substrate 317. In an embodiment, the bonding pad 323 may not overlap with the dummy TSV 311 and may not be in physical contact with the dummy TSV 311. The material of the bonding layer 321 may be silicon oxide (SiO x , where x>0), silicon nitride (SiN x , where x>0), silicon oxynitride (SiO x N y, where x>0 and y>0), tetraethyl orthosilicate (TEOS) or other suitable dielectric materials, and the bonding pad 323 may include a conductive pad (e.g., a copper pad), a conductive via (e.g., a copper via), or a combination thereof. The bonding layer 321 may be formed by: depositing a dielectric material on the semiconductor die 350 and the insulating material 356 using a CVD process (e.g., a plasma enhanced CVD process or other suitable process); patterning the dielectric material to form a bonding layer 321 including an opening or a hole; and filling the opening or hole defined in the bonding layer 321 with a conductive material to form a bonding pad 323 embedded in the bonding layer 321.

[0084] Fig.18 The semiconductor die 250 and one or more dummy dies 358 are shown bonded to the previously Fig.17 . According to some embodiments, a dummy die 358 may be placed to provide structural support to the integrated chip package 20 and reduce the risk of warping or cracks. In some embodiments, the dummy die 358 may be formed of a semiconductor material, such as silicon, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, etc., or a combination thereof. In some embodiments, the dummy die 358 may be formed of a dielectric material, such as a ceramic material, quartz, another electrically inert material, etc., or a combination thereof. In some embodiments, the dummy die 358 may be a metal or a metal alloy, such as a tin-nickel alloy, etc. In some embodiments, the dummy die 358 is formed of two or more different materials, such as a plurality of different material layers. According to some embodiments, the dummy die 358 may be substantially free of any active devices, functional circuits, etc. For example, the dummy die 358 may include a dummy die substrate (e.g., a bulk silicon substrate) and a dummy die bonding layer 138. The dummy die bonding layer 138 may include an oxide (e.g., silicon oxide) and may be used to bond the dummy die 358 to the bonding layer 321 disposed over the semiconductor die 350 and the insulating material 356. The dummy die bonding layer 138 of each dummy die 358 may be bonded to the bonding layer 321 using a fusion bonding process similar to that previously described in Fig.17 The fusion bonding process for bonding carrier substrate 352 to semiconductor die 350 is described in .

[0085] Still reference Fig.18, the semiconductor die 250 is bonded to the integrated chip package 20, for example, in a hybrid bonding configuration. The semiconductor die 250 may also be referred to as the top die subsequently. The semiconductor die 250 is disposed face-down and bonded to the semiconductor die 350, so that the front side of the semiconductor die 250 is bonded to the back side of the semiconductor die 350. The semiconductor die 250 is bonded to the bonding layer 321 on the back side of the semiconductor die 350 and the bonding pads 323 in the bonding layer 321. For example, the bonding layer 121 of the semiconductor die 250 may be directly bonded to the bonding layer 321 on the semiconductor die 350, and the bonding pads 123 of the semiconductor die 250 may be directly bonded to the bonding pads 323 of the semiconductor die 350. In an embodiment, the bonding between the bonding layer 121 and the bonding layer 321 may be an oxide-to-oxide bonding, etc. The hybrid bonding process also directly bonds the bonding pads 123 of the semiconductor die 250 to the bonding pads 323 on the semiconductor die 350 by direct metal-to-metal bonding. The hybrid bonding process can be similar to that previously described for Figure 7 The process of bonding semiconductor die 150 to wafer 200 is described in detail in . Thus, the electrical connection between semiconductor die 250 and semiconductor die 350 is provided by the physical connection of bonding pad 123 to bonding pad 323 .

[0086] exist Fig.19 In the embodiment, an insulating material 360 (also referred to as a gap filling material or sealant) is formed over the semiconductor die 250, the bonding layer 321, and the dummy die 358 to seal the semiconductor die 250 and each of the dummy die 358. The insulating material 360 fills the gap between the semiconductor die 250 and the corresponding dummy die 358. According to some embodiments, the insulating material 360 may be an oxide (e.g., silicon dioxide), etc. The insulating material 360 may be formed by spin coating, high-density CVD, etc. After forming the insulating material 360, a planarization process may be performed to remove excess material of the insulating material 360 located over the semiconductor die 250 and the dummy die 358 to expose the top surfaces of the substrate 117, the dummy TSV 111, and the dummy die 358. After the planarization process, the top surfaces of the substrate 117, the dummy TSV 111, and the dummy die 358 may be flush with the top surface of the insulating material 360 (within process variations). The planarization process may be a grinding process, a chemical mechanical polishing (CMP) process, etc. However, any suitable planarization process may be utilized.

[0087] exist Fig. 20360 , the carrier substrate 366 is bonded to the insulating material 360 , the dummy die 358 , and the top surface of the semiconductor die 250 (e.g., the back side of the semiconductor die 250 ). The carrier substrate 366 may include a bulk substrate (e.g., a semiconductor substrate) or a wafer, and may be formed of a material such as silicon, ceramic, glass, etc. The carrier substrate 366 is bonded to the insulating material 360 , the dummy die 358 , and the back side of the semiconductor die 250 using a suitable technique such as fusion bonding. For example, in various embodiments, the carrier substrate 366 may be bonded to the semiconductor die 250 , the dummy die 358 , and the insulating material 360 using a bonding layer 364 on the surface of the carrier substrate 366 and a bonding layer 362 on the surfaces of the insulating material 360 , the dummy die 358 , and the semiconductor die 250. In some embodiments, the bonding layer 362 and the bonding layer 364 may each include silicon oxide formed using a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. In other embodiments, bonding layer 364 on carrier substrate 366 and bonding layer 362 on dummy die 358 and semiconductor die 250 may be formed by thermal oxidation of silicon surfaces on carrier substrate 366 , dummy die 358 , and semiconductor die 250 .

[0088] Before bonding, one or more of the bonding layers 362 / 364 may be subjected to surface treatment. The surface treatment may include plasma treatment. The plasma treatment may be implemented in a vacuum environment. After the plasma treatment, the surface treatment may also include a cleaning process (e.g., rinsing with deionized water, etc.) that may be applied to at least one of the bonding layers 362 / 364. Then, the carrier substrate 366 is aligned with the insulating material 360, the dummy die 358, and the semiconductor die 250, and pressed against each other at a temperature between, for example, about 21 degrees and about 25 degrees, so that the carrier substrate 366 is in contact with the insulating material 360, the semiconductor die 250, and the dummy die 358 and bonded to the insulating material 360, the semiconductor die 250, and the dummy die 358. The bonding process may be enhanced by a subsequent annealing step. For example, this may be accomplished by heating the semiconductor die 250, the insulating material 360, the dummy die 358, and the carrier substrate 366 to a temperature ranging from 140°C to 500°C.

[0089] Fig.21The removal of the carrier substrate 352 is shown. In an embodiment, the carrier substrate 352 and the bonding layer 354 can be removed by a planarization process to expose the dielectric layer 320 and the insulating material 356. The planarization process can be a grinding process, a CMP process, etc. However, any suitable planarization process can be used. A dielectric layer 368 is then formed on the bottom surface of the integrated chip package 20, such as on the exposed surface of the dielectric layer 320 and the insulating material 356. In an embodiment, the dielectric layer 368 may include silicon oxide, silicon nitride, silicon oxynitride, a polymer, etc., and may be deposited by PVD, CVD, ALD, etc.

[0090] After dielectric layer 368 is formed, a first opening is formed in dielectric layer 368 to expose the surface of contact pad 324. The first opening can be formed using an acceptable etching technique. After the first opening is formed, dielectric layer 370 is formed on dielectric layer 368 and in the first opening. For example, dielectric layer 370 can be formed on the sidewalls in the first opening and on the exposed surface of contact pad 324 located within the first opening. Dielectric layer 370 can include a polymer, such as polyimide (PI), etc. Dielectric layer 370 can be formed using spin coating, lamination, etc.

[0091] After forming dielectric layer 370, the lateral portion of dielectric layer 370 located within the first opening is removed to re-expose contact pad 324. The lateral portion of dielectric layer 370 can be removed using an acceptable etching technique. After removing the lateral portion of dielectric layer 370, the remaining portion of dielectric layer 370 remains disposed on the sidewalls of each of the first openings.

[0092] Further references Fig.21 , an under bump metal (UBM) 372 is formed in the first opening for external connection to the contact pad 324. The UBM 372 has a bump portion located on and extending along the main surface of the dielectric layer 370, and has a through hole portion extending through the dielectric layer 370 and the dielectric layer 368 to physically and electrically couple the contact pad 324. Therefore, the UBM 372 is electrically coupled to the TSV 312 and the metallization pattern 326 of the semiconductor die 350. In addition, the UBM 372 is also electrically connected to the metallization pattern 126 and the contact pad 124 of the semiconductor die 250 through the BPV 130, the bonding pad 123, and the bonding pad 323. The UBM 372 can be formed of the same material as the metallization patterns 126 and 326.

[0093] After forming the UBM 372, a conductive connector 374 is formed on the UBM 372. The conductive connector 374 can be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by chemical nickel plating-chemical palladium plating-immersion gold technology (ENEPIG), etc. The conductive connector 374 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, the conductive connector 374 is formed by initially forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, reflow can be implemented to shape the material into a desired bump shape. The conductive connector 374 can be used to couple and electrically connect the integrated chip package 20 to other external devices, such as, for example, a packaging substrate, etc.

[0094] Fig. 22 1 shows a cross-sectional view of an intermediate step during a process for forming an integrated chip package 20 according to an alternative embodiment. Unless otherwise specified, like reference numerals in this embodiment (and subsequently discussed embodiments) denote components formed by the same process. FIG. 10A to FIG. 21 Therefore, the process steps and applicable materials may not be repeated herein.

[0095] Fig. 22 The embodiment shown in shows an integrated chip package 20 including a semiconductor die 250, wherein the semiconductor die 250 does not include any dummy TSV 111. Instead, a bonding pad 123 in a peripheral region 140 (which may also be referred to as an edge region) of the semiconductor die 250 may be formed. These bonding pads 123 in the peripheral region 140 serve as dummy bonding pads and may not be used for functional electrical or interconnection purposes. In addition, dummy bonding pad vias (BPVs) 131 may be formed in the peripheral region 140 of the dielectric layer 120 of the semiconductor die 250. Each dummy BPV 131 may be in physical contact with a corresponding bonding pad 123 in the peripheral region 140. The dummy BPV 131 may be formed in a similar manner and using similar materials as the previously described BPV 130, and may not be used for functional electrical or interconnection purposes. In some embodiments, only the bonding pads 123 in the peripheral region 140 are formed, and the dummy BPV 131 is not formed.

[0096] Embodiments of the present disclosure have some advantageous features. Embodiments include a method for forming an integrated chip package, the method including bonding a semiconductor die (e.g., a top die) to a semiconductor wafer (e.g., a bottom die). The top die may include a pseudo substrate through hole (TSV) disposed at a peripheral region (also referred to as an edge region) of the top die. The semiconductor wafer may also include a pseudo substrate through hole (TSV) disposed at a peripheral region (also referred to as an edge region) of the semiconductor wafer. For example, pseudo TSVs may be uniformly distributed in the top die along the edge region of the top die. Pseudo TSVs may also be uniformly distributed in the semiconductor wafer along the edge region of the semiconductor wafer. Pseudo TSVs include metal, and are used to increase the metal density of the edge region of the top die, and reduce the difference between the metal density of the edge region of the top die and the metal density of the center region of the top die. Therefore, the difference between the coefficient of thermal expansion (CTE) of the edge region of the top die and the coefficient of thermal expansion (CTE) of the center region of the top die is reduced. This allows the thermal stress generated in the top die to be reduced, and causes the risk of reduced warpage of the top die. This ensures that the edge region of the top die does not bend upward (also referred to as tilting) away from the top surface of the semiconductor wafer, and allows sufficient physical contact between the bonding pads of the edge region of the top die and the corresponding bonding pads of the semiconductor wafer. In this way, the bonding between the top die and the semiconductor wafer is improved, and device reliability is enhanced. In addition, preventing the edge region of the top die from tilting upward away from the top surface of the semiconductor wafer reduces the risk of forming a gap between the top die and the semiconductor wafer. Therefore, the risk of chemical damage or moisture damage to the exposed surfaces of the top die and the semiconductor wafer located within the gap during the processing steps subsequently implemented is reduced.

[0097] According to an embodiment, a package includes: a first die located above a first side of a second die and bonded to a first side of the second die, wherein the second die includes: a first substrate; a first interconnect structure located above the first substrate; a sealing ring disposed within the first interconnect structure; a first dummy through substrate via (TSV) extending through an edge region of the first substrate of the second die and in physical contact with the sealing ring; and a functional TSV extending through a central region of the first substrate of the second die. In an embodiment, in an embodiment, the second die further includes a metallization pattern disposed in the first interconnect structure, wherein the sealing ring surrounds the metallization pattern, and wherein the first dummy TSV and the functional TSV partially extend through the first interconnect structure. In an embodiment, the first dummy TSV is disposed around the functional TSV, and wherein the first dummy TSV is disposed below the sealing ring and overlaps the sealing ring. In an embodiment, the package further includes a conductive connector located on a second side of the second die, the conductive connector being electrically coupled to the functional TSV and the metallization pattern. In an embodiment, the concentration of the first dummy TSV under the corner region of the sealing ring is higher than the concentration of the first dummy TSV under other regions of the sealing ring. In an embodiment, the second die further includes a second dummy TSV extending through an edge region of the second die, wherein the second dummy TSV is not in physical contact with the seal ring. In an embodiment, the second dummy TSV is disposed adjacent to a corner region of the seal ring, and wherein, in a top view, the second dummy TSV is disposed within an inner perimeter of the seal ring.

[0098] According to an embodiment, a package includes: a first die, including: a first substrate; a first interconnect structure, located on the first substrate; a first sealing ring, disposed within the first interconnect structure; and a first dummy substrate through via (TSV), extending through an edge region of the first substrate of the first die, wherein the first dummy TSV overlaps the first sealing ring; and a second die, disposed below the first die, the first die being bonded to a first side of the second die, the second die including: a second substrate; a functional TSV, extending through a central region of the second substrate of the second die; a second interconnect structure, located on the second substrate; a second sealing ring, disposed within the second interconnect structure; and a second dummy TSV, extending through an edge region of the second substrate of the second die, wherein the second dummy TSV is disposed to be located around the functional TSV. In an embodiment, the second dummy TSV overlaps the second sealing ring, wherein the first dummy TSV is in physical contact with the first sealing ring, and the second dummy TSV is in physical contact with the second sealing ring. In an embodiment, the second die further includes: a third dummy TSV, disposed adjacent to a corner region of the second sealing ring, wherein, in a top view, the third dummy TSV is disposed within an inner perimeter of the second sealing ring. In an embodiment, the second die further comprises a first metallization pattern disposed in the second interconnect structure, and wherein the second seal ring surrounds the first metallization pattern. In an embodiment, the package further comprises a conductive connector located on a second side of the second die, the conductive connector being electrically coupled to the functional TSV and the first metallization pattern. In an embodiment, the second pseudo TSV is evenly distributed along the second seal ring. In an embodiment, the second pseudo TSV extends through the second substrate and the second interconnect structure, and wherein the first pseudo TSV partially extends through the first interconnect structure. In an embodiment, each of the second pseudo TSVs extends through a gap between adjacent portions of the second seal ring in the second interconnect structure.

[0099] According to an embodiment, a method for manufacturing a semiconductor device includes: forming a top die, wherein forming the top die includes: forming a device layer on a front side of a substrate; forming a first dummy substrate through via (TSV) extending through the device layer and an edge region of the substrate; forming a functional TSV extending through the device layer and a central region of the substrate, wherein the first dummy TSV is disposed around the functional TSV; and forming an interconnect structure over the front side of the substrate, wherein forming the interconnect structure includes forming a sealing ring that overlaps with the first dummy TSV and is in physical contact with the first dummy TSV; and bonding the top die to the bottom die, wherein bonding the top die to the bottom die includes bonding a first bonding pad of the top die to a second bonding pad of the bottom die. In an embodiment, the method further includes: forming a second dummy TSV extending through an edge region of the device layer and the substrate, and wherein, after forming the interconnect structure over the front side of the substrate, the second dummy TSV is not in physical contact with the sealing ring. In an embodiment, the second dummy TSV is disposed adjacent to a corner region of the sealing ring, wherein, in a top view, the second dummy TSV is disposed within an inner perimeter of the sealing ring. In an embodiment, the first dummy TSVs are uniformly distributed along the seal ring and uniformly distributed around the functional TSVs. In an embodiment, the first dummy TSVs are non-uniformly distributed along the seal ring and non-uniformly distributed around the functional TSVs.

[0100] Some embodiments of the present application provide a package, comprising: a first die, located above a first side of a second die and bonded to the first side of the second die, wherein the second die comprises: a first substrate; a first interconnect structure, located above the first substrate; a sealing ring, disposed within the first interconnect structure; a first dummy substrate through via (TSV), extending through an edge region of the first substrate of the second die and in physical contact with the sealing ring; and a functional substrate through via, extending through a central region of the first substrate of the second die.

[0101] In some embodiments, the second die further comprises a metallization pattern disposed in the first interconnect structure, wherein the seal ring surrounds the metallization pattern, and wherein the first dummy substrate via and the functional substrate via partially extend through the first interconnect structure. In some embodiments, the first dummy substrate via is disposed around the functional substrate via, and wherein the first dummy substrate via is disposed below and overlaps the seal ring. In some embodiments, the package further comprises a conductive connector on a second side of the second die, the conductive connector being electrically coupled to the functional substrate via and the metallization pattern. In some embodiments, the concentration of the first dummy substrate via under the corner region of the seal ring is higher than the concentration of the first dummy substrate via under other regions of the seal ring. In some embodiments, the second die further comprises a second dummy substrate via extending through the edge region of the second die, wherein the second dummy substrate via is not in physical contact with the seal ring. In some embodiments, the second dummy substrate via is disposed adjacent to the corner region of the seal ring, and wherein, in a top view, the second dummy substrate via is disposed within an inner perimeter of the seal ring.

[0102] Some other embodiments of the present application provide a package, comprising: a first die, comprising: a first substrate; a first interconnect structure, located on the first substrate; a first sealing ring, arranged in the first interconnect structure; and a first dummy substrate through hole (TSV), extending through an edge area of ​​the first substrate of the first die, wherein the first dummy substrate through hole overlaps with the first sealing ring; and a second die, arranged below the first die, the first die being bonded to a first side of the second die, the second die comprising: a second substrate; a functional substrate through hole, extending through a central area of ​​the second substrate of the second die; a second interconnect structure, located on the second substrate; a second sealing ring, arranged in the second interconnect structure; and a second dummy substrate through hole, extending through an edge area of ​​the second substrate of the second die, wherein the second dummy substrate through hole is arranged to be located around the functional substrate through hole.

[0103] In some embodiments, the second pseudo substrate via overlaps the second sealing ring, wherein the first pseudo substrate via is in physical contact with the first sealing ring, and the second pseudo substrate via is in physical contact with the second sealing ring. In some embodiments, the second die further includes: a third pseudo substrate via disposed adjacent to a corner region of the second sealing ring, wherein, in a top view, the third pseudo substrate via is disposed within an inner perimeter of the second sealing ring. In some embodiments, the second die further includes a first metallization pattern disposed in the second interconnect structure, and wherein the second sealing ring surrounds the first metallization pattern. In some embodiments, the package further includes a conductive connector located on a second side of the second die, the conductive connector being electrically coupled to the functional substrate via and the first metallization pattern. In some embodiments, the second pseudo substrate via is uniformly distributed along the second sealing ring. In some embodiments, the second pseudo substrate via extends through the second substrate and the second interconnect structure, and wherein a portion of the first pseudo substrate via extends through the first interconnect structure. In some embodiments, each of the second pseudo substrate vias extends through a gap between adjacent portions of the second sealing ring in the second interconnect structure.

[0104] Some other embodiments of the present application provide a method for manufacturing a semiconductor device, the method comprising: forming a top die, wherein forming the top die comprises: forming a device layer on a front side of a substrate; forming a first dummy substrate through hole (TSV) extending through the device layer and an edge region of the substrate; forming a functional substrate through hole extending through the device layer and a central region of the substrate, wherein the first dummy substrate through hole is arranged around the functional substrate through hole; and forming an interconnect structure over the front side of the substrate, wherein forming the interconnect structure comprises forming a sealing ring, the sealing ring overlaps with the first dummy substrate through hole and is in physical contact with the first dummy substrate through hole; and bonding the top die to a bottom die, wherein bonding the top die to the bottom die comprises bonding a first bonding pad of the top die to a second bonding pad of the bottom die. In some embodiments, the method further comprises: forming a second dummy substrate through hole extending through the device layer and an edge region of the substrate, and wherein, after forming the interconnect structure over the front side of the substrate, the second dummy substrate through hole is not in physical contact with the sealing ring. In some embodiments, the second dummy substrate via is disposed adjacent to a corner region of the seal ring, wherein, in a top view, the second dummy substrate via is disposed within an inner perimeter of the seal ring. In some embodiments, the first dummy substrate via is uniformly distributed along the seal ring and uniformly distributed around the functional substrate via. In some embodiments, the first dummy substrate via is non-uniformly distributed along the seal ring and non-uniformly distributed around the functional substrate via.

[0105] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A package comprising: A first die is located above and bonded to a first side of a second die, wherein the second die comprises: a first substrate; a first interconnect structure, located above the first substrate; a sealing ring, disposed in the first interconnection structure; a first dummy through substrate via (TSV) extending through an edge region of the first substrate of the second die and in physical contact with the seal ring; and A functional through substrate via extends through a central region of the first substrate of the second die.

2. The package according to claim 1, wherein: The second die also includes a metallization pattern disposed in the first interconnect structure, wherein the seal ring surrounds the metallization pattern, and wherein the first dummy through substrate via and the functional through substrate via partially extend through the first interconnect structure.

3. The package according to claim 2, wherein: The first dummy substrate through hole is disposed around the functional substrate through hole, and wherein the first dummy substrate through hole is disposed below the sealing ring and overlaps the sealing ring. 4 . The package of claim 3 , further comprising a conductive connector on a second side of the second die, the conductive connector electrically coupled to the functional substrate via and the metallization pattern.

5. The package according to claim 3, wherein: A concentration of the first dummy substrate vias under a corner region of the seal ring is higher than a concentration of the first dummy substrate vias under other regions of the seal ring.

6. The package according to claim 1, wherein: The second die also includes a second dummy through substrate via extending through the edge region of the second die, wherein the second dummy through substrate via is not in physical contact with the seal ring.

7. The package according to claim 6, wherein: The second dummy substrate via is disposed adjacent to a corner region of the seal ring, and wherein, in a top view, the second dummy substrate via is disposed within an inner perimeter of the seal ring.

8. A package comprising: The first die comprises: a first substrate; a first interconnect structure, located on the first substrate; a first sealing ring disposed in the first interconnect structure; and a first dummy through substrate via (TSV) extending through an edge region of the first substrate of the first die, wherein the first dummy through substrate via overlaps the first seal ring; and A second tube die is arranged below the first tube die, the first tube die is bonded to a first side of the second tube die, and the second tube die comprises: a second substrate; a functional through substrate via extending through a central region of the second substrate of the second die; a second interconnect structure, located on the second substrate; a second sealing ring disposed in the second interconnect structure; and A second dummy substrate through hole extends through an edge region of the second substrate of the second die, wherein the second dummy substrate through hole is arranged to be located around the functional substrate through hole.

9. The package according to claim 8, wherein: The second dummy substrate via overlaps the second seal ring, wherein the first dummy substrate via is in physical contact with the first seal ring, and the second dummy substrate via is in physical contact with the second seal ring.

10. A method for manufacturing a semiconductor device, the method comprising: forming a top die, wherein forming the top die comprises: forming a device layer on the front side of the substrate; forming a first dummy through substrate via (TSV) extending through the device layer and an edge region of the substrate; forming a functional substrate through hole extending through the device layer and a central region of the substrate, wherein the first dummy substrate through hole is disposed around the functional substrate through hole; and forming an interconnect structure over the front side of the substrate, wherein forming the interconnect structure comprises forming a seal ring overlapping and in physical contact with the first dummy substrate via; and Bonding the top die to a bottom die, wherein bonding the top die to the bottom die includes bonding a first bond pad of the top die to a second bond pad of the bottom die.

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