Chip packaging structure
By combining the dies in the Chiplet package structure and connecting them through bonded leads, the problems of complex process and low transmission efficiency in the SoC package structure are solved, and more efficient signal transmission and smaller package size are achieved.
Patent Information
- Application Number
- CN202411237657.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-04
- Publication Date
- 2024-12-10
AI Technical Summary
The existing SoC packaging structures lead to problems such as difficult process, high cost and low transmission efficiency, especially due to the long connection distance between chips, resulting in complex manufacturing and low transmission rates.
The Chiplet package structure is adopted to fit the dies of different functions on the substrate through shape matching, and electrically connect them through bonded leads to shorten the connection distance between the dies, simplify the manufacturing process and improve the transmission efficiency.
By shortening the connection distance between the dies, the transmission rate of the semiconductor device and the reliability of the packaging structure are improved, the cost is reduced, and the package size is minimized.
Smart Images
Figure CN119108377A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a chiplet packaging structure, and more specifically, to a chiplet packaging structure that improves the interconnection density and transmission efficiency of the packaging structure. Background Art
[0002] In the semiconductor industry, demands for high capacity and high transmission rate of semiconductor elements and electronic products using the semiconductor elements have increased. Fig.10 It is a system on chip (SoC) packaging structure in the prior art. Fig.11 yes Fig.10 A side view of an example of a SoC package structure. Fig.12 yes Fig.11 Schematic diagram of the circuit interconnection structure of the SoC packaging structure. Fig.13 and Fig.14 They are Fig.10 Schematic diagrams of circuit interconnection structures of two other examples of SoC package structures.
[0003] Reference Fig.10 , Fig.11 and Fig.12 The SoC packaging structure includes a plurality of chips Die1, Die0 and Die2 arranged on a substrate in a flip chip manner. The chips Die1, Die0 and Die2 are electrically connected to each other through a silicon bridge arranged in the substrate. Fig.13 , the chips Die1, Die0 and Die2 are electrically connected to each other through an interposer and a silicon bridge disposed in the interposer. Fig.14 , the chips Die1, Die0 and Die2 are electrically connected to each other through a fan-out interposer and a silicon bridge disposed in the fan-out interposer. Such a structure may lead to problems such as difficult process, high cost and low transmission efficiency.
[0004] Therefore, it is necessary to provide a packaging structure including a chiplet (also known as a small chip or a chip fragment). Chiplet is a new chip design and manufacturing method that integrates dies with different functions on a substrate. In the chiplet packaging structure, the connection distance between dies and between dies and external components can be shortened, thereby simplifying the manufacturing process and improving transmission efficiency. Summary of the invention
[0005] The present disclosure provides a chiplet packaging structure with improved reliability.
[0006] According to some embodiments of the present disclosure, a chiplet packaging structure is provided, comprising a substrate; and at least two bare chips located on the substrate, wherein the at least two bare chips include a first bare chip and a second bare chip, and the first bare chip and the second bare chip have different functions from each other and shapes that match each other.
[0007] According to some embodiments of the present disclosure, the first die and the second die may be arranged face to face and fit into each other to form a first rectangle in a top view.
[0008] According to some embodiments of the present disclosure, the first die and the second die may be connected to each other through first bonding wires, and the first bonding wires may be disposed along sides of the first die and the second die facing each other to electrically connect the first die to the second die.
[0009] According to some embodiments of the present disclosure, in a top view, the first die may have a C-shape, and the second die may have a T-shape.
[0010] According to some embodiments of the present disclosure, each of the first die and the second die may have an L-shape in a top view.
[0011] According to some embodiments of the present disclosure, in a top view, the first die may have an L-shape in a top view, and the second die may have a rectangular shape having an area smaller than that of the first die.
[0012] According to some embodiments of the present disclosure, the at least two dies may further include a third die and a fourth die, which are arranged face to face and fit together to form a second rectangle in a top view. The second rectangle may be arranged side by side with the first rectangle and have their sides aligned with each other.
[0013] According to some embodiments of the present disclosure, the third die and the fourth die may be connected to each other via a second bonding wire. The second bonding wire may be arranged along the sides of the third die and the fourth die facing each other to electrically connect the third die to the fourth die. The first rectangle and the second rectangle may be connected to each other via a third bonding wire. The third bonding wire may be arranged along the sides of the first rectangle and the second rectangle facing each other to electrically connect the first rectangle to the second rectangle.
[0014] According to some embodiments of the present disclosure, in a top view, the first die may have a C-shape, the second die may have a T-shape, and each of the third die and the fourth die may have an L-shape. The third bonding wires may include a first group of sub-leads electrically connecting the second die to the third die and a second group of sub-leads electrically connecting the second die to the fourth die, and the first group of sub-leads and the second group of sub-leads may be spaced apart from each other.
[0015] According to some embodiments of the present disclosure, each of the first and second bonding wires may include a plurality of groups of sub-leads that are spaced apart from each other and are respectively connected to different sides facing each other of a pair of chips that match each other.
[0016] According to some embodiments of the present disclosure, in a top view, the first die may have a C-shape, and the second die may have a rectangular shape having an area smaller than that of the first die. The at least two dies may further include a plurality of third dies identical to the second die, and the plurality of third dies may be vertically stacked on the second die. The first die may be disposed on the substrate in a flip chip manner.
[0017] According to some embodiments of the present disclosure, the first die, the second die, and the plurality of third dies may be connected through through silicon vias.
[0018] According to some embodiments of the present disclosure, the first die may be configured as an interposer layer disposed between a substrate and a second die.
[0019] According to some embodiments of the present disclosure, an upper portion of the first die may have a recessed portion, and the second die may be embedded in the recessed portion and electrically connected to the first die through bonding wires.
[0020] According to some embodiments of the present disclosure, the recessed portions may include multiple ones so that the first die has an inverted T-shape in a cross-sectional view, the second die may include multiple ones and are respectively arranged in each recessed portion, the length of the second die is the same as the length of the recessed portion, and the thickness of the second die is the same as the depth of the recessed portion. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The above and other objects and features of the present disclosure will become more apparent from the following detailed description in conjunction with the accompanying drawings.
[0022] Figure 1 A top view of a chiplet packaging structure according to an embodiment of the present disclosure is shown.
[0023] Figures 2 to 4 A top view of a first die and a second die according to other embodiments of the present disclosure is shown.
[0024] Figure 5A and Figure 5B A side view and a top view of a chiplet packaging structure according to another embodiment of the present disclosure are respectively shown.
[0025] Figure 6 A side view of a chiplet packaging structure according to another embodiment of the present disclosure is shown.
[0026] Fig. 7A and Figure 7BA side view and a top view of a chiplet packaging structure according to another embodiment of the present disclosure are respectively shown.
[0027] Figure 8 A schematic diagram illustrating a method of forming L-shaped dies on a wafer according to an embodiment of the present disclosure is shown.
[0028] Fig. 9 A schematic diagram showing a method of forming rectangular-shaped dies on a wafer according to an embodiment of the present disclosure is shown.
[0029] Fig.10 A schematic diagram of a system-on-chip packaging structure in the prior art is shown.
[0030] Fig.11 Shows Fig.10 Side view of the system-on-chip package structure in FIG.
[0031] Fig.12 Shows Fig.11 Schematic diagram of the circuit interconnection structure of the system-on-chip package structure.
[0032] Fig.13 According to another example Fig.10 Schematic diagram of the circuit interconnection structure of the system-on-chip package structure.
[0033] Fig.14 According to another example Fig.10 Schematic diagram of the circuit interconnect structure of the system-on-chip packaging structure. DETAILED DESCRIPTION
[0034] Hereinafter, example embodiments of the present disclosure will be described more fully with reference to the accompanying drawings. However, the example embodiments may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the exemplary embodiments to those skilled in the art. The present invention is not limited to the above-described embodiments, and various variations and modifications may be made without departing from the scope of the present invention.
[0035] In the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when an element is referred to as being "on" another element, the element can be directly on the other element or there may be intervening elements. In addition, it will be understood that when a layer is referred to as being "between" two layers, the layer can be the only layer between the two layers or there may be one or more intervening layers. Like reference numerals refer to like elements throughout.
[0036] Figure 1FIG. 2 shows a top view of a chiplet packaging structure according to an embodiment of the present disclosure. Figures 2 to 4 FIG. 2 shows a top view of a first die and a second die according to other embodiments of the present disclosure. Figure 1 As shown, the chiplet packaging structure 1 may include a substrate SUB and at least two dies located on the substrate SUB. The at least two dies may be a first die D1 and a second die D2. The first die D1 and the second die D2 may have different functions and matching shapes.
[0037] In an embodiment, the substrate SUB may be, for example, a printed circuit board, a flexible substrate, an interposer substrate, etc. The first die D1 and the second die D2 may be chips that perform different functions. In other words, the first die D1 and the second die D2 may be small-sized chips that divide a wafer or a large-sized SoC packaged chip according to different functions according to the chiplet technology. In addition, the first die D1 and the second die D2 may be chips from different suppliers. Compared with the SOC packaging structure in the prior art, the chiplet packaging structure according to an embodiment of the present disclosure can provide a shorter connection distance between the dies by embedding the first die and the second die whose shapes match each other together, thereby shortening the interconnection path, speeding up the transmission speed of the electrical signal, improving the overall transmission rate of the semiconductor device, and minimizing the package size.
[0038] In an embodiment, the first die D1 and the second die D2 may be arranged face to face and fit with each other to form a first rectangle 10 in a top view. For example, in a top view, the first die D1 may have a C-shape and the second die D2 may have a T-shape. The first die D1 having a C-shape and the second die D2 having a T-shape may fit with each other to form the first rectangle 10. Figure 1 As shown in , the first rectangle 10 may have a length T1 in a first direction (eg, X direction) and a width T2 in a second direction (eg, Y direction), and the length T1 may be greater than the width T2.
[0039] like Figure 1As shown in , the first die D1 may have a length t11 in the X direction, and the length t11 may be equal to the length T1 of the first rectangle 10. The first die D1 may have different widths in the Y direction. For example, the first die D1 may include a middle portion P1 and a first edge portion E11 and a second edge portion E12 respectively disposed at both sides of the middle portion P1. The length of the middle portion P1 of the first die D1 in the X direction may be d11. The first edge portion E11 and the second edge portion E12 of the first die D1 may have the same length d12 in the X direction. The length t11 of the first die D1 may be greater than the length d11 of the middle portion P1, and the length d11 of the middle portion P1 may be greater than the length d12 of the first edge portion E11 and the second edge portion E12. In addition, the first edge portion E11 and the second edge portion E12 of the first die D1 may have the same width t12 in the Y direction. The width of the middle portion P1 of the first die D1 in the Y direction may be t13. Widths t12 of the first and second edge portions E11 and E12 of the first die D1 may be greater than a width t13 of the middle portion P1 .
[0040] like Figure 1 As shown in , the second die D2 may have a length t21 in the X direction and may have different widths in the Y direction. For example, the second die D2 may include a middle portion P2 and a first edge portion E21 and a second edge portion E22 respectively disposed at both sides of the middle portion P2. The length of the middle portion P2 of the second die D2 in the X direction may be d21. The first edge portion E11 and the second edge portion E12 of the second die D2 may have the same length d22 in the X direction. The length t21 of the second die D2 may be greater than the length d21 of the middle portion P2, and the length d21 of the middle portion P2 may be greater than the length d22 of the first edge portion E11 and the second edge portion E12. In addition, the first edge portion E21 and the second edge portion E22 of the second die D2 may have the same width t22 in the Y direction. The width of the middle portion P2 of the second die D2 may be t23. The width t23 of the middle portion P2 of the second die D2 may be greater than the width t22 of the first edge portion E21 and the second edge portion E22.
[0041] like Figure 1As shown in , the length t11 of the first die D1 in the X direction may be equal to the length t21 of the second die D2 in the X direction. The length t21 of the second die D2 may be greater than the length d22 of the first edge portion E21 and the second edge portion E22 of the second die D2. The width t13 of the middle portion P1 of the first die D1 may be less than the width t23 of the middle portion P2 of the second die D2. The length T1 of the first rectangle 10 in the X direction may be equal to the length t11 of the first die D1 and the length t21 of the second die D2, or may be equal to the sum of twice the length d12 of the first edge portion E11 and the second edge portion E12 of the first die D1 and the length d11 of the middle portion P1, or may be equal to the sum of twice the length d22 of the first edge portion E11 and the second edge portion E12 of the second die D2 and the length d21 of the middle portion P2. The width T2 of the first rectangle 10 in the Y direction may be substantially equal to the sum of the width t12 of the first edge portion E11 and the second edge portion E12 of the first die D1 and the width t22 of the first edge portion E21 and the second edge portion E22 of the second die D2, or substantially equal to the sum of the width t13 of the middle portion P1 of the first die D1 and the width t23 of the middle portion P2 of the second die D2. However, the embodiments of the present disclosure are not limited thereto, and the length and width of each of the first die D1 and the second die D2 may have any size that matches each other's shapes.
[0042] In an embodiment, the first die D1 and the second die D2 may be connected to each other through a first bonding wire W1, and the first bonding wire W1 may be provided along the sides of the first die D1 and the second die D2 facing each other to electrically connect the first die D1 to the second die D2. In an embodiment, the first bonding wire W1 may include a conductive material such as a metal, for example, copper or gold. Although not shown, a plurality of pads may be provided on the sides of the first die D1 and the second die D2 facing each other. The plurality of pads may include a conductive material such as a metal, for example, copper.
[0043] like Figure 1 As shown in , the middle portion P1 of the first die D1 may include an inner side edge PS11 facing the second die D2. The first edge portion E11 of the first die D1 may include inner side edges ES11 and ES12 facing the second die D2. The second edge portion E12 of the first die D1 may include inner side edges ES13 and ES14 facing the second die D2. The middle portion P2 of the second die D2 may include inner side edges PS21, PS22, and PS23 facing the first die D1. The first edge portion E21 of the second die D2 may include an inner side edge ES21 facing the first die D1. The second edge portion E22 of the second die D2 may include an inner side edge ES22 facing the first die D1.
[0044] In an embodiment, the first bonding wire W1 may include a plurality of groups of sub-wires. The plurality of groups of sub-wires may be spaced apart from each other and may be respectively connected to different sides of a pair of die that match each other and face each other. Figure 1 As shown in the figure, the first bonding lead W1 may include a first group of sub-leads W1_1 arranged between the inner side edge ES11 of the first edge portion E11 of the first die D1 and the inner side edge ES21 of the first edge portion E21 of the second die D2, a second group of sub-leads W1_2 arranged between the inner side edge PS11 of the middle portion P1 of the first die D1 and the inner side edge PS21 of the middle portion P2 of the second die D2, a third group of sub-leads W1_3 arranged between the inner side edge ES14 of the second edge portion E12 of the first die D1 and the inner side edge PS23 of the middle portion P2 of the second die D2, and a fourth group of sub-leads W1_4 arranged between the inner side edge ES13 of the second edge portion E12 of the first die D1 and the inner side edge ES22 of the second edge portion E22 of the second die D2. However, the embodiments of the present disclosure are not limited thereto, and although not shown, the first bonding leads W1 may further include a fifth group of sub-leads arranged between the inner side ES12 of the first edge portion E11 of the first die D1 and the inner side PS22 of the middle portion P2 of the second die D2, or may not include any of the first to fourth groups of sub-leads W1_1 to W1_4. The first to fourth groups of sub-leads W1_1 to W1_4 may be spaced apart from each other, and may include the same or different numbers of bonding leads. The first to fourth groups of sub-leads W1_1 to W1_4 may be formed of the same or different conductive materials.
[0045] In the chiplet packaging structure provided in the embodiment of the present disclosure, the first bonding wire W1 can be directly arranged between the first die D1 and the second die D2, which can simplify the process difficulty and improve the reliability of the semiconductor device compared with the silicon bridge interconnection arranged in an additional layer in the prior art.
[0046] In an embodiment, at least two dies in the chiplet packaging structure 1 may further include a third die D3 and a fourth die D4. The third die D3 and the fourth die D4 may be arranged face to face and fit together to form a second rectangle 20 in a top view. For example, in a top view, each of the third die D3 and the fourth die D4 may have an L-shape to fit together to form the second rectangle 20. Figure 1 As shown in , the second rectangle 20 may have a length T3 in the X direction and a width T4 in the Y direction, and the length T3 may be greater than the width T4.
[0047] like Figure 1As shown in , the second rectangle 20 may be arranged side by side with the first rectangle 10 and the sides thereof may be aligned with each other. For example, the second rectangle 20 may be disposed below the first rectangle 10 in the Y direction. The length T3 of the second rectangle 20 may be equal to the length T1 of the first rectangle 10 so that the two sides thereof in the X direction are aligned with each other in the Y direction. Depending on the shapes of the third die D3 and the fourth die D4, the width T4 of the second rectangle 20 may be the same as or different from the width T2 of the first rectangle 10.
[0048] like Figure 1 As shown in , similar to the first die D1 and the second die D2, each of the third die D3 and the fourth die D4 may include a plurality of parts having different lengths and widths. The relationship between the length and width of each part may be the same as described above with reference to the first die D1 and the second die D2, and will not be repeated here. However, the embodiments of the present disclosure are not limited thereto, and the length and width of each of the third die D3 and the fourth die D4 may have any size that matches the shapes of each other.
[0049] In an embodiment, the third die D3 and the fourth die D4 may be connected to each other through second bonding wires W2 , and the second bonding wires W2 may be disposed along sides of the third die D3 and the fourth die D4 facing each other to electrically connect the third die D3 to the fourth die D4 .
[0050] In an embodiment, the second bonding wire W2 may include a first group of sub-leads W2_1, a second group of sub-leads W2_2, and a third group of sub-leads W2_3. The three groups of sub-leads may be spaced apart from each other and respectively connected to different sides of a pair of bare chips D3 and D4 that match each other and face each other. Specifically, the arrangement of the second bonding wire W2 may be the same as described above with reference to the first bonding wire W1, and will not be repeated here.
[0051] In an embodiment, the first rectangle 10 and the second rectangle 20 may be connected to each other through a third bonding wire W3. The third bonding wire W3 may be disposed along the sides of the first rectangle 10 and the second rectangle 20 facing each other to electrically connect the first rectangle 10 to the second rectangle 20.
[0052] like Figure 1 As shown in , similar to the first bonding wire W1 and the second bonding wire W2, the third bonding wire W3 may include a first group of sub-leads W3_1 and a second group of sub-leads W3_2. The first group of sub-leads W3_1 may electrically connect the second die D2 to the third die D3. The second group of sub-leads W3_2 may electrically connect the second die D2 to the fourth die D4. The first group of sub-leads W3_1 and the second group of sub-leads W3_2 may be spaced apart from each other and may be spaced apart from each of the first bonding wire W1 and the second bonding wire W2.
[0053] Although referenced Figure 1 The specific shapes, structures, and connection relationships of the first die D1, the second die D2, the third die D3, and the fourth die D4 included in the chiplet packaging structure 1 are described, but the embodiments of the present disclosure are not limited thereto. The chiplet packaging structure 1 may also include more pairs of dies whose shapes match each other, such as a fifth die, a sixth die, and the like. In addition, in addition to paired dies, the chiplet packaging structure 1 may also include a single die or three dies, as long as it or they match the shape of other adjacent dies. However, the shape matching relationship and the interconnection relationship between the dies are not limited to Figure 1 The following will take the first die D1 and the second die D2 as an example to describe other embodiments in which the first die D1 and the second die D2 can be matched in shape to be embedded and connected to each other.
[0054] Reference Figure 2 , similar to Figure 1 As shown in the third die D3 and the fourth die D4, each of the first die D1a and the second die D2a may have the same L-shape. The first die D1a and the second die D2a may be arranged facing each other and may include three pairs of inner sides that match each other. For example, in the present embodiment, the inner sides of the first die D1a having an L-shape and the second die D2a having an L-shape may fit together to form a first rectangle 10a.
[0055] In the first rectangle 10a, the first bonding wire W1a can electrically connect the first die D1a and the second die D2a to each other. Figure 1 The difference is that the first bonding wire W1a includes only two groups of sub-wires.
[0056] Reference Figure 3 In the top view, the first die D1b may have an L-shape, the second die D2b may have a rectangular shape, and the area of the second die D2b may be smaller than that of the first die D1b. The first die D1b and the second die D2b may be arranged facing each other and may include two pairs of inner sides that match each other. For example, in the present embodiment, the first die D1b having an L-shape and the second die D2b having a rectangular shape may be fitted to match each other to form a first rectangle 10b.
[0057] In the first rectangle 10b, the first bonding wire W1b may electrically connect the first die D1b and the second die D2b to each other. The first bonding wire W1b may include two groups of sub-leads electrically connecting two groups of inner sides of the first die D1b and the second die D2b facing each other, respectively.
[0058] Reference Figure 4 , similar to Figure 1As shown in the first die D1 and the second die D2, the first die D1c may have a C-shape, and the second die D2c may have a T-shape. The first die D1c and the second die D2c may be arranged facing each other, and may include five pairs of inner sides that match each other. For example, in this embodiment, the first die D1c having a C-shape and the second die D2c having a T-shape may be matched with each other to form a first rectangle 10c.
[0059] and Figure 1 Compared with the first rectangle 10 shown in FIG. 1 , the first die D1c and the second die D2c in the first rectangle 10c may include a greater embedding depth. Figure 4 As shown in , the first rectangle 10c may have a length T5 in the X direction and a width T6 in the Y direction, and the length T5 may be smaller than the width T6.
[0060] In the first rectangle 10c, the first bonding wire W1c can electrically connect the first die D1c and the second die D2c to each other. Figure 1 The difference is that the first bonding wire W1c includes five groups of sub-wires.
[0061] Although not shown, reference Figures 2 to 4 The first dies D1a, D1b and D1c and the second dies D2a, D2b and D2c, the first bonding wires W1a, W1b and W1c, the first rectangles 10a, 10b and 10c described above can be similarly applied to Figure 1 The third die D3 and the fourth die D4, the second bonding wire W2, and the second rectangle 20 in the chiplet packaging structure 1.
[0062] In the chiplet packaging structure 1 according to the embodiment of the present disclosure, the first die D1, the second die D2, the third die D3 and the fourth die D4 may be configured as chips that perform specific functions, such as a CPU chip, an input / output interface chip, a chip including a circuit for implementing artificial intelligence operations, a graphics chip and at least one of a media chip, but the example is not limited thereto. In addition, the first die D1, the second die D2, the third die D3 and the fourth die D4 may be dies from different suppliers. Therefore, the chiplet packaging structure 1 according to the present disclosure may have increased integration and improved functionality. In addition, since the first die D1 and the second die D2 and the third die D3 and the fourth die D4 match and fit each other, the connection distance between adjacent dies from the first die D1 to the fourth die D4 may be reduced, thereby improving the signal transmission efficiency between the dies and improving the reliability of the chiplet packaging structure 1.
[0063] Figure 5AFIG. 2 shows a side view of a chiplet packaging structure according to another embodiment of the present disclosure. Figure 5B A top view of a chiplet packaging structure according to another embodiment of the present disclosure is shown.
[0064] Reference Figure 5A , the chiplet package structure 2 may include a substrate SUB, a first die D1 arranged on the substrate SUB, and second to fourth dies D2, D3, and D4 vertically stacked on the first die D1 along a third direction (e.g., Z direction). The first to fourth dies D1 to D4 may be configured as chips that perform specific functions. In the chiplet package structure 2, the first die D1 may be disposed on the substrate SUB in a flip-chip manner. For example, a connection terminal CP such as a solder or a bump may be provided to electrically connect the upper surface of the substrate SUB to the lower surface of the first die D1 as an active surface.
[0065] Reference Figure 5B , the first die D1 may have a C-shape, and the second to fourth dies D2 to D4 may have the same rectangular shape. The areas of the second to fourth dies D2, D3, and D4 may be smaller than the area of the first die D1. For example, in a top view, the first die D1 having a C-shape and the second to fourth dies D2 to D4 having a rectangular shape may be matched with each other to form a rectangle.
[0066] In the rectangle, the first die D1 can be electrically connected to the second die D2 to the fourth die D4 through the bonding wires WB. Figure 5B As shown in FIG. 1 , the bonding wire WB may include three groups of sub-wires, but the embodiments of the present disclosure are not limited thereto. In addition, although not shown, the second to fourth dies D2 to D4 may be electrically connected to each other through bonding wires.
[0067] In the chiplet packaging structure 2 according to the embodiment of the present disclosure, the second die D2 to the fourth die D4 can be arranged in a mosaic manner in the space defined by the first die D1, so that the signal transmission distance between the first die D1 to the fourth die D4 can be reduced, thereby improving the transmission rate and interconnection density of the chiplet packaging structure 2.
[0068] Figure 6 A side view of a chiplet packaging structure according to another embodiment of the present disclosure is shown.
[0069] Reference Figure 6, the chiplet package structure 3 may include a substrate SUB, a first die D1 arranged on the substrate SUB, and second to fourth dies D2 to D4 vertically stacked on the first die D1 along the Z direction. In this embodiment, the first die D1 may be configured as an interposer layer IL placed between the substrate SUB and the second die D2. The second to fourth dies D2 to D4 may be configured as chips that perform specific functions. The interposer layer IL, the second die D2, the third die D3, and the fourth die D4 of the chiplet package structure 3 may have the same Figure 5B The chiplet package structure 2 shown in FIG. 1 has the same shape matching and interlocking relationship as the corresponding elements of the chiplet package structure 2. In the chiplet package structure 3, the interposer layer IL can be set on the substrate SUB through the connection terminal CP. For example, the connection terminal CP such as solder can be set to electrically connect the upper surface of the substrate SUB with the lower surface of the interposer layer IL.
[0070] In the present embodiment, the chiplet packaging structure 3 may further include a through silicon via TV penetrating each of the second die D2 to the fourth die D4, and a bump BP electrically connecting the through silicon vias TV to each other. In the chiplet packaging structure 3, the bump BP and the through silicon via TV may provide an electrical path between the interposer layer IL, the second die D2, the third die D3, and the fourth die D4. The number of through silicon vias TV and bump BP is not limited to Figure 6 Rather, various changes may be made.
[0071] In the chiplet packaging structure 3 according to the embodiment of the present disclosure, the signal transmission distance between the interposer layer IL and the second die D2, between the second die D2 and the third die D3, and between the third die D3 and the fourth die D4 can be reduced, thereby improving the transmission rate and interconnection density of the chiplet packaging structure 3.
[0072] Fig. 7A FIG. 2 shows a side view of a chiplet packaging structure according to another embodiment of the present disclosure. Figure 7B A top view of a chiplet packaging structure according to another embodiment of the present disclosure is shown.
[0073] Reference Fig. 7A , the chiplet package structure 4 may include a substrate SUB, a first die D1 arranged on the substrate SUB, and a second die D2 and a third die D3 arranged on the first die D1. The first die D1 to the third die D3 may be configured as chips that perform specific functions. In the chiplet package structure 4, the first die D1 may be disposed on the substrate SUB in a flip-chip manner. For example, a connection terminal CP such as a solder or a bump may be provided to electrically connect the upper surface of the substrate SUB to the lower surface of the first die D1 as an active surface.
[0074] In the present embodiment, the first die D1 may have an inverted T-shape. In other words, the first die D1 may have a protrusion disposed at the center and two concave portions on both sides of the protrusion. The second die D2 and the third die D3 having the same shape may be respectively embedded in the two concave portions of the first die D1, so that the cross-section of the chiplet packaging structure 4 may have a rectangular shape. For example, the second die D2 and the third die D3 may have the same thickness as the depth of the concave portion, and the second die D2 and the third die D3 may have the same length as the length of the concave portion. The top surfaces of the second die D2 and the third die D3 may be coplanar with the top surface of the first die D1 (i.e., the top surface of the protrusion).
[0075] Reference Figure 7B In the top view, the first die D1 can be electrically connected to the second die D2 and the third die D3 through the bonding wires WB. The bonding wires WB can be arranged along the inner side edges of the protrusions of the first die D1 facing the second die D2 and the inner side edges facing the third die D3. Therefore, the connection distance between the second die D2 and the third die D3 and the first die D1 can be reduced, thereby improving the transmission rate and interconnection density of the chiplet packaging structure 4.
[0076] Figure 8 A schematic diagram showing a method of forming an L-shaped die on a wafer according to an embodiment of the present disclosure is shown. Fig. 9 A schematic diagram showing a method of forming rectangular-shaped dies on a wafer according to an embodiment of the present disclosure is shown.
[0077] exist Figure 8 and Fig. 9 , wafers 101 and 201 may be wafers used in a semiconductor chip production process, for example, each of them may have a diameter of 6 inches, 8 inches, or 12 inches. According to an embodiment of the present disclosure, a plurality of L-shaped wafer units 101U may be repeatedly formed on wafer 101. A plurality of rectangular-shaped wafer units 201U may be repeatedly formed on wafer 201. The sizes of wafer units 101U and 201U are not particularly limited and may be variously changed.
[0078] In an embodiment, instead of using a diamond tool, the steps of forming the wafer units 101U and 201U may be implemented using lasers emitted by one or more laser sources. For example, the laser source may emit lasers to the wafers 101 and 201, so that the properties of the wafers at the laser irradiation point change. By moving the laser irradiation point relative to the wafer 101 or 201, an L-shaped or rectangular cutting line segment may be formed on the wafer 101 or 201. In an embodiment, the laser emitted by the laser source may be an infrared laser or an ultraviolet laser, or other types of suitable lasers known to those skilled in the art.
[0079] By reference Figure 8 and Fig. 9 The method described above can be used to produce Figure 1 7 describe dies having various shapes such as an L-shape and a rectangular shape.
[0080] By summarizing and reviewing, the embodiments of the present disclosure provide a chiplet packaging structure with improved transmission efficiency. In the chiplet packaging structure according to the embodiments of the present disclosure, a wafer or a large-size chip can be cut into at least two bare chips or small chips with the same shape and / or different shapes by, for example, laser cutting technology, and at least two bare chips or small chips with the same shape and / or different shapes can be matched and embedded with each other, and electrically connected by bonding wires arranged on one or more sides facing each other, so that the signal transmission distance between bare chips or small chips can be shortened, the overall transmission efficiency of the package can be improved, the size of the package can be minimized, and the use cost can be reduced.
[0081] Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any manner without departing from the spirit and scope of the present disclosure. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.
Claims
1. A chiplet packaging structure, include: substrate; as well as At least two dies, located on a substrate, The at least two die include a first die and a second die, and the first die and the second die have different functions and matching shapes.
2. The chiplet packaging structure according to claim 1, in, The first die and the second die are arranged face to face and fit into each other to form a first rectangle in a top view.
3. The chiplet packaging structure according to claim 2, in, The first die and the second die are connected to each other through first bonding wires, which are disposed along sides of the first die and the second die facing each other to electrically connect the first die to the second die.
4. The chiplet packaging structure according to claim 3, in, The at least two dies further include a third die and a fourth die, the third die and the fourth die are arranged face to face and fit together to form a second rectangle in a top view, and The second rectangle is arranged side by side with the first rectangle and the sides thereof are aligned with each other.
5. The chiplet packaging structure according to claim 4, in, The third die and the fourth die are connected to each other through second bonding wires, the second bonding wires are arranged along sides of the third die and the fourth die facing each other to electrically connect the third die to the fourth die, and The first rectangle and the second rectangle are connected to each other through a third bonding wire, and the third bonding wire is provided along sides of the first rectangle and the second rectangle facing each other to electrically connect the first rectangle to the second rectangle.
6. The chiplet packaging structure according to claim 5, in, In a top view, the first die has a C-shape, the second die has a T-shape, each of the third die and the fourth die has an L-shape, and The third bonding wires include a first group of sub-leads electrically connecting the second die to the third die and a second group of sub-leads electrically connecting the second die to the fourth die, and the first group of sub-leads and the second group of sub-leads are spaced apart from each other.
7. The chiplet packaging structure according to claim 5, in, Each of the first bonding wire and the second bonding wire includes a plurality of groups of sub-leads that are spaced apart from each other and are respectively connected to different sides facing each other of a pair of die that match each other.
8. The chiplet packaging structure according to claim 1, in, In a top view, the first die has a C-shape, and the second die has a rectangular shape having an area smaller than the first die, The at least two dies further include a plurality of third dies identical to the second die, the plurality of third dies being vertically stacked on the second die, and The first bare chip is disposed on the substrate in a flip chip manner.
9. The chiplet packaging structure according to claim 8, in, The first die, the second die, and the plurality of third dies are connected through through silicon vias.
10. The chiplet packaging structure according to claim 1, in, The first die has a recessed portion at an upper portion thereof, and the second die is embedded in the recessed portion and is electrically connected to the first die through bonding wires.