Super junction device and method of fabricating the same

Abstract

The application provides a super-junction device and a manufacturing method thereof. The super-junction device comprises a gallium oxide substrate, an N-type epitaxial layer on the surface of the gallium oxide substrate, a high-resistance layer formed in the surface of the side of the N-type epitaxial layer away from the gallium oxide substrate, a plurality of multi-stage grooves in the N-type epitaxial layer, the multi-stage grooves comprising N sub-grooves arranged along a first direction, and the N sub-grooves having different sizes in a second direction, wherein N is not less than 3, the first direction is perpendicular to the plane where the gallium oxide substrate is located and points to the gallium oxide substrate, and the second direction is perpendicular to the first direction, and a first P-type oxide layer covering the surface of the multi-stage grooves, wherein the surface of the multi-stage grooves comprises the bottom of the multi-stage grooves and the sidewall of the multi-stage grooves. The super-junction device has high withstand voltage performance and low process difficulty.

Description

Technical Field

[0001] The present application relates to the technical field of power devices, and in particular to a super junction device and a method for manufacturing the same. Background Art

[0002] In recent years, the application of power devices has become increasingly widespread. From fast charging for mobile phones and new energy vehicles to photovoltaic power generation and high-voltage power grid transmission, they have gradually penetrated into all aspects of life, bringing great convenience to our daily lives. Therefore, power devices will play a vital role in improving people's quality of life in the future. However, the voltage resistance performance of existing power devices needs to be improved. Summary of the Invention

[0003] In view of this, the present application provides a super junction device and a method for manufacturing the same, the scheme is as follows:

[0004] A super junction device, comprising:

[0005] Gallium oxide substrate;

[0006] An N-type epitaxial layer located on the surface of the gallium oxide substrate, wherein a high-resistance layer is formed on a surface of the N-type epitaxial layer away from the gallium oxide substrate;

[0007] a plurality of multi-level trenches in the N-type epitaxial layer, the multi-level trenches comprising N sub-trenches arranged along a first direction, wherein the N sub-trenches have different sizes in a second direction, wherein N is not less than 3, the first direction is perpendicular to the plane of the gallium oxide substrate and points toward the gallium oxide substrate, and the second direction is perpendicular to the first direction;

[0008] A first P-type oxide layer covers the surface of the multi-level trench, wherein the surface of the multi-level trench includes the bottom of the multi-level trench and the sidewall of the multi-level trench.

[0009] Optionally, the N-type epitaxial layer includes a plurality of N-type epitaxial units, the portion of the N-type epitaxial layer located between adjacent multi-level trenches is an N-type epitaxial unit, and the first P-type oxide layer on the sidewall of at least one sub-trench in the multi-level trench and the N-type epitaxial unit at its corresponding position meet a charge balance condition, and the charge balance condition is Among them, W NiO Characterizes the width of the first P-type oxide layer on the sidewall of a sub-trench in the multi-level trench, N NiO Characterizes the concentration of the first P-type oxide layer on the sidewall of the sub-trench, Characterizes the width of the epitaxial unit at the corresponding position of this sub-trench, Characterizes the concentration of the epitaxial unit at the corresponding position of this sub-trench.

[0010] Optionally, dimensions of the N sub-grooves in the second direction gradually decrease along the first direction.

[0011] Optionally, in the first direction, sizes of the N sub-grooves in the second direction vary uniformly along the first direction.

[0012] Optionally, the multi-level trenches penetrate the N-type epitaxial layer or the multi-level trenches do not penetrate the N-type epitaxial layer.

[0013] Optionally, in the first direction, the shape of the multi-level groove in a top view is a strip, a circle, a rectangle or a hexagon.

[0014] Optionally, the super junction device includes a cell region, a transition region and a terminal region, the terminal region is located at the periphery of the cell region, and the transition region is located between the cell region and the terminal region.

[0015] Optionally, the method further includes: a second P-type oxide layer covering the surface of a portion of the first P-type oxide layer located in the terminal region of the super junction device.

[0016] Optionally, the second P-type oxide layer further extends to cover a portion of the surface of the transition region.

[0017] Optionally, the plurality of multi-level trenches include a first multi-level trench located in the cell region and a second multi-level trench located in the terminal region, and the first P-type oxide layer and the second P-type oxide layer located on the surface of the second multi-level trench expose at least a portion of the bottom of the second multi-level trench.

[0018] A method for manufacturing a super junction device, comprising:

[0019] Growing an N-type epitaxial layer on a gallium oxide substrate, and forming a high-resistance layer on a surface of the N-type epitaxial layer away from the gallium oxide substrate;

[0020] forming a plurality of multi-level trenches in the N-type epitaxial layer, the multi-level trenches including N sub-trenches arranged along a first direction, wherein the N sub-trenches have different sizes in a second direction, wherein N is not less than 3, the first direction is perpendicular to the plane of the gallium oxide substrate and points toward the gallium oxide substrate, and the second direction is perpendicular to the first direction;

[0021] A first P-type oxide layer covering the surface of the multi-level trench is formed on the surface of the multi-level trench, wherein the surface of the multi-level trench includes the bottom of the multi-level trench and the sidewalls of the multi-level trench.

[0022] Optionally, the super junction device includes a cell region, a transition region and a terminal region, the terminal region is located outside the cell region, and the transition region is located between the cell region and the terminal region. The method also includes: forming a second P-type oxide layer on the surface of the portion of the first P-type oxide layer located in the terminal region of the super junction device.

[0023] Optionally, the second P-type oxide layer further extends to cover a portion of the surface of the transition region.

[0024] Optionally, the plurality of multi-level trenches include a first multi-level trench located in the cell region and a second multi-level trench located in the terminal region, and the method further includes: removing at least a portion of the first P-type oxide layer and the second P-type oxide layer located at the bottom of the second multi-level trench.

[0025] Optionally, the first P-type oxide layer is a NiO layer, and forming the first P-type oxide layer covering the surface of the multi-level groove on the surface of the multi-level groove includes: first filling metal nickel into the multi-level groove, and then oxidizing the metal nickel located in the multi-level groove in an oxygen atmosphere to form the first P-type oxide layer covering the surface of the multi-level groove on the surface of the multi-level groove.

[0026] In the superjunction device provided in the embodiment of the present application, the gallium oxide substrate is an N-type gallium oxide substrate, and the N-type epitaxial layer is an N-type gallium oxide epitaxial layer, thereby improving the voltage resistance performance of the superjunction device.

[0027] In the superjunction device provided in the embodiment of the present application, the N-type epitaxial layer 20 has a plurality of multi-level grooves, and the multi-level grooves include N sub-grooves arranged along the first direction X, and the sizes of the N sub-grooves in the second direction Y are not completely the same, wherein the N is not less than 3, so that when the thickness and concentration of the first P-type oxide layer located on the surface of the multi-level grooves change, the probability that at least part of the position in the multi-level grooves and the N-type epitaxial layer meet the charge balance condition can be increased through the multiple sub-grooves of different sizes, thereby reducing the probability that the reverse breakdown voltage of the superjunction device will be significantly reduced due to a slight change in the thickness and concentration of the first P-type oxide layer, thereby improving the reverse breakdown voltage of the superjunction device.

[0028] In addition, in the superjunction device provided in the embodiment of the present application, since the thickness and concentration of the first P-type oxide layer vary slightly, a plurality of sub-grooves of unequal sizes can be used so that at least part of the position in the multi-level trenches satisfies the charge balance condition with the N-type epitaxial layer. Therefore, during the manufacture of the superjunction device, the process control requirements for the concentration of the first P-type oxide layer during formation are relatively low, thereby increasing the doping concentration window of the first P-type oxide layer and reducing the process difficulty of the superjunction device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0030] The structures, proportions, sizes, etc. depicted in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not intended to limit the conditions under which this application can be implemented, and therefore have no substantive technical significance. Any structural modifications, changes in proportional relationships, or adjustments in size, without affecting the efficacy and objectives that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application.

[0031] Figure 1 Schematic diagram of the structure of a single-stage trench gallium oxide superjunction diode formed by sputtering a P-type NiO layer;

[0032] Figure 2 A schematic structural diagram of a super junction device provided in one embodiment of the present application;

[0033] Figure 3 A schematic structural diagram of a super junction device provided in another embodiment of the present application;

[0034] Figure 4 A schematic diagram of a top view of a multi-level trench in a super junction device provided by one embodiment of the present application;

[0035] Figure 5 A schematic diagram of a top view of a multi-level trench in a super junction device provided by another embodiment of the present application;

[0036] Figure 6 A schematic diagram of a top view of a multi-level trench in a super junction device provided in yet another embodiment of the present application;

[0037] Figure 7 A schematic diagram of a top view of a multi-level trench in a super junction device provided by another embodiment of the present application;

[0038] Figure 8 Schematic diagram of the voltage withstand capability of super junction devices;

[0039] Figure 9-Figure 26 A schematic diagram of some structures involved in the manufacturing process of a super junction device manufacturing method provided in one embodiment of the present application. DETAILED DESCRIPTION

[0040] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0041] It will be apparent to those skilled in the art that various modifications and variations can be made in this application without departing from the spirit or scope of this application. Therefore, this application is intended to cover modifications and variations of this application that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the embodiments provided in the examples of this application can be combined with each other without contradiction.

[0042] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0043] As described in the background technology section, the voltage resistance performance of existing power devices needs to be improved.

[0044] It should be noted that in power device applications, the Baliga figure-of-merit (BFOM) is an indicator used to indicate the suitability of semiconductor materials for power electronics. It is expressed as: BFOM = εμE3, where ε is the dielectric constant, μ is the mobility, and E is the breakdown field strength of the semiconductor. The BFOM value is roughly positively correlated with the sixth power of the bandgap width Eg. Therefore, a larger bandgap width means that wide-bandgap semiconductors have lower power loss and higher conversion efficiency in power device applications, thereby achieving more excellent and ideal power electronics applications.

[0045] Among wide bandgap semiconductor materials, Ga2O3 has a bandgap width of 4.8eV, an ideal breakdown electric field strength of 8MV / cm and a BFOM value of up to 3400, which is about 4 times that of GaN and 10 times that of SiC. It is an ideal material for making high-voltage devices.

[0046] However, there are currently no reports on the successful realization of p-type doping in Ga2O3. This makes it impossible to construct superjunction devices by forming homogeneous p-type doped regions through epitaxial backfill or ion implantation like Si and SiC to alleviate the contradiction between low conduction loss and high withstand voltage of the device.

[0047] Specifically, the reasons why Ga2O3 cannot form a homogeneous P-type doped region through epitaxial backfill or ion implantation like Si and SiC include: it is difficult to find acceptor impurities with small activation energy; theoretical calculations show that the maximum dispersion of the valence band of Ga2O3 is small and the effective mass is very large, resulting in the free holes being almost a local distribution of small μ; theoretical predictions have been made specifically for Ga2O3 that due to local lattice distortion, the local self-capture energy of free holes in the volume is very large, which leads to the formation of small poles, which undoubtedly prohibits the conduction of effective holes.

[0048] In view of this, researchers began to invest in heterogeneous PN junctions. The P-type materials currently studied in heterogeneous PN junctions include NiO, Cu2O, SnO, etc. Among them, NiO has become the mainstream choice with its large bandgap width of 3.6-4.0eV and controllable P-type doping. In 2020, Lu et al. reported a heterojunction constructed by NiO thin film and β-Ga2O3 prepared by sputtering, realizing the first β-Ga2O3 bipolar device with a kilovolt breakdown voltage. Subsequently, many researchers have made significant progress in improving the performance of NiO / β-Ga2O3 heterojunctions. In addition, the NiO / β-Ga2O3 heterojunction structure has also been widely used in other device structures, such as junction barrier Schottky diodes (JBS), junction field effect transistors (JFETs), and edge termination (ET) structures.

[0049] It should be noted that ordinary power devices can directly sputter NiO on the surface of β-Ga2O3 to form a heterojunction, which is similar to thin film deposition, and the direction of its PN junction is vertical; while superjunction devices need to form a PN junction in the horizontal direction. In order to overcome the manufacturing difficulties of superjunction devices caused by the lack of effective P-type doping in gallium oxide, the inventors have found that grooves can be dug in the gallium oxide epitaxial layer and NiO thin films can be sputtered in the grooves to form a charge balance area, thereby forming a larger breakdown voltage and lower on-resistance. Figure 1 As shown, Figure 1 The figure shows a schematic structural diagram of a single-stage trench gallium oxide superjunction diode formed by sputtering a P-type NiO layer 01.

[0050] but, Figure 1The structure shown has a problem of relatively high difficulty in manufacturing process. This is because during the manufacturing process, on the one hand, the P-type NiO layer 01 needs to be evenly sputtered on the sidewalls of the groove 02 to form good coverage, and at the same time, the concentration of the P-type nickel oxide layer 01 needs to be precisely controlled so that it can just deplete the n-type Ga2O3 on both sides. Both processes are difficult to achieve in relatively deep grooves. A slight change in the thickness and concentration of the P-type NiO layer on the sidewalls of the groove will greatly reduce the reverse breakdown voltage of the power device. On the other hand, the terminal area of ​​the power device also needs to adopt a high-efficiency junction terminal structure to match the superjunction structure of the cell area, thereby achieving the withstand voltage of the entire device. During the specific production, it is necessary to etch a relatively wide groove in the terminal area, and then remove the NiO layer on the other side and bottom of the groove to maintain the charge balance with the cell area. However, this approach will make the metal on the NiO layer (i.e., the anode) particularly difficult to make. The Schottky metal (i.e., the anode) needs to cover no more than the side wall of the NiO layer in the terminal area, and at the same time have an electrical connection with the NiO layer in the terminal area. The thickness of the sidewall NiO layer is often in the range of 100nm-300nm, which places extremely high requirements on the metal covering process and is not suitable for mass production.

[0051] In view of this, an embodiment of the present application provides a super junction device and a method for manufacturing the same, so as to improve the voltage resistance performance of the super junction device and reduce the process difficulty of the super junction device.

[0052] Specifically, such as Figure 2 As shown, the super junction device provided in the embodiment of the present application includes:

[0053] Gallium oxide substrate 10;

[0054] An N-type epitaxial layer 20 is located on the surface of the gallium oxide substrate 10 , and a high-resistance layer 21 is formed on the surface of the N-type epitaxial layer 20 away from the gallium oxide substrate 10 ;

[0055] a plurality of multi-level trenches in the N-type epitaxial layer 20, the multi-level trenches including N sub-trenches arranged along a first direction X, wherein the N sub-trenches have different sizes in a second direction Y, wherein N is not less than 3, the first direction X is perpendicular to the plane of the gallium oxide substrate 10 and points toward the gallium oxide substrate 10, and the second direction Y is perpendicular to the first direction X;

[0056] A first P-type oxide layer 30 covers the surface of the multi-level trench, wherein the surface of the multi-level trench includes the bottom of the multi-level trench and the sidewall of the multi-level trench.

[0057] Optionally, in one embodiment of the present application, the gallium oxide substrate is an N-type gallium oxide substrate, the N-type epitaxial layer is an N-type gallium oxide epitaxial layer, and the high-resistance layer is an N-type gallium oxide high-resistance layer, but the present application does not limit this and it depends on the specific situation.

[0058] In the superjunction device provided in the embodiment of the present application, the gallium oxide substrate is an N-type gallium oxide substrate, and the N-type epitaxial layer is an N-type gallium oxide epitaxial layer, thereby improving the voltage resistance performance of the superjunction device.

[0059] It should be noted that, in this embodiment, the N-type epitaxial layer includes a plurality of N-type epitaxial units, the portion of the N-type epitaxial layer located between adjacent multi-level trenches is an N-type epitaxial unit, and the first P-type oxide layer at at least one sub-trench in the multi-level trench and the N-type epitaxial unit at its corresponding position meet the charge balance condition, and the charge balance condition is Among them, W NiO Characterizes the width (thickness) of the first P-type oxide layer on the sidewall of a sub-trench in the multi-level trench, N NiO Characterizes the concentration of the first P-type oxide layer on the sidewall of the sub-trench, Characterizes the width of the epitaxial unit at the corresponding position of this sub-trench, Characterizes the concentration of the epitaxial unit at the corresponding position of this sub-trench.

[0060] For example, the multi-level trench includes the i-th multi-level trench and the i+1-th multi-level trench, the portion of the N-type epitaxial layer located between the i-th multi-level trench and the i+1-th multi-level trench is the i-th epitaxial unit, the product of the thickness and concentration of the first P-type oxide layer at the j-th sub-trench in the i-th multi-level trench and the first P-type oxide layer at the j-th sub-trench in the i+1-th multi-level trench is equal to the product of the width and concentration of the portion corresponding to the j-th sub-trench position in the i-th epitaxial unit, wherein i and j are both integers not less than 1.

[0061] It should be noted that when the first P-type oxide layer at a sub-trench in the multi-level trench and the N-type epitaxial unit at its corresponding position meet the charge balance condition, the current conduction area at other sub-trenches in the multi-level trench will become larger, and the overall on-resistance of the superjunction device will become smaller, thereby making the superjunction device have a smaller on-resistance.

[0062] In the superjunction device provided in the embodiment of the present application, the N-type epitaxial layer 20 has a plurality of multi-level grooves, and the multi-level grooves include N sub-grooves arranged along the first direction X, and the sizes of the N sub-grooves in the second direction Y are not completely the same, wherein the N is not less than 3, so that when the thickness and concentration of the first P-type oxide layer located on the surface of the multi-level grooves change, the probability that at least part of the position in the multi-level grooves and the N-type epitaxial layer meet the charge balance condition can be increased through the multiple sub-grooves of different sizes, thereby reducing the probability that the reverse breakdown voltage of the superjunction device will be significantly reduced due to a slight change in the thickness and concentration of the first P-type oxide layer, thereby improving the reverse breakdown voltage of the superjunction device.

[0063] In addition, in the superjunction device provided in the embodiment of the present application, since the thickness and concentration of the first P-type oxide layer vary slightly, a plurality of sub-grooves of unequal sizes can be used so that at least part of the position in the multi-level trenches satisfies the charge balance condition with the N-type epitaxial layer. Therefore, during the manufacture of the superjunction device, the process control requirements for the concentration of the first P-type oxide layer during formation are relatively low, thereby increasing the doping concentration window of the first P-type oxide layer and reducing the process difficulty of the superjunction device.

[0064] Optionally, in one embodiment of the present application, the dimensions of the N sub-grooves in the second direction gradually decrease along the first direction, so as to reduce the process difficulty of the multi-level grooves while ensuring that the dimensions of the N sub-grooves in the second direction are not exactly the same, but the present application does not limit this, and it depends on the specific situation.

[0065] In addition, in this embodiment, the dimensions of the N sub-grooves in the second direction gradually decrease along the first direction, and a step surface may be formed at the boundary region of the adjacent sub-grooves in the first direction, such as Figure 2 As shown in the dotted box in the figure, the uniformity of the formation of the portion of the first P-type oxide layer located on the side walls of each sub-trench can be improved, and the first P-type oxide layer can be uniformly formed on the surface of the multi-level trench, so as to reduce the process difficulty on the basis of ensuring the uniformity of the portion of the first P-type oxide layer located on the side walls of each sub-trench.

[0066] Specifically, in one embodiment of the present application, the N sub-grooves satisfy at least one of a first condition and a second condition in the second direction, wherein the first condition includes that the maximum value of the size of the N sub-grooves in the second direction is not greater than 5 microns, and the minimum value is not less than 500 nanometers, but the present application does not limit the specific numerical values ​​of the maximum and minimum values ​​of the size of the N sub-grooves in the second direction, which depends on the process capabilities; the second condition includes that the maximum value of the size of the N sub-grooves in the second direction does not exceed the target size + 1 micron, and the minimum value is not less than the target size - 1 micron, wherein the target size is determined according to the charge balance condition.

[0067] Optionally, in one embodiment of the present application, in the first direction, the dimensions of the N sub-grooves in the second direction vary uniformly along the first direction, but this application does not limit this and the specific circumstances may vary. Specifically, in the first direction, the dimension difference between adjacent sub-grooves in the same multi-level trench in the second direction may be 0.2 microns, but this application does not limit this and the specific circumstances may vary.

[0068] Based on any of the above embodiments, in one embodiment of the present application, continue as follows Figure 2 As shown, the multi-level trench does not penetrate the N-type epitaxial layer 20 to increase the reverse breakdown voltage of the super junction device; in another embodiment of the present application, as shown Figure 3 As shown, the multi-level trenches penetrate the N-type epitaxial layer 20 to reduce the overall resistance of the super junction device and reduce the power of the super junction device. This application does not limit this and it depends on the specific situation.

[0069] It should be noted that when the multi-level trenches penetrate the N-type epitaxial layer, the overall resistance of the superjunction device is small, the power is small, and accordingly, the reverse breakdown voltage is also small; when the multi-level trenches do not penetrate the N-type epitaxial layer, the overall resistance of the superjunction device is large, the power is large, and accordingly, the reverse breakdown voltage is also large.

[0070] Based on any of the above embodiments, in one embodiment of the present application, the first P-type oxide layer is a NiO layer, a Cu2O layer or a SnO layer. The present application does not limit this, and the specific situation depends on the circumstances.

[0071] It should be noted that, in this embodiment, the super junction device includes a cell region and a terminal region. The cell region is the functional region of the super junction device, and the terminal region is located outside the cell region and is used to disperse the electric field, alleviate the sharp corner discharge of the cell region, alleviate the discharge concentration phenomenon in the cell region, and increase the reverse breakdown voltage of the super junction device.

[0072] Optionally, in an embodiment of the present application, the super-junction device further comprises a transition region between the cell region and the terminal region, i.e. the super-junction device comprises a cell region, a transition region and a terminal region, the terminal region is located at the periphery of the cell region, and the transition region is located between the cell region and the terminal region, so as to increase the distance between the cell region and the terminal region, thereby ensuring that the subsequently formed second electrode layer can electrically connect the cell region and the terminal region, and the second electrode layer will not cover the part of the sidewall of the multi-stage trench of the first P-type oxide layer in the terminal region, and the process difficulty of the super-junction device is reduced.

[0073] Since the transition region is arranged between the cell region and the terminal region, the charge balance condition of the first P-type oxide layer is destroyed to a certain extent, therefore, in an embodiment of the present application, as shown in Figure 2 and Figure 3 the super-junction device further comprises a second P-type oxide layer 40 covering the surface of the part of the first P-type oxide layer 30 in the terminal region of the super-junction device. It should be noted that in the present embodiment, the second P-type oxide layer at at least one sub-trench in the multi-stage trench and the N-type epitaxial unit at the corresponding position thereof also satisfy the charge balance condition, and the charge distribution of the cell region in the super-junction device is adjusted to alleviate the reduction of the reverse breakdown voltage caused by the charge imbalance of the cell region.

[0074] Optionally, in an embodiment of the present application, the second P-type oxide layer further extends to cover part of the surface of the transition region, so that the second P-type oxide layer can be formed on part of the surface of the transition region, and the process difficulty of the part of the second P-type oxide layer in the terminal region is reduced, but the present application does not make any limitation thereon, and the specific conditions are determined as appropriate.

[0075] Specifically, in an embodiment of the present application, the second P-type oxide layer can be a NiO layer, a Cu2O layer or a SnO layer; it should be noted that the materials of the first P-type oxide layer and the second P-type oxide layer can be the same or different, and the present application does not make any limitation thereon, and the specific conditions are determined as appropriate.

[0076] It should be noted that, in this embodiment, the multi-level trenches are only located in the cell region and the terminal region, and the transition region is not provided with multi-level trenches. Optionally, based on any of the above embodiments, in one embodiment of the present application, the plurality of multi-level trenches include a first multi-level trench located in the cell region and a second multi-level trench located in the terminal region, and the first P-type oxide layer and the second P-type oxide layer located on the surface of the second multi-level trench expose at least a portion of the bottom of the second multi-level trench, so that the terminal region of the super junction device has a better charge balance state, so that the terminal region has a higher withstand voltage.

[0077] Optionally, in one embodiment of the present application, the sidewall of the second multi-level trench away from the cell region is covered with the second P-type oxide layer to increase the switching speed of the super junction device when used as a power switch and reduce switching losses, but the present application is not limited to this. In other embodiments of the present application, the sidewall of the second multi-level trench away from the cell region may not be covered with the second P-type oxide layer, depending on the specific circumstances.

[0078] Based on any of the above embodiments, in one embodiment of the present application, in the first direction, the top view of the multi-level groove is in the shape of a strip (eg Figure 4 As shown), round (as Figure 5 As shown), rectangle (as Figure 6 as shown) or hexagonal (as Figure 7 ), or other shapes, which are not limited in this application and will be determined in specific circumstances. It should be noted that, in the first direction, when the top view of the multi-level trenches is a hexagonal shape, the top views of adjacent rows of multi-level trenches are staggered in a plane parallel to the gallium oxide substrate to increase the reverse breakdown voltage of the superjunction device, but this application does not limit this and will be determined in specific circumstances.

[0079] Based on any of the above embodiments, in one embodiment of the present application, continue as follows Figure 2 and Figure 3 As shown, the super junction device further includes: a first electrode layer located on a side of the gallium oxide substrate away from the N-type epitaxial layer. Optionally, the first electrode layer is a cathode layer.

[0080] Specifically, in one embodiment of the present application, the first electrode layer includes a stacked Ti metal layer and an Au metal layer, wherein the Ti metal layer is located between the Au metal layer and the gallium oxide substrate. Specifically, in one embodiment of the present application, the thickness of the Ti metal layer ranges from 20 nm to 200 nm, and the thickness of the Au metal layer ranges from 80 nm to 1000 nm. For example, the thickness of the Ti metal layer is 20 nm and the thickness of the Au metal layer is 80 nm, or the thickness of the Ti metal layer is 200 nm and the thickness of the Au metal layer is 1000 nm. This application does not impose any limitation on this, and the specific thickness depends on the circumstances.

[0081] Based on any of the above embodiments, in one embodiment of the present application, continue as follows Figure 2 and Figure 3 As shown, the super junction device further includes: a second electrode layer electrically connected to a portion of the N-type epitaxial layer located in the cell region, the second electrode layer covering the cell region, and optionally, the second electrode layer is an anode layer.

[0082] Based on the above embodiments, in one embodiment of the present application, if the super junction device further includes a transition region, the second electrode layer may further extend toward the transition region to cover a portion of the surface of the transition region to reduce the process difficulty of forming the second electrode layer, but the present application does not limit this, as long as the second electrode layer does not cover the terminal region.

[0083] Specifically, in one embodiment of the present application, the second electrode layer includes a stacked Ni metal layer and an Au metal layer, and the Ni metal layer is located between the Au metal layer and the N-type epitaxial layer. Specifically, in one embodiment of the present application, the thickness of the Ni metal layer ranges from 20nm to 200nm, and the thickness of the Au metal layer ranges from 80nm to 1000nm. For example, the thickness of the Ni metal layer is 20nm, and the thickness of the Au metal layer is 80nm, or the thickness of the Ni metal layer is 200nm, and the thickness of the Au metal layer is 1000nm. This application does not limit this, and the specific situation depends on the circumstances.

[0084] Optionally, in one embodiment of the present application, continue as Figure 2 and Figure 3 As shown, the super junction device further includes a passivation layer 60 , which covers the terminal region of the super junction device and exposes at least a portion of the second electrode layer 50 to facilitate electrical connection of the second electrode layer 50 to the outside.

[0085] Specifically, in one embodiment of the present application, the passivation layer is a silicon oxide layer formed by a deposition process, and has a thickness of about 1 μm, but the present application does not limit this, and the specific situation depends on the circumstances.

[0086] As shown in Figure 8 , Fig. 2 is a schematic diagram of the withstand voltage capability of the super-junction device, wherein curve B represents the withstand voltage capability of the super-junction device as shown in Figure 8 ; curve A represents the withstand voltage capability of the super-junction device as provided by the embodiment of the present application. Figure 1 As shown in Figure 1 , curve B represents the withstand voltage capability of the super-junction device as shown in Figure 8 ; curve A represents the withstand voltage capability of the super-junction device as provided by the embodiment of the present application. Figure 1 As can be seen, the withstand voltage capability of the super-junction device as provided by the embodiment of the present application is not much different from the withstand voltage capability of the super-junction device as shown in Figure 1 . However, compared with the super-junction device as shown in , the process difficulty of the super-junction device as provided by the embodiment of the present application is greatly reduced. Therefore, the super-junction device as provided by the embodiment of the present application has higher withstand voltage performance and lower process difficulty.

[0087] In addition, the manufacturing method of the super-junction device as provided by the embodiment of the present application can be applied to manufacture the super-junction device provided by any of the above embodiments. Specifically, the manufacturing method of the super-junction device as provided by the embodiment of the present application comprises:

[0088] S1: growing an N-type epitaxial layer on a gallium oxide substrate, and forming a high-resistance layer in the surface of the N-type epitaxial layer away from the gallium oxide substrate. Optionally, the gallium oxide substrate is an N-type gallium oxide substrate, the N-type epitaxial layer is an N-type gallium oxide epitaxial layer, and the high-resistance layer is an N-type gallium oxide high-resistance layer.

[0089] Specifically, in one embodiment of the present application, growing an N-type epitaxial layer on a gallium oxide substrate, and forming a high-resistance layer in the surface of the N-type epitaxial layer away from the gallium oxide substrate comprises:

[0090] As shown in Figure 9 , an N-type epitaxial layer 20 is grown on a gallium oxide substrate 10 by using an HVPE epitaxial growth method;

[0091] As shown in Figure 10 , a first thickness of a preset element is implanted in the surface of the N-type epitaxial layer 20 away from the gallium oxide substrate 10, and annealing is performed to complete the activation of the preset element, so as to form a high-resistance layer 21 in the surface of the N-type epitaxial layer 20 away from the gallium oxide substrate 10.

[0092] It should be noted that HVPE (Hydride Vapor Phase Epitaxy) is a new technology for preparing nitride materials. Its specific process is to use hydrogen to deposit nitride crystals on a substrate at high temperature. In other embodiments of the present application, other methods can also be used to generate an N-type epitaxial layer on the oxide substrate. This application does not limit this, and the specific process depends on the circumstances.

[0093] It should also be noted that, in this embodiment, the formation of the high-resistance layer can reduce the electric field intensity on the surface of the N-type epitaxial layer, thereby reducing leakage.

[0094] Specifically, in one embodiment of the present application, the preset element may be nitrogen, magnesium, or beryllium. This application does not limit this, and the specific situation may vary. Taking nitrogen as an example, the first thickness ranges from 0.5 μm to 1 μm, and the doping concentration of nitrogen in the first thickness of the N-type epitaxial layer is 2e16 cm -3 ~2e18cm -3 , but this application does not limit this and it depends on the specific circumstances.

[0095] Optionally, in one embodiment of the present application, the thickness of the N-type epitaxial layer is in the range of 5 μm to 10 μm, and the doping concentration of the N-type epitaxial layer is in the range of 5E15 cm -3 ~2E16cm -3 , but this application does not limit this and it depends on the specific circumstances.

[0096] Continuing with the example of nitrogen as the preset element, based on the above embodiment, in one embodiment of the present application, the preset element is implanted into a first thickness within the surface of the N-type epitaxial layer away from the gallium oxide substrate, and annealed to complete the activation of the preset element, which includes: implanting the preset element into a first thickness within the surface of the N-type epitaxial layer away from the gallium oxide substrate, and then annealing at 1100° C. for 30 minutes to complete the activation of the preset element.

[0097] Optionally, in one embodiment of the present application, after a preset element is implanted into the N-type epitaxial layer within a first thickness away from the surface of the gallium oxide substrate, the N-type epitaxial layer is placed in an activation furnace at 1100° C. and annealed for 30 minutes to complete the activation of the preset element, but the present application does not limit this and it depends on the specific circumstances.

[0098] Optionally, in one embodiment of the present application, after forming an N-type epitaxial layer on the surface of the gallium oxide substrate and before forming a high-resistance layer on a surface of the N-type epitaxial layer away from the gallium oxide substrate, the manufacturing method further includes:

[0099] S11: forming a first electrode layer on a side of the gallium oxide substrate 10 away from the N-type epitaxial layer 20, such as Figure 11 and Figure 12 As shown, in this embodiment, a first electrode layer 11 is first formed on the side of the gallium oxide substrate 10 away from the N-type epitaxial layer 20, and then a high-resistance layer 21 is formed on the surface of the N-type epitaxial layer 20 away from the gallium oxide substrate 10. Optionally, the first electrode layer 21 is a cathode layer.

[0100] Specifically, in one embodiment of the present application, forming a first electrode layer on a side of the gallium oxide substrate away from the N-type epitaxial layer includes:

[0101] depositing a first electrode layer on a side of the gallium oxide substrate away from the N-type epitaxial layer;

[0102] The first electrode layer is annealed in a nitrogen atmosphere at 450° C. to 500° C. to form an ohmic contact with the gallium oxide substrate.

[0103] Optionally, in one embodiment of the present application, the first electrode layer includes a stacked Ti metal layer and an Au metal layer, and the Ti metal layer is located between the Au metal layer and the gallium oxide substrate. Specifically, in one embodiment of the present application, the thickness of the Ti metal layer ranges from 20nm to 200nm, and the thickness of the Au metal layer ranges from 80nm to 1000nm. For example, the thickness of the Ti metal layer is 20nm, and the thickness of the Au metal layer is 80nm, or the thickness of the Ti metal layer is 200nm, and the thickness of the Au metal layer is 1000nm. This application does not limit this, and the specific circumstances may vary.

[0104] S2: If Figure 13 As shown, a plurality of multi-level trenches 22 are formed in the N-type epitaxial layer 20. The multi-level trenches 22 include N sub-trenches arranged along a first direction X, and the sizes of the N sub-trenches in a second direction Y are not completely the same, wherein N is not less than 3, the first direction X is perpendicular to the plane of the gallium oxide substrate 10 and points to the gallium oxide substrate 10, and the second direction Y is perpendicular to the first direction X.

[0105] Optionally, in one embodiment of the present application, continue as Figure 13 As shown, the dimensions of the N sub-grooves in the second direction gradually decrease along the first direction, so as to reduce the process difficulty of the multi-level grooves while ensuring that the dimensions of the N sub-grooves in the second direction are not exactly the same, but the present application does not limit this and it depends on the specific situation.

[0106] Specifically, in one embodiment of the present application, continue as follows Figure 13As shown, the multi-level trenches do not penetrate the N-type epitaxial layer to increase the reverse breakdown voltage of the super junction device; in another embodiment of the present application, the multi-level trenches penetrate the N-type epitaxial layer to reduce the overall resistance of the super junction device and reduce the power of the super junction device. The present application does not limit this, and the specific situation depends on the circumstances.

[0107] Based on any of the above embodiments, in one embodiment of the present application, in the first direction, the top view of the multi-level groove is in the shape of a strip (eg Figure 4 As shown), round (as Figure 5 As shown), rectangle (as Figure 6 as shown) or hexagonal (as Figure 7 ), or other shapes, which are not limited in this application and will be determined in specific circumstances. It should be noted that, in the first direction, when the top view of the multi-level trenches is a hexagonal shape, the top views of adjacent rows of multi-level trenches are staggered in a plane parallel to the gallium oxide substrate to increase the reverse breakdown voltage of the superjunction device, but this application does not limit this and will be determined in specific circumstances.

[0108] S3: forming a first P-type oxide layer covering the surface of the multi-level trench on the surface of the multi-level trench, wherein the surface of the multi-level trench includes the bottom of the multi-level trench and the sidewall of the multi-level trench.

[0109] It should be noted that, in this embodiment, the N-type epitaxial layer includes a plurality of N-type epitaxial units, and the portion of the N-type epitaxial layer located between adjacent multi-level trenches is an N-type epitaxial unit. Figure 13 In the dotted box portion 23, the first P-type oxide layer on the sidewall of at least one sub-trench in the multi-level trench 22 and the N-type epitaxial unit 23 at its corresponding position meet the charge balance condition, and the charge balance condition is Among them, W NiO Characterizes the width of the first P-type oxide layer on the sidewall of a sub-trench in the multi-level trench, N NiO Characterizes the concentration of the first P-type oxide layer on the side of the sub-trench, Characterizes the width of the epitaxial unit at the corresponding position of this sub-trench, Characterizes the concentration of the epitaxial unit at the corresponding position of this sub-trench. Wherein, the width is the dimension along the second direction Y.

[0110] For example, the multi-level trench includes the i-th multi-level trench and the i+1-th multi-level trench, the portion of the N-type epitaxial layer located between the i-th multi-level trench and the i+1-th multi-level trench is the i-th epitaxial unit, and the product of the thickness and concentration of the first P-type oxide layer at the j-th sub-trench in the i-th multi-level trench and the j-th sub-trench in the i+1-th multi-level trench is equal to the product of the width and concentration of the portion corresponding to the j-th sub-trench position in the i-th epitaxial unit, wherein i and j are both integers not less than 1.

[0111] Specifically, in one embodiment of the present application, the N sub-grooves satisfy at least one of a first condition and a second condition in the second direction, wherein the first condition includes that the maximum value of the size of the N sub-grooves in the second direction is not greater than 5 microns, and the minimum value is not less than 500 nanometers, but the present application does not limit the specific numerical values ​​of the maximum and minimum values ​​of the size of the N sub-grooves in the second direction, which depends on the process capabilities; the second condition includes that the maximum value of the size of the N sub-grooves in the second direction does not exceed the target size + 1 micron, and the minimum value is not less than the target size - 1 micron, wherein the target size is determined according to the charge balance condition.

[0112] Optionally, in one embodiment of the present application, in the first direction, the dimensions of the N sub-grooves in the second direction vary uniformly along the first direction, but this application does not limit this and the specific circumstances may vary. Specifically, in the first direction, the dimensions of adjacent sub-grooves in the same multi-level trench in the second direction may vary by 0.2 microns, but this application does not limit this and the specific circumstances may vary.

[0113] Based on any of the above embodiments, in one embodiment of the present application, the first P-type oxide layer is a NiO layer, a Cu2O layer or a SnO layer. The present application does not limit this, and the specific situation depends on the circumstances.

[0114] Specifically, in one embodiment of the present application, forming a first P-type oxide layer covering the surface of the multi-level trench includes:

[0115] like Figure 14 As shown, a first P-type oxide layer 30 is formed covering the surface of the multi-level trench 22 and the surface of the N-type epitaxial layer 20 away from the gallium oxide substrate 10;

[0116] like Figure 15As shown, a first photoresist layer 31 is formed on the side of the first P-type oxide layer 30 away from the surface of the multi-level trench 22. The first photoresist layer 31 covers the first P-type oxide layer 30 and completely fills the multi-level trench 22. The first P-type oxide layer 30 includes a first portion located on the surface of the multi-level trench 22 and a second portion located on the surface of the N-type epitaxial layer 20.

[0117] Continue as Figure 15 As shown, the first photoresist layer 31 is partially removed (eg, planarized), the portion of the first photoresist layer 31 located on the surface of the second portion is removed, and the portion of the first photoresist layer located on the surface of the first portion is retained;

[0118] like Figure 16 As shown, the second portion is removed, that is, the portion of the first P-type oxide layer 30 located on the surface of the N-type epitaxial layer 20 is removed;

[0119] like Figure 17 As shown, the remaining portion of the first photoresist layer is removed, and only the portion of the first P-type oxide layer 30 located at the bottom of the multi-level trench 22 and the sidewall of the multi-level trench 22 is retained.

[0120] Optionally, based on the above embodiment, in one embodiment of the present application, forming a first P-type oxide layer covering the surface of the multi-level grooves and the surface of the N-type epitaxial layer on a side away from the gallium oxide substrate includes: forming the first P-type oxide layer covering the surface of the multi-level grooves and the surface of the N-type epitaxial layer on a side away from the gallium oxide substrate by a thin film sputtering process, wherein the surface of the multi-level grooves includes the bottom of the multi-level grooves and the sidewalls of the multi-level grooves. It should be noted that the thin film sputtering process is a physical vapor deposition (PVD) technology that is mainly used to prepare various functional thin films. Specifically, the thin film sputtering process sputters atoms or molecules from the surface of the target material through momentum transfer and deposits them onto the substrate material, thereby forming the desired thin film.

[0121] In another embodiment of the present application, the first P-type oxide layer is a NiO layer, and forming the first P-type oxide layer covering the surface of the multi-level trench and the surface of the N-type epitaxial layer away from the gallium oxide substrate includes: first filling metallic nickel into the multi-level trench, and then oxidizing the metallic nickel in the multi-level trench in an oxygen atmosphere to form the first P-type oxide layer on the surface of the multi-level trench covering the surface of the multi-level trench and the surface of the N-type epitaxial layer away from the gallium oxide substrate.

[0122] In the method for manufacturing a superjunction device provided in an embodiment of the present application, the gallium oxide substrate is an N-type gallium oxide substrate, and the N-type epitaxial layer is an N-type gallium oxide epitaxial layer, thereby improving the voltage resistance performance of the superjunction device.

[0123] Moreover, in the manufacturing method of the super junction device provided in the embodiment of the present application, the N-type epitaxial layer 20 has a plurality of multi-level grooves, and the multi-level grooves include N sub-grooves arranged along the first direction X, and the sizes of the N sub-grooves in the second direction Y are not completely the same, wherein the N is not less than 3, so that when the thickness and concentration of the first P-type oxide layer located on the surface of the multi-level grooves change, the probability that at least part of the position in the multi-level grooves and the N-type epitaxial layer meet the charge balance condition can be increased through a plurality of sub-grooves of different sizes, thereby reducing the probability that the reverse breakdown voltage of the super junction device will be significantly reduced due to a slight change in the thickness and concentration of the first P-type oxide layer, thereby improving the reverse breakdown voltage of the super junction device.

[0124] In addition, in the manufacturing method of the super junction device provided in the embodiment of the present application, since the thickness and concentration of the first P-type oxide layer vary slightly, a plurality of sub-grooves of unequal sizes can be used so that at least part of the position in the multi-level trenches and the N-type epitaxial layer meet the charge balance condition. Therefore, during the manufacturing process of the super junction device, the process control requirements for the concentration of the first P-type oxide layer during formation are relatively low, the doping concentration window of the first P-type oxide layer is improved, and the process difficulty of the super junction device is reduced.

[0125] In addition, in the manufacturing method of the super junction device provided in the embodiment of the present application, the dimensions of the N sub-grooves in the second direction gradually decrease along the first direction, and a step surface can be formed in the junction area of ​​the adjacent sub-grooves in the first direction, thereby improving the uniformity of the formation of the portion of the first P-type oxide layer located on the side walls of each sub-groove, and further allowing the first P-type oxide layer to be uniformly formed on the surface of the multi-level groove, so as to reduce the process difficulty on the basis of ensuring the uniformity of the portion of the first P-type oxide layer located on the side walls of each sub-groove.

[0126] It should be noted that, in this embodiment, the super junction device includes a cell region and a terminal region. The cell region is the functional region of the super junction device, and the terminal region is located outside the cell region and is used to disperse the electric field, alleviate the sharp corner discharge of the cell region, alleviate the discharge concentration phenomenon in the cell region, and increase the reverse breakdown voltage of the super junction device.

[0127] Optionally, in one embodiment of the present application, the super junction device further includes a transition region located between the cell region and the terminal region, that is, the super junction device includes a cell region, a transition region and a terminal region, the terminal region is located at the periphery of the cell region, and the transition region is located between the cell region and the terminal region to increase the distance between the cell region and the terminal region, thereby reducing the process difficulty of the super junction device on the basis of ensuring that the subsequently formed second electrode layer can electrically connect the cell region and the terminal region, and the second electrode layer will not cover the portion of the side wall of the multi-level trench of the first P-type oxide layer located in the terminal region.

[0128] Since the provision of the transition region between the cell region and the terminal region will destroy the charge balance condition formed by the first P-type oxide layer to a certain extent, in one embodiment of the present application, the manufacturing method further includes:

[0129] S4: forming a second P-type oxide layer on the surface of a portion of the first P-type oxide layer located in the terminal region of the superjunction device. It should be noted that, in this embodiment, the second P-type oxide layer in at least one sub-trench in the multi-level trench and the N-type epitaxial unit at its corresponding position also meet a charge balance condition, thereby adjusting the charge distribution in the cell region of the superjunction device to alleviate the reduction in reverse breakdown voltage caused by charge imbalance in the cell region.

[0130] Optionally, in one embodiment of the present application, the second P-type oxide layer also extends to cover part of the surface of the transition zone, thereby ensuring that the subsequently formed second electrode layer can electrically connect the cell area and the terminal area, and the second electrode layer will not cover the side walls of the multi-level grooves located in the terminal area, so that the second P-type oxide layer can be formed on part of the surface of the transition zone, thereby reducing the process difficulty of forming the part of the second P-type oxide layer located in the terminal area, but the present application does not limit this, and it depends on the specific situation.

[0131] Specifically, in one embodiment of the present application, the second P-type oxide layer may be a NiO layer, a Cu2O layer or a SnO layer; it should be noted that the materials of the first P-type oxide layer and the second P-type oxide layer may be the same or different, and the present application does not limit this, and it depends on the specific circumstances.

[0132] The super junction device provided in the embodiments of the present application is described below by taking the super junction device including the transition region as an example.

[0133] Specifically, in one embodiment of the present application, forming a second P-type oxide layer on a surface of a portion of the first P-type oxide layer located in a terminal region of the super junction device includes:

[0134] like Figure 18 As shown, a second photoresist layer 32 is formed on the surface of the N-type epitaxial layer 20 and the surface of the first P-type oxide layer 30, and the second photoresist layer 32 completely fills the multi-level trench;

[0135] Continue as Figure 18 As shown, the second photoresist layer 32 is partially removed (eg, planarized) to expose at least a portion of the surface of the transition region of the super junction device and the terminal region;

[0136] like Figure 19 As shown, a second P-type oxide layer 40 is formed on the surface of the second photoresist layer 32 and the surface of the super junction device in an area not covered by the second photoresist layer 32. Optionally, the second P-type oxide layer 40 is formed by a thin film sputtering process.

[0137] like Figure 20 As shown, the second photoresist layer 32 and a portion of the second P-type oxide layer 40 located on the surface thereof are removed.

[0138] It should be noted that, in this embodiment, the multi-level grooves are only located in the cell region and the terminal region, and the transition region is not provided with multi-level grooves.

[0139] Optionally, based on any of the above embodiments, in one embodiment of the present application, the multiple multi-level trenches include a first multi-level trench located in the cell area and a second multi-level trench located in the terminal area, and the method also includes: removing at least part of the bottom area of ​​the second multi-level trench so that the terminal area of ​​the super junction device has a better charge balance state, so that the terminal area has a higher voltage resistance.

[0140] Optionally, in one embodiment of the present application, the sidewall of the second multi-level trench away from the cell region is covered with the second P-type oxide layer to increase the switching speed of the super junction device when used as a power switch and reduce switching losses, but the present application is not limited to this. In other embodiments of the present application, the sidewall of the second multi-level trench away from the cell region may not be covered with the second P-type oxide layer, depending on the specific circumstances.

[0141] Specifically, in one embodiment of the present application, removing at least a portion of the bottom of the second multi-level trench includes:

[0142] like Figure 21 As shown, a third photoresist layer 41 covering the super junction device is formed, and the third photoresist layer 41 covers the cell region, the transition region and the terminal region;

[0143] Continue as Figure 21As shown, the third photoresist layer 41 is partially removed to expose the bottom of the multi-level groove located in the terminal area, that is, to expose the bottom of the second multi-level groove;

[0144] like Figure 22 As shown, the first P-type oxide layer and the second P-type oxide layer are removed from the bottom of the second multi-level trench;

[0145] like Figure 23 As shown, the third photoresist layer 41 is removed.

[0146] Specifically, in one embodiment of the present application, the second P-type oxide layer may be a NiO layer, a Cu2O layer, or a SnO layer, which is not limited in this application and depends on the specific circumstances. Optionally, in one embodiment of the present application, the second P-type oxide layer may be the same material as the first P-type oxide layer, such as if the first P-type oxide layer is a NiO layer and the second P-type oxide layer is also a NiO layer, which is not limited in this application and the first P-type oxide layer and the second P-type oxide layer may also be different materials, which depends on the specific circumstances.

[0147] Based on any of the above embodiments, in one embodiment of the present application, the method further includes: forming a second electrode layer electrically connected to the portion of the N-type epitaxial layer located in the cell region, the second electrode layer covering the cell region, and the second electrode layer being an anode layer. Optionally, if the superjunction device further includes a transition region, the second electrode layer may further extend into the transition region to cover a portion of the surface of the transition region, thereby reducing the difficulty of forming the second electrode layer. However, this application is not limited to this, as long as the second electrode layer does not cover the terminal region.

[0148] Specifically, in one embodiment of the present application, forming a second electrode layer electrically connected to a portion of the N-type epitaxial layer located in the cell region includes:

[0149] like Figure 24 As shown, a fourth photoresist layer 42 is formed in the plurality of multi-level trenches, and the fourth photoresist layer 42 is planarized to form the fourth photoresist layer 42 filling the plurality of multi-level trenches;

[0150] like Figure 25 As shown, a second electrode layer 50 is formed on the surface of the super junction device, and the second electrode layer 50 is patterned so that the second electrode layer 50 at least completely covers the cell area and exposes the terminal area. Optionally, the second electrode layer 50 also extends to the transition area to cover a part of the transition area.

[0151] Optionally, in an embodiment of the present application, the second electrode layer comprises a laminated Ni metal layer and Au metal layer, and the Ni metal layer is located between the Au metal layer and the N-type epitaxial layer. Specifically, in an embodiment of the present application, the thickness of the Ni metal layer ranges from 20 nm to 200 nm, and the thickness of the Au metal layer ranges from 80 nm to 1000 nm, for example, the thickness of the Ni metal layer is 20 nm, and the thickness of the Au metal layer is 80 nm, or the thickness of the Ni metal layer is 200 nm, and the thickness of the Au metal layer is 1000 nm, which is not limited in the present application and is subject to change as appropriate.

[0152] On the basis of any of the above embodiments, in an embodiment of the present application, after the second electrode layer is formed, the method further comprises: Figure 26 as shown, forming a passivation layer 60 covering the termination region of the super-junction device, and at least exposing part of the second electrode layer 50 to facilitate electrical connection of the second electrode layer 50 with the outside world.

[0153] Taking the super-junction device comprising a transition region as an example, specifically, in an embodiment of the present application, the passivation layer covering the termination region of the super-junction device and at least exposing part of the second electrode layer comprises:

[0154] forming a passivation layer covering the termination region of the super-junction device, the transition region and the cell region;

[0155] opening the passivation layer to at least expose part of the second electrode layer to facilitate electrical connection of the second electrode layer with the outside world.

[0156] Optionally, in an embodiment of the present application, the passivation layer is a silicon oxide layer, and the forming process is a deposition process, and the thickness is about 1 μm, but the present application is not limited thereto and is subject to change as appropriate.

[0157] In summary, in the method for manufacturing the super-junction device provided in the embodiments of the present application, the N-type epitaxial layer 20 has a plurality of multi-stage grooves, the multi-stage grooves comprise N sub-grooves arranged along a first direction X, and the sizes of the N sub-grooves in a second direction Y are not completely the same, wherein N is not less than 3, so that when the thickness and concentration of the first P-type oxide layer located on the surface of the multi-stage groove change, the probability that at least part of the positions in the multi-stage groove and the N-type epitaxial layer meet the charge balance condition can be increased through the plurality of sub-grooves with different sizes, the probability that the reverse breakdown voltage of the super-junction device greatly decreases due to slight changes in the thickness and concentration of the first P-type oxide layer is reduced, and the reverse breakdown voltage of the super-junction device is improved.

[0158] In addition, in the manufacturing method of the superjunction device provided in the embodiment of the present application, since the thickness and concentration of the first P-type oxide layer vary slightly, a plurality of sub-grooves of unequal sizes can be used so that at least part of the position in the multi-level grooves satisfies the charge balance condition with the N-type epitaxial layer. Therefore, during the manufacturing process of the superjunction device, the process control requirements for the concentration when the first P-type oxide layer is formed are relatively low, the doping concentration window of the first P-type oxide layer is improved, and the process difficulty of the superjunction device is reduced, so that the superjunction device manufactured by the manufacturing method of the superjunction device provided in the embodiment of the present application has higher voltage resistance and lower process difficulty.

[0159] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on the differences from other embodiments, and reference can be made to the common and similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple. For relevant parts, refer to the description of the methods.

[0160] It should be noted that throughout the description of this application, it should be understood that the drawings and descriptions of the embodiments are illustrative rather than restrictive. Like reference numerals throughout the embodiments identify like structures. Furthermore, for ease of understanding and description, the drawings may exaggerate the thickness of some layers, films, panels, regions, and the like.

[0161] It should also be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such article or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the article or device comprising the aforementioned elements.

[0162] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A super junction device, characterized in that: include: Gallium oxide substrate; An N-type epitaxial layer located on the surface of the gallium oxide substrate, wherein a high-resistance layer is formed on a surface of the N-type epitaxial layer away from the gallium oxide substrate; a plurality of multi-level trenches in the N-type epitaxial layer, the multi-level trenches comprising N sub-trenches arranged along a first direction, wherein the N sub-trenches have different sizes in a second direction, wherein N is not less than 3, the first direction is perpendicular to the plane of the gallium oxide substrate and points toward the gallium oxide substrate, and the second direction is perpendicular to the first direction; a first P-type oxide layer covering the surface of the multi-level trench, wherein the surface of the multi-level trench includes the bottom of the multi-level trench and the sidewalls of the multi-level trench; In which, the super junction device includes a cell region, a transition region and a terminal region, the terminal region is located at the periphery of the cell region, the transition region is located between the cell region and the terminal region, and the super junction device also includes: a second P-type oxide layer covering the surface of the portion of the first P-type oxide layer located in the terminal region of the super junction device.

2. The super junction device according to claim 1, wherein: The N-type epitaxial layer includes a plurality of N-type epitaxial units, the portion of the N-type epitaxial layer located between adjacent multi-level trenches is an N-type epitaxial unit, and the first P-type oxide layer on the sidewall of at least one sub-trench in the multi-level trench and the N-type epitaxial unit at its corresponding position meet the charge balance condition, and the charge balance condition is ,in, Characterizes the width of the first P-type oxide layer on the sidewall of a sub-trench in a multi-level trench. Characterizes the concentration of the first P-type oxide layer on the sidewall of the sub-trench, Characterizes the width of the epitaxial unit at the corresponding position of this sub-trench, Characterizes the concentration of the epitaxial unit at the corresponding position of this sub-trench.

3. The super junction device according to claim 1, wherein: Dimensions of the N sub-grooves in the second direction gradually decrease along the first direction.

4. The super junction device according to claim 3, wherein: In the first direction, dimensions of the N sub-grooves in the second direction vary uniformly along the first direction.

5. The super junction device according to claim 1, wherein: The multi-level trenches penetrate the N-type epitaxial layer or the multi-level trenches do not penetrate the N-type epitaxial layer.

6. The super junction device according to claim 1, wherein: In the first direction, the shape of the multi-level groove in a top view is a strip, a circle, a rectangle or a hexagon.

7. The super junction device according to claim 1, wherein: The second P-type oxide layer further extends to cover a portion of the surface of the transition region.

8. The super junction device according to claim 1, wherein: The multiple multi-level trenches include a first multi-level trench located in the cell area and a second multi-level trench located in the terminal area. The first P-type oxide layer and the second P-type oxide layer located on the surface of the second multi-level trench expose at least a portion of the bottom area of ​​the second multi-level trench.

9. A method for manufacturing a super junction device, characterized in that: include: Growing an N-type epitaxial layer on a gallium oxide substrate, and forming a high-resistance layer on a surface of the N-type epitaxial layer away from the gallium oxide substrate; forming a plurality of multi-level trenches in the N-type epitaxial layer, the multi-level trenches including N sub-trenches arranged along a first direction, wherein the N sub-trenches have different sizes in a second direction, wherein N is not less than 3, the first direction is perpendicular to the plane of the gallium oxide substrate and points toward the gallium oxide substrate, and the second direction is perpendicular to the first direction; forming a first P-type oxide layer covering the surface of the multi-level trench on the surface of the multi-level trench, wherein the surface of the multi-level trench includes the bottom of the multi-level trench and the sidewall of the multi-level trench; The super junction device includes a cell region, a transition region and a terminal region, the terminal region is located outside the cell region, and the transition region is located between the cell region and the terminal region. The method also includes: forming a second P-type oxide layer on the surface of the portion of the first P-type oxide layer located in the terminal region of the super junction device.

10. The super junction device according to claim 9, characterized in that: The second P-type oxide layer further extends to cover a portion of the surface of the transition region.

11. The super junction device according to claim 9 or 10, characterized in that: The plurality of multi-level trenches include a first multi-level trench located in the cell region and a second multi-level trench located in the terminal region. The method further includes: removing at least a portion of the first P-type oxide layer and the second P-type oxide layer located at the bottom of the second multi-level trench.

12. The super junction device according to claim 10, wherein: The first P-type oxide layer is a NiO layer, and forming the first P-type oxide layer covering the surface of the multi-level groove includes: first filling the multi-level groove with metallic nickel, and then oxidizing the metallic nickel located in the multi-level groove in an oxygen atmosphere to form the first P-type oxide layer covering the surface of the multi-level groove on the surface of the multi-level groove.

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