Cutting process

Abstract

The present application discloses a cutting path processing method, which relates to the field of semiconductor technology. The cutting path processing method provided in the embodiment of the present application includes etching a wafer along a passivation layer to an epitaxial layer to form a first groove; in the first groove, etching the wafer to a substrate by a wet etching process to form a second groove, and the first groove and the second groove form a cutting path. Since the epitaxial layer is etched by a wet etching process, the internal stress of the epitaxial layer can be effectively released, and the sidewalls and bottom walls of the obtained cutting path are relatively smooth. And wet etching of the epitaxial layer to the substrate only takes a few minutes to achieve, which has a higher etching efficiency than the dry etching process. In addition, the by-products of dry etching are easily accumulated in the cutting path, while the by-products of wet etching are easily discharged with the etching solution.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a cutting path processing method. Background Art

[0002] In the chip manufacturing process, an epitaxial layer is grown on the wafer substrate to achieve specific functions. Usually, the epitaxial layer is a multi-layer structure (dozens or even hundreds of layers). As the number of epitaxial layers increases, the introduced stress will gradually accumulate, and these stresses may have an adverse effect on subsequent wafer processing, and even cause wafer damage when processing and cutting wafers. In some existing technologies, before cutting the wafer to form a single chip, a cutting path is made on the surface of the wafer. The cutting path is a groove structure, which can provide a clear cutting path for the cutting process and reduce cutting errors; at the same time, it can also release stress to a certain extent to avoid chip damage during the cutting process. However, the current cutting path is formed by dry etching. This processing method is inefficient, and the inner wall of the cutting path is relatively rough, which has limited effect on stress release of the epitaxial layer. Summary of the invention

[0003] The purpose of the present invention includes providing a cutting path processing method, which has high processing efficiency and can effectively release the stress of the epitaxial layer and reduce the risk of wafer damage.

[0004] The embodiments of the present invention can be implemented as follows:

[0005] In a first aspect, the present invention provides a cutting path processing method for processing a cutting path on a wafer, wherein the wafer includes a substrate, an epitaxial layer, and a passivation layer stacked in sequence, and the cutting path processing method includes:

[0006] Etching the wafer along the passivation layer to the epitaxial layer to form a first trench;

[0007] In the first groove, the wafer is etched to the substrate by a wet etching process to form a second groove, and the first groove and the second groove form a cutting path.

[0008] In an optional embodiment, in the first groove, etching the wafer to the substrate by a wet etching process to form a second groove includes:

[0009] coating photoresist onto the wafer having the first trench formed thereon;

[0010] defining a second groove pattern on the surface of the target epitaxial layer by a photolithography process;

[0011] Based on the second groove pattern, etching the target epitaxial layer to the substrate using an etching solution to form a second groove;

[0012] The target epitaxial layer includes an epitaxial layer located at the bottom of the first trench, and the width of the second trench pattern is smaller than the width of the first trench.

[0013] In an optional embodiment, the spacing between the first sidewall of the second groove pattern and the second sidewall of the first groove is 5-10 μm; the spacing between the third sidewall of the second groove pattern and the fourth sidewall of the first groove is 5-10 μm;

[0014] The first side wall and the second side wall are on the same side; the third side wall and the fourth side wall are on the same side.

[0015] In an optional embodiment, the width of the first groove is 30-70 μm, and the width of the second groove pattern is 15-50 μm.

[0016] In an optional embodiment, based on the second groove pattern, etching the target epitaxial layer to the substrate using an etching solution to form a second groove includes:

[0017] Using deionized water to clean the surface of the wafer having the second groove pattern formed thereon;

[0018] Spraying etching liquid onto the surface of the wafer while the wafer is rotating at a first rotation speed;

[0019] Spraying etching liquid onto the surface of the wafer while the wafer is rotating at a second rotational speed, the second rotational speed being lower than the first rotational speed;

[0020] Static etching of the wafer for a first preset time to form a second groove;

[0021] The wafer formed with the second groove is cleaned and dried.

[0022] In an optional embodiment, the cutting path processing method further includes:

[0023] When the opening ratio P is not greater than 5%, C=A;

[0024] When the opening ratio P is in the range of (5%, 10%], C = (P / 0.05-1) × 10 + A;

[0025] Among them, the opening rate P is the area ratio of the first groove on the wafer, the C is the amount of etching solution sprayed onto the surface of the wafer when the wafer rotates at the second speed, the unit is mL, and A is a constant, and the value range is 30~50.

[0026] In an optional embodiment, the cutting path processing method further includes: when the opening ratio P is greater than 10%, C=A;

[0027] When the opening rate P is greater than 10%, after the wafer is etched statically for a first preset time, the cutting path processing method further includes:

[0028] Obtaining an etching depth of the wafer;

[0029] According to the etching depth of the wafer, the wafer is etched for a second preset time to form a second groove;

[0030] Among them, the opening rate P is the area ratio of the first groove on the wafer, the C is the amount of etching solution sprayed onto the surface of the wafer when the wafer rotates at the second speed, the unit is mL, and A is a constant, and the value range is 30~50.

[0031] In an optional embodiment, the etching liquid is sprayed onto the surface of the wafer for 1 to 10 seconds while the wafer is rotating at a first rotation speed, the first rotation speed is 500 to 1000 r / min; and / or the second rotation speed is 15 to 50 r / min.

[0032] In an optional implementation, the first preset duration is 100-200 seconds.

[0033] In an optional embodiment, the epitaxial layer contains gallium arsenide and / or indium phosphide, and the etching solution contains phosphoric acid, hydrogen peroxide and water.

[0034] In an optional embodiment, the ratio of phosphoric acid, hydrogen peroxide and water in the etching solution is 2-4:1:2-6.

[0035] In an optional embodiment, after the wafer is etched to the substrate to form a second groove in the first groove by a wet etching process, the sawing road processing method further includes:

[0036] Annealing the wafer;

[0037] The step of annealing the wafer includes: keeping the wafer at 250-350° C. for 0.5-3 hours, and cooling it to room temperature.

[0038] The beneficial effects of the cutting path processing method provided by the embodiment of the present invention include:

[0039] The cutting path processing method provided in the embodiment of the present application includes etching a wafer along the passivation layer to the epitaxial layer to form a first groove; in the first groove, etching the wafer to the substrate by a wet etching process to form a second groove, and the first groove and the second groove form a cutting path. Since the epitaxial layer is etched by a wet etching process, the internal stress of the epitaxial layer can be effectively released, and the side walls and bottom walls of the obtained cutting path are relatively smooth. And wet etching of the epitaxial layer to the substrate only takes a few minutes to achieve, which has a higher etching efficiency than the dry etching process. In addition, the by-products of dry etching are easily accumulated in the cutting path, while the by-products of wet etching are easily discharged with the etching solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1 A partial schematic diagram of a wafer (without processed cutting paths) according to an embodiment of the present application;

[0042] Figure 2 This is a flow chart of a cutting path processing method in one embodiment of the present application;

[0043] Figures 3 to 5 This is an intermediate schematic diagram of a cutting path processing process in one embodiment of the present application;

[0044] Figure 6 This is a first schematic diagram of a cutting path produced in an embodiment of the present application;

[0045] Figure 7 A second schematic diagram of a cutting path produced in an embodiment of the present application;

[0046] Figure 8 It is a schematic diagram of the side wall of the cutting road manufactured in one embodiment of the present application.

[0047] Icon: 100 - substrate; 200 - epitaxial layer; 300 - passivation layer; 400 - cutting road; 410 - first trench; 420 - second trench; 500 - photoresist. DETAILED DESCRIPTION

[0048] In the related art, as the epitaxial layer on the wafer substrate is formed, stress will exist inside the epitaxial layer. Taking the manufacture of gallium arsenide-based vertical cavity chips as an example, the total number of epitaxial layers ranges from dozens to hundreds of layers, and the stress in the epitaxial layer will cause severe wafer warping. When the wafer is subsequently processed (such as wafer thinning, grinding, gold plating, cleaning) and subsequently cut to form a single chip, there will be a risk of fragments (or broken pieces). For cutting wafers, some practices do not perform cutting path processing. At this time, due to the large stress of the wafer, it is easy to cause the wafer to crack during cutting, resulting in chip damage. Other practices are to process and form cutting paths on the epitaxial layer, which can calibrate and guide the cutting position, and after the cutting path is processed, a certain amount of stress can be released to reduce the risk of broken pieces. However, in the related process, a dry etching process is usually used to form a cutting path, which has problems such as low process efficiency (often requiring tens of minutes of etching), rough wall surface of the cutting path, limited stress release, and easy accumulation of by-products in the cutting path.

[0049] To this end, an embodiment of the present application provides a cutting road processing method, which etches the epitaxial layer through a wet etching process to form a cutting road with smooth walls, high processing efficiency, good stress release effect, and easy removal of by-products.

[0050] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0051] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0052] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0053] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, they are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the invention is usually placed when used. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0054] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0055] It should be noted that, in the absence of conflict, the features in the embodiments of the present invention may be combined with each other.

[0056] Figure 1 A partial schematic diagram of a wafer (unprocessed cutting path) provided in an embodiment of the present application. The cutting path processing method provided in an embodiment of the present application is used to process and form a cutting path 400 on a wafer. Figure 1As shown, the wafer includes a substrate 100, an epitaxial layer 200 and a passivation layer 300 which are stacked in sequence. The material of the substrate 100 can be selected from silicon, silicon carbide, etc. The epitaxial layer 200 is a multi-layer structure, and its specific material and setting method can be designed according to the type of chip to be produced. In this embodiment, the epitaxial layer 200 is a gallium arsenide-based vertical cavity chip epitaxial structure. The vertical cavity chip (Vertical Cavity Surface Emitting Laser, VCSEL, vertical cavity surface emitting laser) is a special semiconductor laser characterized in that light is emitted vertically from the top or bottom of the chip. The epitaxial layer 200 can specifically include structures such as an N-DBR reflective layer, an active layer, a P-DBR reflective layer, etc. which are stacked in sequence. The specific setting method of the epitaxial structure of the vertical cavity chip can refer to the prior art and will not be repeated here. The passivation layer 300 is disposed on a side of the epitaxial layer 200 facing away from the substrate 100 , and its function is to protect the epitaxial layer 200 . The passivation layer 300 may be made of silicon nitride, silicon oxide, aluminum oxide or other types of materials.

[0057] Figure 2 This is a flow chart of a cutting path processing method in one embodiment of the present application; Figures 3 to 5 FIG. 4 is an intermediate schematic diagram of a cutting path 400 during processing in one embodiment of the present application. Figures 2 to 5 As shown, the cutting path processing method provided in the embodiment of the present application includes the following steps:

[0058] In step S100 , the wafer is etched along the passivation layer 300 to the epitaxial layer 200 to form a first trench 410 .

[0059] In the embodiment of the present application, a photolithography pattern of the first groove 410 (hereinafter referred to as the first groove pattern) can be formed on the passivation layer 300 by exposure and development. The first groove pattern exposes the area where the first groove 410 is to be formed, that is, the area where the cutting road 400 is to be formed. Then, the passivation layer 300 exposed by the first groove pattern is etched away to form the first groove 410. The bottom of the first groove 410 extends to the epitaxial layer 200, such as Figure 3 The etching method of the first trench 410 may be dry etching, such as reactive ion etching (RIE), or wet etching, such as buffered oxide etching (BOE).

[0060] In one embodiment, a dry etching process is used to etch the wafer along the passivation layer 300 to the epitaxial layer 200 to form the first groove 410; dry etching of the passivation layer can avoid the appearance of voids in the contact area between the passivation layer 300 and the epitaxial layer 200. It can be understood that if dry etching is used to form the first groove 410, the width of the first groove pattern should be consistent with the width of the first groove 410 to be manufactured.

[0061] In this embodiment, the width of the first groove 410 is the width of the opening of the final cut street 400, and should be designed according to the width of the cut street 400 to be manufactured. Optionally, the width W1 of the first groove 410 is 30-70 μm, such as 50 μm.

[0062] In step S200 , a second groove 420 is formed by etching the wafer to the substrate 100 in the first groove 410 through a wet etching process. The first groove 410 and the second groove 420 form a cutting street 400 .

[0063] In the embodiment of the present application, the second trench 420 is formed on the epitaxial layer 200 at the bottom of the first trench 410 by wet etching, the bottom of the second trench 420 extends to the substrate 100 , and the first trench 410 and the second trench 420 together form a cutting path 400 .

[0064] In the actual production process, the total number of epitaxial layers of GaAs-based vertical cavity chips (hereinafter referred to as wafers) ranges from dozens to hundreds of layers. During the epitaxial growth of the wafer, the periodic DBR layer increases and the introduced stress gradually accumulates, which leads to serious warping of the P surface of the wafer. Based on the above technical problems, the cutting path processing method proposed in this application uses wet etching to form the cutting path, which greatly reduces the stress of the wafer, reduces the warping of the P surface of the wafer, and effectively reduces the risk of wafer breakage during grinding, thinning, N-side gold plating, thin-film cleaning and cutting and splitting.

[0065] Furthermore, the cutting road processing method described in the embodiment of the present application forms the cutting road by two etching methods (i.e., the first etching forms the first groove first, and the second groove is formed based on the first groove and the wet etching process, and then the cutting road is formed), so as to avoid the etching solution directly using the wet etching to cause the wrong etching of the area outside the cutting road to be formed on the wafer. That is, the first groove is formed by one etching to define the formation area of ​​the cutting road (i.e., define the width of the cutting road to be formed), and then the second groove pattern is formed based on the width of the first groove (i.e., the width of the cutting road to be formed); then the second groove is formed by wet etching according to the second groove pattern; finally, the cutting road is formed based on the first groove and the second groove. It can be understood that in the etching process, when the depth of one etching is deep, it is easy for the groove side wall to become rough near the bottom, that is, the deeper the etching depth, the worse the etching quality. Moreover, the inclination degree of the side wall near the bottom is different from that of the side wall near the top (especially wet etching). In the embodiment of the present application, two etchings are used to complete the production of the cutting path 400. The depth of the two etchings is relatively thin, and the etching quality is also better. The passivation layer 300 is etched for the first time to form the first groove 410. The etching depth is relatively shallow, and the first groove 410 formed is clear. The epitaxial layer 200 is wet-etched for the second time to form the second groove 420. The etching depth is also relatively shallow, and the sidewall formed by wet etching is smooth. If both etchings are wet etching, the slope of the sidewall is easier to keep consistent than one deeper etching with two shallower etchings.

[0066] In the embodiment of the present application, step S200 specifically includes:

[0067] Step S210 , coating the photoresist 500 onto the wafer having the first trench 410 formed thereon.

[0068] In the embodiment of the present application, the photoresist 500 coated in step S210 covers the passivation layer 300 and the epitaxial layer 200 at the bottom of the first trench 410 .

[0069] Step S220 , defining a second groove pattern on the surface of the target epitaxial layer by a photolithography process.

[0070] In this embodiment, the target epitaxial layer includes an epitaxial layer at the bottom of the first trench 410, which will be subsequently etched away to form the second trench 420. The second trench pattern exposes a portion of the target epitaxial layer. In this embodiment, the width of the second trench pattern is smaller than that of the first trench 410.

[0071] like Figure 4As shown in FIG. 1 , the second groove pattern used for etching to form the second groove 420 is equivalent to a window on the photoresist 500, which can expose a portion of the target epitaxial layer at the bottom of the first groove 410. Since the wet etching process not only etches the epitaxial layer 200 in the depth direction (i.e., the stacking direction of the epitaxial layer 200), but also performs lateral etching, i.e., in the direction of the epitaxial layer 200, the epitaxial layer 200 is etched in the horizontal direction. Figure 4 Therefore, the width of the second groove pattern should be smaller than that of the first groove 410. Optionally, a distance is reserved between the two sides of the second groove pattern in the width direction and the two side walls of the first groove 410, that is, a space for lateral etching is reserved. In this way, the width of the opening of the second groove 420 formed by wet etching can be as consistent as possible with the width of the first groove 410, thereby improving the flatness of the side wall of the cutting road 400 finally produced.

[0072] Optionally, the width W2 of the second groove pattern used to etch the second groove 420 is 15-50 μm. Optionally, the second groove pattern has a first sidewall and a third sidewall spaced apart in its width direction, and the first groove 410 has a second sidewall and a fourth sidewall spaced apart in its width direction, the first sidewall and the second sidewall are on the same side, and the third sidewall and the fourth sidewall are on the same side. The spacing between the first sidewall of the second groove pattern and the second sidewall of the first groove 410 is 5-10 μm, and the spacing between the third sidewall of the second groove pattern and the fourth sidewall of the first groove is 5-10 μm; that is, the two sides of the second groove pattern in the width direction are 5-10 μm away from the two sidewalls of the first groove 410 respectively. In a specific embodiment, the width W1 of the first groove 410 is 50 μm, the width W2 of the second groove pattern is 30 μm, and its two sides in the width direction are 10 μm away from the two sidewalls of the first groove 410 respectively. In this embodiment, the first groove 410 has a guiding property for the second groove 420. The groove bottom of the first groove 410 contacts the groove top of the second groove 420. When the design width W1 of the first groove 410 is 50 μm and the design width W2 of the second groove pattern is 30 μm, the specific position of the second groove pattern can be set with the middle point of the width of the first groove 410 as the center position, so that the distance from the two side walls of the second groove pattern to the two side walls of the groove bottom of the first groove 410 is 10 μm.

[0073] In this embodiment, the photoresist 500 may be a positive photoresist. When the photoresist 500 is coated, the speed is 3000 r / min for coating, and the coating is baked at 100° C. for 120 seconds. The dose (DOSE) of the photoresist used when exposing the photoresist 500 is 30 mJ / cm2, and after developing in a developer having a TMAH (tetramethylammonium hydroxide, a compound that enhances solubility) content of 2.38%, a second groove pattern is formed.

[0074] In step S230 , based on the second trench pattern, an etching solution is used to etch the target epitaxial layer to the substrate 100 to form a second trench 420 .

[0075] The epitaxial layer 200 exposed by the second groove pattern can be etched and removed by a wet etching process, and the substrate 100 is etched to expose the substrate 100, thereby forming a second groove 420 in the epitaxial layer 200. After the second groove 420 is formed, the photoresist 500 can be removed. The second groove 420 and the first groove 410 formed previously together constitute a cutting road 400. Figure 5 During the wet etching process, the etching solution will also laterally erode a portion of the epitaxial layer 200. Since the lateral etching time of the end (opening end) of the second trench 420 away from the substrate 100 is longer than that of the end close to the substrate 100, the shape of the second trench 420 is a structure with a narrow bottom and a wide opening, that is, the sidewall of the second trench 420 has a certain inclination angle.

[0076] Optionally, step S220 specifically includes:

[0077] Step S221 , using deionized water to clean the surface of the wafer where the first groove is formed.

[0078] Specifically, an automatic single-wafer cleaning device may be used to clean the wafer using deionized water while the wafer is rotating at high speed. Specifically, the wafer rotation speed may be 800-1200 r / min, such as 1000 r / min.

[0079] Step S222: spraying etching liquid onto the surface of the wafer while the wafer is rotating at a first rotation speed.

[0080] The purpose of this step is to make the etching liquid quickly wet the entire surface of the wafer, so that the etching liquid sprayed in the subsequent step S223 can be more evenly distributed on the wafer surface, so that the degree of etching in the middle and edge of the wafer tends to be consistent, thereby improving the uniformity of etching. The first speed is a higher speed. Optionally, the first speed is 500~1000r / min, such as 800 r / min. The spraying time of the etching liquid in step S222 can be selected as 1~10s, such as 3s; the spraying flow rate can be selected as 10mL / s.

[0081] Step S223, spraying etching liquid onto the surface of the wafer while the wafer is rotating at a second rotational speed, wherein the second rotational speed is lower than the first rotational speed.

[0082] In this embodiment, the second rotation speed is a relatively low rotation speed, and the etching liquid sprayed on the surface of the wafer during the process of the wafer rotating at the second rotation speed will remain on the surface of the wafer and participate in the etching of the epitaxial layer 200. Optionally, the second rotation speed is 15~50r / min, for example, 25r / min. Since the surface of the wafer has been soaked with the etching liquid in step S222, the etching liquid sprayed in the low-speed process in step S223 can be evenly distributed on various positions of the wafer surface, and it is not easy to cause uneven distribution due to the liquid surface tension of the etching liquid itself. In addition, the rotation of the wafer at a low speed is conducive to the uniform distribution of the etching liquid, and at the same time, the etching liquid will not be separated from the wafer due to excessive centrifugal force, thereby ensuring the subsequent etching effect.

[0083] The amount of etching solution sprayed in step S223 should be designed according to the amount of epitaxial layer 200 to be etched. It should be understood that the more cutting paths 400 need to be made on the wafer and the larger the area, the more etching solution is needed. Specifically, the amount of etching solution sprayed C in step S223 satisfies the following relationship:

[0084] When the opening ratio P is not greater than 5%, C=A;

[0085] When the opening ratio P is in the range of (5%, 10%], C = (P / 0.05-1) × 10 + A;

[0086] When the opening ratio P is greater than 10%, C=A;

[0087] Among them, the porosity is the area ratio of the first groove 410 on the wafer, specifically, the value obtained by dividing the opening area of ​​the first groove 410 (that is, the opening area of ​​the cutting path 400) by the single-sided area of ​​the wafer. The unit of the spraying amount C is mL, and the value range of A is 30~50. In a specific embodiment, A is 40, that is, when the porosity P is not greater than 5%, the spraying amount C of the etching solution in step S223 is 40mL; when the porosity P is in the range of (5%, 10%], the spraying amount C is 40mL~50mL.

[0088] Optionally, in step S223, the spraying flow rate of the etching solution is 10 mL, and the spraying time is 3-5 s. The spraying time and the spraying flow rate can be adjusted according to the required amount of etching solution.

[0089] Step S224, leaving the wafer to etch for a first preset time period.

[0090] After step S223, a certain amount of etching liquid is evenly distributed on the wafer. At this time, the etching is allowed to stand for a preset time so that the etching liquid can etch downward along the photolithography pattern until the substrate 100; at the same time, the etching liquid will also etch laterally by a certain amount. For example, when the thickness of the epitaxial layer 200 is 10μm, when the etching liquid etches to the substrate 100, the two sides of the photolithography pattern in the width direction are taken as the zero point, and the etching liquid will also etch 4~7μm more on both sides of the groove. Therefore, in step S210, the photolithography pattern used to etch the second groove 420 will be designed to be narrow, thereby reserving space for lateral etching and avoiding excessive lateral etching to damage the chip.

[0091] Optionally, the preset time length is 100-200 seconds, such as 140 seconds. As described in step S223, if the dicing road 400 occupies a large proportion on the wafer and is not completely etched after step S224, etching liquid may be added to perform static etching again.

[0092] Furthermore, when the aperture ratio P is greater than 10%, the spraying amount C=A is not enough to complete the etching. Therefore, after the wafer is left to etch for a first preset time, the etching depth of the wafer is obtained, and the wafer is left to etch for a second preset time according to the etching depth of the wafer. The reason why the spraying amount C=A is set when the aperture ratio P is greater than 10% is that if too much etching solution is sprayed at one time, it may lead to poor etching effect, such as the etching solution on the wafer is easy to overflow. Therefore, an appropriate amount (such as 40mL) of etching solution is sprayed first, and after the static etching in step S224 is completed, the etching rate is calculated according to the etching depth, and the etching solution is replenished according to the unfinished etching amount, and static etching is performed again.

[0093] Step S225, cleaning and drying the wafer.

[0094] After the second groove 420 is formed by etching, the cutting path 400 is formed. After that, the wafer surface can be cleaned with deionized water to clean the etching liquid during the high-speed rotation of the wafer. Since the high-speed rotation can provide a large centrifugal force, the byproducts of etching are easily discharged from the cutting path 400 along with the liquid flow. After that, the moisture on the wafer surface can be blown dry with hot nitrogen.

[0095] Optionally, the epitaxial layer 200 of the wafer in this embodiment contains gallium arsenide and / or indium phosphide; the etching solution contains phosphoric acid, hydrogen peroxide and water. The etching solution containing phosphoric acid and hydrogen peroxide can effectively corrode gallium arsenide and indium phosphide without corroding the photoresist 500. Optionally, the ratio of phosphoric acid, hydrogen peroxide and water in the etching solution is 2~4:1:2~6. In a specific embodiment, the ratio of phosphoric acid, hydrogen peroxide and water is 3:1:4.

[0096] After the cutting road 400 is formed by the wet etching process, the stress of the epitaxial layer 200 is released, which alleviates the problem of wafer warping due to stress, and facilitates subsequent wafer processing (such as thinning) and cutting. In addition, the wet etching process of the epitaxial layer only takes a few minutes, which has higher processing efficiency than dry etching.

[0097] In an embodiment of the present application, after the cutting road 400 is completed, that is, after step S200, if the wafer still has a relatively obvious warping problem (for example, the height difference between the highest and lowest points of the wafer is greater than 50μm), the wafer can be annealed. Specifically, the step of annealing the wafer may include: keeping the wafer at 250~350℃ for 0.5~3h and cooling it to room temperature. The heating and insulation process can be carried out in a quartz furnace tube, and after the insulation is completed, it can be cooled with the furnace or air-cooled to room temperature. Specifically, it can be heated to 300℃ in a quartz furnace tube, kept warm for 1h, and then cooled to room temperature with the furnace. At this time, the stress of the epitaxial layer 200 can be further released.

[0098] Figure 6 This is a first schematic diagram of a cutting street 400 manufactured in an embodiment of the present application; Figure 7 This is a second schematic diagram of a cutting street 400 manufactured in an embodiment of the present application; Figure 8 FIG. 4 is a schematic diagram of the side wall of the cutting path 400 manufactured in one embodiment of the present application. Figures 6 to 8 As shown, the cutting road 400 obtained by the cutting road processing method of the embodiment of the present application is flat, smooth and has no obvious burrs. Figure 7 In this embodiment, the width of the second groove pattern is 57.4 μm. Due to the lateral corrosion of the etching solution, the opening width of the second groove 420 on the epitaxial layer 200 is finally 67 μm. Figure 7 and Figure 8 As shown, the sidewall of the cutting street 400 at the epitaxial layer 200 (ie, the sidewall of the second trench 420 ) is an inclined slope.

[0099] In summary, the embodiment of the present application provides a cutting path processing method, which includes etching a wafer along a passivation layer to an epitaxial layer to form a first groove; in the first groove, etching the wafer to a substrate by a wet etching process to form a second groove, and the first groove 410 and the second groove 420 form a cutting path 400. Since the epitaxial layer 200 is etched by a wet etching process, the internal stress of the epitaxial layer 200 can be effectively released, and the side walls and bottom walls of the obtained cutting path 400 are relatively smooth. And wet etching of the epitaxial layer 200 to the substrate 100 only takes a few minutes to achieve, which has a higher etching efficiency than the dry etching process. In addition, the by-products of dry etching are easily accumulated in the cutting path 400, while the by-products of wet etching are easily discharged with the etching solution.

[0100] It should be understood that the cutting path processing method described in the present application is not only applicable to vertical cavity chips, but also applicable to other chips containing multi-layer stacking structures.

[0101] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A method for processing a cutting path, for processing a cutting path on a wafer, wherein the wafer comprises a substrate, an epitaxial layer and a passivation layer stacked in sequence, characterized in that: The cutting path processing method comprises: Etching the wafer along the passivation layer to the epitaxial layer to form a first groove; In the first groove, the wafer is etched to the substrate to form a second groove by a wet etching process, and the first groove and the second groove form a cutting road; In the first groove, etching the wafer to the substrate to form a second groove by a wet etching process, comprising: Applying photoresist to the wafer having the first groove formed thereon; defining a second groove pattern on the surface of the target epitaxial layer by a photolithography process; Based on the second groove pattern, etching the target epitaxial layer to the substrate using an etching solution to form the second groove; The target epitaxial layer includes an epitaxial layer located at the bottom of the first trench, and the width of the second trench pattern is smaller than the width of the first trench.

2. The cutting path processing method according to claim 1, characterized in that: The spacing between the first sidewall of the second groove pattern and the second sidewall of the first groove is 5-10 μm; the spacing between the third sidewall of the second groove pattern and the fourth sidewall of the first groove is 5-10 μm; Wherein, the first side wall and the second side wall are on the same side; the third side wall and the fourth side wall are on the same side.

3. The cutting path processing method according to claim 2, characterized in that: The width of the first groove is 30-70 μm, and the width of the second groove pattern is 15-50 μm.

4. The cutting path processing method according to any one of claims 1 to 3, characterized in that: Based on the second groove pattern, etching the target epitaxial layer to the substrate using an etching solution to form the second groove comprises: Using deionized water to clean the surface of the wafer having the second groove pattern formed thereon; Spraying the etching liquid onto the surface of the wafer while the wafer is rotating at a first rotation speed; Spraying the etching liquid onto the surface of the wafer while the wafer is rotating at a second rotation speed, wherein the second rotation speed is lower than the first rotation speed; Static etching of the wafer for a first preset time to form the second groove; The wafer with the second groove formed thereon is cleaned and dried.

5. The cutting path processing method according to claim 4, characterized in that: The cutting path processing method further comprises: When the opening ratio P is not greater than 5%, C=A; When the porosity P is in the range of (5%, 10%], C=(P / 0.05-1)×10+A; wherein the porosity P is the area ratio of the first groove on the wafer, the C is the amount of etching solution sprayed onto the surface of the wafer when the wafer rotates at the second speed, in mL, and A is a constant, and its value range is 30~50.

6. The cutting path processing method according to claim 4, characterized in that: The cutting path processing method further includes: when the opening rate P is greater than 10%, C=A; When the opening rate P is greater than 10%, after the wafer is etched statically for a first preset time, the cutting path processing method further includes: Obtaining the etching depth of the wafer; According to the etching depth of the wafer, the wafer is etched for a second preset time to form a second groove; Among them, the opening rate P is the area ratio of the first groove on the wafer, the C is the amount of etching solution sprayed onto the surface of the wafer when the wafer rotates at the second speed, the unit is mL, and A is a constant, and the value range is 30~50.

7. The cutting path processing method according to claim 4, characterized in that: Spraying the etching solution onto the surface of the wafer for 1 to 10 seconds while the wafer is rotating at the first speed, wherein the first speed is 500 to 1000 r / min; And / or, the second rotational speed is 15~50r / min.

8. The cutting path processing method according to claim 4, characterized in that: The first preset time length is 100~200s.

9. The cutting path processing method according to claim 1, characterized in that: The epitaxial layer contains gallium arsenide and / or indium phosphide, and the etching solution contains phosphoric acid, hydrogen peroxide and water.

10. The cutting path processing method according to claim 9, characterized in that: The ratio of phosphoric acid, hydrogen peroxide and water in the etching solution is 2-4:1:2-6.

11. The cutting path processing method according to claim 10, characterized in that: After the wafer is etched in the first groove by a wet etching process until a second groove is formed in the substrate, the cutting path processing method further includes: annealing the wafer; Wherein, annealing the wafer comprises: keeping the wafer at 250-350° C. for 0.5-3 h, and cooling to room temperature.

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