A current-limiting protection circuit controlled by soft start

Abstract

The present invention belongs to the field of chips and provides a current-limiting protection circuit controlled by soft start. The circuit includes an operational amplifier, a first N-type MOS transistor, a second N-type MOS transistor, a first resistor, a second resistor, and a current mirror. The non-inverting input terminal of the operational amplifier is connected to the soft start reference voltage, its output terminal is connected to the gate of the first N-type MOS transistor, its inverting input terminal is connected to the source of the first N-type MOS transistor and one end of the first resistor, the other end of the first resistor is grounded, the drain of the first N-type MOS transistor and the gate of the second N-type MOS transistor are respectively connected to both ends of the current mirror, one end of the second resistor is connected to the gate of the second N-type MOS transistor, and its other end is grounded. The resistance value of the first resistor is equal to that of the second resistor, the width-to-length ratio of the current mirror is 1:1, the source of the second N-type MOS transistor outputs a driving signal to the gate of the low-side NMOS transistor of the chip, and its drain is connected to the power supply; the present invention can make the driving voltage of the low-side NMOS transistor of the chip remain at a relatively low level during soft start, thereby realizing current-limiting protection.

Description

Technical Field

[0001] The present invention relates to the field of chips, and particularly to a current-limiting protection circuit controlled by soft start. Background Art

[0002] Currently, the main method for the current-limiting protection circuit of the Low Side NMOS inside the chip is as follows:

[0003] Use an external resistor R1 of the chip for current limiting, as Figure 1 shown, Figure 1 The circuit is an external circuit of the chip, mainly used to generate the voltage of VGH. The Low Side NMOS (low-side NMOS transistor) inside the chip is at Figure 1 LXA. The Low Side NMOS inside the chip refers to that in an integrated circuit, the source of the NMOS transistor is connected to the ground, and the drain is connected to the load. Its main function is to control the current flow of the load and is usually used in switching circuits.

[0004] Such as Figure 2 the BOOST boost circuit in the working asynchronous mode shown, its output voltage AVDD and LXA are used for Figure 1 the VGH generation circuit in, and the Low Side NMOS inside the chip is connected between LXA and GND.

[0005] The specific current-limiting protection principle is as follows: Before the Charge Pump (charge pump) mode starts to work, since the voltages of the upper and lower plates of the FlyCap (C1) have been charged to VIN, when the Charge Pump mode starts, the LSNMOS is turned on, that is, the voltage of LXA starts to switch. When switching, the voltage of LXA will instantaneously drop from VIN to 0V, generating a large switching current. Adding a resistor R1 between LXA and C1 can play a role in current limiting and prevent the phenomenon that the LSNMOS is burned out due to excessive switching current.

[0006] In the above method, the current limiting is relatively dependent on the external resistor R1. If no resistor R1 is added between the FLY CAP and LXA, the current may be too large, causing the Low Side NMOS inside the chip to burn out. Summary of the Invention

[0007] In view of the above technical problems, the present invention provides a current-limiting protection circuit controlled by soft start, so that the driving voltage of the low-side NMOS transistor of the chip remains at a relatively low level during soft start, thereby realizing current-limiting protection.

[0008] Other features and advantages of the present invention will become apparent through the following detailed description, or be learned in part through the practice of the present invention.

[0009] The present invention discloses a current-limiting protection circuit controlled by soft start. The current-limiting protection circuit is disposed inside a chip. The current-limiting protection circuit includes an operational amplifier, a first N-type MOS transistor, a second N-type MOS transistor, a first resistor, a second resistor, and a current mirror. The non-inverting input terminal of the operational amplifier is connected to a soft start reference voltage, its output terminal is connected to the gate of the first N-type MOS transistor, its inverting input terminal is connected to the source of the first N-type MOS transistor and one end of the first resistor, the other end of the first resistor is grounded, the drain of the first N-type MOS transistor and the gate of the second N-type MOS transistor are respectively connected to both ends of the current mirror, one end of the second resistor is connected to the gate of the second N-type MOS transistor, and its other end is grounded. The resistance value of the first resistor is equal to that of the second resistor, the aspect ratio of the current mirror is 1:1, the source of the second N-type MOS transistor outputs a driving signal to the gate of the low-side NMOS transistor of the chip, and its drain is connected to the power supply.

[0010] Further, the current mirror includes a first P-type MOS transistor and a second P-type MOS transistor. The gates of the first P-type MOS transistor and the second P-type MOS transistor are connected together and their drains are respectively connected to the power supply. The source of the first P-type MOS transistor is connected to its gate and the drain of the first N-type MOS transistor. The source of the second P-type MOS transistor is respectively connected to the gate of the second N-type MOS transistor and one end of the second resistor.

[0011] Further, a small current branch and a capacitor are disposed between the second N-type MOS transistor and the low-side NMOS transistor. The small current branch is used to remain closed before the end of soft start and charge the capacitor at the end of soft start. After the capacitor is charged, it is used to drive the low-side NMOS transistor.

[0012] Further, the small current branch includes a third P-type MOS transistor. The gate of the third P-type MOS transistor is connected to a soft start end signal, the source is connected between the second N-type MOS transistor and the low-side NMOS transistor, and the drain is connected to the power supply.

[0013] The technical solution of the present invention has the following beneficial effects:

[0014] Soft start is adopted to control the GATE driving voltage of the low-side NMOS transistor, so that it is at a lower level during the soft start process, thereby achieving current-limiting protection; after the soft start ends, the low-side NMOS transistor can restore to normal driving ability; an operational amplifier with a negative feedback structure is used as a buffer, which can isolate the larger noise at the low-side NMOS transistor, prevent the noise from having a greater impact on the soft start reference voltage, and protect other front-stage circuits. Description of the Drawings

[0015] Figure 1Schematic diagram of the VGH generation circuit in Charge Pump mode disclosed in the background art of this specification;

[0016] Figure 2 Schematic diagram of the BOOST boost circuit operating in asynchronous mode disclosed in the background art of this specification;

[0017] Figure 3 Schematic diagram of the current-limiting protection circuit controlled by soft start in the embodiments of this specification;

[0018] Figure 4 Schematic diagram of another current-limiting protection circuit controlled by soft start in the embodiments of this specification. Detailed implementation manners

[0019] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present invention. However, those skilled in the art will realize that the technical solutions of the present invention can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. can be used. In other cases, well-known technical solutions are not shown or described in detail to avoid obscuring the various aspects of the present invention.

[0020] As Figures 1-3 shown, an embodiment of this specification provides a current-limiting protection circuit controlled by soft start. The current-limiting protection circuit is disposed inside the chip and includes an operational amplifier 1, a first N-type MOS transistor NM1, a second N-type MOS transistor NM2, a first resistor R1, a second resistor R2, and a current mirror 2. The positive input terminal of the operational amplifier 1 is connected to the soft start reference voltage, its output terminal is connected to the gate of the first N-type MOS transistor NM1, its negative input terminal is connected to the source of the first N-type MOS transistor NM1 and one end of the first resistor R1, the other end of the first resistor R1 is grounded, the drain of the first N-type MOS transistor NM1 and the gate of the second N-type MOS transistor NM2 are respectively connected to both ends of the current mirror 2, one end of the second resistor R2 is connected to the gate of the second N-type MOS transistor NM2, its other end is grounded, the resistance value of the first resistor R1 is equal to that of the second resistor R2, the width-to-length ratio of the current mirror 2 is 1:1, the source of the second N-type MOS transistor NM2 outputs a driving signal to the gate of the low-side NMOS transistor LSNMOS of the chip, and its drain is connected to the power supply VDD.

[0021] Among them, the current mirror 2 includes a first P-type MOS transistor PM1 and a second P-type MOS transistor PM2. The gates of the first P-type MOS transistor PM1 and the second P-type MOS transistor PM2 are connected, and the drains are respectively connected to the power supply VDD. The source of the first P-type MOS transistor PM1 is connected to its gate and the drain of the first N-type MOS transistor NM1. The source of the second P-type MOS transistor PM2 is respectively connected to the gate of the second N-type MOS transistor NM2 and one end of the second resistor R2.

[0022] This embodiment mainly makes an improved design inside the chip. During the soft start process, the GATE drive voltage (NDRV) of the low-side NMOS transistor LSNMOS is reduced, that is, the VGS of the LSNMOS is reduced, thereby reducing the current of the LSNMOS during the switching process, playing a role in current limiting protection and preventing it from being burned out. When the soft start time ends, the voltage of the NDRV is increased again to restore the normal drive ability of the LSNMOS.

[0023] Please continue to refer to Figures 1-3 , during the soft start process, Figure 3 The soft start reference voltage VREF_SST in slowly rises. Under the clamping action of the operational amplifier, VFB = VREF_SST, I1 = VFB / R1. The first P-type MOS transistor PM1 and the second P-type MOS transistor PM2 form a current mirror, and the ratio of their W / L is 1:1. Then I2 = I1, VG = I2*R2. In this circuit, the first resistor R1 is designed to be equal to the second resistor R2. Then VG = VFB = VREF_SST, VLP = VREF_SST - VGS2, where VLP is used as the power supply voltage of the GATE drive circuit of the LSNMOS. When the low-side NMOS transistor LSNMOS is turned on, NDRV = VLP, achieving the purpose of current limiting by reducing the GATE drive voltage NDRV of the low-side NMOS transistor LSNMOS and reducing its VGS during the soft start process.

[0024] In another implementation, as Figure 4 shown, a small current branch 3 and a capacitor C1 are provided between the second N-type MOS transistor NM2 and the low-side NMOS transistor LSNMOS. The small current branch 3 is used to remain closed before the end of the soft start and charge the capacitor C1 at the end of the soft start. After the capacitor C1 is charged, it is used to drive the low-side NMOS transistor.

[0025] Specifically, the small current branch 3 includes a third P-type MOS transistor PM3. The gate of the third P-type MOS transistor PM3 is connected to the soft start end signal, the source is connected between the second N-type MOS transistor NM2 and the low-side NMOS transistor, and the drain is connected to the power supply.

[0026] At the end of soft start, the voltage of VREF_SST rises to VDD. To ensure the normal static operating point of the circuit, VFB = VDD - VGS1, VG = VFB = VDD - VGS1, VLP = VG - VGS2, that is, VLP = VDD - VGS1 - VGS2. It can be seen that after the soft start ends, the voltage of VLP is relatively low. When LSNMOS is turned on, the voltage of NDRV is also relatively low, resulting in its weak driving ability. Therefore, an additional small current branch 3 needs to be added to slowly charge the capacitor C1 after the soft start ends, so that VLP gradually returns to the VDD voltage, that is, when LSNMOS is turned on, NDRV = VLP = VDD, and the normal driving ability of LSNMOS is restored.

[0027] As Figure 4 shown, a small current branch 3 is added, and its current magnitude is I and is controlled by the soft start end signal. Before the soft start ends, SST_ENDB remains high, and this current branch is turned off, VLP = VREF_SST - VGS2; at the end of the soft start, SST_ENDB becomes low, and this small current branch 3 is turned on to charge the capacitor C1 until the charging stops when VLP = VDD. At this time, the voltage domain of NDRV is VLP = VDD, and the normal driving ability of LSNMOS is restored.

[0028] In the above embodiment, by using soft start to control the GATE driving voltage of the low-side NMOS transistor, making it at a relatively low level during the soft start process, current limiting protection is achieved; after the soft start ends, the low-side NMOS transistor can restore to its normal driving ability; using an operational amplifier with a negative feedback structure as a buffer can isolate the relatively large noise at the low-side NMOS transistor, prevent the noise from having a greater impact on the soft start reference voltage, and protect other front-stage circuits.

[0029] Those skilled in the art will readily think of other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present invention, which follow the general principles of the present invention and include the well-known common general knowledge or conventional technical means in the technical field not disclosed by the present invention. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present invention are pointed out by the claims.

Claims

1. A current-limiting protection circuit controlled by soft start, characterized in that, The current limiting protection circuit is arranged inside the chip. The current limiting protection circuit includes an operational amplifier, a first N-type MOS transistor, a second N-type MOS transistor, a first resistor, a second resistor, and a current mirror. The non-inverting input terminal of the operational amplifier is connected to the soft start reference voltage, its output terminal is connected to the gate of the first N-type MOS transistor, its inverting input terminal is connected to the source of the first N-type MOS transistor and one end of the first resistor, the other end of the first resistor is grounded, the drains of the first N-type MOS transistor and the second N-type MOS transistor are respectively connected to both ends of the current mirror, one end of the second resistor is connected to the gate of the second N-type MOS transistor, and the other end thereof is grounded. The resistance value of the first resistor is equal to that of the second resistor, the width-to-length ratio of the current mirror is 1:1, the source of the second N-type MOS transistor outputs a driving signal to the gate of the low-side NMOS transistor of the chip, and its drain is connected to the power supply; a current branch and a capacitor are arranged between the second N-type MOS transistor and the low-side NMOS transistor. The current branch is used to remain closed before the end of soft start and charge the capacitor at the end of soft start. After the capacitor is charged, it is used to drive the low-side NMOS transistor.

2. The current-limiting protection circuit controlled by soft start according to claim 1, characterized in that The current mirror includes a first P-type MOS transistor and a second P-type MOS transistor. The gates of the first P-type MOS transistor and the second P-type MOS transistor are connected to each other and the drains are respectively connected to the power supply. The source of the first P-type MOS transistor is connected to its gate and the drain of the first N-type MOS transistor. The source of the second P-type MOS transistor is respectively connected to the gate of the second N-type MOS transistor and one end of the second resistor.

3. A current-limiting protection circuit controlled by soft start according to claim 1, characterized in that, The current branch includes a third P-type MOS transistor. The gate of the third P-type MOS transistor is connected to the soft start end signal, the source is connected between the second N-type MOS transistor and the low-side NMOS transistor, and the drain is connected to the power supply.

Images