Signal generating circuit
By designing a signal generation circuit including oscillation circuit, charge and discharge circuit, comparator and frequency division feedback circuit, the problem that the same oscillation circuit in the prior art cannot output different frequency signals, and multi-frequency output is realized, satisfying the system-on-chip chip Stability requirements for high-precision clock modules.
Patent Information
- Application Number
- CN202411204978.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-29
- Publication Date
- 2024-12-10
AI Technical Summary
In the prior art, the same oscillation circuit cannot output oscillation signals of different frequencies, and cannot meet the stability and multi-frequency requirements of the system-on-chip chip for high-precision clock modules.
A signal generation circuit is designed, including an oscillation circuit, a charge and discharge circuit, a comparator and a frequency-dividing feedback circuit. By controlling the charging time of the charge and discharge circuit, the oscillation signals of different frequencies are output using the comparator and a frequency-dividing feedback circuit.
The same oscillation circuit outputs oscillation signals of different frequencies, meets the needs of multiple frequencies, and improves the flexibility and stability of the signal generation circuit.
Smart Images
Figure CN119109419A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of circuit technology, and in particular to a signal generating circuit. Background Art
[0002] With the continuous development of communication, Internet of Things, sensors and biomedicine, the requirements for SoC (System on Circuits) chips are getting higher and higher, making them develop in the direction of lower cost, lower power consumption and more stability. It is an urgent need to provide these electronic systems with a high-precision clock module with stable and reliable performance.
[0003] In the related art, the same oscillation circuit can only output an oscillation signal of one frequency, and the same oscillation circuit cannot output oscillation signals of different frequencies. Summary of the invention
[0004] The purpose of this application is to provide a signal generating circuit to address the deficiencies in the above-mentioned prior art so as to solve the above-mentioned technical problems existing in the related art.
[0005] To achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:
[0006] In a first aspect, an embodiment of the present application provides a signal generating circuit, the signal generating circuit comprising: an oscillating circuit, the oscillating circuit comprising: a current source, a charging and discharging circuit, a comparator, and a frequency dividing feedback circuit;
[0007] The power supply end of the current source is connected to the first end of the charge-discharge circuit and the second end of the charge-discharge circuit respectively, the first end of the charge-discharge circuit is connected to the negative input end of the comparator, and the second end of the charge-discharge circuit is connected to the positive input end of the comparator;
[0008] The output end of the comparator is connected to the clock input end of the frequency division feedback circuit, and the output end of the comparator is also connected to the first control end of the charge and discharge circuit. The control end of the frequency division feedback circuit is used to input a frequency control signal, and the control signal output end of the frequency division feedback circuit is connected to the second control end of the charge and discharge circuit. The oscillation signal output end of the frequency division feedback circuit is used to output an oscillation signal corresponding to the frequency control signal.
[0009] Optionally, the charging and discharging circuit includes: a first resistor, a second resistor, a first capacitor, a first switching device, and a second switching device;
[0010] Wherein, one end of the first resistor is the first end of the charge-discharge circuit, one end of the first capacitor is the second end of the charge-discharge circuit, and the control end of the first switch device is the second control end of the charge-discharge circuit; the other end of the first resistor is grounded through the second resistor, and the other end of the first resistor is also grounded through the first switch device;
[0011] The other end of the first capacitor is grounded, one end of the first capacitor is grounded through the second switch device, and the control end of the second switch device is the first control end of the charge and discharge circuit.
[0012] Optionally, the frequency division feedback circuit includes: a first sub-frequency division feedback circuit, a second sub-frequency division feedback circuit, a third sub-frequency division feedback circuit, and an OR gate circuit;
[0013] The clock input terminal of the first sub-frequency division feedback circuit is the clock input terminal of the frequency division feedback circuit; the control output terminal of the first sub-frequency division feedback circuit is connected to the control terminal of the first sub-frequency division feedback circuit, and the output terminal of the first sub-frequency division feedback circuit is respectively connected to the clock input terminal of the second sub-frequency division feedback circuit and the clock input terminal of the third sub-frequency division feedback circuit;
[0014] The control end of the second sub-frequency division feedback circuit is the control end of the frequency division feedback circuit; the control signal output end of the second sub-frequency division feedback circuit is the control signal output end of the frequency division feedback circuit; the output end of the second sub-frequency division feedback circuit is connected to the first input end of the OR gate circuit;
[0015] The output end of the third sub-frequency division feedback circuit is connected to the second input end of the OR gate circuit, the reset end of the third sub-frequency division feedback circuit is connected to the reset signal output end of the second sub-frequency division feedback circuit, and the output end of the third sub-frequency division feedback circuit is connected to the control end of the third sub-frequency division feedback circuit; the output end of the OR gate circuit is the oscillation signal output end of the frequency division feedback circuit.
[0016] Optionally, the first sub-frequency division feedback circuit comprises: a first trigger and a first inverter;
[0017] The clock input end of the first trigger is the clock input end of the frequency division feedback circuit; the control output end of the first trigger is the control output end of the first sub-frequency division feedback circuit; the output end of the first trigger is connected to the input end of the first inverter, and the output end of the first inverter is the output end of the first sub-frequency division feedback circuit.
[0018] Optionally, the second sub-frequency division feedback circuit includes: a second trigger, a second inverter and an AND gate circuit;
[0019] The clock input terminal of the second flip-flop is the clock input terminal of the second sub-frequency division feedback circuit, the control terminal of the second flip-flop is the control terminal of the second sub-frequency division feedback circuit, the output terminal of the second flip-flop is the reset signal output terminal of the second sub-frequency division feedback circuit, and the output terminal of the second flip-flop is connected to the input terminal of the second inverter; the output terminal of the second inverter is the control signal output terminal of the second sub-frequency division feedback circuit, and is connected to the first input terminal of the AND gate circuit;
[0020] The output end of the first sub-frequency division feedback circuit is connected to the second input end of the AND gate circuit, and the output end of the AND gate circuit is the output end of the second sub-frequency division feedback circuit.
[0021] Optionally, the third sub-frequency division feedback circuit includes: a third trigger, a third inverter, a fourth inverter and a fifth inverter, including:
[0022] The clock input terminal of the third trigger is the clock input terminal of the third sub-frequency division feedback circuit, the reset terminal of the third trigger is the reset terminal of the third sub-frequency division feedback circuit, and the output terminal of the third trigger is connected to the input terminal of the fifth inverter through the fourth inverter;
[0023] The output end of the fifth inverter is the output end of the third sub-frequency division feedback circuit, and the control end of the third trigger is the control end of the third sub-frequency division feedback circuit; the output end of the fifth inverter is connected to the input end of the third inverter, and the output end of the third inverter is connected to the control end of the third trigger.
[0024] Optionally, the signal generating circuit further comprises: a failure detection circuit;
[0025] The oscillation signal output end of the frequency division feedback circuit is connected to the input end of the failure detection circuit, the failure detection circuit is used to perform frequency failure detection on the oscillation signal, and the output end of the failure detection circuit is used to output a detection signal for the oscillation signal, and the detection signal is used to indicate whether the oscillation signal has a frequency failure.
[0026] Optionally, the failure detection circuit includes: a pulse generating circuit, a capacitor discharge ramp circuit and a digital latch circuit;
[0027] The input end of the pulse generating circuit is the input end of the failure detection circuit, the output end of the pulse generating circuit is connected to the input end of the capacitor discharge ramp circuit, the output end of the capacitor discharge ramp circuit is connected to the input end of the digital latch circuit, and the output end of the digital latch circuit is the output end of the failure detection circuit.
[0028] Optionally, the capacitor discharge ramp circuit includes: a second capacitor, a third capacitor, a third switch device, a fourth switch device, a fifth switch device, a sixth switch device, and a seventh switch device;
[0029] The input end of the capacitor discharge ramp circuit includes: the control end of the third switch device and the control end of the fourth switch device, the first end of the third switch device and the first end of the fourth switch device are both connected to the power supply voltage end, and the output end of the capacitor discharge ramp circuit includes: the second end of the third switch device and the second end of the fourth switch device;
[0030] The control end of the fifth switch device, the first end of the fifth switch device, the control end of the sixth switch device, and the control end of the seventh switch device are respectively used to receive input bias current; the second end of the fifth switch device is grounded, the first end of the sixth switch device is connected to the second end of the third switch device, and the second end of the sixth switch device is grounded; the first end of the seventh switch device is connected to the second end of the fourth switch device, and the second end of the seventh switch device is grounded.
[0031] Optionally, the third switch device and the fourth switch device are P-type metal-oxide semiconductor field effect transistors (MOS tubes), and the fifth switch device, the sixth switch device, and the seventh switch device are N-type MOS tubes.
[0032] The beneficial effects of the present application are as follows: an embodiment of the present application provides a signal generating circuit, the signal generating circuit includes: an oscillation circuit, the oscillation circuit includes: a current source, a charge and discharge circuit, a comparator, and a frequency division feedback circuit; the power supply end of the current source is respectively connected to the first end of the charge and discharge circuit and the second end of the charge and discharge circuit, the first end of the charge and discharge circuit is connected to the negative input end of the comparator, and the second end of the charge and discharge circuit is connected to the positive input end of the comparator; the output end of the comparator is connected to the clock input end of the frequency division feedback circuit, and the output end of the comparator is also connected to the first control end of the charge and discharge circuit, the control end of the frequency division feedback circuit is used to input a frequency control signal, the control signal output end of the frequency division feedback circuit is connected to the second control end of the charge and discharge circuit, and the oscillation signal output end of the frequency division feedback circuit is used to output an oscillation signal corresponding to the frequency control signal. A frequency control signal is input to the control end of the frequency-dividing feedback circuit, and the charging time of the charging and discharging circuit is controlled according to the frequency control signal through the control signal output end of the frequency-dividing feedback circuit and the second control end of the charging and discharging circuit. The charging time of the charging and discharging circuit is controlled through the output end of the comparator and the first control end of the charging and discharging circuit, so that the oscillation circuit can output an oscillation signal corresponding to the frequency control signal, that is, the oscillation signal output for different frequency control signals is also different, thereby realizing the use of the same oscillation circuit to output oscillation signals of different frequencies. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0034] Figure 1 A schematic diagram of a signal generating circuit provided in an embodiment of the present application Figure 1 ;
[0035] Figure 2 A schematic diagram of the structure of an oscillation circuit provided in an embodiment of the present application;
[0036] Figure 3 A schematic diagram of the structure of a charging and discharging circuit provided in an embodiment of the present application;
[0037] Figure 4 A schematic diagram of the structure of a comparator provided in an embodiment of the present application;
[0038] Figure 5 A schematic diagram of the structure of a frequency division feedback circuit provided in an embodiment of the present application;
[0039] Figure 6 A schematic diagram of a signal generating circuit provided in an embodiment of the present application Figure 2 ;
[0040] Figure 7 A schematic diagram of a failure detection circuit provided in an embodiment of the present application;
[0041] Figure 8 A schematic diagram of the structure of a pulse generating circuit provided in an embodiment of the present application;
[0042] Fig. 9 A schematic diagram of a capacitor discharge ramp circuit provided in an embodiment of the present application;
[0043] Fig.10 A schematic diagram of the structure of a digital latch circuit provided in an embodiment of the present application. DETAILED DESCRIPTION
[0044] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.
[0045] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0046] In the description of the present application, it should be noted that if the terms "upper", "lower", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, or is the orientation or position relationship in which the product of the application is usually placed when used. It is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.
[0047] In addition, the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0048] It should be noted that, in the absence of conflict, the features in the embodiments of the present application may be combined with each other.
[0049] Figure 1 A schematic diagram of a signal generating circuit provided in an embodiment of the present application Figure 1 ,like Figure 1 As shown, the signal generating circuit may include: an oscillating circuit 100 , wherein the oscillating circuit 100 includes: a current source 101 , a charging and discharging circuit 102 , a comparator 103 , and a frequency division feedback circuit 104 .
[0050] The power supply end of the current source 101 is connected to the first end and the second end of the charge-discharge circuit 102 respectively, the first end of the charge-discharge circuit 102 is connected to the negative input end of the comparator 103, and the second end of the charge-discharge circuit 102 is connected to the positive input end of the comparator 103;
[0051] In addition, the output end of the comparator 103 is connected to the clock input end of the frequency division feedback circuit 104, and the output end of the comparator 103 is also connected to the first control end of the charge and discharge circuit 102. The control end of the frequency division feedback circuit 104 is used to input a frequency control signal, and the control signal output end of the frequency division feedback circuit 104 is connected to the second control end of the charge and discharge circuit 102. The oscillation signal output end of the frequency division feedback circuit 104 is used to output an oscillation signal corresponding to the frequency control signal.
[0052] In some embodiments, a frequency control signal is input to the control end of the frequency division feedback circuit 104, and the frequency control signal is a low-level signal; the second control end of the charge and discharge circuit 102 is controlled by the control signal output end of the frequency division feedback circuit 104, and the first control end of the charge and discharge circuit 102 is controlled by the output end of the comparator 103, so that the charge and discharge time of the charging circuit is shortened, and then the charge and discharge frequency of the charging circuit is increased, and the output end of the comparator 103 outputs a high-frequency clock signal to the clock input end of the frequency division feedback circuit 104, so that the oscillation signal output end of the frequency division feedback circuit 104 outputs a high-frequency oscillation signal.
[0053] In other embodiments, a frequency control signal is input to the control end of the frequency division feedback circuit 104, and the frequency control signal is a high-level signal; the second control end of the charge and discharge circuit 102 is controlled by the control signal output end of the frequency division feedback circuit 104, and the first control end of the charge and discharge circuit 102 is controlled by the output end of the comparator 103, so that the charge and discharge time of the charge and discharge circuit 102 becomes longer, and then the charge and discharge frequency of the charging circuit becomes lower, and the output end of the comparator 103 outputs a low-frequency clock signal to the clock input end of the frequency division feedback circuit 104, so that the oscillation signal output end of the frequency division feedback circuit 104 outputs a low-frequency oscillation signal.
[0054] Optionally, the oscillation signal may be a square wave signal. The oscillation signal output terminal of the frequency-dividing feedback circuit 104 in the oscillation circuit may output a high-frequency square wave signal or a low-frequency square wave signal.
[0055] It should be noted that the current source 101 can be referred to as I_CHG for short, and the number of the current sources 101 can be one, two, or any other number, which is not specifically limited in the embodiments of the present application.
[0056] In summary, an embodiment of the present application provides a signal generating circuit, which includes: an oscillation circuit, which includes: a current source 101, a charge and discharge circuit 102, a comparator 103, and a frequency division feedback circuit 104; the power supply end of the current source 101 is respectively connected to the first end of the charge and discharge circuit 102 and the second end of the charge and discharge circuit 102, the first end of the charge and discharge circuit 102 is connected to the negative input end of the comparator 103, and the second end of the charge and discharge circuit 102 is connected to the positive input end of the comparator 103; the output end of the comparator 103 is connected to the clock input end of the frequency division feedback circuit 104, and the output end of the comparator 103 is also connected to the first control end of the charge and discharge circuit 102, the control end of the frequency division feedback circuit 104 is used to input a frequency control signal, the control signal output end of the frequency division feedback circuit 104 is connected to the second control end of the charge and discharge circuit 102, and the oscillation signal output end of the frequency division feedback circuit 104 is used to output an oscillation signal corresponding to the frequency control signal. A frequency control signal is input to the control end of the frequency division feedback circuit 104, and the charging time of the charge and discharge circuit 102 is controlled according to the frequency control signal through the control signal output end of the frequency division feedback circuit 104 and the second control end of the charge and discharge circuit 102. The charging time of the charge and discharge circuit 102 is controlled through the output end of the comparator 103 and the first control end of the charge and discharge circuit 102, so that the oscillation circuit can output an oscillation signal corresponding to the frequency control signal, that is, the oscillation signal output for different frequency control signals is also different, thereby achieving the output of oscillation signals of different frequencies using the same oscillation circuit.
[0057] Optionally, Figure 2 A schematic diagram of the structure of an oscillator circuit provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, the charge and discharge circuit 102 includes: a first resistor 1021 , a second resistor 1022 , a first capacitor 1023 , a first switch device 1024 and a second switch device 1025 .
[0058] One end of the first resistor 1021 is the first end of the charge and discharge circuit 102.
[0059] One end is the second end of the charge and discharge circuit 102, and the control end of the first switch device 1024 is the second control end of the charge and discharge circuit 102; the other end of the first resistor 1021 is grounded through the second resistor 1022, and the other end of the first resistor 1021 is also grounded through the first switch device 1024; the other end of the first capacitor 1023 is grounded, and one end of the first capacitor 1023 is grounded through the second switch device 1025, and the control end of the second switch device 1025 is the first control end of the charge and discharge circuit 102.
[0060] Among them, VDD (positive voltage of power supply) is used to power two current sources 101.
[0061] In the embodiment of the present application, a current source 101 is used to charge the first capacitor 1023 and to supply power to one end of the first resistor 1021. A comparator 103 is used to compare the capacitor charging voltage at one end of the first capacitor 1023 and the resistor voltage drop at one end of the first resistor 1021. If the charging voltage is greater than the resistor voltage drop, the second switch device 1025 is controlled to close to discharge the first capacitor 1023. The output signal of the comparator 103 is flipped, causing the levels of some nodes in the frequency division feedback circuit 104 to be reversed. Because the capacitor discharges very quickly, the second switch device 1025 is disconnected, causing the first capacitor 1023 to start charging again. When the resistor charging voltage is greater than the resistor voltage drop next time, the output signal of the comparator 103 is flipped again, causing the levels of some nodes in the frequency division feedback circuit 104 to continue to be reversed, and then the oscillation signal output end of the frequency division feedback circuit 104 is used to output an oscillation signal corresponding to the frequency control signal.
[0062] In some embodiments, the control end of the frequency-dividing feedback circuit 104 inputs a frequency control signal, and the frequency control signal is a low-level signal; the control end of the first switch device 1024 is controlled by the control signal output end of the frequency-dividing feedback circuit 104, so that the first switch device 1024 is closed; when the first switch device 1024 is closed, the second resistor 1022 is short-circuited, and the current only flows through the first resistor 1021, and the resistance voltage drop input to the negative input end of the comparator 103 is reduced, that is, the threshold value referenced by the comparator 103 during comparison is reduced, so that the time required for charging the first capacitor 1023 is shorter, thereby making the charge and discharge frequency of the first capacitor 1023 higher. At the same time, the output of the comparator 103 will also affect the frequency-dividing feedback circuit 104, and finally the oscillation signal output end of the frequency-dividing feedback circuit 104 outputs a high-frequency oscillation signal.
[0063] In other embodiments, the control end of the frequency-dividing feedback circuit 104 inputs a frequency control signal, and the frequency control signal is a high-level signal; the control end of the first switch device 1024 is controlled by the control signal output end of the frequency-dividing feedback circuit 104, so that the first switch device 1024 is disconnected; when the first switch device 1024 is disconnected, the first resistor 1021 and the second resistor 1022 are connected in series, and the current flows through the first resistor 1021 and the second resistor 1022, and the resistance voltage drop input to the negative input end of the comparator 103 increases, that is, the threshold value referenced by the comparator 103 during comparison increases, so that the time required for charging the first capacitor 1023 is longer, thereby making the charge and discharge frequency of the first capacitor 1023 lower. At the same time, the output of the comparator 103 will also affect the frequency-dividing feedback circuit 104, and finally the oscillation signal output end of the frequency-dividing feedback circuit 104 outputs a low-frequency oscillation signal.
[0064] It is worth noting that the high-frequency oscillation signal can be a high-frequency square wave signal. According to the circuit principle of generating high-frequency square wave information, the negative input terminal voltage of the comparator 103 can be: V IN- =I·R, where R represents the resistance of the first resistor 1021. The output of the comparator 103 will be reversed when the charging voltage input at the positive input terminal reaches the input voltage at the negative input terminal of the comparator 103. The charging speed of the first capacitor 1023 is:
[0065]
[0066] Wherein, I represents the current flowing through the first capacitor 1023 , and C represents the capacitance of the first capacitor 1023 .
[0067] Then the solution can be obtained to obtain the frequency f of the high-frequency square wave signal osc , and the relationship between the capacitance C of the first capacitor 1023 and the resistance R of the first resistor 1021 is:
[0068]
[0069] Similarly, the frequency f of the low-frequency square wave signal can be calculated osc , and the relationship between the capacitance C of the first capacitor 1023 and the resistance R of the first resistor 1021 is:
[0070]
[0071] In practical applications, the first capacitor 1023 may be composed of a selectable capacitor array, and the frequency of the oscillation circuit is adjusted by adjusting the capacitance of the capacitor array.
[0072] Optionally, the first switch device 1024 and the second switch device 1025 may both be N-type MOS transistors (metal-oxide semiconductor field effect transistors). Figure 3 A schematic diagram of a charging and discharging circuit provided in an embodiment of the present application is shown in FIG. Figure 3As shown, one end of the first resistor 1021 is connected to the OUTN terminal, and the OUTN terminal is used to connect to the negative input terminal of the first comparator 103. The other end of the first resistor 1021 is grounded through the second resistor 1022. The other end of the first resistor 1021 is also grounded to VSS (circuit common ground terminal voltage) through the drain and source of the first switch device 1024. The gate of the first switch device 1024 is connected to the SEL1 terminal, and the SEL1 terminal is used to connect to the control signal output terminal of the frequency division feedback circuit 104; one end of the first capacitor 1023 is connected to the OUTP terminal, and the OUTP terminal is used to connect to the positive input terminal of the first comparator 103. The other end of the first capacitor 1023 is grounded to VSS. One end of the first capacitor 1023 is grounded through the drain and source of the second switch device 1025. The gate of the second switch device 1025 is connected to the CTR terminal, and the CTR terminal is used to connect to the output terminal of the comparator 103.
[0073] like Figure 3 As shown, the charge and discharge circuit 102 also includes: an eighth switch device 1026, a ninth switch device 1027, and a tenth switch device 1028. Among them, the eighth switch device 1026, the ninth switch device 1027, and the tenth switch device 1028 are all P-type MOS tubes. One end of the first resistor 1021 is also connected to the drain of the ninth switch device 1027, one end of the first capacitor 1023 is connected to the drain of the tenth switch device 1028, the gate of the eighth switch device 1026, the gate of the ninth switch device 1027, and the gate of the tenth switch device 1028 are connected, and the source of the eighth switch device 1026, the source of the ninth switch device 1027, and the source of the tenth switch device 1028 are all connected to VDD. The drain of the eighth switch device is connected to the PIBRI terminal, and the PIBRI terminal is used to input bias current.
[0074] It should be noted that the bias current at the PIBR1 end is provided by an external bias circuit, and the SEL1 end is connected to the control signal output end of the frequency division feedback circuit 104, and is used to select the output frequency mode of the oscillation circuit. When the signal at the SEL1 end is at a high level, the first switch device 1024 is turned on, which is a high frequency mode, and when the signal at the SEL1 end is at a low level, the first switch device 1024 is turned off, which is a low frequency mode. The signal at the CTR end can be a signal fed back after the output of the comparator 103 is buffered by two inverters. When the signal at the CTR end is at a high level, the second switch device 1025 is turned on, and the first capacitor 1023 is quickly discharged, and then the second switch device 1025 is turned off, and the first capacitor 1023 continues to charge.
[0075] Optionally, Figure 4 A schematic diagram of the structure of a comparator provided in an embodiment of the present application is shown in FIG. Figure 4As shown, the comparator 103 includes: an eleventh switch device 1031, a twelfth switch device 1032, a thirteenth switch device 1033, a fourteenth switch device 1034, a fifteenth switch device 1035, a sixteenth switch device 1036, a seventeenth switch device 1037, an eighteenth switch device 1038, a nineteenth switch device 1039, and a twentieth switch device 1040.
[0076] Among them, the source of the eleventh switch device 1031, the source of the twelfth switch device 1032, the source of the thirteenth switch device 1033, and the source of the fourteenth switch device 1034 are connected to the VDD terminal, the gate of the eleventh switch device 1031, the drain of the eleventh switch device 1031, the gate of the twelfth switch device 1032, the gate of the thirteenth switch device 1033, and the gate of the fourteenth switch device 1034 are connected to PIBR2, and the PIBR2 terminal is used to input bias current. The drain of the twelfth switch device 1032 is respectively connected to the source of the sixteenth switch device 1036 and the source of the seventeenth switch device 1037, and the drain of the twelfth switch device 1032 is also connected to the drain of the thirteenth switch device 1033 through the drain and source of the fifteenth switch device 1035, and the gate of the fifteenth switch device 1035 is connected to the SEL2 terminal.
[0077] In addition, the gate of the sixteenth switch device 1036 is connected to the VN terminal, and the gate of the seventeenth switch device 1037 is connected to the VP terminal. The VN terminal is the positive input terminal of the comparator 103, and the VP terminal is the negative input terminal of the comparator 103. The drain of the sixteenth switch device 1036 is connected to the VSS terminal through the drain and source of the eighteenth switch device 1038, the drain of the seventeenth switch device 1037 is connected to the VSS terminal through the drain and source of the nineteenth switch device 1039, and the gate of the eighteenth switch device 1038 is connected to the gate of the nineteenth switch device 1039. The drain of the eighteenth switch device 1038 is connected to the gate of the eighteenth switch device 1038, the drain of the nineteenth switch device 1039 is connected to the gate of the twentieth switch device 1040, the drain of the fourteenth switch device 1034 is connected to the VSS terminal through the drain and source of the twentieth switch device 1040, and the drain of the twentieth switch device 1040 is the output terminal of the comparator 103.
[0078] It should be noted that Figure 3The structure of the comparator 103 is a two-stage structure of a five-tube amplifier and a source follower. The mode selection SEL2 signal controls the bias current switch of the five tubes. In the high-frequency mode, the bias current switch is closed, and the bias current of the five tubes is 10I, where the bias current I is the bias current PIBR2 provided externally. In the low-frequency mode, the bias current switch is disconnected, and the bias current of the five tubes is 5I. For the two-stage operational amplifier, the larger the bias current, the larger the gain-bandwidth product. Among them, when the SEL1 signal is high, the SEL2 signal is low, and the fifteenth switch device 1035 is closed as the bias current switch, and the current is turned on.
[0079] Optionally, Figure 5 A structural diagram of a frequency division feedback circuit provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, the frequency division feedback circuit 104 includes: a first sub-frequency division feedback circuit 1041, a second sub-frequency division feedback circuit 1042, a third sub-frequency division feedback circuit 1043, and an OR gate circuit 1044;
[0080] The clock input terminal of the first sub-frequency division feedback circuit 1041 is the clock input terminal of the frequency division feedback circuit 104; the control output terminal of the first sub-frequency division feedback circuit 1041 is connected to the control terminal of the first sub-frequency division feedback circuit 1041, and the output terminal of the first sub-frequency division feedback circuit 1041 is respectively connected to the clock input terminal of the second sub-frequency division feedback circuit 1042 and the clock input terminal of the third sub-frequency division feedback circuit 1043;
[0081] The control end of the second sub-frequency division feedback circuit 1042 is the control end of the frequency division feedback circuit 104; the control signal output end of the second sub-frequency division feedback circuit 1042 is the control signal output end of the frequency division feedback circuit 104; the output end of the second sub-frequency division feedback circuit 1042 is connected to the first input end of the OR gate circuit 1044;
[0082] The output end of the third sub-frequency division feedback circuit 1043 is connected to the second input end of the OR gate circuit 1044, the reset end of the third sub-frequency division feedback circuit 1043 is connected to the reset signal output end of the second sub-frequency division feedback circuit 1042, and the output end of the third sub-frequency division feedback circuit 1043 is connected to the control end of the third sub-frequency division feedback circuit 1043; the output end of the OR gate circuit 1044 is the oscillation signal output end of the frequency division feedback circuit 104.
[0083] In the embodiment of the present application, a frequency control signal is input to the control end of the second sub-frequency division feedback circuit 1042, and the frequency control signal is a low-level signal. The third sub-frequency division feedback circuit 1043 is reset by the second sub-frequency division feedback circuit 1042, and the third sub-frequency division feedback circuit 1043 does not play a role in frequency division. In this way, the output end of the OR gate circuit 1044 can output a high-frequency oscillation signal.
[0084] In addition, a frequency control signal is input to the control end of the second sub-frequency division feedback circuit 1042, and the frequency control signal is a high-level signal. The third sub-frequency division feedback circuit 1043 is controlled to work normally through the second sub-frequency division feedback circuit 1042, and the third sub-frequency division feedback circuit 1043 plays a role of frequency division, so that the output end of the OR gate circuit 1044 can output a low-frequency oscillation signal.
[0085] Alternatively, if Figure 2 As shown, the first sub-frequency division feedback circuit 1041 includes: a first trigger 1041a and a first inverter 1041b;
[0086] The clock input terminal of the first trigger 1041a is the clock input terminal of the frequency division feedback circuit 104; the control output terminal of the first trigger 1041a is the control output terminal of the first sub-frequency division feedback circuit 1041; the output terminal of the first trigger 1041a is connected to the input terminal of the first inverter 1041b, and the output terminal of the first inverter 1041b is the output terminal of the first sub-frequency division feedback circuit 1041.
[0087] In the embodiments of the present application, Figure 2 As shown, the clock input terminal of the first flip-flop 1041a can be called the Clk terminal, the control terminal of the first flip-flop 1041a can be called the D terminal, the output terminal of the first flip-flop 1041a can be called the Q terminal, and the control output terminal of the first flip-flop 1041a can be called end.
[0088] Among them, the first trigger 1041a The terminal is connected to the D terminal of the first trigger 1041a.
[0089] Alternatively, if Figure 2 As shown, the second sub-frequency division feedback circuit 1042 includes: a second trigger 1042a, a second inverter 1042b and an AND gate circuit 1042c;
[0090] The clock input terminal of the second flip-flop 1042a is the clock input terminal of the second sub-frequency division feedback circuit 1042, the control terminal of the second flip-flop 1042a is the control terminal of the second sub-frequency division feedback circuit 1042, the output terminal of the second flip-flop 1042a is the reset signal output terminal of the second sub-frequency division feedback circuit 1042, and the output terminal of the second flip-flop 1042a is connected to the input terminal of the second inverter 1042b; the output terminal of the second inverter 1042b is the control signal output terminal of the second sub-frequency division feedback circuit 1042, and is connected to the first input terminal of the AND gate circuit 1042c;
[0091] The output end of the first sub-frequency division feedback circuit 1041 is connected to the second input end of the AND gate circuit 1042 c , and the output end of the AND gate circuit 1042 c is the output end of the second sub-frequency division feedback circuit 1042 .
[0092] Among them, Figure 2 As shown, the clock input terminal of the second trigger 1042a can be called the Clk terminal of the second trigger 1042a, the control terminal of the second trigger 1042a can be called the D terminal of the second trigger 1042a, and the output terminal of the second trigger 1042a can be called the Q terminal of the second trigger 1042a.
[0093] Alternatively, if Figure 2 As shown, the third sub-frequency division feedback circuit 1043 includes: a third trigger 1043a, a third inverter 1043b, a fourth inverter 1043c and a fifth inverter 1043d, including:
[0094] The clock input terminal of the third flip-flop 1043a is the clock input terminal of the third sub-frequency division feedback circuit 1043, the reset terminal of the third flip-flop 1043a is the reset terminal of the third sub-frequency division feedback circuit 1043, and the output terminal of the third flip-flop 1043a is connected to the input terminal of the fifth inverter 1043d through the fourth inverter 1043c;
[0095] The output end of the fifth inverter 1043d is the output end of the third sub-frequency division feedback circuit 1043, and the control end of the third trigger 1043a is the control end of the third sub-frequency division feedback circuit 1043; the output end of the fifth inverter 1043d is connected to the input end of the third inverter 1043b, and the output end of the third inverter 1043b is connected to the control end of the third trigger 1043a.
[0096] Among them, Figure 2 As shown, the clock input terminal of the third trigger 1043a can be called the Clk terminal of the third trigger 1043a, the control terminal of the third trigger 1043a can be called the D terminal of the third trigger 1043a, and the output terminal of the third trigger 1043a can be called the Q terminal of the second trigger 1042a.
[0097] It should be noted that the Q end of the second trigger 1042a outputs a low level to control the reset of the third trigger 1043a, and the oscillation circuit outputs a high-frequency oscillation signal. The Q end of the second trigger 1042a outputs a high level to control the normal operation of the third trigger 1043a, and the oscillation circuit outputs a low-frequency oscillation signal. The resistance value of the first resistor 1021 can be R, and the resistance value of the second resistor 1022 can be 3R. When the third trigger 1043a works normally, the frequency output by the third trigger 1043a is half of the output frequency of the first trigger 1041a.
[0098] Optionally, Figure 6 A schematic diagram of a signal generating circuit provided in an embodiment of the present application Figure 2 ,like Figure 6 As shown, the signal generating circuit further includes: a failure detection circuit 200 .
[0099] The oscillation signal output end of the frequency division feedback circuit 104 is connected to the input end of the failure detection circuit 200. The failure detection circuit 200 is used to perform frequency failure detection on the oscillation signal. The output end of the failure detection circuit 200 is used to output a detection signal for the oscillation signal. The detection signal is used to indicate whether the oscillation signal has a frequency failure.
[0100] It should be noted that, when the frequency of the oscillation signal is normal, the output end of the failure detection circuit 200 outputs a detection signal for the oscillation signal, and the detection signal is a low-level signal, which indicates that the frequency of the oscillation signal output by the oscillation circuit is normal, that is, the oscillation signal output by the oscillation circuit is valid. When the frequency of the oscillation signal is too low, the output end of the failure detection circuit 200 outputs a detection signal for the oscillation signal, and the detection signal is a high-level signal, and the low-level signal indicates that the frequency of the oscillation signal output by the oscillation circuit is too low, that is, the oscillation signal output by the oscillation circuit is invalid. Thus, the frequency detection function of the oscillation circuit can be realized by the failure detection circuit 200.
[0101] Optionally, Figure 7 A schematic diagram of a failure detection circuit provided in an embodiment of the present application is shown in FIG. Figure 7 As shown, the failure detection circuit 200 includes: a pulse generating circuit 201, a capacitor discharge ramp circuit 202 and a digital latch circuit 203;
[0102] Among them, the input end of the pulse generating circuit 201 is the input end of the failure detection circuit 200, the output end of the pulse generating circuit 201 is connected to the input end of the capacitor discharge ramp circuit, the output end of the capacitor discharge ramp circuit is connected to the input end of the digital latch circuit 203, and the output end of the digital latch circuit 203 is the output end of the failure detection circuit 200.
[0103] In some embodiments, the oscillation circuit outputs an oscillation signal to the pulse generating circuit 201, the pulse generating circuit 201 generates a pulse signal based on the oscillation signal, the pulse generating circuit 201 outputs the pulse signal to the capacitor discharge ramp circuit, the capacitor discharge ramp circuit generates a ramp signal based on the pulse signal, the capacitor discharge ramp circuit 202 outputs a ramp signal to the digital latch circuit 203, and the digital latch circuit 203 generates a detection signal based on the ramp signal.
[0104] The ramp signal may be a triangular wave signal.
[0105] Optionally, Figure 8 A schematic diagram of a pulse generating circuit provided in an embodiment of the present application is shown in FIG. Figure 8 As shown, the pulse generating circuit 201 includes: a sixth inverter 2011, a seventh inverter 2012, a third resistor 2013, an eighth inverter 2014, a first NAND gate 2015, a fourth resistor 2016, a ninth inverter 2017, a second NAND gate 2018, a fourth capacitor 2019, and a fifth capacitor 2020.
[0106] like Figure 8 As shown, the input end of the sixth inverter 2011 is connected to the OSC_OUT end, wherein the OSC_OUT end is the oscillation signal output end of the frequency division feedback circuit 104; the output end of the sixth inverter 2011 is respectively connected to the input end of the seventh inverter 2012 and one end of the fourth resistor 2016, the output end of the seventh inverter 2012 is connected to the input end of the eighth inverter 2014 through the third resistor 2013, the output end of the seventh inverter 2012 is also connected to the fourth capacitor 2019 through the third resistor 2013, the output end of the seventh inverter 2012 and the output end of the eighth inverter 2014 are both connected to the input end of the first NAND gate circuit 2015, and the output end of the first NAND gate circuit 2015 is represented by V o1 .
[0107] In addition, the other end of the fourth resistor 2016 is grounded through the fifth capacitor 2020, and the other end of the fourth resistor 2016 is also connected to the input end of the ninth inverter 2017. The output end of the ninth inverter 2017 and one end of the fourth resistor 2016 are connected to the input end of the second NAND gate circuit 2018. The output end of the second NAND gate circuit 2018 is represented by V o2 The first NAND gate circuit 2015 outputs a first pulse signal, and the second NAND gate circuit 2018 outputs a second pulse signal.
[0108] It is worth noting that the main delay of the pulse generating circuit 201 is achieved through resistor and capacitor delay, and the pulse signal is obtained after being reversed by the inverter and processed by the NAND gate. The pulse signal width is the resistor and capacitor delay time, and the time difference between the two pulse signals is half a cycle of the square wave signal output by the oscillation circuit minus the pulse width.
[0109] Optionally, Fig. 9 A schematic diagram of a capacitor discharge ramp circuit provided in an embodiment of the present application is shown in FIG. Fig. 9 As shown, the capacitor discharge ramp circuit includes: a second capacitor 2021, a third capacitor 2022, a third switch device 2023, a fourth switch device 2024, a fifth switch device 2025, a sixth switch device 2026, and a seventh switch device 2027;
[0110] Among them, the input end of the capacitor discharge ramp circuit includes: the control end of the third switch device 2023 and the control end of the fourth switch device 2024, the first end of the third switch device 2023 and the first end of the fourth switch device 2024 are both connected to the VDD power supply voltage end, and the output end of the capacitor discharge ramp circuit includes: the second end of the third switch device 2023 and the second end of the fourth switch device 2024; one end of the second capacitor 2021 and one end of the third capacitor 2022 are both connected to the power supply voltage end, the other end of the second capacitor 2022 is connected to the second end of the third switch device 2023, and the other end of the third capacitor 2022 is connected to the second end of the fourth switch device 2024.
[0111] The control end of the fifth switch device 2025, the first end of the fifth switch device 2025, the control end of the sixth switch device 2026, and the control end of the seventh switch device 2027 are respectively used to receive the bias current input through the NIBR end; the second ends of the five switch devices are grounded, the first end of the sixth switch device 2026 is connected to the second end of the third switch device 2023, and the second end of the sixth switch device 2026 is grounded; the first end of the seventh switch device 2027 is connected to the second end of the fourth switch device 2024, and the second end of the seventh switch device 2027 is grounded VSS.
[0112] Among them, Fig. 9 As shown, the third switch device 2023 and the fourth switch device 2024 are P-type MOS transistors, and the fifth switch device, the sixth switch device 2026, and the seventh switch device 2027 are N-type MOS transistors. The control end of the third switch device 2023 and the control end of the fourth switch device 2024 are gate electrodes, the first end of the third switch device 2023 and the first end of the fourth switch device 2024 are source electrodes, and the second end of the third switch device 2023 and the second end of the fourth switch device 2024 are drain electrodes. In addition, the control end of the fifth switch device 2025, the control end of the sixth switch device 2026, and the control end of the seventh switch device 2027 are gate electrodes, the first end of the fifth switch device 2025, the first end of the sixth switch device 2026, and the first end of the seventh switch device 2027 are drain electrodes, and the second end of the fifth switch device 2025, the second end of the sixth switch device 2026, and the second end of the seventh switch device 2027 are source electrodes.
[0113] It should be noted that the control end of the third switch device 2023 is connected to the VN end, and the control end of the fourth switch device 2024 is connected to the VP end; the VN end is connected to the V o1 The pulse generating circuit 201 is connected so that the first pulse signal is input to the control terminal of the third switch device 2023; the VP terminal is connected to the V o2The pulse generating circuit 201 is connected to the control terminal of the fourth switch device 2024 so that the second pulse signal is input to the control terminal of the fourth switch device 2024. The drain of the third switch device 2023 is connected to the OUTN terminal, and the first ramp signal is output through the OUTN terminal; the drain of the fourth switch device 2024 is connected to the OUTP terminal, and the second ramp signal is output through the OUTP terminal.
[0114] In the embodiment of the present application, the two-terminal output of the pulse generating signal is connected to the two input terminals VN and VP of the capacitor discharge ramp circuit. For the upper plates of the second capacitor 2021 and the third capacitor 2022, they are directly connected to the working voltage. For the lower plates of the second capacitor 2021 and the third capacitor 2022, there are two paths, one of which is connected to the working voltage through the input P tube, and the other is connected to the ground through the N tube. When the gate terminal of the input P tube is at a low level, the on-resistance of the P tube is very small, and the lower plate can be quickly charged to the working voltage. When the gate terminal of the P tube is at a high level, the lower plate has only one path to the ground, and there is also an on-resistance of the N tube on this path. The current size on this path is determined by the current size of the N tube current mirror, and the discharge is slowed down.
[0115] It is worth noting that the OUTN terminal quickly jumps to a high level at the falling edge of the input signal at the VN terminal, and starts to discharge slowly at the rising edge of the input signal. The same applies to the OUTP terminal. The frequency of the oscillation circuit determines the time from the start of slow discharge to the next jump to a high level for the OUTP terminal and the OUTN terminal. Since the second capacitor 2021 and the third capacitor 2022 are fixed in size, it can also be said that the oscillation circuit frequency and the input pulse signal width determine the level flip point from the start of slow discharge to the next jump to a high level for the OUTP terminal and the OUTN terminal. This level flip point decreases as the oscillation circuit frequency decreases. Under normal conditions, the oscillation circuit frequency can ensure that the level flip point remains at a higher potential, and the output of the NAND gate of the next stage remains at a low level. If the oscillation circuit frequency is too low and the level flip point is at a lower potential, the output of the NAND gate of the next stage remains at a high level, and finally outputs a high level. The frequency detection function of the oscillation circuit is realized.
[0116] Optionally, Fig.10 A schematic diagram of a digital latch circuit provided in an embodiment of the present application is shown in FIG. Fig.10 As shown, the digital latch circuit 203 includes: a tenth inverter 2031, a first OR gate circuit 2032, an eleventh inverter 2033, a first AND gate circuit 2034, a second OR gate circuit 2035, a first Schmitt trigger 2036, a second Schmitt trigger 2037, a NAND gate circuit 2038, a third OR gate circuit 2039, and a twelfth inverter 2040.
[0117] Among them, the input end of the tenth inverter 2031 is connected to the EN end (enable end), the output end of the tenth inverter 2031 is connected to the first input end of the first OR gate circuit 2032, the output end of the first OR gate circuit 2032 is connected to the input end of the eleventh inverter 2033, the output end of the eleventh inverter 2033 is connected to the first input end of the first AND gate circuit 2034, the EN end is also connected to the second input end of the first AND gate circuit 2034, the output end of the first AND gate circuit 2034 is connected to the first input end of the second OR gate circuit 2035, the output end of the second OR gate circuit 2035 is connected to the OUT end, and the OUT end outputs the detection signal.
[0118] In addition, the IN1 terminal is connected to the input terminal of the first Schmitt trigger 2036, the IN2 terminal is connected to the input terminal of the first Schmitt trigger 2036, the IN1 terminal is used to connect to the OUTN terminal in the capacitor discharge ramp circuit, the IN2 terminal is used to connect to the OUTP terminal in the capacitor discharge ramp circuit, the output terminal of the first Schmitt trigger 2036 and the output terminal of the second Schmitt trigger 2037 are respectively connected to the first input terminal and the second input terminal of the NAND gate circuit 2038, the output terminal of the NAND gate circuit 2038 is respectively connected to the first input terminal of the third OR gate circuit 2039, the second input terminal of the third OR gate circuit 2039 is connected to the output terminal of the eleventh inverter 2033, the output terminal of the third OR gate circuit 2039 is connected to the input terminal of the twelfth inverter 2040, the output terminal of the twelfth inverter 2040 is connected to the second input terminal of the first OR gate circuit 2032, and the output terminal of the NAND gate circuit 2038 is connected to the second input terminal of the second OR gate circuit 2035.
[0119] In the embodiment of the present application, the measurement frequency of the failure detection module of the oscillation circuit is mainly determined by the bias current input to the NIBR terminal in the capacitor discharge ramp circuit and the second capacitor 2021 and the third capacitor 2022 in the main circuit. The larger the bias current, the smaller the capacitance, the faster the discharge speed, and the higher the oscillator frequency threshold detected.
[0120] In summary, the embodiment of the present application provides a signal generating circuit, wherein a frequency control signal is input to the control end of the frequency division feedback circuit 104, and the charging time of the charge and discharge circuit 102 is controlled according to the frequency control signal through the control signal output end of the frequency division feedback circuit 104 and the second control end of the charge and discharge circuit 102, and the charging time of the charge and discharge circuit 102 is controlled through the output end of the comparator 103 and the first control end of the charge and discharge circuit 102, so that the oscillation circuit can output an oscillation signal corresponding to the frequency control signal, that is, the oscillation signals output for different frequency control signals are also different, thereby realizing the use of the same oscillation circuit to output oscillation signals of different frequencies.
[0121] By adjusting the resistance values of the first resistor 1021 and the second resistor 1022, the oscillation circuit can have two modes, high frequency and low frequency. In the high frequency mode, the oscillation circuit can output a high frequency oscillation signal, and in the low frequency mode, the oscillation circuit can output a low frequency oscillation signal. The oscillation circuit can be based on an RC relaxation oscillator, and the charging voltage reversal threshold in the charge and discharge circuit 102 is changed by a control signal to generate square wave signals of different frequencies, and the charge and discharge reversal threshold is achieved by changing the resistance value on the current path.
[0122] Furthermore, the oscillation signal is processed into a pulse signal with a phase difference of about half a cycle, and the discharge path of the capacitor is controlled by the pulse signal to realize the frequency failure detection of the oscillator. When the frequency of the oscillation signal is too low, the failure detection circuit 200 jumps.
[0123] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A signal generating circuit, characterized in that: The signal generating circuit comprises: an oscillating circuit, and the oscillating circuit comprises: a current source, a charging and discharging circuit, a comparator, and a frequency dividing feedback circuit; The power supply end of the current source is connected to the first end of the charge-discharge circuit and the second end of the charge-discharge circuit respectively, the first end of the charge-discharge circuit is connected to the negative input end of the comparator, and the second end of the charge-discharge circuit is connected to the positive input end of the comparator; The output end of the comparator is connected to the clock input end of the frequency division feedback circuit, and the output end of the comparator is also connected to the first control end of the charge and discharge circuit. The control end of the frequency division feedback circuit is used to input a frequency control signal, and the control signal output end of the frequency division feedback circuit is connected to the second control end of the charge and discharge circuit. The oscillation signal output end of the frequency division feedback circuit is used to output an oscillation signal corresponding to the frequency control signal.
2. The circuit according to claim 1, characterized in that The charging and discharging circuit comprises: a first resistor, a second resistor, a first capacitor, a first switching device and a second switching device; Wherein, one end of the first resistor is the first end of the charge-discharge circuit, one end of the first capacitor is the second end of the charge-discharge circuit, and the control end of the first switch device is the second control end of the charge-discharge circuit; the other end of the first resistor is grounded through the second resistor, and the other end of the first resistor is also grounded through the first switch device; The other end of the first capacitor is grounded, one end of the first capacitor is grounded through the second switch device, and the control end of the second switch device is the first control end of the charge and discharge circuit.
3. The circuit according to claim 1, characterized in that The frequency division feedback circuit comprises: a first sub-frequency division feedback circuit, a second sub-frequency division feedback circuit, a third sub-frequency division feedback circuit, and an OR gate circuit; The clock input terminal of the first sub-frequency division feedback circuit is the clock input terminal of the frequency division feedback circuit; the control output terminal of the first sub-frequency division feedback circuit is connected to the control terminal of the first sub-frequency division feedback circuit, and the output terminal of the first sub-frequency division feedback circuit is respectively connected to the clock input terminal of the second sub-frequency division feedback circuit and the clock input terminal of the third sub-frequency division feedback circuit; The control end of the second sub-frequency division feedback circuit is the control end of the frequency division feedback circuit; the control signal output end of the second sub-frequency division feedback circuit is the control signal output end of the frequency division feedback circuit; the output end of the second sub-frequency division feedback circuit is connected to the first input end of the OR gate circuit; The output end of the third sub-frequency division feedback circuit is connected to the second input end of the OR gate circuit, the reset end of the third sub-frequency division feedback circuit is connected to the reset signal output end of the second sub-frequency division feedback circuit, and the output end of the third sub-frequency division feedback circuit is connected to the control end of the third sub-frequency division feedback circuit; the output end of the OR gate circuit is the oscillation signal output end of the frequency division feedback circuit.
4. The circuit according to claim 3, characterized in that The first sub-frequency division feedback circuit comprises: a first trigger and a first inverter; The clock input end of the first trigger is the clock input end of the frequency division feedback circuit; the control output end of the first trigger is the control output end of the first sub-frequency division feedback circuit; the output end of the first trigger is connected to the input end of the first inverter, and the output end of the first inverter is the output end of the first sub-frequency division feedback circuit.
5. The circuit according to claim 3, characterized in that The second sub-frequency division feedback circuit includes: a second trigger, a second inverter and an AND gate circuit; The clock input terminal of the second flip-flop is the clock input terminal of the second sub-frequency division feedback circuit, the control terminal of the second flip-flop is the control terminal of the second sub-frequency division feedback circuit, the output terminal of the second flip-flop is the reset signal output terminal of the second sub-frequency division feedback circuit, and the output terminal of the second flip-flop is connected to the input terminal of the second inverter; the output terminal of the second inverter is the control signal output terminal of the second sub-frequency division feedback circuit, and is connected to the first input terminal of the AND gate circuit; The output end of the first sub-frequency division feedback circuit is connected to the second input end of the AND gate circuit, and the output end of the AND gate circuit is the output end of the second sub-frequency division feedback circuit.
6. The circuit according to claim 3, characterized in that The third sub-frequency division feedback circuit includes: a third trigger, a third inverter, a fourth inverter and a fifth inverter, including: The clock input terminal of the third trigger is the clock input terminal of the third sub-frequency division feedback circuit, the reset terminal of the third trigger is the reset terminal of the third sub-frequency division feedback circuit, and the output terminal of the third trigger is connected to the input terminal of the fifth inverter through the fourth inverter; The output end of the fifth inverter is the output end of the third sub-frequency division feedback circuit, and the control end of the third trigger is the control end of the third sub-frequency division feedback circuit; the output end of the fifth inverter is connected to the input end of the third inverter, and the output end of the third inverter is connected to the control end of the third trigger.
7. The circuit according to claim 1, characterized in that The signal generating circuit further comprises: a failure detection circuit; The oscillation signal output end of the frequency division feedback circuit is connected to the input end of the failure detection circuit, the failure detection circuit is used to perform frequency failure detection on the oscillation signal, and the output end of the failure detection circuit is used to output a detection signal for the oscillation signal, and the detection signal is used to indicate whether the oscillation signal has a frequency failure.
8. The circuit according to claim 7, characterized in that The failure detection circuit includes: a pulse generating circuit, a capacitor discharge ramp circuit and a digital latch circuit; The input end of the pulse generating circuit is the input end of the failure detection circuit, the output end of the pulse generating circuit is connected to the input end of the capacitor discharge ramp circuit, the output end of the capacitor discharge ramp circuit is connected to the input end of the digital latch circuit, and the output end of the digital latch circuit is the output end of the failure detection circuit.
9. The circuit according to claim 8, characterized in that The capacitor discharge ramp circuit includes: a second capacitor, a third capacitor, a third switch device, a fourth switch device, a fifth switch device, a sixth switch device, and a seventh switch device; The input end of the capacitor discharge ramp circuit includes: the control end of the third switch device and the control end of the fourth switch device, the first end of the third switch device and the first end of the fourth switch device are both connected to the power supply voltage end, and the output end of the capacitor discharge ramp circuit includes: the second end of the third switch device and the second end of the fourth switch device; one end of the second capacitor and one end of the third capacitor are both connected to the power supply voltage end, the other end of the second capacitor is connected to the second end of the third switch device, and the other end of the third capacitor is connected to the second end of the fourth switch device; The control end of the fifth switch device, the first end of the fifth switch device, the control end of the sixth switch device, and the control end of the seventh switch device are respectively used to receive input bias current; the second end of the fifth switch device is grounded, the first end of the sixth switch device is connected to the second end of the third switch device, and the second end of the sixth switch device is grounded; the first end of the seventh switch device is connected to the second end of the fourth switch device, and the second end of the seventh switch device is grounded.
10. The circuit according to claim 9, characterized in that The third switch device and the fourth switch device are P-type metal-oxide semiconductor field effect transistors (MOS) tubes, and the fifth switch device, the sixth switch device and the seventh switch device are N-type MOS tubes.