Digital phased array circuit

Abstract

The invention provides a digital phased array circuit, which comprises a radio frequency front end module, a radio frequency transceiving channel module, a data conversion module and a beam forming module, wherein the radio frequency front-end module is packaged on a chip corresponding to the radio frequency front-end module in a system-level manner; at least one target module in the data conversion module and the beam forming module is respectively integrated on respective corresponding first chips, other modules except the target module are combined and integrated on a second chip, and the power consumption of the first chip is lower than that of the second chip. Therefore, the target module can be monolithically integrated on the first chip, and the other modules can be combined and integrated on the second chip, so that the advantages and capabilities of different processes can be utilized, the circuit complexity of the target module can be reduced, and the cost performance and the economic added value can be improved; and system-level packaging and monolithic integration are beneficial to realizing miniaturization and low power consumption of the digital phased array circuit, and large-scale application and popularization of a large-scale digital phased array are facilitated.

Description

Technical Field

[0001] The present disclosure relates to the intersection of communication technology and integrated circuits, and in particular to a digital phased array circuit. Background Art

[0002] At present, phased array technology has been widely used in radar, communication and other fields. Digital phased array circuit refers to phased array circuit based on digital beamforming, which has the advantage of flexible beam generation. However, digital phased array circuits in related technologies have the problems of high power consumption and high cost, which cannot meet the application of digital phased array antennas in power-constrained environments. Summary of the invention

[0003] The present disclosure aims to solve one of the technical problems in the related art at least to some extent.

[0004] To this end, the first aspect of the present disclosure proposes a digital phased array circuit, including: an RF front-end module, an RF transceiver channel module, a data conversion module and a beamforming module; wherein the RF front-end module is system-level packaged on its corresponding chip; the data conversion module and at least one target module in the beamforming module are respectively integrated on their respective corresponding first chips, and the remaining modules except the target module are combined and integrated on a second chip, and the power consumption of the first chip is lower than that of the second chip.

[0005] The digital phased array circuit of the disclosed embodiment includes an RF front-end module, an RF transceiver channel module, a data conversion module and a beamforming module, wherein the RF front-end module is system-level packaged on its corresponding chip, and at least one target module in the data conversion module and the beamforming module is respectively integrated on the first chip corresponding to each other, and the remaining modules except the target module are integrated on the second chip, and the power consumption of the first chip is lower than that of the second chip. Therefore, the target module can be integrated on the first chip on a single chip, and the remaining modules can be integrated on the second chip on a single chip, which helps to utilize the advantages of different processes, helps to reduce the circuit complexity of the target module, and improves the cost-effectiveness and economic added value. The system-level packaging and monolithic integration help to achieve the miniaturization and low power consumption of the digital phased array circuit, which is convenient for the large-scale application and popularization of large-scale digital phased arrays.

[0006] In addition, the digital phased array circuit proposed in the above embodiment of the present disclosure may also have the following additional technical features:

[0007] In one embodiment of the present disclosure, the RF transceiver channel module includes a multi-channel receiver and a multi-channel transmitter, wherein the multi-channel receiver is integrated from multiple receiving channels, and the multi-channel transmitter is integrated from multiple transmitting channels.

[0008] In one embodiment of the present disclosure, the multi-channel receiver and the multi-channel transmitter are respectively integrated on their corresponding chips, or the multi-channel receiver and the multi-channel transmitter are combined and integrated on the same chip.

[0009] In one embodiment of the present disclosure, the multi-channel receiver and the multi-channel transmitter are of zero intermediate frequency architecture.

[0010] In one embodiment of the present disclosure, any receiving channel includes a low noise amplifier and a first voltage amplifier, and the gain of the low noise amplifier is greater than the gain of the first voltage amplifier; any transmitting channel includes a power amplifier and a second voltage amplifier, and the gain of the power amplifier is greater than the gain of the second voltage amplifier.

[0011] In one embodiment of the present disclosure, for any transceiver channel, the any transceiver channel includes a RF domain circuit and an analog domain circuit, the gain of the analog domain circuit is greater than the gain of the RF domain circuit, wherein the any transceiver channel is any receiving channel or any transmitting channel.

[0012] In one embodiment of the present disclosure, the data conversion module includes a multi-channel analog-to-digital converter, a multi-channel digital-to-analog converter, a serializer and a deserializer. The multi-channel analog-to-digital converter and the serializer are integrated on a third chip, and the multi-channel digital-to-analog converter and the deserializer are integrated on a fourth chip. The third chip and the fourth chip are the same chip or different chips.

[0013] In one embodiment of the present disclosure, the sample-and-hold circuit in the data conversion module is a non-large capacitor architecture.

[0014] In one embodiment of the present disclosure, the beamforming module is an application specific integrated circuit ASIC.

[0015] In one embodiment of the present disclosure, the beamforming module is a multi-voltage domain architecture and / or a multi-clock domain architecture.

[0016] Additional aspects and advantages of the present disclosure will be given in part in the following description and in part will be obvious from the following description or learned through practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and / or additional aspects and advantages of the present disclosure will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0018] Figure 1 A schematic diagram of the structure of a digital phased array circuit provided by an embodiment of the present disclosure;

[0019] Figure 2A schematic diagram of the structure of a radio frequency front-end module provided in an embodiment of the present disclosure;

[0020] Figure 3 A schematic diagram of the structure of another radio frequency front-end module provided in an embodiment of the present disclosure;

[0021] Figure 4 A schematic diagram of the structure of a radio frequency transceiver channel module provided in an embodiment of the present disclosure;

[0022] Figure 5 A schematic diagram of the structure of a multi-channel receiver provided by an embodiment of the present disclosure;

[0023] Figure 6 A schematic diagram of the structure of a multi-channel transmitter provided by an embodiment of the present disclosure;

[0024] Figure 7 A schematic diagram of the structure of another digital phased array circuit provided by an embodiment of the present disclosure; DETAILED DESCRIPTION

[0025] Embodiments of the present disclosure are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0026] The digital phased array circuit according to the embodiment of the present disclosure is described below with reference to the accompanying drawings.

[0027] Figure 1 A schematic diagram of the structure of a digital phased array circuit provided in an embodiment of the present disclosure.

[0028] like Figure 1 As shown, the digital phased array circuit 100 of the embodiment of the present disclosure includes a radio frequency front-end module 101, a radio frequency transceiver channel module 102, a data conversion module 103 and a beamforming module 104. The radio frequency front-end module 101 is SIP (System In A Package) on its corresponding chip, at least one target module in the data conversion module 103 and the beamforming module 104 is respectively integrated on the first chip corresponding to each other, and the remaining modules except the target module are integrated on the second chip, and the power consumption of the first chip is lower than that of the second chip.

[0029] It should be noted that power consumption refers to the amount of energy consumed by a device per unit time.

[0030] It should be noted that the integration methods of the RF front-end module 101, the RF transceiver channel module 102, the data conversion module 103 and the beamforming module 104 may include the following:

[0031] Mode 1: The data conversion module 103 is integrated on the first chip, and the RF front-end module 101, the RF transceiver channel module 102, and the beamforming module 104 are integrated on the second chip.

[0032] It can be understood that the target module in Mode 1 only includes the data conversion module 103 .

[0033] Mode 2: The beamforming module 104 is integrated on the first chip, and the RF front-end module 101, the RF transceiver channel module 102, and the data conversion module 103 are integrated on the second chip.

[0034] It can be understood that in mode 2, the target module only includes the beamforming module 104 .

[0035] Mode 3: The data conversion module 103 and the beamforming module 104 are respectively integrated on their corresponding first chips, and the RF front-end module 101 and the RF transceiver channel module 102 are integrated on the second chip.

[0036] It is understandable that continuing Figure 1 For example, the target module in mode 3 includes a data conversion module 103 and a beamforming module 104 .

[0037] It should be noted that the RF front-end module 101 is used to complete the low-noise amplification and power amplification of the transmitting and receiving antenna array element signals, the RF transceiver channel module 102 is used to complete the conversion between the analog zero intermediate frequency and the corresponding carrier radio frequency, the data conversion module 103 is used to complete the conversion between the analog zero intermediate frequency and the digital signal, and the beamforming module 104 is used to complete the beam synthesis and diversity of each array receiving antenna signal or each array element to be transmitted in the digital domain.

[0038] It should be noted that there are no excessive limitations on the specific structures of the RF front-end module 101 , the RF transceiver channel module 102 , the data conversion module 103 and the beamforming module 104 .

[0039] In one embodiment, if Figure 2 As shown, if the working mode of the digital phased array circuit 100 is TDD (Time Division Duplexing), the RF front-end module 101 includes a single-pole double-throw switch, a power amplifier and a low-noise amplifier.

[0040] In one embodiment, if Figure 3As shown, if the working mode of the digital phased array circuit 100 is FDD (Frequency Division Duplexing), the RF front-end module 101 includes a duplexer, a power amplifier and a low noise amplifier.

[0041] In one implementation, if the working mode of the digital phased array circuit 100 is a mixture of multiple modes, the RF front-end module 101 includes a single-pole double-throw switch, a duplexer, a power amplifier, and a low-noise amplifier.

[0042] In one implementation, the RF transceiver channel module 102 includes a receiving channel and a transmitting channel, wherein the receiving channel corresponds to a receiving phased array, and the transmitting channel corresponds to a transmitting phased array.

[0043] In one implementation, the data conversion module 103 includes an ADC (Analog-To-Digital Converter) and a DAC (Digital-To-Analog Converter), wherein the ADC is used to convert an analog signal into a digital signal, and the DAC is used to convert a digital signal into an analog signal.

[0044] In one implementation, the sample-and-hold circuit in the data conversion module 103 is a non-capacitor architecture, which helps to reduce the power consumption of the digital phased array circuit.

[0045] In one embodiment, the beamforming module 104 is an ASIC (Application Specific Integrated Circuit). Therefore, compared with the related art that mostly uses FPGA (Field Programmable Gate Array) for beamforming, the present solution can use ASIC for beamforming, which helps to reduce the power consumption of the digital phased array circuit, and ASIC can flexibly configure the bit width, rate and multiplier, has input and output symmetry, and is suitable for a variety of application scenarios with transceiver array scales, bandwidths, and beam quantities.

[0046] In one embodiment, the beamforming module 104 is a multi-voltage domain architecture and / or a multi-clock domain architecture, which helps to reduce the power consumption of the digital phased array circuit, and can realize dynamic configuration of the voltage domain and the clock domain according to the function and performance requirements of the beamforming module, and has strong applicability.

[0047] It should be noted that there are no excessive restrictions on the manufacturing processes of the RF front-end module 101, the RF transceiver channel module 102, the data conversion module 103, and the beamforming module 104. The design requirements of each module may be different, wherein the design requirements include operating frequency, power, power supply, efficiency, cost, etc.

[0048] In one embodiment, the RF transceiver channel module 102 includes a transmission channel, and the final output device (such as a power amplifier) ​​of the transmission channel is manufactured based on the III-V compound process. It can be understood that the power capacity and power conversion efficiency of the III-V compound process are higher than those of the silicon-based CMOS (Complementary Metal Oxide Semiconductor) process, and the power consumption of the final output device of the transmission channel is relatively large. In this solution, the final output device of the transmission channel is manufactured based on the III-V compound process, which helps to reduce the power consumption of the final output device of the transmission channel.

[0049] In one embodiment, the RF transceiver channel module 102 includes a receiving channel, and the first-stage input device of the receiving channel (such as a front-end low noise amplifier and a switch) is manufactured based on the III-V compound process. It can be understood that the noise coefficient and insertion loss of the III-V compound process are lower than those of the silicon-based CMOS process. In this solution, the first-stage input device of the receiving channel is manufactured based on the III-V compound process, which helps to improve the receiving performance of the first-stage input device of the receiving channel.

[0050] In one embodiment, the digital phased array circuit 100 is manufactured based on silicon-based CMOS technology except for the first-stage input device of the receiving channel and the final-stage output device of the transmitting channel. It can be understood that the silicon-based CMOS technology has the advantages of high integration, low power consumption, and miniaturization, which helps to realize the monolithic integration of the RF transceiver channel module, the data conversion module, and the beamforming module, and helps to reduce the power consumption of the digital phased array circuit.

[0051] In summary, the digital phased array circuit according to the embodiment of the present disclosure includes an RF front-end module, an RF transceiver channel module, a data conversion module and a beamforming module, wherein the RF front-end module is system-level packaged on its corresponding chip, and at least one target module in the data conversion module and the beamforming module is respectively integrated on the first chip corresponding to each other, and the remaining modules except the target module are integrated on the second chip, and the power consumption of the first chip is lower than that of the second chip. Therefore, the target module can be integrated on the first chip on a single chip, and the remaining modules can be integrated on the second chip on a single chip, which helps to utilize the advantages of different processes, helps to reduce the circuit complexity of the target module, and improves the cost-effectiveness and economic added value. In addition, the system-level packaging and monolithic integration help to achieve the miniaturization and low power consumption of the digital phased array circuit, which is convenient for large-scale application and popularization of large-scale digital phased arrays.

[0052] Based on any of the above embodiments, Figure 4 As shown, the RF transceiver channel module 102 includes a multi-channel receiver 1 and a multi-channel transmitter 2, wherein the multi-channel receiver 1 is obtained by integrating multiple receiving channels, and the multi-channel transmitter 2 is obtained by integrating multiple transmitting channels. Thus, multiple receiving channels can be integrated to obtain a multi-channel receiver, and multiple transmitting channels can be integrated to obtain a multi-channel transmitter. Multi-channel integration helps to improve the performance of phased array channels, and can share and reuse common circuits to reduce power consumption.

[0053] It should be noted that any receiving channel corresponds to a receiving phased array, and any transmitting channel corresponds to a transmitting phased array. There is no excessive limitation on the number of receiving channels included in the multi-channel receiver 1, and there is no excessive limitation on the number of transmitting channels included in the multi-channel transmitter 2. For example, the number of integrated channels can be 8, 16, or 32.

[0054] In one embodiment, the multi-channel receiver 1 and the multi-channel transmitter 2 are integrated on their respective corresponding chips, or the multi-channel receiver 1 and the multi-channel transmitter 2 are integrated on the same chip. It can be understood that monolithic integration helps to achieve miniaturization and low power consumption of digital phased array circuits.

[0055] In one embodiment, the multi-channel receiver 1 and the multi-channel transmitter 2 are of zero intermediate frequency architecture. It can be understood that the zero intermediate frequency architecture has the advantages of high integration, low circuit complexity, and low power consumption. In this solution, the multi-channel receiver and the multi-channel transmitter are of zero intermediate frequency architecture, which helps to reduce the circuit complexity and power consumption of the multi-channel receiver and the multi-channel transmitter.

[0056] It should be noted that there are no excessive restrictions on the specific structure of any receiving channel or any transmitting channel.

[0057] In one embodiment, any receiving channel includes a low noise amplifier and a first voltage amplifier, and the gain of the low noise amplifier is greater than the gain of the first voltage amplifier. It can be understood that the power consumption of the low noise amplifier is lower than the power consumption of the first voltage amplifier. In this solution, the gain borne by the low noise amplifier is relatively large, which helps to improve power conversion efficiency, reduce heat loss, and reduce the power consumption of the digital phased array circuit.

[0058] In one embodiment, any transmission channel includes a power amplifier and a second voltage amplifier, and the gain of the power amplifier is greater than the gain of the second voltage amplifier. It can be understood that the power consumption of the power amplifier is lower than the power consumption of the second voltage amplifier. In this solution, the gain borne by the power amplifier is larger, which helps to improve power conversion efficiency, reduce heat loss, and reduce the power consumption of the digital phased array circuit.

[0059] In one embodiment, for any transceiver channel, any transceiver channel includes a radio frequency domain circuit and an analog domain circuit, and the gain of the analog domain circuit is greater than the gain of the radio frequency domain circuit, wherein any transceiver channel is any receiving channel or any transmitting channel. It can be understood that the power consumption of the analog domain circuit is lower than the power consumption of the radio frequency domain. In this solution, the gain of the analog domain circuit is larger, which helps to improve power conversion efficiency, reduce heat loss, and reduce the power consumption of the digital phased array circuit.

[0060] In one embodiment, if Figure 5 As shown, the multi-channel receiver 1 includes 1st to Nth receiving channels, and any receiving channel includes a low noise amplifier, a transconductance amplifier, a mixer, a transimpedance amplifier, a low pass filter and a programmable gain amplifier. The transconductance amplifier, the transimpedance amplifier and the programmable gain amplifier together constitute a first voltage amplifier, and N is a positive integer.

[0061] In one embodiment, if Figure 6 As shown, the multi-channel transmitter 2 includes the first to M transmission channels, and any transmission channel includes a low-pass filter, a variable gain amplifier, a mixer, a buffer and a driver amplifier. The driver amplifier is a power amplifier, the variable gain amplifier is a second voltage amplifier, and M is a positive integer.

[0062] In one implementation, the driving amplifier is a Doherty power amplifier, which has the advantage of high power conversion efficiency.

[0063] In one implementation, the mixer is a passive mixer, which has the advantages of low power consumption and high linearity.

[0064] In one implementation, the filter and the programmable gain amplifier together form a transconductance amplifier, which can realize multiplexing of the filter and the programmable gain amplifier to reduce power consumption.

[0065] In one implementation, the filter is a programmable operational amplifier main architecture, which can achieve different power consumption in different bandwidth modes to reduce power consumption.

[0066] On the basis of any of the above embodiments, the data conversion module 102 includes a multi-channel analog-to-digital converter, a multi-channel digital-to-analog converter, a serializer and a deserializer, the multi-channel analog-to-digital converter and the serializer are integrated on a third chip, the multi-channel digital-to-analog converter and the deserializer are integrated on a fourth chip, and the third chip and the fourth chip are the same chip or different chips. Thus, the multi-channel analog-to-digital converter can be integrated, and the multi-channel digital-to-analog converter can be integrated, and the multi-channel integration can share and reuse common circuits (such as reference sources, clock distribution networks, high-speed interfaces, temperature sensors, etc.), and the serializer and the deserializer are both serial interfaces, and the serializer and the deserializer can be multiplexed, which helps to reduce circuit complexity and reduce power consumption.

[0067] In one implementation, both the analog-to-digital converter and the digital-to-analog converter are hybrid pipeline-successive approximation hybrid architectures, and are manufactured based on digital logic technology to reduce power consumption.

[0068] In one implementation, the interface level standard of the data conversion module 102 includes low voltage difference differential logic to reduce the interface voltage swing.

[0069] Based on any of the above embodiments, Figure 7 As shown, the RF front-end module 101 includes a power amplifier and a low-noise amplifier, the RF channel transceiver module 102 includes a receiving channel composed of a low-noise amplifier, a mixer and a low-pass filter, and a transmitting channel composed of a power amplifier, a mixer and a low-pass filter, the data conversion module 103 includes an analog-to-digital converter and a digital-to-analog converter, and the beamforming module 104 is a dedicated integrated circuit, which includes a configuration interface, a high-speed interface, a first processing circuit, and a second processing circuit, wherein the first processing circuit is used to perform amplitude-phase weighted processing on multiple beams of the receiving channel, and the second processing circuit is used to perform amplitude-phase weighted processing on multiple beams of the transmitting channel.

[0070] It should be noted that Figures 1 to 7 The digital phased array circuit shown is only an example of the digital phased array circuit of the embodiment of the present disclosure, and is not a limitation of the digital phased array circuit of the embodiment of the present disclosure.

[0071] In the description of this specification, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0072] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0073] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A digital phased array circuit, characterized in that: include: RF front-end module, RF transceiver channel module, data conversion module and beamforming module; wherein, The RF front-end module system-level package is on its corresponding chip; The data conversion module and at least one target module in the beamforming module are respectively integrated on their respective corresponding first chips, and the remaining modules except the target module are integrated on a second chip, and the power consumption of the first chip is lower than that of the second chip.

2. The circuit according to claim 1, characterized in that The radio frequency transceiver channel module includes a multi-channel receiver and a multi-channel transmitter, wherein the multi-channel receiver is obtained by integrating multiple receiving channels, and the multi-channel transmitter is obtained by integrating multiple transmitting channels.

3. The circuit according to claim 2, characterized in that The multi-channel receiver and the multi-channel transmitter are respectively integrated on corresponding chips, or the multi-channel receiver and the multi-channel transmitter are integrated on the same chip.

4. The circuit according to claim 2, characterized in that The multi-channel receiver and the multi-channel transmitter are of zero intermediate frequency architecture.

5. The circuit according to claim 2, characterized in that Any receiving channel includes a low noise amplifier and a first voltage amplifier, and the gain of the low noise amplifier is greater than the gain of the first voltage amplifier; Any transmission channel includes a power amplifier and a second voltage amplifier, and the gain of the power amplifier is greater than the gain of the second voltage amplifier.

6. The circuit according to claim 2, characterized in that For any transceiver channel, the any transceiver channel includes a radio frequency domain circuit and an analog domain circuit, and the gain of the analog domain circuit is greater than the gain of the radio frequency domain circuit, wherein the any transceiver channel is any receiving channel or any transmitting channel.

7. The circuit according to claim 1, characterized in that The data conversion module includes a multi-channel analog-to-digital converter, a multi-channel digital-to-analog converter, a serializer and a deserializer. The multi-channel analog-to-digital converter and the serializer are integrated on a third chip, and the multi-channel digital-to-analog converter and the deserializer are integrated on a fourth chip. The third chip and the fourth chip are the same chip or different chips.

8. The circuit according to claim 1, characterized in that The sampling and holding circuit in the data conversion module is a large capacitor-free architecture.

9. The circuit according to claim 1, characterized in that The beamforming module is an application specific integrated circuit ASIC.

10. The circuit according to claim 1, characterized in that The beamforming module is a multi-voltage domain architecture and / or a multi-clock domain architecture.

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