Network equipment and dual master control switching method

Abstract

The invention provides network equipment and a dual-master control switching method. The network equipment comprises a switching board provided with a switching chip, a management board provided with an interface expansion management module, a service board provided with an interface expansion chip and a dual-master control board provided with a CPU (Central Processing Unit), the CPU is respectively connected with the exchange chip and the interface expansion management module; the interface expansion management module is respectively connected with the exchange chip and the interface expansion chip; the CPU is used for managing the exchange chip in a data plane; and the interface expansion management module is used for managing the interface expansion chip on the monitoring plane. According to the invention, data plane management is carried out on the switching chip through the CPU integrated on the double main control boards, and monitoring plane management is carried out on the interface expansion chip by adding the management board and configuring the interface expansion management module, so that independent configuration of MCU independent control units on the main control boards, the switching board and the service board is avoided; on the basis of keeping the reliability of the dual-master control system, the hardware design cost is greatly reduced, and the system management complexity is remarkably simplified.

Description

Technical Field

[0001] The present invention relates to the field of network communication technology, and in particular to a network device and a dual-master switching method. Background Art

[0002] In large-scale data center networks, to ensure business continuity and reliability, core network equipment usually uses dual master control devices. Once the active master control device encounters a system failure or hardware anomaly, the active master control device is switched to the backup master control device to ensure that user services continue to run without interruption.

[0003] Due to the relatively high construction cost of dual-master network systems, this configuration is mainly used in core networks or central network layers, and less in edge network nodes. However, as network services become more diverse and complex, users' requirements for network reliability continue to increase. Especially in new data center networks, edge network devices that connect servers and intelligent computing nodes have reliability requirements comparable to those of traditional core network devices. Therefore, there is a growing demand for dual-master devices that can reduce costs while ensuring high reliability.

[0004] Figure 1 The system architecture diagram of a traditional dual-master network device is shown. In this architecture, the dual-master network device is mainly composed of three business modules: the main control board, the switch board, and the business board. Among them, the main control board 1 and the main control board 2, and the switch board 1 and the switch board 2 are redundant. Each business module is equipped with a CPU and an MCU (Micro Control Unit), in which the CPU is responsible for the management of the data plane, and the MCU is responsible for the management of the monitoring plane. The main control board 1 and the main control board 2 are connected to the switch board and the business board to realize the communication management, information synchronization, and configuration distribution of the CPU and MCU on these modules.

[0005] However, Figure 1 The dual-master design shown still has some defects. Figure 1 As shown in the figure, each service module must be configured with a CPU and an MCU, and a switching chip must also be integrated on the switching board and the service interface board. This configuration significantly increases the cost of hardware design. Secondly, multiple CPUs, multiple MCUs, and multiple switching chips are interconnected to complete management functions, making system management more complicated. In addition, this solution cannot meet the application requirements of local network equipment for a single switching chip. Therefore, how to provide a design solution to reduce the cost of dual-master network equipment and meet the application requirements of local network equipment for a single switching chip is a technical problem that needs to be solved. Summary of the invention

[0006] One of the purposes of the present invention is to provide a network device and a dual-master switching method, which can reduce the dual-master design cost and management complexity of the network device, and at the same time can meet the application requirements of the central office network device for a single switching chip. The embodiment of the present invention can be implemented as follows:

[0007] In a first aspect, the present invention provides a network device, comprising a switching board provided with a switching chip, a management board provided with an interface extension management module, a service board provided with an interface extension chip, and a dual main control board provided with a CPU; the CPU is respectively connected to the switching chip and the interface extension management module; the interface extension management module is respectively connected to the switching chip and the interface extension chip; the CPU is used to manage the switching chip on the data plane; the interface extension management module is used to manage the interface extension chip on the monitoring plane.

[0008] In an optional embodiment, the network device of the present invention also includes a shared storage unit; the shared storage unit is used to maintain operation data and configuration data; when a master-slave switch occurs on the dual main control boards, the shared storage unit switches from a state connected to the CPU on the original master main control board to a state connected to the CPU on the new master main control board.

[0009] In an optional embodiment, a logic processing control unit is provided on both main control boards; the logic processing control unit is connected to the CPU; when a master-slave switching occurs on the dual main control boards, the logic processing control unit on the new master main control board is used to generate a heartbeat control signal; wherein the heartbeat control signal is used to indicate the channel between the CPU on the new master main control board and the switching chip, the interface expansion management module and the shared storage unit.

[0010] In an optional embodiment, the switch board is provided with a switch board switch module, and the management board is provided with a management board switch module; the switch board switch module is respectively connected to the CPU and the switch chip; the management board switch module is respectively connected to the CPU and the interface extension management module; the switch board switch module and the management board switch module are used to switch from a state of being connected to the CPU on the original main control board to a state of being connected to the CPU on the new main control board when receiving the heartbeat control signal sent by the logic processing control unit on the new main control board.

[0011] In an optional embodiment, the network device of the present invention also includes a storage switch module; the storage switch module is respectively connected to the CPU and the shared storage unit; the storage switch module is used to switch from a state of being connected to the CPU on the original main control board to a state of being connected to the CPU on the new main control board when receiving the heartbeat control signal sent by the logic processing control unit on the new main control board.

[0012] In an optional implementation manner, the logic processing control unit is further used to determine the active main control board and the standby main control board from among the dual main control boards through a negotiation mechanism during the initialization process.

[0013] In an optional embodiment, there are one or two switching boards; when there are two switching boards, the interface expansion chip is used to receive data from one of the switching boards; when a data link interruption occurs, it switches to receiving data from another switching board.

[0014] In a second aspect, the present invention provides a dual-master switching method, which is applied to a network device, wherein the network device includes a switching board provided with a switching chip, a management board provided with an interface extension management module, a service board provided with an interface extension chip, and a dual-master control board provided with a CPU; the CPU is respectively connected to the switching chip and the interface extension management module; the interface extension management module is respectively connected to the switching chip and the interface extension chip; the CPU is used to manage the switching chip in the data plane; the interface extension management module is used to manage the interface extension chip in the monitoring plane; the method includes: when the dual-master switching conditions are met, the standby master control board in the dual-master control board is switched to a new master master control board; the channel between the CPU of the new master master control board itself and the switching chip and the interface extension management module is controlled and connected; wherein the dual-master switching conditions are: the channel between the CPUs on the dual-master control boards is abnormal or the heartbeat signal of the CPU on the original master master control board is lost.

[0015] In an optional embodiment, the network device also includes a shared storage unit; the shared storage unit is used to maintain operation data and configuration data; the method also includes: controlling the shared storage unit to switch from a state connected to the CPU on the original main control board to a state connected to the CPU on the new main control board.

[0016] In an optional embodiment, a logic processing control unit is provided on both the dual main control boards; the logic processing control unit is connected to the CPU; the method further comprises: when a master-slave switching occurs on the dual main control boards, a heartbeat control signal is generated by the logic processing control on the new master main control board; wherein the heartbeat control signal is used to indicate the channel between the CPU on the new master main control board and the switching chip, the interface expansion management module and the shared storage unit.

[0017] A network device and a dual-master switching method provided by the present invention have the following advantages: First, the present invention introduces a dual-master architecture with centralized management. On the one hand, the embodiment of the present invention specifically handles the monitoring of the interface expansion chip by adding a management board and equipping it with an interface expansion management module; on the other hand, the present invention centrally manages the data plane of the switching chip and the interface expansion management module through the CPU integrated on the dual-master boards. This design avoids the need to configure an MCU independent control unit separately on the main control board, the switching board, and the service board, greatly reduces the cost of hardware design while retaining the reliability of the dual-master system, and significantly simplifies the management complexity of the system. In addition, the embodiment of the present invention does not limit the number of switching boards, which means that the embodiment of the present invention allows the switching board to be one or more. This flexibility not only meets the needs of the local network equipment for a single switching chip, but also adapts to those network equipment that require multiple switching chips to adapt to different application scenarios and needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 A system architecture diagram of a traditional dual-master network device is shown;

[0020] Figure 2 A dual-master control system architecture diagram of a network device provided by an embodiment of the present invention;

[0021] Figure 3 Another dual-master control system architecture diagram of a network device provided by an embodiment of the present invention;

[0022] Figure 4 A structural block diagram of a main control board provided for an embodiment of the present invention;

[0023] Figure 5A schematic diagram of the architecture between a service board, a switch board, and a management board in a network device provided by an embodiment of the present invention is shown;

[0024] Figure 6 A schematic diagram of a partial dual-master control architecture of a network device provided by an embodiment of the present invention;

[0025] Figure 7 A schematic diagram of a dual-master control architecture of a network device with multiple switching chips provided by an embodiment of the present invention;

[0026] Figure 8 A functional block diagram of the switch board backup redundancy provided by an embodiment of the present invention;

[0027] Fig. 9 A schematic flow chart of a dual master switching method provided for the implementation of the present invention;

[0028] Fig.10 A schematic diagram of a dual master initialization process in a network device provided by an embodiment of the present invention;

[0029] Fig.11 A schematic diagram of a dual master switching process in a network device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0031] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0033] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, they are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the invention is usually placed when used. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0034] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0035] It should be noted that, in the absence of conflict, the features in the embodiments of the present invention may be combined with each other.

[0036] First, relevant terms in the embodiments of the present invention are introduced.

[0037] Data Center Switch: Data Center Switch is designed for large data centers to connect core network devices, including servers, storage devices, and network devices. It processes large amounts of data and provides high-performance computing and cloud services.

[0038] Campus switch: Campus switches are switches that are specially deployed in campuses and office buildings. They are mainly used to connect end-user devices such as IP phones, surveillance cameras, APs (Access Points) and ACs (Access Controllers). They are designed to meet the network connection needs between multiple buildings or office areas on campus.

[0039] Dual-control network equipment: refers to a network device that uses two main control chips. In a dual-control network device, one main control board is in the active state and the other is in the standby state. The active main control board is responsible for managing the entire system, while the standby main control board monitors the status of the entire system. When the active main control board fails, the standby main control board immediately switches to the new active main control board to take over the system to ensure that the network device's services are not affected.

[0040] Gearbox chip: It is an integrated chip with rate conversion and increased driving capability. It can convert a single 100G interface with a data transmission rate of 112Gbps into four parallel 25Gbps channels, and can also merge four independent 25Gbps channels into a 112Gbps high-speed interface, providing a flexible data transmission solution to meet the needs of different application scenarios.

[0041] Data plane and monitoring plane: In network communications, the data plane usually refers to the software and hardware in network devices (such as routers and switches) responsible for packet forwarding, providing complete data forwarding capabilities for network devices; the monitoring plane refers to the business responsible for monitoring the operating status of software and hardware, such as power supply, fan, temperature, etc., which represent the health status.

[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0043] See also Figure 2 , Figure 2 A dual-master control system architecture diagram of a network device provided in an embodiment of the present invention. The network device 00 may be, but is not limited to, a router, a switch, etc., and the switch may be, but is not limited to, a data center switch, a campus switch, etc. It should be understood that Figure 2 and Figure 1 The same color lines have the same meanings. Figure 2 I will not go into details here.

[0044] exist Figure 2 In the embodiment, the network device 00 includes a main control board 10 and a main control board 11, a switch board 20, a management board 30 and a service board 40 ( Figure 2 The physical connections between the boards are omitted. Figure 2 The one switch board 20 and one service board 40 shown in the figure are only examples, but should not be understood as a limitation on the number of switch boards 20 and service boards 40. The switch board 20 and service board 40 in the embodiment of the present invention can be one or more. In particular, there can be two switch boards 20, which are designed to be redundant with each other.

[0045] The main control board 10 is provided with CPU0, the main control board 11 is provided with CPU1 (the connection between CPU0 and CPU1 is omitted in the figure), the switching board 20 is provided with a switching chip, the management board 30 is provided with an interface extension management module, and the business board 40 is provided with an interface extension chip; CPU0 and CPU1 are respectively connected to the switching chip and the interface extension management module; the interface extension management module is respectively connected to the switching chip and the interface extension chip.

[0046] It should be understood that Figure 2The connection relationship between CPU0 and CPU1 and the switch chip and interface expansion management module is also drawn. In fact, in the normal operation of the network device 00, the switch chip and the interface expansion management module are only connected to the channel between CPU0 or CPU1. The specific CPU to be connected depends on the role allocation of the main control board 10 or the main control board 11, that is, whether it serves as the main control board or the backup main control board. This design ensures the efficient operation of the system and the flexible failover capability.

[0047] In one embodiment of the present invention, high-speed buses can be used to connect CPU0 and CPU1 to the switching chip and the interface expansion management module, and between the interface expansion management module and the switching chip and the interface expansion chip. The high-speed bus can be, but is not limited to, a PCIe (Peripheral Component Interconnect express) bus.

[0048] It should be made clear that Figure 2 The connecting lines shown in the figure not only represent the existence of physical lines, but can also be understood as communication channels between hardware components, that is, bridges for data interaction between the two parties. For example, the connecting line between CPU0 and CPU1 can represent an IPU (Intelligent Processing Unit) channel; the connecting line between the interface extension management module and the interface extension chip represents a monitoring management channel, which is used to perform configuration and monitoring tasks; and the connecting line between the switching chip and the interface extension chip represents a data channel, which is responsible for transmitting actual data loads. These channels can be, but are not limited to, composed of high-speed bus technologies, such as a PCIe bus or a USB bus. For ease of description and understanding, the embodiments of the present invention will subsequently name the channel based on the PCIe bus as a "PCIe channel" and the channel based on the USB bus as a "USB channel."

[0049] The CPU is used to manage the switching chip on the data plane; the interface extension management module is used to manage the interface extension chip on the monitoring plane.

[0050] Specifically, the CPU is responsible for key management tasks such as the ports and protocol data table entries of the switching chip. In addition, the CPU is also responsible for transmitting high-speed signals to the interface expansion management module. These signals are converted on the interface expansion management module and adapted to management interfaces of various communication protocols. These management interfaces may include, but are not limited to, QSPI (Quad Serial Peripheral Interface), I2C (Inter-Integrated Circuit), SMI (Serial Management Interface), etc. Through these management interfaces, the interface expansion management module can implement accurate and efficient management and control of various business interfaces on the business board 40 to ensure smooth operation and performance optimization of the system.

[0051] The dual master control architecture in the network device 00 provided in the embodiment of the present invention is Figure 2 Compared with the traditional dual-master control architecture shown in the figure, the present invention has the following advantages: First, the present invention introduces a dual-master control architecture with centralized management. On the one hand, the embodiment of the present invention specifically handles the monitoring of the interface expansion chip by adding a management board and equipping an interface expansion management module; on the other hand, the embodiment of the present invention uses the CPU integrated on the dual-master control board to centrally manage the data plane of the switching chip and the interface expansion management module, and uses the interface expansion management module to centrally manage the monitoring plane of the interface expansion chip. This design avoids the configuration of MCU independent control units on the main control board, the switching board and the service board separately, greatly reduces the cost of hardware design on the basis of retaining the reliability of the dual-master control system, and significantly simplifies the management complexity of the system. In addition, the embodiment of the present invention does not limit the number of switching boards, which means that the embodiment of the present invention allows the switching board to be one or more. This flexibility not only meets the needs of the local network equipment for a single switching chip, but also adapts to those network equipment that require multiple switching chips to adapt to different application scenarios and needs.

[0052] In order to synchronize information between the two main control boards after the active and standby main control boards switch, Figure 2 Based on the dual-master architecture shown in FIG. 1 , the embodiment of the present invention further adds a shared storage unit 50. Figure 3 , Figure 3 Another dual-master control architecture diagram of a network device provided by an embodiment of the present invention. Figure 3 The connection relationship between the shared storage unit 50 and CPU0 and CPU1 is simultaneously drawn. However, in the actual operation of the network device 00, the shared storage unit 50 is only connected to one of CPU0 and CPU1, which depends on which of the main control board 10 and the main control board 11 is the main control board and which is the standby main control board.

[0053] like Figure 3 As shown, the shared storage unit 50 can be, but is not limited to, an embedded storage device, such as a USB eMMC memory. The shared storage unit 50 can be used to maintain system operation data, configuration data, etc. It can be connected to the CPU via a high-speed bus, which can be, but is not limited to, a USB bus.

[0054] It is understandable that during the normal operation of the business system, the channel between the CPU on the active main control board and the shared storage unit 50 is in an on state, and the channel between the CPU on the standby main control board and the shared storage unit 50 is in an off state. At this time, the data generated by the operation of the active main control board is stored in the shared storage unit 50, and the data generated by the operation of the standby main control board is stored in its own storage component such as FLASH. When the active-standby switching occurs between the dual main control boards, the channel between the shared storage unit 50 and the new active main control board is connected, and the new active main control board mounts the shared storage unit 50, and the information synchronization of the dual main control can be achieved by reading configuration files, operation logs and other information.

[0055] For example, in Figure 3 In the figure, assuming that the main control board 10 is the main control board and the main control board 11 is the standby main control board, the main control board 10 and the USB eMMC memory are connected by a USB bus. In normal operation, the USB channel between the main control board 10 and the USB eMMC memory is turned on, and the USB channel between the main control board 11 and the USB eMMC memory is turned off. The operation data and configuration data of the main control board 10 are stored in the USB eMMC memory, while the operation data of the main control board 11 is stored in its own FLASH. After the main control board 10 and the main control board 11 are switched between the main and standby main control boards, the USB channel between the main control board 10 and the USB eMMC memory is turned off, and the USB channel between the main control board 11 and the USB eMMC memory is turned on. At this time, the main control board 11 can mount the USB eMMC memory for information synchronization.

[0056] In order to effectively implement the active / standby switching between the two main control boards, Figure 2 and Figure 3 Under the dual main control architecture shown, the embodiment of the present invention is provided with a logic processing control unit on both main control boards. The logic processing control units between the dual main control boards can be interconnected, and the logic processing control unit inside each main control board is connected to the CPU.

[0057] In one embodiment of the present invention, the functions of the logic processing control unit include:

[0058] Function 1: During the initialization process, the active main control board and the standby main control board are determined between the two main control boards through a negotiation mechanism.

[0059] This can be understood as: the dual main control boards can negotiate with each other through the logic processing control unit to determine the active main control board and the standby main control board, and constrain the heartbeat signal of the active main control board to a fixed period and frequency, while the standby main control card is constrained to another period and frequency.

[0060] Function 2: When the dual main control boards switch from active to standby, the logic processing control unit on the new active main control board is used to generate a heartbeat control signal to indicate that the channel between the CPU on the new active main control board and the switching chip, interface expansion management module and shared storage unit is turned on.

[0061] For ease of understanding, continue with Figure 3 For example, assuming that the main control board 10 is the main control board, and the main control board 10 is the standby main control board. At this time, the channels between CPU0 and the switching chip, the interface expansion management module, and the shared storage unit 50 are connected, while the channels between CPU1 and them are closed. When the main control board 11 is switched to the main control board, it can generate a heartbeat control signal through the logic processing control unit as the new main control board to achieve the purpose of connecting the channels between CPU1 and the switching chip, the interface expansion management module, and the shared storage unit 50.

[0062] In an optional implementation, the logic processing control unit may be, but is not limited to, a CPLD (Complex Programmable Logic Device).

[0063] In one embodiment of the present invention, when the active / standby switching condition of the dual main control boards is met, the standby main control board in the dual main control boards will be switched to become the new active main control board.

[0064] The dual-controller master-slave switching conditions may include: the IPU channel between the CPUs on the dual-controller boards is abnormal, that is, the IPU management channel state changes from the UP state to the DOWN state; or the heartbeat signal of the CPU on the original active control board is lost. The UP state refers to the connected state, and the DOWN state refers to the disconnected state.

[0065] In order to timely monitor whether the dual-master active-standby switching condition is triggered, the system can sense the IPU management channel status or heartbeat signal through a high-reliability monitoring module. Once the dual-master active-standby switching condition is triggered, the standby main control board can be notified to switch to the new active main control board. At the same time, the standby active main control board, as the new active main control board, uses its own logic processing control unit to generate a heartbeat control signal to instruct the switch board 20 and the management board 30 to conduct the channel between the CPU and the switch chip and the interface expansion management module on the new active main control board, as well as the channel between the shared storage unit 50.

[0066] For ease of understanding, the above functions are described below assuming that the logic processing control unit is CPLD.

[0067] See also Figure 4 , Figure 4 A structural block diagram of a main control board provided by an embodiment of the present invention: CPLD0 is provided on the main control board 10, CPLD1 is provided on the main control board 11, CPU0 is connected to CPLD0, CPU1 is connected to CPLD1, and CPLD0 and CPLD1 are connected to each other. Figure 4 The various connection relationships in can be implemented by, but are not limited to, a high-speed bus such as a PCIe bus.

[0068] like Figure 4 As shown in the figure, CPLD0 and CPLD1 use a negotiation mechanism to determine which main control board plays the active role and which one plays the standby role. CPU0 and CPU1 each send a stable heartbeat signal to their corresponding CPLD to indicate their normal operation status. Once an abnormality is detected in the IPU channel between CPU0 and CPU1, or the CPU heartbeat signal on the active main control board is lost, the CPLD on the standby main control board can generate a heartbeat control signal to reconfigure the conduction state.

[0069] Of course, in Figure 4 The example scenario in which both CPLD0 and CPLD1 may generate the heartbeat control signal is shown in FIG. However, in actual operation, when the roles of the active and standby main control boards are switched, only one of CPLD0 or CPLD1 is responsible for generating the heartbeat control signal. Which CPLD performs this task depends on which of the main control boards 10 and 11 is the active main control board. This mechanism ensures the high availability and fault recovery capability of the system.

[0070] In order to achieve smooth connection between the new main control board and the switch board 20 and the management board 30, and ensure barrier-free transmission of data and control signals, Figure 4 Based on the examples, the embodiment of the present invention makes improvements to the switch board 20 and the management board 30, specifically including:

[0071] On the switch board 20, the embodiment of the present invention sets a switch board switch module 201, which is connected to the CPU and the switch chip. On the management board 30, the embodiment of the present invention sets a management board switch module 301, which is connected to the CPU and the interface expansion management module.

[0072] The switching board switch module 201 and the management board switch module 301 are used to switch from the state of being connected to the CPU on the original main control board to the state of being connected to the CPU on the new main control board when receiving the heartbeat control signal sent by the logic processing control unit on the new main control board.

[0073] In order to facilitate understanding of the above connection relationship and functions, Figure 4 Based on this, the present invention provides Figure 5 , Figure 5 The schematic diagram of the architecture between the service board, the switch board and the management board in the network device provided by the embodiment of the present invention is shown. Figure 5 The example in which the logic processing control unit is a CPLD is still used for illustration, but this should not be understood as a limitation to the logic processing control unit. Figure 5 (a) and (b) in the figure respectively show the functional module composition of the switch board 20 and the management board 30. The figure omits the switch chip and the service board 40 connected to the interface expansion management module.

[0074] by Figure 5 Taking (a) in the figure as an example, it can be seen that: CPU0 and CPU1 are connected to the switching chip through the switching board switch module 201. The communication between CPU0 and CPU1 and the switching board switch module 201, as well as the communication between the switching board switch module 201 and the switching chip, can be achieved through a high-speed bus, such as a PCIe bus. In the normal operation of the system, the two channels between CPU0 and CPU1 and the switching board switch module 201 are not activated at the same time. Only one channel remains on and the other remains off to ensure the stability and certainty of signal transmission. The same principle applies to CPLD0 and CPLD1, where only one CPLD will send a heartbeat control signal to the switching board switch module 201. Which CPLD is responsible for it depends on the master-slave role allocation between the main control board 10 and the main control board 11. This design can improve the response speed and reliability of the system.

[0075] In an optional implementation, the switching board switch module 201 and the management board switch module 301 may both be low-cost high-speed analog switch modules, such as a PCIe analog switch.

[0076] Taking the PCIe analog switch as an example, assume that the main control board 10 is the main control board, and the main control board 11 is the standby main control board. At this time, the PCIe channel between CPU0 and the PCIe analog switch is in the open state, the PCIe channel between CPU1 and the PCIe analog switch is in the closed state, and CPU0 is connected to the switching chip and the interface expansion management module. When the dual main control boards switch between the main control board and the standby board, the main control board 11 becomes the new main control board, and CPLD1 sends a heartbeat control signal to the PCIe analog switch. After receiving the signal, the PCIe analog switch opens the channel with CPU1, and the PCIe channel between CPU0 and the PCIe analog switch is closed. The main control board 11 takes over the main control board 10 and continues to work.

[0077] Similarly, in order to achieve smooth channel between the new main control board and the shared storage unit 50 and ensure data synchronization, the embodiment of the present invention adds a storage switch module 60 between the dual main control boards and the shared storage unit 50, which is connected to the CPU and the shared storage unit 60 respectively.

[0078] The storage switch module is used to switch from a state connected to the CPU on the original main control board to a state connected to the CPU on the new main control board when receiving a heartbeat control signal sent by the logic processing control unit on the new main control board.

[0079] To understand the above connections and functions, please refer to Figure 6 , Figure 6 A schematic diagram of a partial dual-master control architecture of a network device provided in an embodiment of the present invention. Figure 6 The example in which the logic processing control unit is a CPLD is still used for illustration, but this should not be understood as a limitation to the logic processing control unit.

[0080] like Figure 5 As shown, it can be seen that CPU0 and CPU1 are interconnected with the shared storage unit 50 through the storage switch module 60. The data interaction between the two groups of CPUs and the storage switch module 60 can be realized through, but not limited to, a high-speed bus such as a USB bus. In actual work, in order to maintain the stability of the system and the consistency of data, only one of the two channels between CPU0 and CPU1 and the storage switch module 60 is in a conducting state, and the other channel is in a closed state. Similarly, only one of CPLD0 and CPLD1 will send a heartbeat control signal to the storage switch module 60 to reconfigure the conduction relationship between the CPU and the shared storage unit 60. Which CPLD specifically performs this task depends on which of the main control board 10 and the main control board 11 is the main main control board.

[0081] In an optional implementation, the storage switch module 60 may be a low-cost high-speed analog switch module, such as a USB analog switch.

[0082] by Figure 6 Taking the storage switch module 60 as a USB analog switch and the shared storage unit as a USB eMMC memory as an example, it is assumed that the main control board 10 is the main control board and the main control board 11 is the standby main control board. At this time, the USB channel between CPU0 and the USB analog switch is in an open state, the USB channel between CPU1 and the USB analog switch is in a closed state, and CPU0 is connected to the USB eMMC memory. When the dual main control boards switch between the main and standby, the main control board 11 becomes the new main control board, and CPLD1 sends a heartbeat control signal to the USB analog switch. After receiving the signal, the USB analog switch opens the USB channel with CPU1, and the USB channel between CPU0 and the USB analog switch is closed. The main control board 11 takes over the main control board 10, and the information synchronization of the dual main control can be achieved by reading configuration files and operation logs and other information.

[0083] It can be seen that in Figures 3 to 6 Under the dual-master control architecture shown in , the embodiment of the present invention can effectively realize the active-standby switching between the dual masters, complete the connection between the CPU on the new master master board and the switching chip and the interface expansion management module, so that the CPU on the new master master board can take over the management of the switching chip, and at the same time can establish a connection with the interface expansion management module to enable the interface expansion management module to manage the interface expansion chip. In addition, after the active-standby switching of the dual master boards occurs, the embodiment of the present invention can also complete the connection between the CPU on the new master master board and the shared storage unit, so that the CPU on the new master master board can mount the shared storage unit to achieve information synchronization of the dual master boards.

[0084] In summary Figures 3 to 6 Under the dual-master control architecture shown, it can be seen that the embodiment of the present invention shows the provided network device 00, which can efficiently handle the master-slave role switching between the dual masters, smoothly complete the conduction channel between the CPU on the new master master board and the switching chip and the interface expansion management module, take over the management of the switching chip, and cooperate with the interface expansion management module to ensure the effective management of the interface expansion chip. In addition, when the master and standby master boards are switched, the embodiment of the present invention can also ensure the smooth connection between the CPU on the new master master board and the shared storage unit, so that the CPU on the new master master board can mount and access the shared storage unit, realize information synchronization between the dual master boards, and ensure data consistency and business continuity.

[0085] The following embodiment of the present invention also provides a dual-master control architecture of a network device 00 with multiple switching chips. Figure 2 It can be seen that Figure 2 The dual-master architecture under the single switch chip shown can well meet the application requirements of the single switch chip of the central office network device. For those network devices that require multiple switch chips, the embodiment of the present invention provides such Figure 7 The network device 00 shown, Figure 7 The dual-master architecture diagram of the network device with multiple switching chips provided by the embodiment of the present invention can meet the application requirements of the network devices with multiple switching chips. Figure 7 Two switch boards 20 and two service boards 40 are used for exemplary description, but this should not be understood as a limitation on the number of switch boards 20 and service boards 40 respectively.

[0086] like Figure 7 As shown, the switch board 20 and the switch board 21 are equipped with a switch chip 0 and a switch chip 1, which can be connected to the service board 40 and the service board 41 through a high-speed Ethernet data interface to achieve high-speed data transmission. In the data plane, the switch board 20 and the switch board 21 perform signal conversion and data processing through the interface expansion chip 0 and the interface expansion chip 1, and finally output as a user data service interface to support various data services and applications. Such a design not only optimizes the data transmission efficiency, but also improves the overall performance of the system.

[0087] On the management board 30, the interface expansion management module may be, but not limited to, FPGA (Field Programmable Gate Array), which may be connected to the service board 40 and the service board 41 through a low-speed management bus. The low-speed management bus may be, but not limited to, IC2 (Inter-Integrated Circuit), QSPI (Quad Serial Peripheral Interface), etc. The interface expansion management module may be responsible for the status monitoring of each service board 40 and the service board 41, the configuration management of the interface expansion chip 0 and the interface expansion chip 1, the optical module management, and other functions.

[0088] On business board 40 and business board 41, business board 40 and business board 41 can increase the number of ports on the business board through interface expansion chip 0 and interface expansion chip 1 respectively, and provide different types of optical service interfaces, including but not limited to SFP, SFP+, SFP28, QSFP, QSFP-DD and other standard interfaces.

[0089] In the embodiment of the present invention, the interface expansion chip 0 and the interface expansion chip 1 have the ability to convert a high-speed interface into multiple parallel low-speed channels, and also have the ability to merge multiple independent low-speed channels into a high-speed interface.

[0090] In an optional implementation manner, the interface expansion chip 0 and the interface expansion chip 1 may be, but are not limited to, a Gearbox chip or the like.

[0091] exist Figure 7 In the example, interface expansion chip 0 and interface expansion chip 1 have data selection function, which enables them to perform the backup task of business data. Figure 8 , 8 is a functional block diagram of the switch board backup redundancy provided in an embodiment of the present invention. Assume that the switch board 20 is the main switch board and the switch board 21 is the redundant switch board. The switch board 20 is the main one and provides a main data link to each of the business boards 40 and 41; correspondingly, the switch board 21 provides a backup data link to each of the business boards 40 and 41. Once the main data link port encounters an abnormality, the interface expansion chip 0 and the interface expansion chip 1 can automatically switch to the backup link to continue to receive business data, thereby ensuring business continuity and avoiding service interruption.

[0092] Combination Figures 2 to 8 It can be seen that the embodiment of the present invention provides a network device 00 (such as Figure 2 and Figure 7 This architecture not only optimizes the active / standby switching process between the dual main control boards, but also ensures that the new active main control board can quickly and seamlessly take over control (as shown in Figure 2). Figures 3 to 6 As shown in Figure 2), and in the case of multiple switching chips, the data backup capability is enhanced, thereby minimizing the risk of business interruption (as shown in Figure 2). Figure 8 The embodiments of the present invention significantly improve the reliability, flexibility and service continuity of the network device 00 through these designs.

[0093] based on Figures 2 to 8 With the same inventive concept, the embodiment of the present invention also provides a dual master switching method, which can be applied to the network device 00 in any of the above embodiments, see Fig. 9 , Fig. 9 A schematic flow chart of a dual master switching method provided for the implementation of the present invention, the method comprising:

[0094] S901, when the master-slave switching condition of the dual main control boards is met, the standby main control board in the dual main control boards is switched to the new master main control board;

[0095] S902: Control and connect the channel between the CPU of the new active main control board and the switching chip and interface expansion management module.

[0096] In the embodiment of the present invention, the dual master control active / standby switching condition has been introduced above and will not be repeated here. The implementation method of controlling the channel between the CPU of the new master control board and the switching chip and the interface expansion management module can be found in Figures 3 to 5 The corresponding implementation contents will not be repeated here.

[0097] In the embodiment of the present invention, the dual master control active / standby switching condition has been described in detail above and will not be repeated here. Figures 3 to 5 The corresponding embodiments have been described in detail, so they will not be repeated here.

[0098] In an optional implementation, the method further includes controlling the shared storage unit to switch from a state of being connected to the CPU on the original active main control board to a state of being connected to the CPU on the new active main control board.

[0099] In an optional embodiment, the method also includes generating a heartbeat control signal through logic processing control on the new active main control board when a master-slave switching occurs on the dual main control boards; wherein the heartbeat control signal is used to indicate the connection of the channel between the CPU on the new active main control board and the switching chip, interface expansion management module and shared storage unit.

[0100] In an optional embodiment, the method also includes receiving a heartbeat control signal sent by a logic processing control unit on the new main control board through a switching board switch module and a management board switch module, and switching the state of connection with the CPU on the original main control board to a state of connection with the CPU on the new main control board.

[0101] In an optional embodiment, the method also includes receiving a heartbeat control signal sent by a logic processing control unit on the new main control board through a storage switch module, and switching the state of connection with the CPU on the original main control board to a state of connection with the CPU on the new main control board.

[0102] In an optional implementation manner, the method further includes, during the initialization process, determining, by the logic processing control unit, a primary main control board and a backup main control board from between the dual main control boards according to a negotiation mechanism.

[0103] In an optional implementation, the method further includes receiving data on one of the switch boards through an interface expansion chip, and when a data link interruption occurs, switching to receiving data on another switch board.

[0104] In order to comprehensively understand the dual master control architecture and dual master control switching method of the network device 00 provided by the embodiment of the present invention, the embodiment of the present invention also provides Fig.10 and Fig.11 Example diagram of . Fig.10 A schematic diagram of a dual master initialization process in a network device provided by an embodiment of the present invention. Fig.11 A schematic diagram of a dual master switching process in a network device provided by an embodiment of the present invention.

[0105] For ease of understanding, Fig.10 and Fig.11 In the figure, the switching board switch module 201 and the management board switch module 301 are both exemplified by PCIe analog switches, the storage switch module 60 is exemplified by USB analog switches, the shared storage unit 50 is exemplified by USB eMMC storage, and the logic processing control unit on the dual main control boards is exemplified by CPLD.

[0106] During initialization, if Fig.10 As shown, the main control board 10 and the main control board 11 in the network device 00 are powered on. At this time, the PCIe management channel is closed by default. First, the management IPU channel between CPU0 and CPU1 is initialized, and CPLD0 and CPLD1 negotiate the roles of the master and standby main control cards to determine that the main control board 10 is the master main control board and the main control board 11 is the standby main control board. Next, the main control board 10 opens the USB channel, loads the USB eMMC storage, and opens the PCIe channel and performs a PCIe component scan, that is, scans the switch board, service board, and management board on the device, and keeps the PCIe channel and USB channel in a closed state from the main control board.

[0107] After the main control board 10 completes the PCIe component scan, it initializes the loading software system. After the software system is loaded, the main control board 10, the switch board 20, the management board 30 and the service board 40 are loaded. After the service configuration is loaded, the service system provides services normally. During the normal operation of the service system, the data and configuration files generated by the system operation are stored in the USB eMMC memory, and the data generated by the operation of the main control board 11 are stored in its own internal storage components. If the service running on the main control board 11 needs to access the PCIe components, it must feedback that it is not supported.

[0108] Next, see Fig.11 When the high-reliability monitoring module in the system senses that the IPU management channel between CPU0 and CPU1 changes from the UP state to the DOWN state or the heartbeat signal between the main control board 10 and the main control board 11 is lost, it will be considered that the main control board 10 has been lost, and then the main control board 11 will be switched to the new main control board.

[0109] The main control board 11 becomes the new main control board, opens the USB channel, mounts the USB eMMC storage, opens the PCIe management channel, and rescans the PCIe components. After the PCIe component scan is successful, the main control board 11 can start reading the operating data and configuration data in the USB eMMC storage after the business software is initialized normally, and the data information of the software is restored. After all the data information is restored, the system works normally.

[0110] The present invention changes the distributed dual-master control architecture of traditional network equipment and introduces a centralized management architecture, which can realize the master-slave backup of the control plane and the backup of the forwarding plane, and build a dual redundancy function. The embodiment of the present invention adopts analog switch devices, and eliminates the original MCU independent control unit on the main control board and the original CPU and MCU independent control units on the service board and the switch board, thereby significantly reducing the cost of hardware design. In addition, through the centralized management function of the CPU on the main control board and the FPGA on the management board, the complexity of system management is reduced, and the overall efficiency and performance are improved.

[0111] Based on the above embodiments, an embodiment of the present invention further provides a storage medium, in which a computer program is stored. When the computer program is executed by a computer, the computer executes the dual master control switching method provided in the above embodiments.

[0112] Based on the above embodiments, the embodiments of the present application further provide a computer program. When the computer program is executed on a computer, the computer executes the dual-master switching method provided in the above embodiments.

[0113] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by instructions. These instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0114] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1A function specified in one or more boxes.

[0115] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0116] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A network device, characterized in that: It comprises a switching board provided with a switching chip, a management board provided with an interface extension management module, a service board provided with an interface extension chip, and a dual main control board provided with a CPU; the CPU is respectively connected to the switching chip and the interface extension management module; the interface extension management module is respectively connected to the switching chip and the interface extension chip; the CPU is used to manage the switching chip in the data plane; The interface extension management module is used to manage the interface extension chip on the monitoring plane.

2. The network device according to claim 1, characterized in that: The network device further comprises a shared storage unit; the shared storage unit is used for maintaining operation data and configuration data; When the dual main control boards switch between active and standby, the shared storage unit switches from being connected to the CPU on the original active main control board to being connected to the CPU on the new active main control board.

3. The network device according to claim 1 or 2, characterized in that: The dual main control boards are both provided with a logic processing control unit; the logic processing control unit is connected to the CPU; When the dual main control boards undergo a master-slave switch, the logic processing control unit on the new master main control board is used to generate a heartbeat control signal; wherein the heartbeat control signal is used to indicate the channel between the CPU on the new master main control board and the switching chip, the interface expansion management module and the shared storage unit.

4. The network device according to claim 3, characterized in that: The switch board is provided with a switch board switch module, and the management board is provided with a management board switch module; the switch board switch module is respectively connected to the CPU and the switch chip; the management board switch module is respectively connected to the CPU and the interface expansion management module; The switching board switch module and the management board switch module are used to switch from a state of being connected to the CPU on the original main control board to a state of being connected to the CPU on the new main control board when receiving the heartbeat control signal sent by the logic processing control unit on the new main control board.

5. The network device according to claim 3, characterized in that: The network device further comprises: a storage switch module; the storage switch module is respectively connected to the CPU and the shared storage unit; The storage switch module is used to switch from a state of being connected to the CPU on the original main control board to a state of being connected to the CPU on the new main control board when receiving the heartbeat control signal sent by the logic processing control unit on the new main control board.

6. The network device according to claim 3, characterized in that: The logic processing control unit is further used to determine the main control board and the standby main control board from the dual main control boards through a negotiation mechanism during the initialization process.

7. The network device according to any one of claims 1, 2, 4, 5 and 6, characterized in that: There are one or more switching boards; when there are two switching boards, the interface expansion chip is used to receive data on one of the switching boards; when a data link interruption occurs, it switches to receiving data on another switching board.

8. A dual master control switching method, characterized in that: Applied to a network device, the network device comprises a switching board provided with a switching chip, a management board provided with an interface extension management module, a service board provided with an interface extension chip, and a dual main control board provided with a CPU; the CPU is respectively connected to the switching chip and the interface extension management module; the interface extension management module is respectively connected to the switching chip and the interface extension chip; the CPU is used to manage the switching chip in the data plane; The interface extension management module is used to manage the interface extension chip on the monitoring plane; the method includes: When the master-slave switching condition of the dual main control boards is met, the standby main control board in the dual main control boards is switched to the new master main control board; Control and conduct the channel between the CPU of the new main control board itself and the switching chip and the interface expansion management module; wherein, the master-slave switching condition of the dual main control boards is: the channel between the CPUs on the dual main control boards is abnormal or the heartbeat signal of the CPU on the original main control board is lost.

9. The dual master switching method according to claim 8, characterized in that: The network device further includes a shared storage unit; the shared storage unit is used to maintain operation data and configuration data; the method further includes: The shared storage unit is controlled to switch from a state of being connected to the CPU on the original main control board to a state of being connected to the CPU on the new main control board.

10. The dual master control switching method according to claim 8 or 9, characterized in that: The dual main control boards are both provided with a logic processing control unit; the logic processing control unit is connected to the CPU; the method further includes: When the dual main control boards undergo a master-slave switch, a heartbeat control signal is generated through the logic processing control on the new master main control board; wherein, the heartbeat control signal is used to indicate the channel between the CPU on the new master main control board and the switching chip, the interface expansion management module and the shared storage unit.

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