Micro-power-consumption redundancy-eliminating task hierarchical general execution circuit

Abstract

The invention relates to a micro-power-consumption redundancy-eliminating task hierarchical general execution circuit, the execution circuit is arranged in a terminal, the terminal is connected with a gateway, and the execution circuit comprises a central controller, a task instruction cache circuit, a sensor control circuit, an off-chip task execution circuit and a data encoder; the central controller analyzes the control instruction of the gateway, controls the erasing of the task instruction cache circuit, outputs the instruction to the sensor control circuit and the off-chip task execution circuit, and controls the data encoder to output uplink data; the sensor control circuit outputs data to the off-chip task execution circuit, and the off-chip task execution circuit outputs control data to the task instruction cache circuit. According to the invention, data processing and sensor control task logic are realized by using a very simple hardware circuit combination, and a traditional task execution mode of operating a software program by using a microprocessor platform is replaced, so that the power consumption, the circuit complexity and the development cost of the terminal are reduced.

Description

Technical Field

[0001] The present invention relates to the field of Internet of Things, and in particular to a micro-power consumption redundant task layering universal execution circuit. Background Art

[0002] The Internet of Things perceives and connects the world through terminals. The traditional terminal architecture is mainly evolved from the embedded computer architecture. Its essence is to use the general computer platform as a carrier and simulate the control method of the target control logic through software, so it has good versatility, such as Figure 1 As shown. However, this method has a lot of redundancy in system design, which limits the optimization space for power consumption and cost. This makes it difficult to further reduce system power consumption and the development cost around the microprocessor remains high.

[0003] In order to solve this problem, some people have proposed to design application-specific integrated circuits (ASICs) to achieve specific functions. Compared with microprocessors, application-specific integrated circuits can complete the same tasks with lower power consumption, but designing application-specific integrated circuits for different scenarios will bring huge development costs. Therefore, application-specific integrated circuits are more suitable for application designs with fixed functions and large scale, but not for IoT terminal designs with variable functions. Another method is to use a dedicated signal conversion circuit to replace the microprocessor, so that the gateway can interact with the sensor data only by wireless signals; however, the essence of this type of terminal design is to transfer all the data processing tasks and sensor control logic originally carried by the microprocessor to the gateway, which will cause a lot of redundancy at the communication level, causing communication congestion in the actual use of the device, making it difficult to achieve large-scale application.

[0004] In general, the existing architecture is difficult to meet the needs of perception terminals for low-cost, long-term, large-scale deployment capabilities. The core reason is the large amount of redundancy brought about by the architecture or communication level in order to meet universality. Therefore, the core problem of traditional IoT terminal design is the high redundancy brought about to ensure universal functions. Specifically, in order to achieve access control and data processing for different sensor chips (such as temperature sensors, hygrometers, barometers, etc.), traditional terminals have to rely on microprocessors, a general computing platform, to have the ability to run embedded software programs, so that users can achieve different control goals by writing embedded software programs. Under this constraint, traditional terminals must rely on microprocessors using general computer architecture to run. The most direct way is to rely on local microprocessors and compromise with universality by increasing architectural redundancy, but this will bring about a series of problems such as complex terminal architecture and difficulty in optimizing cost and power consumption. Secondly, it is to use the microprocessor on the gateway side, but this will cause the underlying signal interaction tasks originally undertaken by the local microprocessor to be transferred to the gateway, thereby bringing a lot of redundancy at the communication level, resulting in a surge in communication overhead, which is difficult to meet the needs of large-scale applications. Summary of the invention

[0005] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a micro-power consumption redundant task layered universal execution circuit to solve the deficiencies of the prior art.

[0006] The object of the present invention is achieved by the following technical scheme: a micro-power consumption redundant task hierarchical universal execution circuit, the execution circuit is arranged in a terminal, the terminal is connected to a gateway, the execution circuit includes a central controller, a task instruction cache circuit, a sensor control circuit, an off-chip task execution circuit and a data encoder; the central controller and the data encoder are respectively connected to a communication interface arranged in the terminal, and the sensor control circuit is connected to a sensor arranged in the terminal; The central controller parses the control instructions of the gateway, controls the erasing and outputting instructions of the task instruction cache circuit to the sensor control circuit and the off-chip task execution circuit, and controls the data encoder to output uplink data; the sensor control circuit outputs data to the off-chip task execution circuit, and the off-chip task execution circuit outputs control data to the task instruction cache circuit.

[0007] The central controller includes a downlink data buffer, a status register, a control instruction parser and a preamble detector; the downlink data buffer is a first shift register with serial input and parallel output, the data stream sent by the gateway is transmitted to the downlink data buffer, the preamble detector enables the control instruction parser when matching the preamble, the control instruction parser completes the parsing of the control instruction, and updates the status register according to the instruction content, generates a control signal, and realizes the control of the rest of the circuit.

[0008] The task instruction cache circuit includes an instruction eraser, a task counter, an off-chip task controller and an instruction register group. The off-chip task controller contains an execution cycle timer and a start delay timer corresponding to each off-chip task; the output end of the instruction eraser is connected to the input end of the instruction register group, and the instruction register group is interconnected with the sensor control circuit; the output end of the off-chip task controller outputs the off-chip task to the off-chip task execution circuit, and the task counter counts the off-chip tasks.

[0009] When the central controller detects a task assignment instruction, it sends a control signal to the task instruction cache circuit to activate the eraser therein. The instruction eraser selects the instruction register to be erased according to the task type and task number carried in the task assignment instruction, and erases the contents therein. If an off-chip task instruction is received, the instruction eraser configures the timer of the corresponding task number in the off-chip task controller, and then the instruction eraser transmits the gateway data stream to the selected instruction register according to the task instruction length information.

[0010] The central controller includes a registration state, a stop state and a running state; when the central controller is in the running state, the task counter cyclically detects whether the start delay timer and the execution cycle timer of each off-chip task have reached the preset time. If a task meets the execution condition, its corresponding task register is output once, that is, the off-chip task is completely executed once; When the off-chip task execution circuit calls a sensor control task, it controls the called task register to output instruction data to the sensor control circuit, and continues to execute the off-chip task only after the sensor control task is completed.

[0011] The sensor control circuit includes a first instruction parser, a second shift register, a delay timer, a raw data register group, an interface configuration unit and a signal interaction unit; When executing the sensor control task, the task instruction cache circuit transfers the sensor control instruction to the second shift register so that the first instruction parser can parse it and send control signals to the remaining units. The delay timer meets the timing requirements of different sensors. The raw data register group is used to temporarily store the data output by the sensor. The signal interaction unit realizes bus signal interaction, pin level reading and writing, and event signal detection functions. The interface configuration unit realizes flexible configuration of the working mode of the sensor interface.

[0012] The off-chip task execution circuit includes a third shift register, a second instruction parser, a data clipping circuit, an operation unit, a data combining circuit and a sensor data register group; The off-chip task execution circuit obtains the off-chip task instruction data through the third shift register, and the second instruction parser controls the remaining circuit structures to execute the instructions. The data combination circuit is responsible for extracting complete sensor data from the original data. The operation unit performs operation processing on the data in the sensor data register group and transmits the operation result back to the sensor data register group. The data clipping circuit is responsible for clipping the operation result and transmitting it to the data encoder.

[0013] The data combining circuit includes a data position mask register and a valid bit mask register. The data combining circuit selects each original data register in turn and determines whether to participate in data combining according to the output of the data position mask register. The original data register participating in data combining and the valid bit mask register start shifting and outputting at the same time. If the current output is valid, the sensing data register shifts and receives the output of the original data register. For a signed number, if the first valid bit is 1, that is, the sensing data is a negative number, the data combining circuit will fill the entire sensing data register with 1 to expand the sign bit.

[0014] The operation unit interval judgment circuit, difference calculation circuit and recursive average value calculation circuit; The interval judgment circuit includes a numerical comparator, which compares the sensing data with the left threshold value and the right threshold value data in sequence, and judges whether the data is valid according to the results of the two comparisons and the type of the instruction, and then transmits the valid flag of the data to the data clipping circuit; the interval judgment circuit controls the response pin level according to the value of the response pin level field contained in the between and outside instructions and the judgment result, so as to notify the external circuit of the change of the sensing data in real time; The difference calculation circuit includes a subtractor, a most recently uploaded data register and a most recent data register; when executing the sub instruction, the difference calculation circuit transfers the target sensor data C to the most recent data register, then calculates the difference between the most recent data C and the most recently uploaded data D, and transfers the calculation result CD back to the sensor data register; the user chooses to perform interval judgment on the calculation result, realizes the threshold detection processing of the change amount of the sensor data, and controls the response pin to output high and low levels, or chooses to skip the interval judgment correction and directly upload the change amount of the sensor data to the gateway. When the instruction is executed, if the sensor data is valid, the latest data is updated to the most recently uploaded data register; The recursive average value calculation circuit comprises a sensing data queue, a queue summing circuit, a summing result register, a right shift circuit and a sampling times counter; when the avg instruction is executed, new sensing data is inserted into the tail of the queue, the queue summing circuit reads the summing result register and the data of the head and tail of the queue, calculates a new summing result, and writes it back to the summing result register; according to the queue length set by the instruction, the right shift circuit shifts the summing result to the right, and transmits the obtained recursive average value back to the sensing data register; the user chooses whether to perform interval judgment on the recursive average value and make a real-time response according to application requirements, and when the value of the sampling times counter reaches the preset upload interval, the upload of the average value will be allowed.

[0015] The data clipping circuit includes a valid flag register and a counter. When executing an upload instruction, the data clipping circuit selects the sensing data register according to the valid flag, and controls it to shift and output data of corresponding bits to the data encoder according to the bit number information carried in the upload instruction.

[0016] The present invention has the following advantages: a micro-power consumption redundancy-free task hierarchical universal execution circuit, which realizes data processing and sensor control task logic with a very simple hardware circuit combination, replaces the traditional task execution method of running software programs on a microprocessor platform, thereby reducing the power consumption, circuit complexity and development cost of the terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a schematic diagram of the architecture of a traditional terminal; Figure 2 It is a structural schematic diagram of the present invention; Figure 3 This is a schematic diagram of the state switching of the central controller; Figure 4 Schematic diagram of the circuit structure of the central controller; Figure 5 A circuit structure diagram of a task instruction cache circuit; Figure 6 It is a circuit structure diagram of the sensor control circuit; Figure 7 A schematic diagram of the circuit structure of an off-chip task execution circuit; Figure 8 It is a schematic diagram of the working principle of the data combining circuit; Fig. 9 This is a schematic diagram of the working principle of the interval judgment circuit; Fig.10 This is a schematic diagram of the working principle of the difference calculation circuit; Fig.11 This is a schematic diagram of the working principle of the recursive average value calculation circuit; Fig.12 A schematic diagram of the encoding format of the device registration signal; Fig.13 This is a schematic diagram of the coding format of the control instruction confirmation signal; Fig.14 A schematic diagram of the encoding format of device status information; Fig.15 Schematic diagram of the encoding format of sensor data. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of the present application provided below in conjunction with the drawings is not intended to limit the scope of protection of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application. The present invention is further described below in conjunction with the drawings.

[0019] like Figure 2 As shown, the present invention specifically relates to a micro-power consumption redundant task hierarchical universal execution circuit, which is arranged in a terminal, and the terminal is connected to a gateway. The gateway is responsible for sending control instructions and task logic to the terminal. The circuit replaces the microprocessor on the terminal to execute the received data processing and sensor control tasks. Compared with the microprocessor, the circuit does not have the ability to generate the task logic of the perception terminal, but only has the task execution function, which is the key to simplifying the terminal into a gateway wireless peripheral.

[0020] Furthermore, it includes a central controller, a task instruction cache circuit, a sensor control circuit, an off-chip task execution circuit, and a data encoder. With the cooperation of each unit, the working principle of the circuit is as follows: 1) Device registration: The UTE circuit (task hierarchical universal execution circuit) is in the registration state after power-on, and will periodically send a device registration signal until it receives a task allocation instruction, thereby registering the terminal number that uniquely identifies this terminal into the network.

[0021] 2) Task reception: When the terminal receives a task assignment instruction, the central controller will parse the various fields in the task assignment instruction and erase and write the task instruction cache circuit accordingly, temporarily storing the received task instruction data in the cache.

[0022] 3) Task execution: The central controller sets the execution cycle and start delay of each off-chip task according to the control instructions. When an off-chip task meets the execution conditions, the task instruction cache circuit outputs the off-chip task instruction to the off-chip task execution circuit. The off-chip task execution circuit first calls the sensor control task in the instruction cache, so that the sensor control circuit executes the task and obtains the raw data. Subsequently, the off-chip task execution circuit processes the raw data according to the instructions.

[0023] 4) Data upload: The data uploaded by the terminal includes device registration signals, control command confirmation signals, device status information, and processed sensor data. The data encoder will generate data with a fixed encoding format under the control of the central controller and transmit it to the communication interface to realize data upload.

[0024] 1. Central controller design; The central controller is responsible for parsing the control instructions of the gateway, controlling the erasure and output of the task instruction cache circuit, and controlling the data encoder to output uplink data. The central controller has three working states: registration state, stop state, and running state. The switching between the three states is as follows: Figure 3 as shown. When the circuit is powered on, the central controller is in the registration state by default. In this state, the central controller will control the data encoder to periodically output the device registration signal until it receives the task assignment instruction from the gateway, and then switch to the stop state. The gateway can assign tasks, query device status, request data retransmission when the terminal is in the stop state, or directly send a task start instruction to switch it to the running state. In the running state, the central controller sends a signal to the task instruction cache circuit to output the off-chip task instruction according to the set execution cycle. When a task stop instruction is received, the central controller will switch to the stop state.

[0025] The circuit structure of the central controller is as follows: Figure 4 As shown. The downlink data buffer is a shift register with serial input and parallel output, and the data stream sent by the gateway will be transmitted here. The preamble detector will enable the control instruction parser when it matches the preamble. Since the downlink data buffer can output instruction data in parallel, the control instruction parser can complete the parsing of the control instruction in a very short time, and update the status register according to the instruction content, generate control signals, and realize the control of the rest of the circuit.

[0026] 2. Task instruction cache circuit design; Although transferring the task logic to the gateway simplifies the terminal development process, it also increases the downlink communication load of the system. In order to solve this problem, the present invention designs a task instruction cache circuit in the UTE circuit. The task instructions sent by the gateway to the terminal will be temporarily stored in the task instruction cache circuit. When the terminal task does not need to be updated, the gateway does not need to send the task instruction again, thereby saving the downlink communication resources of the system. The circuit structure of the task instruction cache circuit is shown in FIG. Figure 5 As shown, it mainly includes instruction eraser, task counter, off-chip task controller and instruction register group. Among them, the off-chip task controller contains the execution cycle timer and start delay timer corresponding to each off-chip task; the instruction register group consists of a group of 256-bit circular shift registers.

[0027] 1. Instruction erase; When the central controller detects a task assignment instruction, it sends a control signal to the task instruction cache circuit to activate the eraser. The eraser selects the instruction register to be erased according to the task type and task number carried in the task assignment instruction, and erases the contents. If an off-chip task instruction is received, the instruction eraser will also configure the timer of the corresponding task number in the off-chip task controller. Subsequently, the eraser will transfer the gateway data stream to the selected instruction register according to the task instruction length information.

[0028] 2. Command output; The task execution logic of the terminal conforms to the hierarchical terminal control framework proposed by the present invention. Under this framework, the gateway controls the execution cycle and startup delay of each off-chip task, and the off-chip task will call the sensor control task to obtain data. When the central controller is in operation, the task counter will cyclically detect whether the startup delay and execution cycle timer of each off-chip task have reached the preset time. If a task meets the execution conditions, its corresponding task register will be output once, that is, the off-chip task will be completely executed once. When calling a sensor control task, the off-chip task execution circuit will control the called task register to output instruction data to the sensor control circuit, and will not continue to execute the off-chip task until the sensor control task is executed.

[0029] 3. Sensor control circuit design; The design goal of the sensor control circuit is to give the processor-free terminal a variety of sensor control capabilities with a low-redundancy circuit design. Its circuit structure is as follows: Figure 6 Based on the analysis of the sensor control task by the present invention, the present invention designs an instruction parser, a shift register, a delay timer, a raw data register group, an interface configuration unit and a signal interaction unit in the sensor control circuit.

[0030] When executing the sensor control task, the task instruction cache circuit will transfer the sensor control instruction to a serial input and parallel output shift register so that the instruction parser can parse it and send control signals to the rest of the circuit. The delay timer can meet the timing requirements of different sensors, and the raw data register group is used to temporarily store the data output by the sensor. In addition, the signal interaction unit has bus signal interaction, pin level reading and writing, and event signal detection functions, and the interface configuration unit can flexibly configure the working mode of the sensor interface.

[0031] 1. Interface configuration unit design; The present invention designs a set of GPIO pin interfaces in the signal interaction unit, which has four working modes commonly used in sensor interfaces: pull-up input, pull-down input, push-pull output, and open-drain output. The interface configuration unit will configure the working mode of the GPIO pin according to the bus interface and the content of the single pin configuration instruction, as follows: (1) Bus interface configuration: The number of bus pins and the working mode usually adopt fixed standards. Therefore, the present invention maps the bus interface groups to GPIO pins. For example, pins 1 to 4 are the first group of SPI interfaces, and pins 5 to 8 are the second group of SPI interfaces. Similarly, pins 1 to 2 are the first group of I2C interfaces, and pins 3 to 4 are the second group of I2C interfaces. For different types of bus interfaces, the GPIO configurator will complete the configuration of all its pins at once. For example, the "MISO" pin of the SPI interface is configured as a pull-down input mode, and the "MOSI", "SCK", and "CS" pins are configured as push-pull output modes.

[0032] (2) Single-pin configuration: The single-pin configuration function allows the terminal to configure the electrical characteristics of the pin more flexibly. For example, when reading and writing levels or detecting event signals on pins other than the bus interface, it is necessary to configure the working mode of a specified single pin. This function enables the UTE circuit to be compatible with more types of sensor chips.

[0033] In addition, the interface configuration unit contains a bus configuration status register for temporarily storing the bus interface configuration status of the current sensor control task. This register can control the multiplexer in the signal interaction unit so that the signal interaction unit can select the correct bus signal interaction module and GPIO pin when executing instructions.

[0034] 2. Signal interaction unit design; The signal interaction unit is used to implement common sensor control logic such as bus signal interaction, pin level reading and writing, event waiting, etc., and transmits the raw data output by the sensor to the raw data register group. The design of its internal circuit structure specifically includes the following contents: (1) Bus signal interaction module: When the sensor control circuit receives a bus read / write instruction, the signal interaction unit selects the bus signal interaction module and GPIO pin according to the interface configuration information temporarily stored in the bus configuration status register. The bus signal interaction module reads and writes data to the sensor according to the instruction content. If the instruction is a data read instruction, the bus signal interaction module transfers the read data byte by byte to the raw data register group as the data source for the off-chip task. In the prototype system of the present invention, two bus signal interaction modules, I2C and SPI, are designed to realize the data interaction function with common sensor chips.

[0035] (2) Pin level reader: The pin level reader configures and reads the level status of a single pin according to the instructions. For the 1-bit pin level data read, the pin level reader will expand it to a byte length (8 bits) and store it in the raw data register group. The signal interaction between the sensor chip and the outside world is essentially realized by a series of pin read and write operations. Therefore, the pin level read and write function enables the terminal to generate various sensor control signals in addition to bus signals, broadening the range of sensor chips that can be controlled by the UTE circuit.

[0036] (3) Event signal detector: The event wait instruction will specify the pin number and the target level. When the signal interaction unit receives the instruction, it will start the event signal detector and send a task blocking signal to the task instruction cache circuit to stop the instruction data output of the task until the level state of the target pin meets the preset conditions or the waiting time expires.

[0037] 4. Design of off-chip task execution circuit; The off-chip task execution circuit can give the processor-free sensing terminal simple data analysis and filtering capabilities, thereby reducing unnecessary data uploads and improving the performance of the IoT system. Figure 7 shown.

[0038] Similar to the sensor control circuit, the off-chip task execution circuit obtains the off-chip task instruction data through the serial input and parallel output shift register, and the instruction parser controls the remaining circuit structures to execute the instructions. The data combination circuit is responsible for extracting complete sensor data from the raw data, and the operation unit will perform operations on the data in the sensor data register group and transmit the operation results back to the sensor data register group. The data clipping circuit is responsible for clipping the operation results and transmitting them to the data encoder.

[0039] 1. Data combining circuit; Most sensor chips store their sensor data in single-byte (8-bit) registers (e.g., TMP125 sensor). Therefore, the first step in sensor data preprocessing is to combine the data scattered in multiple registers to obtain complete sensor data. In order to achieve this function, the present invention designs a data combination unit in the off-chip task execution circuit. Its working principle is as follows: Figure 8 shown.

[0040] The data position mask, valid bit mask, sensor data, and raw data are stored in serial output shift registers of different lengths. The data combining circuit selects each raw data register in turn and determines whether it participates in the data combining based on the output of the data position mask register. The raw data register participating in the combining will start shifting and outputting at the same time as the valid bit mask register. If the current output is valid (the output of the valid bit mask register is "1"), the sensor data register shifts and receives the output of the raw data register. For signed numbers, if the first valid bit is "1", that is, the sensor data is a negative number, the data combining circuit will fill the entire sensor data register with "1" to expand the sign bit. Figure 8 The final result of combining the data is "0001100100" (the picture is flipped left and right).

[0041] The present invention designs the sensor data generated by the combination as 24-bit signed integer data, which can cover the common sensor data value range. The design of the data combination circuit is based on the observation of the sensor data characteristics of the present invention, and the efficient extraction of sensor data is completed with a simplified circuit without the assistance of a microprocessor, providing a data source for the operation unit.

[0042] 2. Arithmetic unit; The computing unit is designed to provide basic data computing capabilities for processor-free terminals with a simplified circuit design, enabling them to filter and integrate sensor data, thereby reducing the amount of uplink communication data and reducing communication overhead. The computing unit has three data processing circuits: interval judgment, difference calculation, and recursive average calculation.

[0043] (1) Interval judgment circuit; The interval judgment circuit can limit the sensor data that the terminal needs to upload to a certain interval range, thereby reducing the uplink communication overhead. The core of this circuit is a numerical comparator that can compare two 24-bit signed data. Fig. 9 As shown, the interval judgment circuit compares the sensing data with the left threshold and the right threshold data in sequence, and determines whether the data is valid based on the results of the two comparisons and the type of instruction, and then transmits the valid flag of the data to the data clipping circuit.

[0044] In addition to filtering the data, the interval judgment circuit also enables the terminal to respond to changes in sensor data in real time. Fig. 9 As shown, the "between" and "outside" instructions contain a response pin level field, and the interval judgment circuit can control the level of the response pin according to the value of the field and the judgment result, thereby notifying the external circuit of the change of the sensor data in real time.

[0045] Among them, between instruction: This instruction contains 5 fields, namely, keyword, sensor data number (2 bits), left threshold (24 bits), right threshold (24 bits), response pin level (1 bit). Its function is to make interval judgment on the specified sensor data and control the response pin level according to the judgment result. outside instruction: This instruction has the same instruction encoding format as "between". The keyword encoding of the two is different, and the judgment results are opposite.

[0046] (2) Difference calculation circuit; For scenarios where sensor data changes slowly, the amount of uplink communication data in the system can be reduced by using a change threshold detection method, that is, the terminal will upload data only when the change in the current sensor data exceeds the threshold. In order to perform change threshold detection preprocessing on sensor data without the assistance of a processor, the present invention designs a simple difference calculation circuit in the off-chip task execution circuit, which is mainly composed of a subtractor, a latest data register and multiple recently uploaded data registers. Its working principle is as follows: Fig.10 shown.

[0047] When the "sub" instruction is executed, the difference calculation circuit will transfer the target sensor data "C" to the latest data register, then calculate the difference between the latest data "C" and the most recently uploaded data "D", and transfer the calculation result "CD" back to the sensor data register. The user can choose to perform interval judgment on the calculation result (i.e., the "sub_between / outside" instruction) to implement threshold detection and processing of the change in sensor data, and control the response pin to output high and low levels; or choose to skip the interval judgment step and directly upload the change in sensor data to the gateway. When the "sub" and "sub_between / outside" instructions are executed, if the sensor data is valid, the latest data will be updated to the most recently uploaded data register.

[0048] Among them, sub instruction: This instruction consists of a keyword and a sensor data number (2 bits). Its function is to calculate the difference of the specified sensor data.

[0049] (3) Recursive average value calculation circuit; Average value aggregation or average value filtering is a commonly used data preprocessing method for sensing terminals. In order to implement this method, the present invention designs a recursive average value calculation circuit. The recursive average value calculation method is: regard the continuous m sampled data as a queue. Each time there is new sampled data, the data at the head of the queue is removed from the queue and the new data is put into the tail of the queue. The average value of the data in the queue is the recursive average value. The working principle of the recursive average value calculation circuit is as follows: Fig.11 shown.

[0050] The recursive average calculation circuit includes a sensor data queue, a queue summing circuit, a summing result register, a right shift circuit, and a sampling counter. Each group of sensor data queues and summing result registers corresponds to an off-chip task, that is, each off-chip task supports recursive average calculation of one sensor data. Since the 24-bit signed number divider is relatively complex, the present invention limits the queue length supported by the recursive average calculation circuit to 2, 4, 8, and 16. The average calculation can be achieved by simply shifting right, thereby achieving the target function with a simple circuit design. The working process of the circuit is as follows: When the "avg" instruction is executed, the new sensor data will be inserted at the end of the queue. Subsequently, the queue summation circuit will read the summation result register and the data at the head and tail of the queue, calculate the new summation result, and write it back to the summation result register. Finally, according to the queue length set by the instruction, the right shift circuit shifts the summation result to the right and transmits the obtained recursive average value back to the sensor data register. Similar to the difference calculation circuit, the user can choose whether to perform interval judgment on the recursive average value and respond in real time according to application requirements. When the value of the sampling counter reaches the preset upload interval, the upload of the average value will be allowed. Using the sampling counter, the terminal can flexibly adjust the level of average value aggregation or mean filtering processing and flexibly control the amount of uplink data.

[0051] Among them, the avg instruction: This instruction contains 4 fields, namely, keyword, sensor data number (2 bits), queue length (2 bits), and upload interval (4 bits). Its function is to calculate the average value of sensor data and specify the interval for uploading the average value.

[0052] 3. Data clipping circuit; In order to be compatible with more sensor chips, the present invention sets the bit length of the sensor data to 24 bits. For some shorter sensor data, bit expansion will bring invalid uplink communication overhead. To solve this problem, the present invention designs a data clipping circuit in the off-chip task execution circuit, which is responsible for clipping the data to be uploaded to the specified bit length. The structure of the circuit is relatively simple, mainly consisting of a valid flag register and a counter. When executing the "upload" instruction, the data clipping circuit selects the sensor data register according to the valid flag, and controls it to shift and output the corresponding number of bits of data to the data encoder according to the bit information carried in the "upload" instruction.

[0053] Among them, the upload instruction: This instruction contains 2 fields, which are the keyword and the number of bits required to upload each sensor data (15 bits). Its function is to remove the invalid bits in the sensor data expanded to 24 bits and reduce the amount of uploaded data.

[0054] 5. Data encoder design; Under the control of the central controller, the data encoder encodes the uploaded data so that the gateway can correctly identify the data of each terminal. Depending on the input control signal, the data encoder can output the following types of data to the communication interface: (1) Device registration signal; The UTE circuit is in the registration state by default after power-on. The central controller will control the data encoder to periodically output the device registration signal. The encoding format of the device registration signal is as follows: Fig.12 shown.

[0055] (2) Control command confirmation signal; In addition to data retransmission and status query instructions, the data encoder will output a confirmation signal after the execution of other control instructions, thereby promptly notifying the gateway of the control instruction reception status and facilitating the gateway to proceed to the next step. The encoding format of the control instruction confirmation signal is as follows: Fig.13 shown.

[0056] (3) Equipment status information; When receiving the status query command, the central controller will control the data encoder to output the current task allocation status of the UTE circuit, that is, the number of off-chip tasks and sensor control tasks in the task instruction cache circuit. The encoding format of the device status information is as follows: Fig.14 As shown, it includes four fields: status preamble, terminal number, number of off-chip tasks, and number of sensor control tasks.

[0057] (4) processed sensor data; The data encoder can temporarily store the sensor data output by the data clipping circuit and use the counter to record its length. According to the rules of uploading data, terminal tasks can be divided into two categories: periodic tasks and event tasks. The data encoder will determine its task type based on whether the current task contains an interval judgment statement. When the off-chip task is completed or a data retransmission instruction is received, the central controller will control the data encoder to encode the sensor data and then output it to the communication interface. The encoding format of the sensor data is as follows: Fig.15 shown.

[0058] The above is only a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed in the present invention, and should not be regarded as excluding other embodiments, but can be used for various other combinations, modifications and improvements, and can be modified within the scope of the concept described in the present invention through the above teachings or the technology or knowledge in the relevant field. The changes and modifications made by those skilled in the art do not deviate from the spirit and scope of the present invention, and should be within the scope of protection of the claims attached to the present invention.

Claims

1. A micro-power redundant task hierarchical general execution circuit, Features: The execution circuit is arranged in the terminal, the terminal is connected to the gateway, and the execution circuit includes a central controller, a task instruction cache circuit, a sensor control circuit, an off-chip task execution circuit and a data encoder; the central controller and the data encoder are respectively connected to the communication interface arranged in the terminal, and the sensor control circuit is connected to the sensor arranged in the terminal; The central controller parses the control instructions of the gateway, controls the erasing and outputting instructions of the task instruction cache circuit to the sensor control circuit and the off-chip task execution circuit, and controls the data encoder to output uplink data; the sensor control circuit outputs data to the off-chip task execution circuit, and the off-chip task execution circuit outputs control data to the task instruction cache circuit.

2. A micro-power consumption redundant task layered general execution circuit according to claim 1, Features: The central controller includes a downlink data buffer, a status register, a control instruction parser and a preamble detector; the downlink data buffer is a first shift register with serial input and parallel output, the data stream sent by the gateway is transmitted to the downlink data buffer, the preamble detector enables the control instruction parser when matching the preamble, the control instruction parser completes the parsing of the control instruction, and updates the status register according to the instruction content, generates a control signal, and realizes the control of the rest of the circuit.

3. A micro-power consumption redundant task layered general execution circuit according to claim 1, Features: The task instruction cache circuit includes an instruction eraser, a task counter, an off-chip task controller and an instruction register group. The off-chip task controller contains an execution cycle timer and a start delay timer corresponding to each off-chip task; the output end of the instruction eraser is connected to the input end of the instruction register group, and the instruction register group is interconnected with the sensor control circuit; the output end of the off-chip task controller outputs the off-chip task to the off-chip task execution circuit, and the task counter counts the off-chip tasks.

4. A micro-power consumption redundant task layered general execution circuit according to claim 3, Features: When the central controller detects a task assignment instruction, it sends a control signal to the task instruction cache circuit to activate the eraser therein. The instruction eraser selects the instruction register to be erased according to the task type and task number carried in the task assignment instruction, and erases the contents therein. If an off-chip task instruction is received, the instruction eraser configures the timer of the corresponding task number in the off-chip task controller, and then the instruction eraser transmits the gateway data stream to the selected instruction register according to the task instruction length information.

5. A micro-power consumption redundant task layered general execution circuit according to claim 3, Features: The central controller includes a registration state, a stop state and a running state; when the central controller is in the running state, the task counter cyclically detects whether the start delay timer and the execution cycle timer of each off-chip task have reached the preset time. If a task meets the execution condition, its corresponding task register is output once, that is, the off-chip task is completely executed once; When the off-chip task execution circuit calls a sensor control task, it controls the called task register to output instruction data to the sensor control circuit, and continues to execute the off-chip task only after the sensor control task is completed.

6. A micro-power consumption redundant task layered general execution circuit according to claim 1, Features: The sensor control circuit includes a first instruction parser, a second shift register, a delay timer, a raw data register group, an interface configuration unit and a signal interaction unit; When executing the sensor control task, the task instruction cache circuit transfers the sensor control instruction to the second shift register so that the first instruction parser can parse it and send control signals to the remaining units. The delay timer meets the timing requirements of different sensors. The raw data register group is used to temporarily store the data output by the sensor. The signal interaction unit realizes bus signal interaction, pin level reading and writing, and event signal detection functions. The interface configuration unit realizes flexible configuration of the working mode of the sensor interface.

7. A micro-power consumption redundant task layered general execution circuit according to claim 1, Features: The off-chip task execution circuit includes a third shift register, a second instruction parser, a data clipping circuit, an operation unit, a data combining circuit and a sensor data register group; The off-chip task execution circuit obtains the off-chip task instruction data through the third shift register, and the second instruction parser controls the remaining circuit structures to execute the instructions. The data combination circuit is responsible for extracting complete sensor data from the original data. The operation unit performs operation processing on the data in the sensor data register group and transmits the operation result back to the sensor data register group. The data clipping circuit is responsible for clipping the operation result and transmitting it to the data encoder.

8. A micro-power consumption redundant task layered general execution circuit according to claim 7, Features: The data combining circuit includes a data position mask register and a valid bit mask register. The data combining circuit selects each original data register in turn and determines whether to participate in data combining according to the output of the data position mask register. The original data register participating in data combining and the valid bit mask register start shifting and outputting at the same time. If the current output is valid, the sensing data register shifts and receives the output of the original data register. For a signed number, if the first valid bit is 1, that is, the sensing data is a negative number, the data combining circuit will fill the entire sensing data register with 1 to expand the sign bit.

9. A micro-power consumption redundant task layered general execution circuit according to claim 7, Features: The operation unit interval judgment circuit, difference calculation circuit and recursive average value calculation circuit; The interval judgment circuit includes a value comparator, which compares the sensing data with the left threshold value and the right threshold value data in sequence, and judges whether the data is valid according to the results of the two comparisons and the type of the instruction, and then transmits the valid flag of the data to the data clipping circuit; The interval judgment circuit controls the response pin level according to the value of the response pin level field contained in the between and outside instructions and the judgment result, thereby notifying the external circuit of the change of the sensor data in real time; The difference calculation circuit includes a subtractor, a most recently uploaded data register and a most recent data register; when executing the sub instruction, the difference calculation circuit transfers the target sensor data C to the most recent data register, then calculates the difference between the most recent data C and the most recently uploaded data D, and transfers the calculation result CD back to the sensor data register; the user chooses to perform interval judgment on the calculation result, realizes the threshold detection processing of the change amount of the sensor data, and controls the response pin to output high and low levels, or chooses to skip the interval judgment correction and directly upload the change amount of the sensor data to the gateway. When the instruction is executed, if the sensor data is valid, the latest data is updated to the most recently uploaded data register; The recursive average calculation circuit comprises a sensor data queue, a queue summing circuit, a summing result register, a right shift circuit and a sampling times counter; when the avg instruction is executed, new sensor data is inserted into the tail of the queue, the queue summing circuit reads the summing result register and the data at the head and tail of the queue, calculates a new summing result, and writes it back to the summing result register; According to the queue length set by the instruction, the right shift circuit shifts the summation result to the right and transmits the obtained recursive average value back to the sensor data register; the user chooses whether to perform interval judgment on the recursive average value and make real-time response according to application requirements. When the value of the sampling times counter reaches the preset upload interval, the upload of the average value will be allowed.

10. A micro-power consumption redundant task layered general execution circuit according to claim 7, Features: The data clipping circuit includes a valid flag register and a counter. When executing an upload instruction, the data clipping circuit selects the sensing data register according to the valid flag, and controls it to shift and output data of corresponding bits to the data encoder according to the bit number information carried in the upload instruction.

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